Display panel and display device

Abstract

The application relates to the technical field of optical display, in particular to a display panel and a display device. An anode via hole of any second sub-pixel in a pixel pair is arranged on one side close to another second sub-pixel, and no isolation structure is arranged between the corresponding two anode via holes. The anode via hole is arranged between two second isolation structures, so that the two first isolation structures are communicated through the second isolation structure. The design makes the second isolation structure parallel to the second direction. In the evaporation process of the display panel, since the evaporation direction is perpendicular to the second direction, the shielding area of the second isolation structure to the evaporation source is reduced during evaporation, so that the spacing distance between the sub-pixels can be increased, and the opening area of the sub-pixel is increased.

Description

Technical Field

[0001] This invention relates to the field of optical display technology, and more specifically to a display panel and display device. Background Technology

[0002] Currently, organic light-emitting diode (OLED) display panels use fine masks for vapor deposition to prepare OLED light-emitting units. These masks are expensive, making the development of new products extremely costly. Furthermore, the bridging area of ​​the fine mask openings limits the effective area of ​​the pixel light-emitting region, hindering the improvement of the aperture ratio. Summary of the Invention

[0003] The purpose of this application is to provide a display panel and a display device.

[0004] This application provides a display panel, the display panel comprising: a driving substrate; a planarization layer disposed on the driving substrate; a pixel definition layer disposed on the planarization layer to form a pixel region, and the planarization layer forming an anode via in the radial direction of the pixel region; an anode disposed on the pixel region extending toward the anode via, the anode being electrically connected to the driving substrate through the anode via; sub-pixels disposed on the pixel region, the sub-pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel being arranged along a first direction and a second direction; and an isolation structure disposed on the pixel definition layer, the isolation structure being oriented away from the driving substrate. The substrate protrudes from one side to isolate the first sub-pixel, the second sub-pixel, and the third sub-pixel. In the second direction, two adjacent second sub-pixels in the same pixel column form a pixel pair. In the pixel pair, the anode via of any second sub-pixel is located on the side closer to the other second sub-pixel. In the pixel pair, the isolation structure includes two first isolation structures and two second isolation structures. The two first isolation structures are respectively located on the outer periphery of the two second sub-pixels, and the two first isolation structures respectively form a communication port on the side closer to the anode via. The two second isolation structures connect the two first isolation structures so that the communication ports of the two first isolation structures are interconnected. The anode via is located between the two first isolation structures. In one exemplary embodiment of this application, in a first direction, the second sub-pixels are arranged at intervals to form a first pixel row, the first sub-pixels and the third sub-pixels are arranged at intervals and alternately to form a second pixel row, and the first pixel row and the second pixel row are arranged at intervals and alternately along a second direction; in a second direction, the second sub-pixels are arranged at intervals to form a first pixel column, the first sub-pixels and the third sub-pixels are arranged at intervals and alternately to form a second pixel column, and the first pixel column and the second pixel column are arranged at intervals and alternately along a first direction.

[0005] In one exemplary embodiment of this application, the pixel column of the second sub-pixel includes at least a first sub-pixel column and a second sub-pixel column. The pixel pair formed by two adjacent second sub-pixels in the first sub-pixel column is a first pixel pair, and the pixel pair formed by two adjacent second sub-pixels in the second sub-pixel column is a second pixel pair. The orthographic projections of the anode vias in the first pixel pair and the anode vias in the second pixel pair are staggered in the second direction.

[0006] In an exemplary embodiment of this application, the anode via corresponding to the first sub-pixel is a first via, the anode via corresponding to the second sub-pixel is a second via, and the anode via corresponding to the third sub-pixel is a third via; in the first direction, the first sub-pixel forms a first plane on the side close to and away from the second via, and the third sub-pixel forms a third plane on the side close to and away from the second via; the first via is disposed outside the first plane of the first sub-pixel away from the second via; the third via is disposed outside the third plane of the third sub-pixel away from the second via.

[0007] In one exemplary embodiment of this application, the first sub-pixel and the third sub-pixel are hexagonal in shape, and the second sub-pixel is quadrilateral in shape.

[0008] In one exemplary embodiment of this application, the pixel pair, the first sub-pixel, and the second sub-pixel are respectively located at the vertices of a virtual rhombus, and the second sub-pixel, the first sub-pixel, and the third sub-pixel have the same center point as the vertices of the virtual rhombus.

[0009] In one exemplary embodiment of this application, within the virtual rhombus, the first sub-pixel, the second sub-pixel, and the third sub-pixel share the second isolation structure.

[0010] In one exemplary embodiment of this application, the pixel definition layer is made of an inorganic material, the pixel definition layer extends along the anode via and the planarization layer, and the isolation structure and the anode via do not overlap in orthographic projection on the driving substrate.

[0011] In one exemplary embodiment of this application, the isolation structure includes a metal layer and an insulating layer. The metal layer is disposed on the pixel definition layer, and the insulating layer is disposed on the metal layer. The width of the insulating layer is greater than the width of the metal layer.

[0012] This application also provides a display device, including the aforementioned display panel.

[0013] This application discloses a display panel and display device, which have the following advantages: A driving substrate is used to drive the display panel. Specifically, the anode is electrically connected to the driving substrate, and the driving substrate drives the sub-pixels to emit light. The first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged along a first direction and a second direction, and are individually packaged through an isolation structure. In the second direction, any two second sub-pixels in the same pixel column form a pixel pair. In the pixel pair, the anode via of any second sub-pixel is located on the side closer to the other second sub-pixel, and there is no isolation structure between the corresponding two anode vias. The anode via is located between two second isolation structures, thereby connecting the two first isolation structures through the second isolation structure. This design makes the second isolation structure parallel to the second direction. In the vapor deposition process of the display panel, since the vapor deposition direction is perpendicular to the second direction, the blocking area of ​​the vapor deposition source by the second isolation structure is reduced during vapor deposition, thereby increasing the spacing between sub-pixels and increasing the opening area of ​​the sub-pixels.

[0014] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 This is a cross-sectional schematic diagram of a display panel in an embodiment of the present invention, wherein the pixel definition layer is made of organic material;

[0018] Figure 2 This is a cross-sectional schematic diagram of a display panel in an embodiment of the present invention, wherein the pixel definition layer is made of inorganic material;

[0019] Figure 3 This is a plan view of a display panel according to an embodiment of the present invention;

[0020] Figure 4 This is a planar schematic diagram of the first sub-pixel, the second sub-pixel, and the third sub-pixel forming a virtual square in a display panel according to an embodiment of the present invention;

[0021] Figure 5 This is a planar schematic diagram of pixel pairs in an embodiment of the present invention;

[0022] Figure 6 yes Figure 5 A cross-sectional schematic diagram of AA in the middle;

[0023] Figure 7 yes Figure 5 A cross-sectional view of BB.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10. Driving substrate; 20. Planarization layer; 21. Anode via; 211. First via; 212. Second via; 213. Third via; 30. Pixel definition layer; 31. Pixel region; 40. Anode; 50. Subpixel; 51. First subpixel; 511. First plane; 52. Second subpixel; 53. Third subpixel; 531. Third plane; 60. Pixel pair; 61. First pixel pair; 62. Second pixel pair; 71. First subpixel column; 72. Second subpixel column; 80. Isolation structure; 81. First isolation structure; 82. Second isolation structure; 83. Connector; 801. Metal layer; 802. Insulating layer; S1. Virtual rhombus; D. Vertex; O. Center point; X1. First direction; X2. Second direction. Detailed Implementation

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0027] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0028] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0029] It should be noted that "multiple" in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0030] Currently, organic light-emitting diode (OLED) display panels use fine masks for vapor deposition to prepare OLED light-emitting units. These masks are expensive, making the development of new products extremely costly. Furthermore, the bridging area of ​​the fine mask openings limits the effective area of ​​the pixel light-emitting region, hindering the improvement of the aperture ratio.

[0031] To address the aforementioned technical problems, this application provides a display panel, as shown in the reference. Figures 1 to 3 illustrate, Figure 1 This is a cross-sectional schematic diagram of a display panel in an embodiment of the present invention, in which the pixel definition layer is made of organic material. Figure 2 This is a cross-sectional schematic diagram of a display panel in an embodiment of the present invention, wherein the pixel definition layer is made of inorganic material; Figure 3 This is a schematic diagram of a display panel in an embodiment of the present invention.

[0032] In some embodiments, refer to Figures 1 to 3As shown, the display panel includes a driving substrate 10, a planarization layer 20, a pixel definition layer 30, an anode 40, sub-pixels 50, and an isolation structure 80: the planarization layer 20 is disposed on the driving substrate 10; the pixel definition layer 30 is disposed on the planarization layer 20 to form a pixel region 31, and the planarization layer 20 forms an anode via 21 in the radial direction of the pixel region; the anode 40 is disposed in the pixel region 31 and extends toward the anode via 21, and the anode 40 is electrically connected to the driving substrate 10 through the anode via 21; the sub-pixels 50 are disposed in the pixel region 31, and the sub-pixels 50 include a first sub-pixel 51, a second sub-pixel 52, and a third sub-pixel 53, which are arranged along a first direction X1 and a second direction X2; in the diagonal direction X3 between the first direction X1 and the second direction X2, the second sub-pixel 52 and the first sub-pixel 51 are spaced apart and staggered; and, the second sub-pixel 52 and the first sub-pixel 51 are arranged in a staggered manner. Three sub-pixels 53 are spaced apart and staggered; an isolation structure 80 is disposed on the pixel definition layer 30, and the isolation structure 80 protrudes from the side away from the driving substrate 10 to isolate the first sub-pixel 51, the second sub-pixel 52 and the third sub-pixel 53; in the second direction, two adjacent second sub-pixels 52 in the same pixel column form a pixel pair 60, and the anode via 21 of any second sub-pixel 52 in the pixel pair 60 is disposed on the side close to the other second sub-pixel 52. In the pixel pair 60, the isolation structure 80 includes two first isolation structures 81 and two second isolation structures 82. The two first isolation structures 81 are respectively disposed on the outer periphery of the two second sub-pixels 52, and the two first isolation structures 81 respectively form a connecting port 83 on the side close to the anode via 21. The two second isolation structures 82 connect the two first isolation structures 81 so that the connecting ports 83 of the two first isolation structures 81 are interconnected, and the anode via 21 is located between the two first isolation structures 81.

[0033] Therefore, the driving substrate 10 is used to drive the display panel. Specifically, the anode 40 is electrically connected to the driving substrate 10, and the driving substrate 10 drives the sub-pixels 50 to emit light. The first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 are arranged along the first and second directions, and are individually packaged through the isolation structure 80. In the second direction, any two second sub-pixels 52 in the same pixel column form a pixel pair 60. In the pixel pair 60, the anode via 21 of any second sub-pixel 52 is located on the side close to the other second sub-pixel 52, and there is no isolation structure 80 between the corresponding two anode vias 21. The anode via 21 is located between two second isolation structures 82, thereby connecting the two first isolation structures 81 by setting the second isolation structure 82. This design makes the second isolation structure 82 parallel to the second direction. In the vapor deposition process of the display panel, since the vapor deposition direction is perpendicular to the second direction, the blocking area of ​​the vapor deposition source by the second isolation structure 82 is reduced during vapor deposition, thereby increasing the spacing between the sub-pixels 50, and thus increasing the opening area of ​​the sub-pixels 50.

[0034] Specifically, during the evaporation of luminescent materials, the evaporation source forms a evaporation cloud along its long side (referred to as the Nozzle direction, hereinafter referred to as such). Because there is no limiting plate to restrict the angle, the evaporation angle (θ1) is relatively large. However, in the movement direction (referred to as the Scan direction, hereinafter referred to as such), the evaporation angle (θ2) can be controlled by the limiting plate. Since the evaporation angles θ1 and θ2 are different, the 'a' value affected in the Nozzle / Scan direction is different (due to uneven film thickness in the 'a' value region, it cannot be used for device light emission; the PDL opening must avoid this region). The pixel spacing (referred to as PDL-Gap) must be greater than 2(a+b), where b is half the width of the isolation structure 80. Currently, for the sake of pixel display effect and lifespan, OLED mobile phone products basically use diamond or diamond-like pixel arrangements, so the isolation structure 80 needs to form a separate partition structure around each pixel. Therefore, the OH circuit structure presents a diagonal line form on the pixel. Since the evaporation angle θ2 is restricted by the limiting plate and the second isolation structure 82 is set parallel to the second direction, the second isolation structure 82 is perpendicular to the Scan direction of the evaporation source. Under the same evaporation incident angle, more of the light-emitting layer and cathode of the sub-pixel 50 can be evaporated on the pixel definition layer 30, thereby reducing the a value to increase the spacing between pixels and thus improving the pixel aperture ratio.

[0035] In some embodiments, refer to Figure 1 and Figure 2 As shown, the driving substrate 10 includes a flexible substrate and a driving circuit. The flexible substrate can be a glass flexible substrate or an organic flexible substrate. The driving circuit can be a thin film transistor (TFT) circuit layer, which is used to drive the light-emitting layer of the OLED. Specifically, the TFT circuit layer includes multiple arrayed driving circuit units, each of which can include a TFT device and a capacitor. Each driving circuit unit corresponds to an anode 40 and an organic light-emitting layer. The TFT device is of the low-temperature polysilicon (LTPS) type or the metal-oxide-semiconductor (MOS) type, such as indium gallium zinc oxide (IGZO).

[0036] In some embodiments, the planarization layer 20 may be made of organic materials such as polyimide.

[0037] In some embodiments, the material of the pixel definition layer 30 can be an organic material or an inorganic material. (See reference...) Figure 1 As shown, the organic material can fill the anode via 21; refer to Figure 2As shown, inorganic materials can be grown according to the morphology of the anode via 21 to form a pixel definition layer 30 that matches the anode via 21. The pixel definition layer 30 extends along the anode via 21 and the planarization layer 20. The isolation structure 80 and the anode via 21 do not overlap in orthographic projection on the driving substrate 10, thereby staggering the isolation structure 80 and the anode via 21. This design enables the isolation structure 80 to have better stability.

[0038] In some embodiments, refer to Figure 1 and Figure 2 As shown, pixel definition layers 30 are spaced apart on planarization layer 20, and the pixel definition layers 30 protrude from the side of planarization layer 20 away from driving substrate 10 to form pixel region 31. Anode vias 21 are located in the area covered by pixel definition layers 30, and the aperture and shape of anode vias 21 can be selected according to actual conditions.

[0039] In some embodiments, refer to Figure 3 As shown, sub-pixel 50 includes sub-pixels of three colors: red, green, and blue. The first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 can each refer to any one of the three colors: red, green, or blue. For details, refer to... Figure 3 As shown, the first sub-pixel 51 is the red sub-pixel 50; the second sub-pixel 52 is the green sub-pixel 50; and the third sub-pixel 53 is the blue sub-pixel 50. The area of ​​the first sub-pixel 51 is larger than the area of ​​the second sub-pixel 52. Specifically, the larger hexagonal sub-pixel is the first sub-pixel 51, the smaller hexagonal sub-pixel is the third sub-pixel 53, and the quadrilateral sub-pixel is the second sub-pixel 52.

[0040] In some embodiments, refer to Figure 3 As shown, the first direction X1 is the horizontal direction of the display panel, and the second direction X2 is the vertical direction of the display panel. The diagonal direction X3 is any direction between the first direction X1 and the second direction X2. Specifically, the diagonal direction X3 is the direction that forms a 45° angle with the first direction X1.

[0041] In some embodiments, refer to Figure 3As shown, in the display panel, one adjacent first sub-pixel 51, two second sub-pixels 52, and one third sub-pixel 53 share the same center point O as the vertex D of the virtual rhombus S1. That is, the line connecting the center points O of the first sub-pixel 51, second sub-pixel 52, and third sub-pixel 53 forms a virtual rhombus S1, which is used to conveniently describe the positional and structural relationships between the various sub-pixels 50. In other embodiments, after arranging multiple first sub-pixels 51, multiple second sub-pixels 52, and multiple third sub-pixels 53, the line connecting their center points O can also form virtual hexagons, octagons, or other polygons. The corresponding diagonal direction X3 also has different tilt angles depending on the shape, selected according to the actual situation.

[0042] In some embodiments, refer to Figure 3 As shown, the diamond or diamond-like arrangement includes: in the first direction X1, second sub-pixels 52 are spaced apart to form a first pixel row, first sub-pixels 51 and third sub-pixels 53 are spaced apart and staggered to form a second pixel row, and the first pixel row and the second pixel row are spaced apart and staggered along the second direction X2; in the second direction X2, second sub-pixels 52 are spaced apart to form a first pixel column, first sub-pixels 51 and third sub-pixels 53 are spaced apart and staggered to form a second pixel column, and the first pixel column and the second pixel column are spaced apart and staggered along the first direction X1. This forms the aforementioned diamond arrangement structure, resulting in a display panel with a long service life and stable performance.

[0043] In some embodiments, refer to Figure 3 As shown, in the first direction X1, the Nth pixel row can be optionally set to consist entirely of second sub-pixels 52, and the first sub-pixels 51 and third sub-pixels 53 in the (N+1)th pixel row can be alternated, and then arranged according to the pattern of the Nth and (N+1)th pixel rows. In the second direction X2, the Mth pixel column can be optionally set to consist entirely of second sub-pixels 52, and the first sub-pixels 51 and third sub-pixels 53 in the (M+1)th pixel column can be alternated, and then arranged according to the pattern of the Mth and (M+1)th pixel columns. Thus, in the diagonal direction X3 between the first direction X1 and the second direction X2, the second sub-pixels 52 and the first sub-pixels 51 are alternately and alternately arranged; and the second sub-pixels 52 and the third sub-pixels 53 are alternately and alternately arranged.

[0044] In some embodiments, refer to Figure 3As shown, pixels are arranged in rows along the first direction X1 and in columns along the second direction X2. Any two second sub-pixels 52 in a pixel column form a pixel pair 60, that is, every two second sub-pixels 52 in a pixel column form a pixel pair 60. Each pixel column has multiple pixel pairs 60. In a pixel pair 60, the anode vias 21 corresponding to the two second sub-pixels 52 are close to each other. In adjacent pixel pairs 60, no anode vias 21 are provided between two adjacent second sub-pixels 52, and they are separated by an isolation structure 80.

[0045] In some embodiments, refer to Figure 3 As shown, the pixel column of the second sub-pixel 52 includes at least a first sub-pixel column 71 and a second sub-pixel column 72. Any two second sub-pixels 52 in the first sub-pixel column 71 form a pixel pair 60, which is the first pixel pair 61. Any two second sub-pixels 52 in the second sub-pixel column 72 form a pixel pair 60, which is the second pixel pair 62. The orthogonal projections of the anode vias 21 in the first pixel pair 61 and the anode vias 21 in the second pixel pair 62 are alternately arranged in the second direction X2. The pixel column of the second sub-pixel 52 may also include multiple other pixel columns; here, the first sub-pixel column 71 and the second sub-pixel column 72 are used as examples. If the Mth pixel column is defined as the first sub-pixel column 71, then the (M+2)th pixel column is the second sub-pixel column 72. If the anode via 21 in the second sub-pixel column 72 is located between the N and N+2 pixel rows, then the anode via 21 in the first sub-pixel column 71 is located between the N+2 and N+4 pixel rows. Thus, the anode via 21 in the first pixel pair 61 and the anode via 21 in the second pixel pair 62 are alternately projected in the second direction X2.

[0046] In some embodiments, refer to Figure 4As shown, the anode via 21 corresponding to the first sub-pixel 51 is the first via 211, the anode via 21 corresponding to the second sub-pixel 52 is the second via 212, and the anode via 21 corresponding to the third sub-pixel 53 is the third via 213. The first via 211 electrically connects the first sub-pixel 51 to the driving substrate 10 to drive the first sub-pixel 51 to emit light; the second via 212 electrically connects the second sub-pixel 52 to the driving substrate 10 to drive the second sub-pixel 52 to emit light; and the third via 213 electrically connects the third sub-pixel 53 to the driving substrate 10 to drive the third sub-pixel 53 to emit light. In the first direction X1, the first sub-pixel 51 forms a first plane 511 on the side near and away from the second via 212, and the third sub-pixel 53 forms a third plane 531 on the side near and away from the second via 212. The first via 211 is located outside the first plane 511 of the first sub-pixel 51 away from the second via 212; the third via 213 is located outside the third plane 531 of the third sub-pixel 53 away from the second via 212. By chamfering both the first sub-pixel 51 and the third sub-pixel 53, the corresponding anode via 211 can be protected, and the waste of pixel openings can be further reduced.

[0047] In some embodiments, refer to Figure 4 As shown, the second sub-pixel 52 has a quadrilateral shape, while the first sub-pixel 51 and the third sub-pixel 53 have hexagonal shapes.

[0048] In some embodiments, refer to Figure 3 and Figure 4 As shown, the display panel also includes an isolation structure 80, which is disposed between the first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 to isolate them. The isolation structure 80 is a "mushroom-top" overhanging structure that acts as a shield during vapor deposition. Specifically, the isolation structure 80 includes a metal layer 801 and an insulating layer 802. The metal layer 801 is disposed on the pixel definition layer 30, and the insulating layer 802 is disposed on the metal layer 801. The width of the insulating layer 802 is greater than the width of the metal layer 801.

[0049] In some embodiments, refer to Figure 6 and Figure 7 As shown, Figure 6 for Figure 5 A schematic diagram of the cross-section of AA in the middle isolation structure 80. Figure 7 for Figure 5 A schematic diagram of the cross-section of BB in the middle isolation structure 80. Figure 6 This is a schematic diagram of a cross-section perpendicular to the oblique direction X3. Figure 7 This is a schematic diagram of a cross-section parallel to the first direction X1. As can be seen from the two diagrams, due to the use of a diamond-shaped arrangement structure, Figure 6The width of the central isolation structure 80 is E. Figure 7 The width of the central isolation structure 80 is F, where E is less than F.

[0050] In some embodiments, refer to Figure 4 As shown, pixel pair 60, first sub-pixel 51, and second sub-pixel 52 are located at vertices D of virtual rhombus S1, and the second sub-pixel 52, first sub-pixel 51, and third sub-pixel 53 share the same center point O as vertex D of virtual rhombus S1. A virtual rhombus S1 has one first sub-pixel 51, two second sub-pixels 52, and one third sub-pixel 53, with the center point O of the first sub-pixel 51, second sub-pixel 52, and third sub-pixel 53 being the intersection of diagonals. The center points O of the first sub-pixel 51, second sub-pixel 52, and third sub-pixel 53 are located at different vertices D of virtual rhombus S1. This design reduces the aperture ratio of the first sub-pixel 51, second sub-pixel 52, and third sub-pixel 53, thereby improving the image display quality of the monitor.

[0051] In some embodiments, refer to Figure 4 As shown, within the virtual rhombus S1, the first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 share the second isolation structure 82. Multiple identical virtual rhombuses S1 can be divided in the display panel, and within each virtual rhombus S1, the first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 can share the second isolation structure 82, thereby improving the uniformity of the display.

[0052] In this application, on the one hand, in pixel pair 60, the anode vias 21 corresponding to the two second sub-pixels 52 are close to each other, and there is no isolation structure 80 between the two anode vias 21 to connect the two second sub-pixels 52. Since there is no isolation structure 80 between the second sub-pixels 52 in pixel pair 60 to connect them, and the anode vias 21 are located at the position where the two second sub-pixels 52 are connected, the waste of pixel area is reduced, the display effect is guaranteed, and the maximum pixel aperture ratio is achieved. On the other hand, the second isolation structure 82 connects the edges of the corresponding first isolation structure 81 to connect the two first isolation structures 81, and there is no need to separate the two anode vias 21 with an isolation structure 80; at the same time, the second isolation structure 82 separating the two sides of the anode via 21 is a straight isolation structure 80, and the cathode overlap distance here is relatively long. Within the virtual rhombus S1, the first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 can all share the second isolation structure 82, thereby improving the uniformity of the display.

[0053] This application also provides a display device, including the display panel described above.

[0054] In this application, unless otherwise expressly specified and limited, the terms "set up (provided)" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0055] In the description of this specification, references to terms such as "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0056] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A display panel, characterized by, The display panel comprises: a driving substrate; a planarization layer disposed on the driving substrate; a pixel definition layer disposed on the planarization layer to form a pixel region, and the planarization layer forms an anode via hole in a radial direction of the pixel region; an anode disposed in the pixel region and extending to the anode via hole, and the anode is electrically connected to the driving substrate through the anode via hole; a sub-pixel disposed in the pixel region, the sub-pixel comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged along a first direction and a second direction; an isolation structure disposed on the pixel definition layer, the isolation structure protruding towards a side away from the driving substrate, and the isolation structure is used for isolating the first sub-pixel, the second sub-pixel, and the third sub-pixel; in the second direction, two adjacent second sub-pixels in the same pixel column form a pixel pair, the anode via hole of any one of the second sub-pixels in the pixel pair is disposed on a side close to the other second sub-pixel, in the pixel pair, the isolation structure comprises two first isolation structures and two second isolation structures, the two first isolation structures are respectively disposed on the outer circumferential sides of the two second sub-pixels, and the two first isolation structures respectively form a communication port on a side close to the anode via hole, the two second isolation structures connect the two first isolation structures to make the communication ports of the two first isolation structures communicate with each other, and the anode via hole is located between the two first isolation structures.

2. The display panel of claim 1, wherein in the first direction, the second sub-pixels are arranged at intervals to form a first pixel row, and the first sub-pixels and the third sub-pixels are arranged at intervals and staggered to form a second pixel row, and the first pixel row and the second pixel row are arranged at intervals and staggered along the second direction; in the second direction, the second sub-pixels are arranged at intervals to form a first pixel column, and the first sub-pixels and the third sub-pixels are arranged at intervals and staggered to form a second pixel column, and the first pixel column and the second pixel column are arranged at intervals and staggered along the first direction.

3. The display panel of claim 1, wherein the pixel column of the second sub-pixel comprises at least a first sub-pixel column and a second sub-pixel column, a pixel pair formed by two adjacent second sub-pixels in the first sub-pixel column is a first pixel pair, a pixel pair formed by two adjacent second sub-pixels in the second sub-pixel column is a second pixel pair, and the orthogonal projections of the anode via holes in the first pixel pair and the second pixel pair in the second direction are staggered.

4. The display panel of claim 1, wherein, The anode via corresponding to the first sub-pixel is a first via, the anode via corresponding to the second sub-pixel is a second via, and the anode via corresponding to the third sub-pixel is a third via; in the first direction, the first sub-pixel forms a first plane on a side close to the second via and a side away from the second via, and the third sub-pixel forms a third plane on a side close to the second via and a side away from the second via; the first via is arranged outside the first plane of the first sub-pixel away from the second via; and the third via is arranged outside the third plane of the third sub-pixel away from the second via.

5. The display panel of claim 4, wherein, The first sub-pixel and the third sub-pixel are hexagons, and the second sub-pixel is a quadrilateral.

6. The display panel of claim 1, wherein, The pixel pair, the first sub-pixel, and the second sub-pixel are located at vertices of a virtual rhombus, and the second sub-pixel, the first sub-pixel, and the third sub-pixel have the same center point as the vertices of the virtual rhombus.

7. The display panel of claim 6, wherein, The first sub-pixel, the second sub-pixel, and the third sub-pixel share the second isolation structure within the virtual rhombus.

8. The display panel of claim 1, wherein, The material of the pixel definition layer is inorganic material, the pixel definition layer is arranged along the anode via and the planarization layer, and the orthogonal projection of the isolation structure and the anode via on the driving substrate does not coincide.

9. The display panel of claim 1, wherein, The isolation structure includes a metal layer and an insulating layer, the metal layer is arranged on the pixel definition layer, and the insulating layer is arranged on the metal layer, and the width of the insulating layer is greater than the width of the metal layer.

10. A display device, characterized by comprising: The display panel includes any one of claims 1 to 9. The display panel includes any one of claims 1 to 9.

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