Semiconductor substrate and method for manufacturing semiconductor substrate

Abstract

The invention provides a semiconductor substrate capable of preventing generation of interface resistance at a bonding interface and a method for manufacturing the semiconductor substrate. This method for manufacturing a semiconductor substrate is provided with: a damaged layer formation step in which a damaged layer is formed on at least one of a first surface to be bonded of a first semiconductor substrate and a second surface to be bonded of a second semiconductor substrate; a specific element introduction step for introducing a specific element to the first bonding target surface and / or the second bonding target surface; a bonding step in which the first bonding target surface and the second bonding target surface are bonded to form a bonded semiconductor substrate having a bonding interface; and a heat treatment step in which the bonded semiconductor substrate is heat-treated, the heat treatment step being a step in which a specific element introduced into the first semiconductor substrate and / or the second semiconductor substrate is moved toward the damaged layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor substrate and a method for manufacturing a semiconductor substrate, and more particularly to a semiconductor substrate and a method for manufacturing a semiconductor substrate capable of preventing the generation of interface resistance at a bonding interface in a bonded semiconductor substrate in which two or more substrates are bonded via a bonding interface by lamination. Background Art

[0002] As an example of manufacturing a bonded semiconductor substrate, a technique of bonding a SiC single crystal to a SiC polycrystal is known. In addition, as a related technique, for example, the technique disclosed in Patent Document 1 is known.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 6387375 Summary of the invention

[0006] Problems to be solved by the invention

[0007] However, if SiC single crystal and SiC polycrystal are directly bonded, the resistance at the bonding interface (interface resistance) may become high, which may affect the device characteristics when a device is manufactured in which a current path is formed across the bonding interface, and is therefore not preferable.

[0008] Therefore, in order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor substrate and a method for manufacturing the semiconductor substrate which can prevent the generation of interface resistance at a bonding interface.

[0009] Means used to solve problems

[0010] In order to solve the above-mentioned problems, a method for manufacturing a semiconductor substrate of the present invention is a method for manufacturing a semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate, wherein the method for manufacturing a semiconductor substrate includes: a damaged layer forming step of forming a damaged layer on at least one of a first bonding target surface of the first semiconductor substrate and a second bonding target surface of the second semiconductor substrate; a specific element introducing step of introducing a specific element into at least one of the first bonding target surface and the second bonding target surface; a bonding step of bonding the first bonding target surface and the second bonding target surface after the damaged layer forming step and after the specific element introducing step to form a bonded semiconductor substrate having a bonding interface; and a heat treatment step of heat-treating the bonded semiconductor substrate, wherein the heat treatment step is a step of moving the specific element introduced into at least one of the first semiconductor substrate and the second semiconductor substrate to the damaged layer of the first semiconductor substrate or the damaged layer of the second semiconductor substrate, and when the first semiconductor substrate and the second semiconductor substrate are N-type semiconductors, a pentavalent element is used as the specific element, and when the first semiconductor substrate and the second semiconductor substrate are P-type semiconductors, a trivalent element is used as the specific element.

[0011] Alternatively, the first semiconductor substrate and the second semiconductor substrate may be any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond.

[0012] The damaged layer forming step may be performed after the damaged layer forming step, or the damaged layer forming step may be performed after the damaged layer introducing step.

[0013] It is also possible that at least any one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B) and aluminum (Al) exists in the damaged layer.

[0014] The damaged layer forming step may be a step of forming the damaged layer by performing at least one of ion implantation, neutral element implantation, and plasma irradiation on at least one of the first bonding target surface and the second bonding target surface.

[0015] The specific element introduction step may be a step of introducing the specific element by performing at least one of ion implantation, neutral element implantation, plasma doping, and thermal diffusion on at least one of the first bonding target surface and the second bonding target surface.

[0016] The specific element may be at least any one of nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

[0017] The heat treatment temperature in the heat treatment step may be 1100°C to 2200°C.

[0018] The method for manufacturing a semiconductor substrate of the present invention may include an irradiation step of irradiating at least one of the first bonding target surface and the second bonding target surface with an argon beam after the damaged layer forming step, after the specific element introducing step, and before the bonding step.

[0019] Alternatively, in the semiconductor substrate manufacturing method of the present invention, the first semiconductor substrate is a SiC polycrystalline substrate and the second semiconductor substrate is a SiC single crystal substrate, the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate, the first semiconductor substrate is a gallium nitride (GaN) substrate and the second semiconductor substrate is a gallium nitride (GaN) substrate, the first semiconductor substrate is a gallium oxide (Ga2O3) substrate and the second semiconductor substrate is a gallium oxide (Ga2O3) substrate, or the first semiconductor substrate is a diamond substrate and the second semiconductor substrate is a diamond substrate, and the semiconductor substrate manufacturing method includes a hydrogen ion implantation step, and hydrogen ions are implanted into the second bonding object surface before the damage layer formation step and before the specific element introduction step.

[0020] The method for manufacturing a semiconductor substrate of the present invention may include a peeling step of peeling the second semiconductor substrate with the microbubble layer as a peeling surface after the bonding step and before the heat treatment step.

[0021] In addition, in order to solve the above-mentioned problem, the semiconductor substrate of the present invention is a semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate joined to the first semiconductor substrate via a bonding interface, wherein the concentration of a specific element in the semiconductor substrate is highest in at least any one of the bonding interface and the region from the bonding interface to about 15 nm.

[0022] Alternatively, the concentration of the specific element at the bonding interface may be 1.0×10 19 atoms / cm 3 ~2.0×10 20 atoms / cm 3 .

[0023] The specific element in the semiconductor substrate may have a high concentration in at least any one of the bonding interface and a region extending from the bonding interface to approximately 15 nm, and a region 40 nm to 60 nm away from the bonding interface.

[0024] Alternatively, the first semiconductor substrate and the second semiconductor substrate may be any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond.

[0025] It is also possible that the semiconductor substrate of the present invention has a damaged layer in at least any one of the bonding interface and the region from the bonding interface to about 15 nm, and it is also possible that at least any one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B) and aluminum (Al) exists in the damaged layer.

[0026] The specific element may be at least any one of nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

[0027] Alternatively, the semiconductor substrate of the present invention is the following semiconductor substrate: the first semiconductor substrate is a SiC polycrystalline substrate, the second semiconductor substrate is a SiC single crystal substrate, and the phosphorus concentration at the bonding interface is 1.0×10 19 atoms / cm 3 ~2.0×10 20 atoms / cm 3 .

[0028] Effects of the Invention

[0029] According to the present invention, it is possible to provide a semiconductor substrate and a method for manufacturing the semiconductor substrate which are capable of preventing generation of interface resistance at a bonding interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to the present invention.

[0031] Figure 2 It is a perspective view showing an example of the semiconductor substrate of the present invention.

[0032] Figure 3 It is a schematic side view of the second semiconductor substrate in the present invention.

[0033] Figure 4 It is a schematic side view of the second semiconductor substrate in the present invention.

[0034] Figure 5 It is an explanatory diagram showing an example of the irradiation step in the present invention.

[0035] Figure 6 FIG. 1 is a schematic side view showing an example of a semiconductor substrate of the present invention.

[0036] Figure 7 FIG. 1 is a schematic side view showing an example of a semiconductor substrate of the present invention.

[0037] Figure 8 It is a graph showing the phosphorus concentration distribution at and near the bonding interface after the peeling step and after the heat treatment step.

[0038] Fig. 9 It is a diagram showing a conduction mechanism model.

[0039] Fig.10 This is a cross-sectional view of a TEG for measuring specific on-resistance.

[0040] Fig.11 This is a diagram for verifying the dependence of the on-resistance on phosphorus ion implantation, among the diagrams for explaining the results of verifying whether or not interface resistance is generated at the bonding interface.

[0041] Fig.12 This is a diagram showing the result of the current-voltage characteristic with phosphorus ion implantation (Example), among the diagrams explaining the result of verifying whether or not interface resistance is generated at the bonding interface.

[0042] Fig.13 This is a graph showing the result of current-voltage characteristics of a case without phosphorus ion implantation (comparative example), among the graphs explaining the result of verifying whether or not interface resistance is generated at the bonding interface. DETAILED DESCRIPTION

[0043] This specification discloses a semiconductor substrate and a method for manufacturing the semiconductor substrate. The semiconductor substrate is characterized in that a surface of a semiconductor layer is bonded to a surface of another semiconductor layer to generate a semiconductor substrate having a bonding interface, and a specific element of the semiconductor layer is moved to a damaged layer by subsequent heat treatment.

[0044] If semiconductor substrates are directly bonded to each other, a potential barrier is generated due to band offset and interface charges, so the interface resistance becomes high. Therefore, a specific element of n-type dopant is introduced near the junction to allow electrons to tunnel through the potential barrier, thereby suppressing the interface resistance.

[0045] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0046] [Semiconductor substrate]

[0047] The semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded to each other via a bonding interface.

[0048] <Structure of semiconductor substrate>

[0049] Figure 2 1 is a perspective view showing an example of a semiconductor substrate of the present invention. The semiconductor substrate 10 of the present invention is a bonded semiconductor substrate, for example, formed in a substantially disk shape having an orientation flat surface. The semiconductor substrate 10 includes a support substrate 11 as an example of a first semiconductor substrate, and a single crystal substrate 13 as an example of a second semiconductor substrate, and the single crystal substrate 13 is bonded to the support substrate 11.

[0050] The single crystal substrate 13 may be, for example, any one of a compound semiconductor (e.g., silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3)), a single element semiconductor (e.g., silicon (Si), carbon (C)), and diamond. These elements are semiconductor materials that can be used to make semiconductor devices.

[0051] Various materials can be used for the support substrate 11. The support substrate 11 preferably has resistance to various thermal processes applied to the single crystal substrate 13. In addition, the support substrate 11 is preferably a material with a small difference in thermal expansion coefficient from the single crystal substrate 13. For example, the support substrate 11 can use silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3), sapphire (Al2O3), quartz (SiO2), and diamond.

[0052] When polycrystalline SiC is used as the support substrate 11, SiC crystals of various polytypes and plane orientations may be mixed. Polycrystalline SiC of various polytypes and plane orientations can be manufactured without strict temperature control, so the cost of manufacturing the support substrate 11 can be reduced.

[0053] The thickness TT1 of the support substrate 11 may be determined so as to obtain mechanical strength that can withstand processing in subsequent steps. For example, when the diameter of the support substrate 11 is 150 (mm), the thickness TT1 may be approximately 350 (μm).

[0054] Figure 8 Graphs showing the distribution of phosphorus concentration at the bonding interface and near the bonding interface after the stripping process and the heat treatment process. The details of these processes will be described later. Figure 8The X-axis takes 0 as the bonding interface between the supporting substrate 11 and the single crystal substrate 13 of the semiconductor substrate 10, and the right side of the dotted line marked in the up-down direction is the supporting substrate 11, and the distance from the bonding interface, i.e., 0, is expressed as the depth of the supporting substrate 11 from the bonding interface. Polycrystalline SiC is used as the supporting substrate 11, and 4H-SiC is used as the single crystal substrate 13. In addition, the left side of the dotted line is the single crystal substrate 13, and similarly to the case of the supporting substrate 11, the distance from the bonding interface, i.e., 0, is expressed as the depth of the single crystal substrate 13 from the bonding interface. In addition, the Y-axis represents the concentration of phosphorus as an example of a specific element. That is, in Figure 8 , it is shown how much phosphorus exists in the bonded semiconductor substrate and at what depth from the bonded interface.

[0055] Figure 8 The solid line in the graph shows the phosphorus concentration in the semiconductor substrate of an example of the present invention. According to the graph, the phosphorus concentration is highest in the region 15 nm away from the bonding interface, and the phosphorus concentration at the bonding interface is 8×10 19 / cm 3 The phosphorus concentration is high in a region 15 nm away from the bonding interface and in a region 50 nm away from the bonding interface.

[0056] Figure 11 to Figure 13 This figure explains the results of verifying whether or not interface resistance is generated at the bonding interface. Figure 11 to Figure 13 In order to show the use of Figure 8 The result of the straight line curve graph of the semiconductor substrate 10 used to measure the on-resistance is equivalent to the result of the "with P ion implantation" case. The "without P ion implantation" case is the result of measuring the on-resistance using a semiconductor substrate of an existing product that has not undergone the specific element introduction process described later. Comparing the two results, it can be seen that the resistance at the bonding interface confirmed in the "without P ion implantation" case is not detected in the "with P ion implantation" case, which can prevent the generation of interface resistance at the bonding interface.

[0057] according to Figure 8 , Figure 11 to Figure 13 As a result, the semiconductor substrate 10 does not generate interface resistance at the bonding interface as follows: the phosphorus concentration is highest in the region 15 nm away from the bonding interface, and the phosphorus concentration at the bonding interface is 8×10 19 / cm 3 The phosphorus concentration is high in a region 15 nm away from the bonding interface and in a region 50 nm away from the bonding interface.

[0058] also, Figure 8 , Figure 11 to Figure 13This is merely the result when phosphorus is used as a specific element for a predetermined semiconductor substrate 10 , and the semiconductor substrate of the present invention is not limited to this result.

[0059] That is, the semiconductor substrate of the present invention is a semiconductor substrate in which the concentration of a specific element is the highest in at least any one of the bonding interface and the region from the bonding interface to about 15 nm. By making the concentration of the specific element the highest in the region close to the bonding interface, the generation of interface resistance at the bonding interface can be prevented. When the concentration of the specific element is the highest in a region farther than about 15 nm from the bonding interface, the influence of the specific element on the bonding interface is small, so there is a risk that the generation of interface resistance at the bonding interface cannot be prevented.

[0060] In the semiconductor substrate of the present invention, the concentration of the specific element at the bonding interface is preferably 1.0×10 19 atoms / cm 3 ~2.0×10 20 atoms / cm 3 At this concentration less than 1.0×10 19 atoms / cm 3 In the case of 2.0×10 20 atoms / cm 3 , then the generation of interface resistance at the bonding interface can be fully prevented.

[0061] In the semiconductor substrate of the present invention, the specific element may have a high concentration in at least any one of the bonding interface and the region from the bonding interface to about 15 nm, and a region 40 nm to 60 nm away from the bonding interface.

[0062] More specifically, based on Figure 8 , Figure 11 to Figure 13 The results shown in the figure show that the semiconductor substrates of the present invention are as follows: the first semiconductor substrate is a SiC polycrystalline substrate, the second semiconductor substrate is a SiC single crystal substrate, and the phosphorus concentration at the bonding interface is 1.0×10 19 atoms / cm 3 ~2.0×10 20 atoms / cm 3 , no resistance was detected at the bonding interface.

[0063] In addition, the specific element is not limited to phosphorus, and can be a trivalent element or a pentavalent element used as a dopant, for example, at least one of nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

[0064] In addition, the semiconductor substrate of the present invention sometimes has a damaged layer described below in at least one of the bonding interface and the region from the bonding interface to about 15 nm, and at least one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B) and aluminum (Al) exists in the damaged layer. In addition, the presence or absence of the damaged layer in the semiconductor substrate can be analyzed by a transmission electron microscope (TEM, Transmission Electron Microscope), and the analysis of the damaged layer can be performed by confirming the crystallinity (the degree of amorphization, the presence or absence of crystal defects) using TEM.

[0065] [Method for manufacturing semiconductor substrate]

[0066] Next, as an example of a method for manufacturing a semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate of the present invention, a method for manufacturing a semiconductor substrate 10 in which a supporting substrate 11 as the first semiconductor substrate is polycrystalline SiC and a single crystal substrate 13 as the second semiconductor substrate is single crystal 4H-SiC is described. Figure 1 The flowchart and the like shown in the figure explain the case where the semiconductor substrate 10 is manufactured using the lift-off technique of the single crystal substrate 13 by ablation of hydrogen atoms.

[0067] First, the supporting substrate 11 and the single crystal substrate 13 are prepared. As the supporting substrate 11 and the single crystal substrate 13, substrates whose surfaces to be bonded are flattened can be obtained. The flattening can be performed by grinding, cutting, or by CMP.

[0068] <Hydrogen ion implantation process (step S0)>

[0069] exist Figure 1 In step S0, a hydrogen ion implantation process is performed to implant hydrogen ions from the bonding target surface 13a of the single crystal substrate 13. When hydrogen ions are implanted into the single crystal substrate 13, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. Figure 3 As shown in the schematic side view of FIG. 1 , the hydrogen implantation layer 15 indicated by the dotted line is formed at a predetermined depth from the bonding target surface 13 a. For example, the hydrogen implantation layer 15 is formed at a depth of about 0.6 μm from the bonding target surface 13 a.

[0070] In addition, the hydrogen ion implantation process is not a necessary process in the present invention, and can also be obtained by purchasing a substrate after hydrogen ion implantation, and then implementing the present invention. For example, it is a process that can be adopted when the first semiconductor substrate is a SiC polycrystalline substrate and the second semiconductor substrate is a SiC single crystal substrate, or the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate. In addition, the hydrogen ion implantation process is a process that can be performed before the damage layer formation process described later and before the specific element introduction process, and can also be performed after the damage layer formation process and after the specific element introduction process.

[0071] <Damage layer forming step (step S1)>

[0072] This step is a step of forming a damaged layer on at least one of the first bonding target surface of the first semiconductor substrate and the second bonding target surface of the second semiconductor substrate. That is, it is a step of forming a damaged layer on the bonding target surface 11a or the bonding target surface 13a, and it is also possible to form a damaged layer on both the bonding target surface 11a and the bonding target surface 13a.

[0073] exist Figure 1 In step S1, a damaged layer is formed on the bonding target surface 13a of the single crystal substrate 13. The damaged layer can be any layer whose crystal structure has changed. Here, the "layer whose crystal structure has changed" includes various forms. For example, it can be a layer whose crystal structure has changed due to the generation of a large number of crystal defects.

[0074] In addition, the method of "a layer having a changed crystal structure" includes a method of changing the crystal structure itself to a structure different from that before the introduction of a specific element. In addition, it includes a method of making the single crystal substrate 13 amorphous. In addition, it includes a method of forming a compound other than SiC. In addition, it includes a method of precipitating a certain element. In addition, these methods are examples. Methods other than these are not excluded.

[0075] In the formation of the damaged layer, ion implantation using an ion implanter is preferably used. By using an ion implanter to implant ions from the surface of the bonding object surface 13a to the inside, the damaged layer can be effectively formed. In addition, in the ion implanter, the depth of implantation can be easily controlled by the acceleration voltage, dose, etc. The elements of the implanted ions can be, for example, silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

[0076] As an example of an embodiment of the present invention, argon (Ar) is used as an element of ions for forming a damaged layer. Specifically, a single crystal substrate 13 is set in an ion implanter, and argon (Ar) is implanted into a surface 13a of the single crystal substrate 13 by ion implantation. The conditions for the ion implantation are, for example, a dose of 10 14 ~10 16 atoms / cm 2 , acceleration voltage 0.1 to 70 kV. During ion implantation, the ion concentration can also be controlled to be the highest on the surface of the single crystal substrate 13. After ion implantation, Figure 4 As shown in the schematic diagram of FIG. 1 , a damaged layer 12 is formed on the surface of a single crystal substrate 13. When Ar is implanted by ion implantation, the crystallinity is destroyed and changes to amorphous. This change can be confirmed by TEM (transmission electron microscope).

[0077] By forming such a damaged layer, as described later, a specific element can easily move within the substrate during a heat treatment step.

[0078] <Specific element introduction step (step S2)>

[0079] This step is a step of introducing a specific element into at least one of the first bonding target surface and the second bonding target surface, that is, a step of introducing a specific element into the bonding target surface 11a or the bonding target surface 13a, or a step of introducing a specific element into both the bonding target surface 11a and the bonding target surface 13a.

[0080] exist Figure 1 In step S2, a specific element introduction process is performed. When the substrate is SiC, the specific element is preferably an element that can bond with Si and C. The following describes the case where phosphorus (P) is used as the specific element in this embodiment. Phosphorus (P) is introduced from the surface 13a of the single crystal substrate 13 to the deep region including the damaged layer 12 by ion implantation. Thus, as Figure 4 As shown in the schematic diagram of FIG. 1 , a doped layer 13 b is formed on the surface layer of the single crystal substrate 13 .

[0081] When the first semiconductor substrate and the second semiconductor substrate are N-type semiconductors, a pentavalent element is used as the specific element, and when the first semiconductor substrate and the second semiconductor substrate are P-type semiconductors, a trivalent element is used as the specific element.

[0082] <Irradiation process (step S3)>

[0083] This step is a step of irradiating at least one of the first joining target surface and the second joining target surface with an argon beam after the damaged layer forming step, after the specific element introducing step, and before the joining step. That is, it is a step of irradiating the joining target surface 11a or the joining target surface 13a with an argon beam, and it is also possible to irradiate both the joining target surface 11a and the joining target surface 13a with an argon beam.

[0084] exist Figure 1 In step S3, an irradiation process is performed. Figure 5 As shown, the single crystal substrate 13 and the supporting substrate 11 are placed in the chamber 101. Next, the single crystal substrate 13 and the supporting substrate 11 are aligned relative to each other. The alignment is performed so that the two substrates can contact each other in a correct positional relationship in the bonding process described later. Next, the chamber 101 is made into a vacuum state. The vacuum degree in the chamber 101 can be, for example, 1×10 -4 ~1×10 -6 Pa around.

[0085] Next, a fast atom bombardment gun (FAB gun) 102 is used to irradiate the bonding target surface 11a of the supporting substrate 11 and the bonding target surface 13a of the single crystal substrate 13 with a neutral element beam of argon (Ar). The neutral element beam of argon (Ar) is uniformly irradiated to the entire surface of the bonding target surface 11a and the entire surface of the bonding target surface 13a. As a result, the oxide film and adsorption layer of the bonding target surface 11a and the bonding target surface 13a can be removed to expose the bonding bond. The state in which the oxide film and adsorption layer are removed to expose the bonding bond is called an active state. In addition, since the irradiation process is a process in a vacuum, the bonding target surface 11a and the bonding target surface 13a can remain in an active state without being oxidized or the like.

[0086] In addition, the irradiation process is not a necessary process, and it can be omitted as long as the two substrates can be bonded by the bonding process described later to form a bonded semiconductor substrate without problems. The irradiation process is a process of removing the oxide and adsorption layer on the surface by sputtering by making atoms or molecules collide with the surface, but it can be considered to replace this process with a process of using reactive gas to chemically react with the contaminants on the surface and remove them by etching. In addition, if it is an adsorbate that is easy to sublimate, it can be removed by sublimation by simply applying heat or light. Instead of the irradiation process, these processes can remove the oxide film and adsorption layer on the bonding object surface to expose the bonding bond.

[0087] <Joining process (step S4)>

[0088] This step is a step of bonding the first bonding target surface and the second bonding target surface to form a bonded semiconductor substrate having a bonding interface after the damaged layer forming step and the specific element introducing step.

[0089] exist Figure 1 In step S4, a bonding process is performed. In the bonding process, the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 are brought into contact in a vacuum in the chamber 101. The bonding bonds existing in the active state of the bonding target surface 11a and the bonding target surface 13a are bonded to each other, so that the support substrate 11 and the single crystal substrate 13 can be bonded. Figure 6 As shown in the schematic diagram of , a structure in which a supporting substrate 11 and a single crystal substrate 13 are bonded together is formed.

[0090] <Peeling process (step S5)>

[0091] This step is a step of applying heat during a peeling step after the bonding step and before the heat treatment step to form a microbubble layer on the hydrogen implantation layer 15, and peeling the second semiconductor substrate with the microbubble layer as the peeling surface. That is, the single crystal substrate 13 is peeled with the hydrogen implantation layer 15 on which the microbubble layer is formed being located on the single crystal substrate 13 as the peeling surface.

[0092] exist Figure 1 In step S5, a stripping process is performed. Specifically, the supporting substrate 11 and the single crystal substrate 13 bonded to each other are heated to about 800°C or above. The stripping atmosphere can be at least one of an inert gas such as argon (Ar), nitrogen (N), or a vacuum atmosphere. The stripping can be performed using rapid thermal annealing (RTA) or a furnace. In this way, the single crystal substrate 13 can be separated at the hydrogen injection layer 15. Therefore, as Figure 7 As shown in the schematic diagram of FIG. 1 , a structure can be formed in which a thin single crystal substrate 13 having a thickness of, for example, 0.6 μm is bonded to a supporting substrate 11 via a doping layer 13 b .

[0093] <Heat treatment process (step S6)>

[0094] This step is a step of heat-treating the bonded semiconductor substrates, and is a step of causing the specific element introduced into the first semiconductor substrate or the second semiconductor substrate to migrate to the damaged layer of the first semiconductor substrate or the damaged layer of the second semiconductor substrate.

[0095] exist Figure 1In step S6, a heat treatment process is performed. In the heat treatment process, the supporting substrate 11, the doping layer 13b and the single crystal substrate 13 are heat treated. The heat treatment temperature is preferably a temperature that activates the introduced phosphorus, and can be heated to 1100°C to 2200°C (preferably around 1700°C). The atmosphere for the heat treatment can be at least one of an atmosphere of an inert gas such as argon (Ar), nitrogen (N), or a vacuum. The heat treatment process can be performed in a furnace after the stripping process. As a result, the phosphorus present in the doping layer 13b moves to the damaged layer 12 near the bonding interface between the supporting substrate 11 and the single crystal substrate 13.

[0096] <Migration of Phosphorus to the Damaged Layer>

[0097] use Figure 8 The following describes a case where phosphorus present in the doping layer 13b is moved to the damaged layer 12 near the bonding interface during the heat treatment process of step S6. The measurement substrate is a 4H-SiC single crystal substrate 13 and a polycrystalline SiC support substrate 11 bonded by the bonding method described in this specification. The phosphorus concentration distribution after the peeling process of step S5 and before the heat treatment process of step S6 and the phosphorus concentration distribution after the heat treatment process of step S6 are measured by SIMS analysis. Figure 8 The vertical axis is the phosphorus concentration (atoms / cm 3 ). The horizontal axis represents the depth (nm) near the interface between the single crystal substrate 13 and the supporting substrate 11 , and the depth 0 nm represents the bonding interface between the supporting substrate 11 and the single crystal substrate 13 .

[0098] By comparing the peak positions of phosphorus concentration after the stripping process in step S5 and after the heat treatment process in step S6, it can be seen that phosphorus obviously moves to the vicinity of the bonding interface through the 1700°C heat treatment in step S6. As a result, there is one concentration peak before the heat treatment process, but there are two concentration peaks in the damaged layer 12 and the doped layer 13b near the bonding interface.

[0099] Figure 8 The circle in the figure represents the phosphorus concentration distribution in the single crystal substrate 13 which is not the damaged layer 12. According to the concentration distribution, since no change in the phosphorus concentration distribution before and after the heat treatment process is observed, it can be seen that even the heat treatment at 1700°C does not cause phosphorus to diffuse away from the bonding interface in the single crystal substrate 13, and phosphorus does not move to the vicinity of the bonding interface by a simple thermal diffusion phenomenon caused by the heating of the substrate. In other words, it is believed that phosphorus moves to the damaged layer 12 near the bonding interface by the heat treatment process and is gettered.

[0100] Without performing the formation of a damaged layer, the introduction of a specific element, and the heat treatment process, an energy barrier is formed at the bonding interface between the single crystal substrate 13 and the supporting substrate 11. However, by performing the formation of a damaged layer, the introduction of a specific element, and the heat treatment process, phosphorus of the N-type dopant moves to the vicinity of the bonding interface, thereby reducing the width of the energy barrier. As a result, a tunnel effect can be obtained, and thus the interface resistance of the bonding interface can be reduced.

[0101] The effects obtained by the technology disclosed in this specification are described from another aspect. The reasons for the generation of non-ohmic electrical characteristics at the bonding interface between the support substrate 11 and the single crystal substrate 13 include the difference in the bandgap potential width between the semiconductor substrates such as the support substrate 11 and the single crystal substrate 13. Fig. 9 As shown, it is believed that there is a potential barrier in quantum mechanics. Fig. 9 In the example, the case where the supporting substrate 11 is a SiC polycrystal with a 3C plane orientation as the main body of the n-type and the band gap potential width is 2.2V is shown. In addition, the case where the single crystal substrate 13 is a SiC single crystal with a 4H plane orientation and the band gap potential width is 3.2V is shown. It is believed that such a potential barrier is generated at the bonding interface and its vicinity due to the difference in the band gap potential width between 4H and 3C, the energy level caused by argon irradiation at the bonding interface, the mismatch of the bonding interface, etc. Moreover, according to the present invention, phosphorus, which is a high-concentration n-type carrier, can be moved to the vicinity of the bonding interface. As a result, a tunnel phenomenon can be induced to produce an improvement in non-ohmic characteristics.

[0102] according to Figure 8 , Fig. 9 The results show that the formation of the damaged layer and the introduction of specific elements are performed not only on the single crystal substrate 13 but also on the supporting substrate 11, thereby further reducing the width of the energy barrier at the bonding interface between the single crystal substrate 13 and the supporting substrate 11.

[0103] That is, the damaged layer forming step in the present invention is preferably a step of forming a damaged layer on the first bonding target surface and the second bonding target surface. In addition, the specific element introducing step in the present invention is preferably a step of introducing a specific element to the first bonding target surface and the second bonding target surface.

[0104] <Effect>

[0105] In the present invention, the surface of a semiconductor layer is bonded to the surface of another semiconductor layer to generate a semiconductor substrate having a bonding interface, and a specific element of the semiconductor layer is moved to the damaged layer by subsequent heat treatment, thereby allowing electrons to tunnel through the potential barrier of the bonding interface, thereby reducing the interface resistance.

[0106] If an element that is difficult to handle, such as phosphorus, is used as an element introduced into the bonding object surface 13a, the manufacturing cost may increase. This is because it is necessary to perform a detoxification treatment of the gas generated from the manufacturing device and increase the regular cleaning frequency of the manufacturing device. Therefore, in the present invention, nitrogen can be used instead of phosphorus as an element introduced in excess. Nitrogen is easier to handle than phosphorus, so the manufacturing cost can be suppressed.

[0107] <Modification>

[0108] An embodiment of the present invention has been described in detail above, but these are merely examples and do not limit the scope of the present invention. For example, as described below, the present invention includes various modifications and changes to the specific examples described above.

[0109] The element used to form the damaged layer may be silicon (Si). In this case, in the composition ratio of the elements at the bonding interface, the proportion of silicon is greater than that of carbon. In this case, it can also be said that the interface is composed of silicon-rich SiC. For example, the composition ratio of silicon is in the range of 50 to 60 atomic%. The interface is formed in a state where silicon exists at a very high concentration, so the crystal structure of SiC cannot be maintained, and the crystal structure changes from SiC. That is, the interface is composed of a composite material containing carbon and silicon. A damaged layer with a lot of crystal defects can be formed at the interface.

[0110] The element used to form the damaged layer may be carbon (C). In this case, in the composition ratio of the elements at the interface, the proportion of carbon is greater than that of silicon. In this case, it can also be said that the interface is composed of carbon-rich SiC. For example, the composition ratio of carbon is in the range of 50 to 60 atomic%. In this case, as described above, the crystal structure also changes from SiC. That is, the interface can form a damaged layer of a composite material containing carbon and silicon.

[0111] The element used to form the damaged layer may be an element that is difficult to become a carrier and has a high damage-forming effect, for example, at least one of rare gases such as helium (He), neon (Ne), argon (Ar), and xenon (Xe), and hydrogen (H).

[0112] The element used to form the damaged layer may be an element that easily becomes a carrier and has a high efficiency in forming damage, for example, at least one of nitrogen (N), phosphorus (P), boron (B) and aluminum (Al).

[0113] In the damaged layer forming process described in step S1, various forming methods can be used. For example, plasma irradiation in which a specific element gas to be irradiated is ionized and irradiated toward the substrate may be used. Alternatively, neutral element implantation may be used.

[0114] In addition, the specific element may be at least one of nitrogen (N), phosphorus (P), boron (B) and aluminum (Al), which are elements that are highly effective in generating electron or hole carriers as n-type or p-type dopants in SiC.

[0115] In addition, in the irradiation step (step S3), ions of a specific element that generates carriers may be irradiated. In the present invention, in the irradiation step, ions of nitrogen, phosphorus, etc. may be further irradiated.

[0116] In addition, in the irradiation step, nitrogen is preferably irradiated. Thus, the process of activating the bonding target surface of the support substrate 11 and the single crystal substrate 13 can also function as a process of introducing nitrogen, phosphorus, etc. into the support substrate 11 and the single crystal substrate 13. Therefore, the introduction process of the specific element (step S2) can be omitted, so the number of processes can be reduced. In addition, the device used to activate the bonding target surface is not limited to the FAB gun, and various devices such as an ion gun can be used.

[0117] In the damaged layer forming step and the specific element introducing step, ion implantation may be performed via a mask material. The mask material may be at least one of a silicon oxide film, a silicon nitride film, and a resist.

[0118] In the damaged layer forming process described in step S1 and the specific element introduction process described in step S2, the case where the damaged layer is formed and the specific element is introduced only in the single crystal substrate 13 is described, but it is not limited to this method. The damaged layer can be formed and the specific element can be introduced in both the single crystal substrate 13 and the supporting substrate 11, or the damaged layer can be formed and the specific element can be introduced only in the supporting substrate 11. For example, in the case where the supporting substrate 11 is polycrystalline SiC that has been subjected to a low resistance treatment, the injection of the specific element that becomes an n-type carrier into the bonding object surface of the supporting substrate 11 can be omitted. As an example of polycrystalline SiC that has been subjected to a low resistance treatment, the case of using polycrystalline SiC into which a specific element has been introduced in advance can be cited.

[0119] For example, phosphorus may be introduced into the single crystal substrate 13 as a specific element, and then argon may be ion-implanted into the single crystal substrate 13 to form the damaged layer 12 on the bonding target surface of the single crystal substrate 13 .

[0120] That is, in the present invention, the damaged layer forming step may be performed after the specific element introducing step, or the damaged layer forming step may be performed after the specific element introducing step.

[0121] In addition, the specific element introduction process can also be performed after the stripping process (step S5). For example, phosphorus ions can be implanted as specific elements from the surface 13 of the single crystal layer into the interior by ion implantation. At this time, various parameters such as acceleration energy and incident angle can be set in a manner that phosphorus becomes maximum near the bonding interface. For example, a multi-stage implantation in which the acceleration energy is changed and multiple implantations are performed can be used to control the phosphorus concentration to become maximum near the bonding interface.

[0122] The specific element that generates carriers in the support substrate 11 and the single crystal substrate 13 is not limited to the method of being introduced through the specific element introduction step. The specific element introduction step can also be omitted by using the support substrate 11 and the single crystal substrate 13 into which the specific element is pre-introduced. In this embodiment, an n-type support substrate 11 and a single crystal substrate 13 doped with nitrogen, phosphorus, etc. at a high concentration can be used. In addition, the concentration of the specific element pre-doped in the substrate can be set to be greater than the concentration of the specific element at the bonding interface introduced in the specific element introduction step. In this embodiment, a support substrate 11 and a single crystal substrate 13 doped with 1×10 19 / cm 3 The above-mentioned n-type supporting substrate 11 and single crystal substrate 13 of nitrogen or phosphorus may be used.

[0123] In addition, in the present invention, the specific element introduction process can be carried out without omitting it. For example, the specific element introduction process can be provided as follows: before the damage layer formation process, the specific element is introduced into the first bonding object surface of the first semiconductor substrate into which the specific element has not been introduced or the second bonding object surface of the second semiconductor substrate into which the specific element has not been introduced.

[0124] The method used in the specific element introduction process (step S2) may be ion implantation, neutral element implantation, plasma doping, but in addition thereto, a thermal diffusion method may also be used. The thermal diffusion method has the principle of heating on the basis of making a specific element such as phosphorus exist in high concentration around the supporting substrate 11 and the single crystal substrate 13. Therefore, on the surface of the supporting substrate 11 and the single crystal substrate 13, the concentration of specific elements such as phosphorus can be maximized. In addition, compared with the case of using the ion implantation method, the width of the concentration distribution of the specific element can be narrowed. Thus, a concentration distribution of a specific element having a width corresponding to the width (about a few nanometers) of the potential barrier that can be passed through by the tunnel effect can be formed. In addition, when the semiconductor material into which the specific element is introduced is SiC, the thermal diffusion coefficient of the impurities of SiC is very small, so it is preferred to perform a heat treatment process for thermal diffusion at a high temperature of about 1100°C or more. Thus, a diffusion of about a few nanometers that can exhibit a tunnel effect can be performed.

[0125] In addition, in the present invention, the stripping step (step S5) and the heat treatment step (step S6) may be combined. Specifically, in the stripping step, heating may be performed at a temperature higher than the temperature at which the specific element migrates to the damaged layer. This can reduce the number of steps.

[0126] In addition, in the present invention, after the heat treatment step (step S6), a single crystal layer of necessary thickness may be epitaxially grown on the single crystal substrate 13. The epitaxial layer is formed as a formation region of various elements. The thickness of the epitaxial layer required to form various elements is approximately 5 μm or more in the case of SiC.

[0127] In addition, when SiC is used for the single crystal substrate 13, it is not limited to single crystal 4H-SiC. Various polymorphic single crystal SiC such as 3C-SiC and 6H-SiC can be used as the single crystal substrate 13. In addition, when SiC polycrystal is used for the support substrate 11, it is not limited to polycrystal 3C-SiC. Various polymorphic polycrystalline SiC can be used.

[0128] Example

[0129] Hereinafter, examples of the present invention will be shown and described in more detail, but the present invention is not limited to the following examples at all.

[0130] In this embodiment, a SiC single crystal substrate is used as the single crystal substrate 13, and a SiC polycrystalline substrate is used as the support substrate 11, and these are bonded to manufacture the semiconductor substrate 10. Then, using the manufactured semiconductor substrate 10, Figure 8 The phosphorus concentrations shown and Fig.11 Determination of the interface resistance shown.

[0131] [Example 1]

[0132] <Manufacturing of Semiconductor Substrate 10>

[0133] As the single crystal substrate 13, a 4H-SiC single crystal substrate having a diameter of 6 inches produced by a sublimation method was used. In addition, as the support substrate 11, a 3C-SiC polycrystalline substrate having a diameter of 6 inches obtained by forming a SiC polycrystalline film by a chemical vapor deposition method was used. First, before the damaged layer forming step, the bonding target surfaces 11a and 13a of the single crystal substrate 13 and the support substrate 11 were mirror-polished and cleaned.

[0134] (Hydrogen ion implantation step S0)

[0135] Hydrogen ions are implanted into the bonding target surface 13a of the single crystal substrate 13 at a depth of about 0.6 μm to form a hydrogen implanted layer 15. The hydrogen implanted layer 15 is amorphized during the hydrogen ion implantation and is peeled off by forming fine bubbles due to heat applied in the subsequent peeling step S5.

[0136] (Damage Layer Forming Step S1)

[0137] In this embodiment, as the damaged layer forming step S1, an ion implanter is used to irradiate argon to the surface 13a of the single crystal substrate 13. The implantation conditions are, for example, a dose of 10 14 ~10 16 atoms / cm 2 , acceleration voltage 0.1~70kV.

[0138] (Specific element introduction step S2)

[0139] Phosphorus ions were implanted from the surface 13a of the single crystal substrate 13 using an ion implanter to form a doped layer 13b. The phosphorus concentration of the surface 13a was 8×10 19 / cm 3 .

[0140] (Irradiation Step S3)

[0141] First, the surfaces 11 a and 13 a to be joined are mirror-polished and cleaned, and then the surfaces 11 a and 13 a to be joined are irradiated with an argon beam.

[0142] Specifically, if Figure 5 As shown in FIG. 1 , the single crystal substrate 13 and the supporting substrate 11 are placed in the chamber 101, and the single crystal substrate 13 and the supporting substrate 11 are aligned relative to each other. Next, the vacuum degree is set to 1×10 -4 ~1×10 -6 The Pa method sets the interior of the chamber 101 to a vacuum state.

[0143] Next, the bonding target surface 11a of the supporting substrate 11 and the bonding target surface 13a of the single crystal substrate 13 are irradiated with a neutral element beam of argon using the FAB gun 102. The neutral element beam of argon is uniformly irradiated onto the entire bonding target surface 11a and the entire bonding target surface 13a.

[0144] (Joining Step S4)

[0145] After the irradiation step, the activated bonding target surface 11a of the supporting substrate 11 and the bonding target surface 13a of the single crystal substrate 13 are brought into contact with each other in the chamber 101 while maintaining a vacuum state, and further pressurized to obtain a bonded substrate of the supporting substrate 11 and the single crystal substrate 13.

[0146] (Peeling Step S5)

[0147] The bonded substrate was heated in an inert atmosphere filled with nitrogen using a furnace, and the single crystal substrate 13 was separated at the hydrogen implantation layer 15 , thereby forming a bonded substrate in which the thin single crystal substrate 13 having a thickness of 0.6 μm was bonded.

[0148] (Heat treatment step S6)

[0149] After the peeling step, the bonded substrate is heated at 1700° C. in an inert atmosphere filled with argon gas in a furnace, thereby obtaining a semiconductor substrate 10 .

[0150] <Evaluation of Semiconductor Substrate 10>

[0151] (Determination of phosphorus concentration)

[0152] The phosphorus concentration of the semiconductor substrate 10 after the heat treatment step was measured by secondary ion mass spectrometry (SIMS). In addition, for comparison, the phosphorus concentration of the bonded substrate before the heat treatment step and after the stripping step was also measured in the same manner. The results are shown in FIG. Figure 8 .

[0153] Figure 8 The X-axis of the semiconductor substrate 10 has 0 as the bonding interface between the support substrate 11 and the single crystal substrate 13, and the right side of the dotted line marked in the up-down direction is the support substrate 11, and the distance from the bonding interface, that is, 0, is expressed as the depth. In addition, the left side of the dotted line is the single crystal substrate 13, and the distance from the bonding interface, that is, 0, is expressed as the depth. In addition, the Y-axis represents the concentration of phosphorus as an example of a specific element. That is, in Figure 8 : shows how much phosphorus exists in the bonded semiconductor substrate and at what depth from the bonded interface.

[0154] Figure 8 The solid line graph in the figure shows the phosphorus concentration in the semiconductor substrate 10, and the dotted line graph shows the phosphorus concentration in the bonded substrate after the stripping process. As can be seen from the solid line graph, in the semiconductor substrate 10, the phosphorus concentration is highest in the region 15 nm away from the bonded interface, and the phosphorus concentration at the bonded interface is 8×10 19 / cm 3 The phosphorus concentration is high in a region 15 nm away from the bonding interface and in a region 50 nm away from the bonding interface.

[0155] In the graph shown by the dotted line, the phosphorus concentration is highest in the region about 30 nm from the bonding interface, so it can be seen that phosphorus has moved to the bonding interface by the heat treatment process. Figure 8The area surrounded by a circle is an area where no damage layer is formed. In the dotted line graph and the solid line graph, the phosphorus concentration is almost unchanged. Therefore, it can be seen that by forming a damage layer, the phosphorus located in the damage layer is easily moved to the bonding interface.

[0156] (Measurement of interface resistance)

[0157] Fig.10 The cross-sectional view of the TEG for measuring the specific on-resistance produced this time is shown. As the surface electrode of the cross-sectional view, an Al film 30 is deposited on a Ti film 20 and then an electrode is formed by patterning. The transfer layer under the Ti film 20 as the surface electrode is a single crystal substrate 13, the polycrystalline support substrate under the single crystal substrate 13 is a support substrate 11, and the back electrode under the support substrate is a Ti film 21.

[0158] The specific on-resistance of the produced TEG was measured using a semiconductor parameter analyzer (manufactured by Agilent). In addition, the specific on-resistance of the TEG produced in the same manner as in the example was measured using a semiconductor substrate produced in the same manner as in the example except that the specific element introduction step was not performed and phosphorus ions were not implanted as a comparison. The results are shown in Fig.11 .

[0159] Fig.11 is a result of the phosphorus ion implantation dependence of the specific on-resistance, Fig.12 is the result of the current-voltage characteristic of phosphorus ion implantation (Example), Fig.13 It is the result of the current-voltage characteristic of the non-phosphorus ion implantation (comparative example). In the comparative example of the non-phosphorus ion implantation, the current-voltage characteristic is not linear, but asymmetric, and its voltage is also 2 orders of magnitude higher than that of the embodiment with phosphorus ion implantation. It shows the resistance at the bonding interface confirmed in the "non-phosphorus ion implantation". On the other hand, it becomes a linear ohmic characteristic in the "phosphorus ion implantation". The resistance observed in the "phosphorus ion implantation" is the resistance of the bonded substrate itself, and the interface resistance is a negligible small value. That is, by the injection of phosphorus ions, the on-resistance is reduced to a level that can be ignored relative to the substrate resistance. That is, the interface resistance is much smaller than the substrate resistance, so it becomes a result that only the substrate resistance can be measured. That is, it can be seen that the resistance at the bonding interface confirmed in the "non-phosphorus ion implantation" is not detected in the "phosphorus ion implantation", which can prevent the generation of interface resistance at the bonding interface.

[0160] Depend on Figure 8 , Figure 11 to Figure 13 The results show that the phosphorus concentration is highest in the region 15 nm from the bonding interface, and the phosphorus concentration at the bonding interface is 8×10 19 / cm 3The semiconductor substrate 10 having a high phosphorus concentration in a region 15 nm from the bonding interface and a region 50 nm away from the bonding interface does not generate interface resistance at the bonding interface.

[0161] (Summarize)

[0162] As described above, according to the present invention, a semiconductor substrate and a method for manufacturing a semiconductor substrate capable of preventing generation of interface resistance at a bonding interface can be provided, and thus the present invention is industrially useful.

[0163] Description of Reference Numerals

[0164] 10: semiconductor substrate; 11: supporting substrate; 11a: bonding object surface; 12: damaged layer; 13: single crystal substrate; 13a: bonding object surface; 13b: doping layer; 15: hydrogen injection layer; 20: Ti film; 21: Ti film; 30: Al film; 101: chamber; 102: FAB gun.

Claims

1. A method for manufacturing a semiconductor substrate, comprising: The method for manufacturing a semiconductor substrate comprises: a damaged layer forming step of forming a damaged layer on at least one of a first bonding target surface of the first semiconductor substrate and a second bonding target surface of the second semiconductor substrate; a specific element introduction step of introducing a specific element into at least one of the first bonding target surface and the second bonding target surface; a bonding step of bonding the first bonding target surface and the second bonding target surface to form a bonded semiconductor substrate having a bonding interface after the damaged layer forming step and the specific element introducing step; as well as a heat treatment step of heat-treating the bonded semiconductor substrate; The heat treatment step is a step of causing the specific element introduced into at least one of the first semiconductor substrate and the second semiconductor substrate to move to the damaged layer of the first semiconductor substrate or the damaged layer of the second semiconductor substrate. When the first semiconductor substrate and the second semiconductor substrate are N-type semiconductors, a pentavalent element is used as the specific element. When the first semiconductor substrate and the second semiconductor substrate are P-type semiconductors, a trivalent element is used as the specific element.

2. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The first semiconductor substrate and the second semiconductor substrate are any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond.

3. The method for manufacturing a semiconductor substrate according to claim 1 or 2, wherein: The damaged layer forming step is performed after the damaged layer forming step, or the damaged layer forming step is performed after the damaged layer introducing step.

4. The method for manufacturing a semiconductor substrate according to claim 1, wherein: At least any one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B) and aluminum (Al) exists in the damaged layer.

5. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The damaged layer forming step is a step of forming the damaged layer by performing at least one of ion implantation, neutral element implantation, and plasma irradiation on at least one of the first bonding target surface and the second bonding target surface.

6. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The specific element introduction step is a step of introducing the specific element by performing at least one of ion implantation, neutral element implantation, plasma doping, and thermal diffusion on at least one of the first bonding target surface and the second bonding target surface.

7. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The specific element is at least any one of nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

8. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The heat treatment temperature in the heat treatment step is 1100°C to 2200°C.

9. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The method for manufacturing a semiconductor substrate includes an irradiation step of irradiating at least one of the first bonding target surface and the second bonding target surface with an argon beam after the damaged layer forming step, after the specific element introducing step, and before the bonding step.

10. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The first semiconductor substrate is a SiC polycrystalline substrate and the second semiconductor substrate is a SiC single crystal substrate, the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate, the first semiconductor substrate is a gallium nitride (GaN) substrate and the second semiconductor substrate is a gallium nitride (GaN) substrate, the first semiconductor substrate is a gallium oxide (Ga2O3) substrate and the second semiconductor substrate is a gallium oxide (Ga2O3) substrate, or the first semiconductor substrate is a diamond substrate and the second semiconductor substrate is a diamond substrate, The method for manufacturing a semiconductor substrate includes a hydrogen ion implantation step of implanting hydrogen ions into the second bonding target surface before the damaged layer forming step and before the specific element introducing step.

11. The method for manufacturing a semiconductor substrate according to claim 10, wherein: The method for manufacturing a semiconductor substrate includes a peeling step of peeling the second semiconductor substrate with the microbubble layer as a peeling surface after the bonding step and before the heat treatment step.

12. A semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, wherein: The concentration of the specific element in the semiconductor substrate is highest in at least any one of the bonding interface and a region extending from the bonding interface to approximately 15 nm.

13. The semiconductor substrate according to claim 12, wherein The concentration of the specific element at the bonding interface is 1.0×10 19 atoms / cm 3 ~2.0×10 20 atoms / cm 3 .

14. The semiconductor substrate according to claim 12 or 13, wherein: The specific element in the semiconductor substrate has a high concentration in at least any one of the bonding interface and a region extending from the bonding interface to approximately 15 nm, and a region 40 nm to 60 nm away from the bonding interface.

15. The semiconductor substrate according to claim 12, wherein The first semiconductor substrate and the second semiconductor substrate are any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond.

16. The semiconductor substrate according to claim 12, wherein The semiconductor substrate includes a damaged layer in at least one of the bonding interface and a region extending from the bonding interface to approximately 15 nm. At least any one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B) and aluminum (Al) exists in the damaged layer.

17. The semiconductor substrate according to claim 12, wherein The specific element is at least any one of nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

18. The semiconductor substrate according to claim 12, wherein The first semiconductor substrate is a SiC polycrystalline substrate, The second semiconductor substrate is a SiC single crystal substrate, The phosphorus concentration at the bonding interface is 1×10 19 atoms / cm 3 ~2.0×10 20 atoms / cm 3 .

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