Data transmission method and device

Abstract

The invention provides a data transmission method and device, relates to the technical field of communication, and is used for improving the data transmission efficiency. The method comprises the steps that first valid data and second valid data are obtained, the first valid data comprise first data from a first bus channel, and the second valid data comprise second data from a second bus channel; a first payload is determined according to the first valid data and the second valid data, and the first payload comprises the first valid data, filling data and at least part of the second valid data which are spliced in sequence; and packaging and transmitting the first payload. In the process, the first payload comprises the first valid data, the filling data and at least part of the second valid data, so that the first payload has no idle (residual) bit width, and when the first payload is packaged and then sent to a receiving side bare chip, the data transmission efficiency is improved.

Description

Data transmission method and device Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method and device. Background Art

[0002] A system on chip (SOC) interconnects its internal subsystems via an on-chip bus. For example, the on-chip bus can be an Advanced Extensible Interface (AXI) bus, an Advanced Extensible Interface Coherent Expansion (ACE) bus, or a Coherent Hub Interface (CHI) bus. Figure 1 shows a schematic diagram of the structure of a SOC, which includes a media subsystem, a central processing unit (CPU) subsystem, and an artificial intelligence (AI) subsystem. The media subsystem includes a video display processor (VDP) module, a communication module (FI), and a first bus; the CPU subsystem includes a CPU, an I / O module, multiple double data rate (DDR) memory modules, and a first bus; and the AI ​​subsystem includes multiple network processing units (NPUs) and a first bus, which can be any of the aforementioned on-chip buses. Specifically, each module or processor in the media subsystem and AI subsystem is interconnected with the first bus in the CPU subsystem via its own first bus to enable data transmission between the multiple subsystems. The SOC shown in Figure 1 is integrated on a single die, taking the AI ​​subsystem as an example, with two NPUs and the CPU subsystem as an example, with three DDR memory modules.

[0003] Currently, when the media subsystem, CPU subsystem, and AI subsystem shown in Figure 1 are integrated on separate dies, multiple dies can be spliced ​​together through the chiplet interface to achieve interconnection between them. However, how to achieve high-efficiency data transmission between different dies through the chiplet interface has become a pressing issue.

[0004] Summary of the Invention

[0005] The present application provides a data transmission method and apparatus, relating to the field of communications technology, for improving data transmission efficiency. The data transmission method is applied to a system-on-chip (SoC), wherein the SoC includes a plurality of mutually coupled dies, the plurality of dies including a first die and a second die, the first die including a first chiplet interface, the second die including a second chiplet interface, and the first die and the second die being able to transmit data via the first chiplet interface and the second chiplet interface. For either the first die or the second die, the die can be a receiving-side die or a transmitting-side die.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a data transmission method is provided for a transmitting-side bare chip, the method comprising: obtaining first valid data and second valid data, the first valid data comprising first data from a first bus channel, and the second valid data comprising second data from a second bus channel; determining a first payload based on the first valid data and the second valid data, wherein the first payload comprises the first valid data, padding data, and at least a portion of the second valid data spliced ​​in sequence; and encapsulating and sending the first payload.

[0008] In the above technical solution, the first valid data and at least part of the second valid data are spliced ​​into a first payload, and the first payload includes the first valid data, padding data and at least part of the second valid data. The first payload is encapsulated and sent to the receiving side bare chip, that is, the first valid data and the second valid data are spliced ​​in one payload and sent. On the other hand, the first payload includes the first valid data, padding data and at least part of the second valid data, that is, there is no idle (remaining) bit width in the first payload, that is, there is no idle bit in the first payload. When the first payload is encapsulated and sent, the efficiency of data transmission is improved.

[0009] In a possible implementation of the first aspect, the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width, wherein the alignment bit width can be a sliding window bit width, and the window size of the sliding window bit width can be fixed. For example, the alignment bit width can be a sliding window bit width when splitting the first payload, and the sliding window bit width can also be called a sliding window read bit width. In the above possible implementation, the starting bit position of the first valid data in the first payload is 0 bit, and the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width, so that the starting bit position of the second valid data in the first payload is also equal to an integer multiple of the alignment bit width. After the first payload is encapsulated, it is sent to the receiving side bare chip. When the receiving side bare chip splits the first payload, it performs a sliding window read on the first payload each time according to the alignment bit width (fixed bit) to quickly determine the first valid data and at least part of the second valid data in the first payload. Compared with the usual situation in which the receiving side bare chip performs sliding window reading on the first payload one bit at a time, the processing delay of the receiving side bare chip is reduced and the processing efficiency is improved.

[0010] In a possible implementation of the first aspect, the bit width of the padding data is smaller than the alignment bit width. In the above possible implementation, the bit width of the padding data is smaller than the alignment bit width. By splicing the padding data after the first valid data, the sum of the bit width of the first valid data and the bit width of the padding data can be made equal to an integer multiple of the alignment bit width, that is, the starting bit position of the second valid data in the first payload is also equal to an integer multiple of the alignment bit width. When the first payload is encapsulated and sent to a receiving-side bare chip, the receiving-side bare chip can quickly determine the first valid data and at least part of the second valid data from the first payload based on the alignment bit width, thereby reducing the processing delay of the receiving-side bare chip and improving processing efficiency.

[0011] In a possible implementation of the first aspect, the alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits. In the above possible implementation, the receiving die can quickly determine the first valid data and at least part of the second valid data from the first payload based on the alignment bit width, thereby reducing processing latency of the receiving die and improving processing efficiency.

[0012] In a possible implementation of the first aspect, the first valid data includes a first channel identifier and the first data, and the second valid data includes a second channel identifier and the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel. In the above possible implementation, the transmission priority of the first data and the second data can be determined based on the first channel identifier and the second channel identifier, thereby improving data usage efficiency. On the other hand, the bit width of the first data can be determined based on the first channel identifier, and the bit width of the second data can be determined based on the second channel identifier. Therefore, when determining the first payload based on the first valid data and the second valid data, the bit width of the padding data can be quickly determined, thereby improving the splicing speed.

[0013] In a possible implementation of the first aspect, the method further includes: determining, based on the first channel identifier and the second channel identifier, a sending priority of the first valid data and the second valid data. In the above possible implementation, the first valid data and the second valid data are sent based on the sending priority of the first valid data and the second valid data, thereby improving the efficiency of using the valid data.

[0014] In a possible implementation of the first aspect, the bit width of the first channel identifier and the bit width of the second channel identifier are both 4 bits. In this possible implementation, the bit width of the first valid data and the bit width of the second valid data can be determined based on the bit width of the channel identifier and the bit width of the second channel identifier. Thus, when determining the first payload based on the first valid data and the second valid data, the bit width of the padding data can be quickly determined, thereby improving the splicing speed.

[0015] In a possible implementation of the first aspect, determining the first payload based on the first valid data and the second valid data includes: if the bit width of the first payload is insufficient to carry the second valid data, padding only a portion of the second valid data into the first payload. In this possible implementation, if the bit width of the first payload is insufficient to carry the second valid data, padding a portion of the second valid data into the first payload, thereby leaving no idle bit width in the first payload, i.e., no idle bits in the first payload. When the first payload is encapsulated and sent to a receiving die, no idle bits are left in the first payload, thereby improving data transmission efficiency.

[0016] In a possible implementation of the first aspect, the method further includes: padding the remaining data of the second valid data excluding the portion of the second valid data into a second payload, the first payload being adjacent to the second payload. In this possible implementation, the remaining data of the second valid data excluding the portion of the second valid data is padded into the second payload adjacent to the first payload. When the second payload is encapsulated and sent to a receiving die, the receiving die can quickly determine the remaining data from the adjacent second payload, thereby improving data determination speed.

[0017] In a possible implementation of the first aspect, determining a first payload based on the first valid data and the second valid data includes: if the remaining bit width of the first payload excluding the bit width occupied by the first valid data, the padding data, and the second valid data is less than or equal to the bit width of the channel identifier, then writing the padding data into the remaining bit width. In the above possible implementation, if the remaining bit width of the first payload excluding the bit width occupied by the first valid data, the padding data, and the second valid data is insufficient to carry the bit width of a channel identifier, then writing the padding data into the remaining bit width, so that there are no idle bits in the first payload. When the first payload is encapsulated and sent to the receiving-side bare chip, there are no idle bits in the first payload, thereby improving the efficiency of data transmission.

[0018] In a possible implementation of the first aspect, the method further includes: if the remaining bit width is greater than the bit width of the channel identifier, obtaining third valid data, the third valid data including third data from a third bus channel; determining the first payload based on the first valid data and the second valid data includes: determining the first payload based on the first valid data, the second valid data, and the third valid data, wherein the first payload includes the first valid data, the padding data, the second valid data, the padding data, and at least a portion of the third valid data, which are sequentially spliced. In the above possible implementation, there are no idle bits in the first payload. When the first payload is encapsulated and sent to the receiving-side bare chip, there are no idle bits in the first payload, thereby improving data transmission efficiency.

[0019] In a possible implementation of the first aspect, the encapsulated first payload includes a message header and a message trailer. In the above possible implementation, the message type and related operations corresponding to the first payload can be quickly determined through the message header and message trailer, thereby improving the processing efficiency of the first payload.

[0020] In a second aspect, a data transmission method is provided for a sending-side bare chip, the method comprising: obtaining first valid data, the first valid data including first data from a first bus channel; determining a first payload based on the first valid data and virtual data, wherein the first payload includes the first valid data, padding data, and the virtual data spliced ​​in sequence, the virtual data including a virtual identifier, the virtual identifier being used to indicate that the virtual data is invalid; and encapsulating and sending the first payload.

[0021] In the above technical solution, if the priority of the first valid data is higher and it is impossible to wait for other valid data for a long time, or, at the current moment, other valid data have been spliced ​​and no other valid data needs to be spliced, and the remaining bit width of the first payload excluding the bit width occupied by the first valid data is greater than the alignment bit width, since the bit width of the padding data is less than the alignment bit width, the padding data cannot be written into the remaining bit width at this time, then the first payload is determined according to the first valid data and the virtual data, wherein the first payload includes the first valid data, the padding data and the virtual data spliced ​​in sequence, and the virtual data is invalid data, so that there is no idle (remaining) bit width in the first payload, that is, there are no idle bits in the first payload. When the first payload is encapsulated into the first target message, there are no idle bits in the message, thereby improving the efficiency of data transmission.

[0022] In a third aspect, a data transmission method is provided for a receiving-side bare chip, the method comprising: receiving and parsing a first target message to obtain a first payload; determining first valid data and at least part of second valid data based on the first payload; sending the first valid data to a first bus channel corresponding to the first valid data, and sending at least part of the second valid data to a second bus channel corresponding to the second valid data.

[0023] In the above technical solution, the first payload is obtained by parsing the first target message, and the first valid data and at least part of the second valid data are determined according to the first payload, thereby improving data receiving efficiency.

[0024] In one possible implementation of the third aspect, determining, based on the first payload, first valid data and at least a portion of second valid data includes: splitting the first payload according to an alignment bit width to obtain the first valid data, padding data, and at least a portion of the second valid data. In this possible implementation, the first payload can be directly split according to the alignment bit width without sequentially accessing each bit in the first payload, thereby reducing data processing latency and further improving data processing efficiency.

[0025] In a possible implementation of the third aspect, the sum of the bit width of the first valid data and the bit width of the padding data is an integer multiple of the alignment bit width. In the above possible implementation, the starting bit position of the first valid data in the first payload is 0 bit, and the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width, so that the starting bit position of the second valid data in the first payload is also equal to an integer multiple of the alignment bit width. The first valid data and at least part of the second valid data can be directly determined based on the alignment bit width without sequentially accessing each bit in the first payload, thereby reducing data processing delay and further improving data processing efficiency.

[0026] In a possible implementation of the third aspect, the bit width of the padding data is smaller than the alignment bit width. In the above possible implementation, the bit width of the padding data is smaller than the alignment bit width. By splicing the padding data after the first valid data, the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width, and the starting bit position of the second valid data in the first payload is also equal to an integer multiple of the alignment bit width. The first valid data and at least part of the second valid data can be directly determined based on the alignment bit width without sequentially accessing each bit in the first payload, thereby reducing data processing delay and further improving data processing efficiency.

[0027] In a possible implementation of the third aspect, the alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits. In the above possible implementation, the first valid data and at least part of the second valid data can be quickly determined from the first target message based on the alignment bit width, thereby reducing data processing delay and improving data processing efficiency.

[0028] In a possible implementation of the third aspect, the first valid data includes a first channel identifier and the first data, and at least a portion of the second valid data includes a second channel identifier and at least a portion of the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel. In the above possible implementation, the transmission priority of the first data and the second data can be determined based on the first channel identifier and the second channel identifier, thereby improving data usage efficiency.

[0029] In a possible implementation of the third aspect, the method further includes: determining a transmission priority of the first valid data and at least a portion of the second valid data based on the first channel identifier and the second channel identifier. In the above possible implementation, the transmission priority of the first data and the second data can be determined based on the first channel identifier and the second channel identifier, thereby improving data usage efficiency.

[0030] In a possible implementation of the third aspect, before sending the first valid data to the first bus channel corresponding to the first valid data and sending at least a portion of the second valid data to the second bus channel corresponding to the second valid data, the method further includes: deleting the first channel identifier in the first valid data and the second channel identifier in at least a portion of the second valid data. In this possible implementation, the accuracy of the transmitted data is ensured.

[0031] In a possible implementation of the third aspect, sending at least a portion of the second valid data to a second bus channel corresponding to the second valid data includes: if at least a portion of the second valid data is partial second valid data, receiving and parsing a second target message to obtain a second payload; determining, based on the second payload, remaining data in the second valid data excluding the partial second valid data; and determining and sending the second valid data based on the remaining data and the partial second valid data. In this possible implementation, sending the second valid data after determining the second valid data from the partial second valid data and the remaining data ensures the accuracy of the sent data.

[0032] In a possible implementation of the third aspect, the method further includes: determining the first valid data, the second valid data, and at least a portion of the third valid data based on the first payload; sending the first valid data to a first bus channel corresponding to the first valid data, sending the second valid data to a second bus channel corresponding to the second valid data, and sending at least a portion of the third valid data to a third bus channel corresponding to the third valid data. In the above possible implementation, sending different valid data to the bus channels corresponding to the valid data ensures the accuracy of the valid data in each bus channel.

[0033] In a possible implementation of the third aspect, the target message includes a message header and a message trailer. In the above possible implementation, the message type and related operations can be quickly determined through the message header and message trailer, thereby improving the efficiency of message processing.

[0034] In a fourth aspect, a data transmission method is provided, the method comprising: receiving and parsing a first target message to obtain a first payload; determining first valid data based on the first payload; and sending the first valid data to a first bus channel corresponding to the first valid data.

[0035] In the above technical solution, the first payload is obtained by parsing the first target message, and the first valid data is determined according to the first payload, thereby improving data receiving efficiency.

[0036] In a fifth aspect, a data transmission device is provided, which includes: an acquisition unit for obtaining first valid data and second valid data, the first valid data including first data from a first bus channel, and the second valid data including second data from a second bus channel; a determination unit for determining a first payload based on the first valid data and the second valid data, wherein the first payload includes the first valid data, padding data and at least part of the second valid data spliced ​​in sequence; an encapsulation unit for encapsulating the first payload; and a sending unit for sending the encapsulated first payload.

[0037] In a possible implementation manner of the fifth aspect, the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width.

[0038] In a possible implementation manner of the fifth aspect, the bit width of the padding data is smaller than the alignment bit width.

[0039] In a possible implementation manner of the fifth aspect, the alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits.

[0040] In a possible implementation of the fifth aspect, the first valid data includes a first channel identifier and the first data, and the second valid data includes a second channel identifier and the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

[0041] In a possible implementation manner of the fifth aspect, the determining unit is further configured to: determine a sending priority of the first valid data and the second valid data according to the first channel identifier and the second channel identifier.

[0042] In a possible implementation manner of the fifth aspect, a bit width of the first channel identifier and a bit width of the second channel identifier are both 4 bits.

[0043] In a possible implementation manner of the fifth aspect, the determining unit is further configured to: if a bit width of the first payload is insufficient to carry the second valid data, only fill the first payload with a portion of the second valid data.

[0044] In a possible implementation manner of the fifth aspect, the determining unit is further configured to fill the second payload with remaining data in the second valid data except the portion of the second valid data, and the first payload is adjacent to the second payload.

[0045] In a possible implementation of the fifth aspect, the determination unit is further used to: if the remaining bit width in the first payload excluding the bit width occupied by the first valid data, the padding data and the second valid data is less than or equal to the bit width of the channel identifier, then write the padding data into the remaining bit width.

[0046] In a possible implementation of the fifth aspect, the acquisition unit is further used to obtain third valid data if the remaining bit width is greater than or equal to the bit width of the channel identifier, and the third valid data includes third data from the third bus channel; determining the first payload based on the first valid data and the second valid data includes: determining the first payload based on the first valid data, the second valid data and the third valid data, wherein the first payload includes the first valid data, padding data, the second valid data, padding data and at least part of the third valid data spliced ​​in sequence.

[0047] In a possible implementation manner of the fifth aspect, the encapsulated first payload includes: a message header and a message trailer.

[0048] In a sixth aspect, a data transmission device is provided, which includes: an acquisition unit for obtaining first valid data, the first valid data including first data from a first bus channel; the determination unit for determining a first payload based on the first valid data and virtual data, wherein the first payload includes the first valid data, padding data and the virtual data spliced ​​in sequence, and the virtual data includes a virtual identifier, which is used to indicate that the virtual data is invalid; an encapsulation unit for encapsulating the first payload; and a sending unit for sending the encapsulated first payload.

[0049] In a seventh aspect, a data transmission device is provided, which includes: a receiving unit for receiving a first target message; a parsing unit for parsing the first target message to obtain a first payload; a determining unit for determining first valid data and at least part of second valid data based on the first payload; and a sending unit for sending the first valid data to a first bus channel corresponding to the first valid data, and sending at least part of the second valid data to a second bus channel corresponding to the second valid data.

[0050] In a possible implementation manner of the seventh aspect, the determining unit is further used to: split the first payload according to the alignment bit width to obtain the first valid data, padding data and at least part of the second valid data.

[0051] In a possible implementation manner of the seventh aspect, the sum of the bit width of the first valid data and the bit width of the padding data is an integer multiple of the alignment bit width.

[0052] In a possible implementation of the seventh aspect, the bit width of the padding data is smaller than the alignment bit width.

[0053] In a possible implementation manner of the seventh aspect, the alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits.

[0054] In a possible implementation of the seventh aspect, the first valid data includes a first channel identifier and first data, and at least part of the second valid data includes a second channel identifier and at least part of the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

[0055] In a possible implementation manner of the seventh aspect, the determining unit is further used to: determine a sending priority of the first valid data and at least part of the second valid data according to the first channel identifier and the second channel identifier.

[0056] In a possible implementation manner of the seventh aspect, a bit width of the first channel identifier and a bit width of the second channel identifier are both 4 bits.

[0057] In a possible implementation manner of the seventh aspect, the apparatus further includes a deleting unit configured to delete the first channel identifier in the first valid data and the second channel identifier in at least part of the second valid data.

[0058] In a possible implementation of the seventh aspect, if at least part of the second valid data is partial second valid data, the receiving unit is also used to receive and parse the second target message to obtain a second payload; the determination unit is also used to determine the remaining data in the second valid data except the partial second valid data based on the second payload; the determination unit is also used to determine the second valid data based on the remaining data and the partial second valid data; the sending unit is also used to send the second valid data.

[0059] In a possible implementation of the seventh aspect, the determination unit is further used to determine the first valid data, the second valid data and at least part of the third valid data based on the first payload; the sending unit is further used to send the first valid data to the first bus channel corresponding to the first valid data, send the second valid data to the second bus channel corresponding to the second valid data, and send at least part of the third valid data to the third bus channel corresponding to the third valid data.

[0060] In a possible implementation manner of the seventh aspect, the target message includes: a message header and a message tail.

[0061] In an eighth aspect, a data transmission device is provided, which includes: a receiving unit for receiving and parsing a first target message to obtain a first payload; a determining unit for determining first valid data based on the first payload; and a sending unit for sending the first valid data to a first bus channel corresponding to the first valid data.

[0062] In another aspect of the present application, a bare chip is provided. The bare chip includes a logic device, and the logic device is used to execute the data transmission method provided by the first aspect or any possible implementation of the first aspect.

[0063] In another aspect of the present application, a bare chip is provided. The bare chip includes a logic device, and the logic device is used to execute the data transmission method provided in the second aspect.

[0064] In another aspect of the present application, a bare chip is provided. The bare chip includes a logic device, and the logic device is used to execute the data transmission method provided by the third aspect or any possible implementation of the third aspect.

[0065] In another aspect of the present application, a bare chip is provided, which includes a logic device, and the logic device is used to execute the data transmission method provided by the above four aspects.

[0066] Another aspect of the present application provides a system on chip, which includes a plurality of bare chips coupled to each other, the plurality of bare chips including a first bare chip and a second bare chip, the first bare chip being used to execute the data transmission method provided by the first aspect or any possible implementation of the first aspect, or the data transmission method provided by the second aspect; the second bare chip being used to execute the data transmission method provided by the third aspect or any possible implementation of the third aspect, or the data transmission method provided by the fourth aspect.

[0067] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are run on a data transmission device, the relevant steps in the above method embodiment are executed.

[0068] In another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is run on a computer device, the data transmission device executes the relevant steps in the above method embodiments.

[0069] It can be understood that the data transmission device, system on chip, bare chip, computer-readable storage medium and computer program product provided above can be used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] FIG1 is a schematic structural diagram of a SOC;

[0071] FIG2 is a schematic structural diagram of another SOC;

[0072] FIG3 is a schematic diagram of the structure of a system on a chip provided in an embodiment of the present application;

[0073] FIG4 is a schematic structural diagram of a bus adapter provided in an embodiment of the present application;

[0074] FIG5 is a flowchart of a data transmission method provided in an embodiment of the present application;

[0075] FIG6 is a schematic diagram of the structure of first valid data provided in an embodiment of the present application;

[0076] FIG7 is a schematic diagram of the structure of a target message provided in an embodiment of the present application;

[0077] FIG8 is a flowchart of another data transmission method provided in an embodiment of the present application;

[0078] FIG9 is a schematic diagram of the structure of a target message provided by the present application;

[0079] FIG10 is a schematic diagram of the structure of another target message provided in an embodiment of the present application;

[0080] FIG11 is a schematic diagram of the structure of another target message provided in an embodiment of the present application;

[0081] FIG12 is a flowchart of another data transmission method provided in an embodiment of the present application;

[0082] FIG13 is a flowchart of another data transmission method provided in an embodiment of the present application;

[0083] FIG14 is a schematic structural diagram of a data transmission device provided in an embodiment of the present application;

[0084] FIG15 is a schematic structural diagram of another data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] In this application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. In addition, the embodiments of this application use words such as "first" and "second" to distinguish between identical or similar items with substantially the same function and effect. For example, the first threshold and the second threshold are merely to distinguish different thresholds and do not define their order of precedence. Those skilled in the art will understand that words such as "first" and "second" do not define the quantity or execution order.

[0086] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0087] Before introducing the embodiments of the present application, relevant knowledge about system on chip (SOC) is first introduced.

[0088] The system on chip (SOC) realizes the interconnection between internal subsystems through the on-chip bus. For example, the on-chip bus may include the advanced extensible interface (AXI) bus, the advanced extensible interface coherent extension (ACE) bus and the coherent hub interface (CHI) bus. The SOC shown in Figure 1 includes: a media subsystem, a central processing unit (CPU) subsystem and an artificial intelligence (AI) subsystem. When the multiple subsystems in the SOC shown in Figure 1 are integrated on a die, each module or processor in the media subsystem and the AI ​​subsystem is interconnected with the first bus in the CPU subsystem through its own first bus to realize data transmission between the multiple subsystems.

[0089] Among them, different on-chip buses (hereinafter referred to as buses) have different protocols, and the number of bus channels defined therein and the bit width of the data transmitted by each bus channel are different. For example, an AXI bus can define 5 bus channels, each of which can be used to transmit data, and the bit width of the data transmitted by each of the 5 bus channels is different. For example, the 5 bus channels include a write address channel and a write data bus channel. The bit width of the write address bus channel can be 101 bits (bit), and the bit width of the write data bus channel can be 152 bits. Optionally, the 5 bus channels do not necessarily have data to be transmitted at the same time, that is, the 5 bus channels are not necessarily valid at the same time. The bus channel can also be called a transmission channel, and the bit width of the data can be called the length of the data.

[0090] When the multiple subsystems in the SOC shown in Figure 1 are respectively integrated on different bare chips, the schematic diagram of the formed system on chip is shown in Figure 2. Figure 2 is a structural schematic diagram of a system on chip, which includes a media bare chip, an AI bare chip and a CPU bare chip. Among them, the media bare chip includes a chiplet interface, the AI ​​bare chip includes a chiplet interface, and the CPU bare chip includes two chiplet interfaces. The media bare chip and the AI ​​bare chip are respectively coupled with the corresponding chiplet interface in the CPU bare chip through their respective chiplet interfaces to achieve interconnection between multiple bare chips. The system on chip described in Figure 2 also includes a subpackaging substrate, which can be used to subpack the multiple bare chips.

[0091] Optionally, when the AI ​​die and the media die transmit data to the corresponding chiplet interface in the CPU die through their respective chiplet interfaces, the AI ​​die and the media die can be the sending side, and the CPU die can be the receiving side; when the two chiplet interfaces in the CPU die transmit data to the chiplet interfaces in the AI ​​die and the media die respectively, the CPU die can be the sending side, and the AI ​​die and the media die can be the receiving side.

[0092] Currently, how to achieve data transmission between different dies through the chiplet interface has become an urgent problem that needs to be solved. Data transmission between different dies can be achieved in the following two ways.

[0093] Method 1: The bus in the transmitting die transmits data to the chiplet interface via multiple bus channels. The chiplet interface collects data from each of the multiple bus channels, and the multiple bus channels receive multiple data. The chiplet interface then transmits the multiple data to the corresponding chiplet interface in the receiving die. However, the multiple data collected by the chiplet interface includes both valid and invalid data. The transmission of invalid data increases power consumption. Furthermore, when the bandwidth of the multiple data is low, the bandwidth utilization of the chiplet interface is reduced, further reducing transmission efficiency.

[0094] Method 2: The bus in the transmitting die transmits data to the chiplet interface via multiple bus channels. The chiplet interface collects and determines valid data from each of the multiple bus channels, resulting in multiple valid data corresponding to the multiple bus channels. For each valid data item, the chiplet interface generates a fixed-bit-width message based on the valid data item. The multiple valid data items then generate multiple messages, which are then transmitted to the corresponding chiplet interface in the receiving die. However, because the message bit width is fixed and the multiple valid data items have different bit widths, generating fixed-bit-width messages based on the valid data results in idle bit widths in the payload of some of the multiple messages, reducing the bandwidth utilization of the chiplet interface and further reducing transmission efficiency.

[0095] Based on this, an embodiment of the present application provides a data transmission method and device for improving data transmission efficiency. The method is applied to an on-chip system, and the method includes: obtaining first valid data and second valid data, the first valid data including first data from a first bus channel, and the second valid data including second data from a second bus channel; determining a first payload based on the first valid data and the second valid data, wherein the first payload includes the first valid data, padding data, and at least part of the second valid data spliced ​​in sequence; encapsulating and sending the first payload. In this process, the first payload includes the first valid data, padding data, and at least part of the second valid data, so that there is no idle (remaining) bit width in the first payload. When the first payload is encapsulated and sent to the receiving side bare chip, the efficiency of data transmission is improved.

[0096] The following describes the structure of the system on chip. Figure 3 is a schematic diagram of the structure of a system on chip provided by an embodiment of the present application. The system on chip includes multiple bare chips coupled to each other. For any one of the multiple bare chips, the bare chip can be used as a bare chip on the receiving side or as a bare chip on the transmitting side. The bare chip includes: a service processing unit 31, a bus 32, and a chip interface 33. In Figure 3, two bare chips are used as an example. The two bare chips are coupled to each other through their respective chip interfaces 33.

[0097] On the sending side, the service processing unit 31 may be configured to generate an access transaction matching the type of the bus 32 according to access requirements and send the access transaction to the bus 32. On the receiving side, the service processing unit 31 may also be configured to receive an access transaction from the bus 32 and perform corresponding processing based on the access transaction.

[0098] On the sending side, the bus 32 can be used to receive information. For example, the bus 32 can be used to receive access transactions from the business processing unit 31. The bus 32 is also used to obtain multiple data based on the access transactions. For example, the bus 32 can split, merge, or perform other related processing on the received access transactions to obtain the multiple data. The bus 32 is also used to send the multiple data to the chip interface 33 via multiple bus channels. On the receiving side, the bus 32 can be used to receive multiple messages from the chip interface 33. The bus 32 is also used to generate access transactions based on the multiple data and the bus protocol. The bus 32 is also used to send the access transactions to the business processing unit 31.

[0099] The core-grain interface 33 can be used to receive, process, and transmit data. The core-grain interface 33 may include a bus adapter 331, a data link layer 332, and an input / output interface 333. The input / output interface 333 may include an input interface and an output interface. For example, on the transmitting side, the bus adapter 331 may be used to receive multiple data items and process them accordingly to obtain a payload. The data link layer 332 may be used to encapsulate the payload to obtain a message. The output interface in the input / output interface 333 may be used to transmit the message. On the receiving side, the input interface in the input / output interface 333 may be used to receive a message. The data link layer 332 may be used to parse the message to obtain the payload. The bus adapter 331 may be used to split the payload to obtain multiple data items. For example, the bus adapter 331 may be used to split the payload according to the alignment bit width to obtain the multiple data items. The input / output interface 333 may also be referred to as the physical layer.

[0100] The structure of the bus adapter in FIG3 will be described in detail below in conjunction with FIG4 .

[0101] FIG4 is a schematic structural diagram of a bus adapter provided in an embodiment of the present application. The bus adapter includes: a receiving module 401 , a storage module 402 , a scheduling module 403 , a splicing module / splitting module 404 and a sending module 405 .

[0102] On the transmitting side, the receiving module 401 can be used to collect data from each of the multiple bus channels, thereby obtaining multiple data. For each of the multiple data, the receiving module 401 is further used to collect channel information of the bus channel from the bus channel corresponding to the data. The channel information is used to indicate the bus channel type. The multiple data correspond to multiple channel information. On the receiving side, the receiving module 401 is also used to receive a payload, for example, the receiving module 401 is also used to receive a payload from the data link layer.

[0103] The storage module 402 may be configured to store the plurality of data and the plurality of channel identifiers.

[0104] The scheduling module 403 may be used to determine the sending priority of the multiple data. For example, the scheduling module 403 may be used to determine the sending priority of the data according to the channel identifier corresponding to each data in the multiple data, so as to determine the sending priority of the multiple data.

[0105] The splicing module / splitting module 404 may include a splicing module and a sending module. The splicing module may be used to splice data, and the sending module may split data. For example, on the sending side, for each new channel message in the multiple channel information, the splicing module may be used to generate a channel identifier corresponding to the channel information, and correspondingly obtain multiple channel identifiers; the splicing module may be used to set the channel identifier corresponding to the data in each of the multiple data, and correspondingly obtain multiple valid data; the splicing module may also be used to splice the multiple valid data according to the sending priority and the alignment bit width to obtain a payload. On the receiving side, the splicing module / splitting module 404 may also be used to split the payload according to the alignment bit width to obtain multiple valid data. For each valid data in the multiple valid data, the splicing module / splitting module 404 may also be used to split the valid data to obtain the corresponding data and channel identifier.

[0106] The sending module 405 can be used to send the payload, for example, on the sending side, the sending module 405 can be used to send the payload to the data link layer. The sending module 405 is also used to send the multiple data, for example, on the receiving side, the sending module 405 is also used to send the multiple data to the bus.

[0107] The data transmission method provided by the embodiment of the present application is described in detail below based on the system on chip shown in Figure 3. For the transmitting side die among the multiple die, the flow chart of the data transmission method is shown in Figure 5.

[0108] FIG5 is a flowchart of a data transmission method provided in an embodiment of the present application, the method comprising:

[0109] S501 obtains first valid data and second valid data, where the first valid data includes first data from a first bus channel, and the second valid data includes second data from a second bus channel.

[0110] The bus adapter can be used to obtain the first valid data and the second valid data. Specifically, the bus adapter can be used to obtain the first data and first channel information from the first bus channel, and to obtain the second data and second channel information from the second bus channel, wherein the first channel information and the second channel information are used to indicate the types of the first bus channel and the second bus channel, respectively. The bus adapter is also used to generate a first channel identifier based on the first channel information and a second channel identifier based on the second channel information, wherein the first channel identifier is used to indicate the first bus channel and the second channel identifier is used to indicate the second bus channel. The bus adapter also sets the first channel identifier and the second channel identifier in the first data and the second data, respectively, to obtain the first valid data and the second valid data accordingly.

[0111] Optionally, the bus adapter may set the first channel identifier and the second channel identifier before the start bit positions of the first data and the second data, respectively, to obtain the first valid data and the second valid data. Alternatively, the first channel identifier and the second channel identifier may be set after the end bit positions of the first data and the second data, respectively, to obtain the first valid data and the second valid data. This application does not impose specific limitations on this.

[0112] In addition, the first bus channel and the second bus channel may be the same bus channel or different bus channels from the same bus. For example, the first bus channel and the second bus channel may both be write address bus channels in an AXI bus, and the first bus channel and the second bus channel may be write address bus channels and write data bus channels in the AXI bus. The first bus channel and the second bus channel may also be different bus channels from different buses. For example, the first bus channel may be a bus channel in a first bus, and the second bus channel may be a bus channel in a second bus, and the first bus and the second bus are different.

[0113] In addition, the bit width of the first valid data is equal to the sum of the bit width of the first channel identifier and the bit width of the first data, and the bit width of the second valid data is equal to the sum of the bit width of the second channel identifier and the bit width of the second data. In practical applications, the bit width of the first channel identifier and the bit width of the second channel identifier can be equal. For example, in one possible implementation, the bit width of the first channel identifier and the bit width of the second channel identifier can both be 4 bits. In the following embodiments, the bit width of the channel identifier is 4 bits as an example.

[0114] Furthermore, the bit width of the first data is related to the first bus channel, and the bit width of the second data is related to the second bus channel, that is, the bit width of the data in different bus channels is different. For any one of the first bus channel and the second bus channel, the bus channel can be a write address bus channel, a read address bus channel, a write data bus channel, a read data bus channel, or a write response bus channel. Among them, the bit width of the data in the write address bus channel and the read address bus channel can be 101 bits, the bit width of the data in the write data bus channel can be 152 bits, the bit width of the data in the read data bus channel can be 138 bits, and the bit width of the data in the write response bus channel can be 9 bits. The bit width of the data in the bus channel can be determined according to actual needs and the experience of relevant technicians, and this application does not make any specific restrictions on this.

[0115] Figure 6 is a schematic diagram of the structure of first valid data provided by an embodiment of the present application. As shown in Figure 6, the first valid data includes first data and a first channel identifier. In Figure 6, the bit width of the first channel identifier is 4 bits and the bit width of the first data is 101 bits.

[0116] Furthermore, the method further includes the bus adapter being configured to determine a transmission priority of the first valid data and the second valid data based on the first channel identifier and the second channel identifier. The transmission priority can be used to determine the order in which the valid data are transmitted. In an embodiment of the present invention, the transmission priority can be used to indicate the order in which the first valid data and the second valid data are transmitted.

[0117] S502: Determine a first payload according to the first valid data and the second valid data, wherein the first payload includes the first valid data, padding data, and at least a portion of the second valid data that are sequentially spliced ​​together.

[0118] The bus adapter may be configured to determine a first payload based on the first valid data and the second valid data. Specifically, the bus adapter may be configured to sequentially concatenate the first valid data, padding data, and the second valid data based on an alignment bit width to obtain the first payload.

[0119] In addition, the alignment bit width can be a sliding window bit width, and the window size of the sliding window bit width can be fixed. For example, the alignment bit width can be the sliding window bit width when splitting the first payload, and the sliding window bit width can also be called the sliding window reading bit width. For example, when the receiving side bare chip splits the first payload, it performs a sliding window read on the first payload according to the alignment bit width (fixed bit) each time to quickly determine the first valid data and the second valid data in the first payload. Compared with the normal situation where the receiving side bare chip performs a sliding window read on the first payload according to one bit each time, the efficiency of the receiving side bare chip in splitting the first payload is improved.

[0120] Secondly, the alignment width can be pre-set. For example, the alignment width can be pre-set by the sending side bare chip, and the sending side bare chip sends the pre-set alignment width to the receiving side bare chip; or, the alignment width can be pre-set by the receiving side bare chip, and the receiving side bare chip sends the pre-set alignment width to the sending side bare chip; or, the alignment width can be pre-configured for the sending side bare chip and the receiving side bare chip. The embodiment of the present application does not make specific restrictions on this. The size of the alignment width can be determined according to actual needs and the experience of relevant technical personnel, and the present application does not make specific restrictions on this. In actual applications, the alignment width can generally be equal to 8 bits (bit), 16 bits, 32 bits, 64 bits or 128 bits. The following embodiments all take the alignment width of 32 bits as an example.

[0121] Furthermore, whether there is padding data between the first valid data and the second valid data, and the bit width of the padding data, can be determined based on the alignment bit width. For example, the transmitting die can be configured to determine whether there is padding data between the first valid data and the second valid data, and the bit width of the padding data, based on the alignment bit width, so that the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width, i.e., the starting bit of the second valid data in the first payload is an integer multiple of the alignment bit width.

[0122] For example, when the alignment bit width is 32 bits and the bit width of the first data is 104 bits, since 104 bits is not an integer multiple of 32 bits, in order to make the starting bit of the second valid data in the first payload an integer multiple of the alignment bit width, there is padding data between the first valid data and the second valid data, and the bit width of the padding data is 24 bits. At this time, the sum of the bit width of the first valid data and the bit width of the padding data is 128 bits, which is 4 times the alignment bit width. Since the starting bit in the first payload is 0 bit, the starting bit of the second valid data in the first payload is 128 bits.

[0123] In one possible implementation, the bit width of the padding data is smaller than the alignment bit width. For example, when the alignment bit width is 32 bits, the bit width of the padding data is smaller than 32 bits. Specifically, the bus adapter can determine the bit width of the padding data based on the bit width of the first valid data and the alignment bit width. In this implementation, the bit width of the padding data is smaller than the alignment bit width, so that the sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width, that is, the starting bit width of the second valid data in the first payload is equal to an integer multiple of the alignment bit width, while increasing the amount of valid data in the first payload and improving the utilization rate of the first payload.

[0124] Furthermore, the bus adapter can be configured to determine the type of data included in the first payload based on the bit width of the first payload, the bit width of the valid data (including the bit width of the first valid data and the bit width of the second valid data), the alignment bit width, and the bit width of the channel identifier. Several cases of the type of data included in the first payload are described below.

[0125] In a first possible embodiment, if the remaining bit width of the first payload, excluding the bit width occupied by the first valid data and the padding data (including the padding data spliced ​​after the first valid data), is capable of carrying the second valid data (i.e., the remaining bit width is greater than the bit width of the second valid data), and the remaining bit width of the first payload, excluding the bit widths occupied by the first valid data, the padding data (including the padding data spliced ​​after the first valid data and the padding data spliced ​​after the second valid data), and the second valid data, is greater than the bit width of the channel identifier, this means that the first payload can still carry more valid data. In this embodiment, third valid data can be obtained, the third valid data including third data from a third bus channel, and at least a portion of the third valid data is written into the remaining bit width. In this case, the first payload includes the first valid data, padding data, the second valid data, the padding data, and at least a portion of the third valid data, which are sequentially spliced ​​together, and the sum of the bit width of the second valid data and the bit width of the padding data following the second valid data is an integer multiple of the alignment bit width.

[0126] In one possible implementation, if the bit width of the second valid data is equal to an integer multiple of the alignment bit width, and the remaining bit width in the first payload excluding the bit width occupied by the first valid data, the padding data (including the padding data spliced ​​after the first valid data) and the second valid data is greater than the bit width of the channel identifier, then there is no padding data between the second valid data and at least part of the third valid data.

[0127] Optionally, the bit width of the first payload can be determined based on actual needs and the experience of relevant technicians, and this application does not make specific restrictions on this. In actual applications, the bit width of the first payload can be 244 bits. The following embodiments all take the bit width of the first payload as 244 bits as an example.

[0128] In a second possible embodiment, if the remaining bit width of the first payload excluding the bit width occupied by the first valid data and the padding data (including the padding data spliced ​​after the first valid data) is greater than the bit width of the second valid data, and the remaining bit width of the first payload excluding the bit width occupied by the first valid data, the padding data (including the padding data spliced ​​after the first valid data and the padding data spliced ​​after the second valid data), and the second valid data is less than or equal to the bit width of the channel identifier, this means that the remaining bit width is insufficient to carry more valid data. In this embodiment, padding data can be written into the remaining bit width. In this case, the first payload includes the first valid data, padding data, the second valid data, and padding data spliced ​​in sequence.

[0129] In a third possible embodiment, if the remaining bit width of the first payload excluding the bit width occupied by the first valid data and the padding data (including the padding data spliced ​​after the first valid data) is greater than the bit width of the second valid data, and the remaining bit width of the first payload excluding the bit width occupied by the first valid data, the padding data (including the padding data spliced ​​after the first valid data) and the second valid data is less than or equal to the bit width of the channel identifier, then the padding data is written into the remaining bit width. At this time, the first payload includes the first valid data, padding data, the second valid data and padding data spliced ​​in sequence.

[0130] In a fourth possible embodiment, if the remaining bit width in the first payload excluding the bit width occupied by the first valid data and the padding data (including the padding data spliced ​​after the first valid data) is insufficient to carry the second valid data, that is, the remaining bit width in the first payload excluding the bit width occupied by the first valid data and the padding data (including the padding data spliced ​​after the first valid data) is smaller than the bit width of the second valid data, only a portion of the second valid data is padded into the first payload. In this case, the first payload includes the first valid data, the padding data, and the portion of the second valid data spliced ​​in sequence.

[0131] Furthermore, the method also includes: the bus adapter fills the remaining data of the second valid data except the part of the second valid data into the second payload, and the first payload is adjacent to the second payload; the data link layer encapsulates the second payload to obtain a second target message.

[0132] In the above possible embodiments, if the bit width of the first valid data is equal to an integer multiple of the alignment bit width, there is no padding data between the first valid data and the second valid data. At this time, the bit width of the padding data between the first valid data and the second valid data is zero.

[0133] It can be seen from the above embodiment that the amount of valid data spliced ​​into the first payload is related to the bit width of the valid data, the bit width of the first payload, and the alignment bit width.

[0134] S503: Encapsulate and send the first payload.

[0135] The data link layer encapsulates the first payload to obtain a first target message. The first target message includes a header, a first payload, and a tail. Specifically, the data link layer generates a header and a tail corresponding to the first payload, and obtains the first target message based on the header, the first payload, and the tail. The input / output interface sends the first target message to the input / output interface in the receiving-side bare chip.

[0136] Secondly, the bit width of the first message is equal to the sum of the bit width of the message header, the bit width of the first payload, and the bit width of the message trailer. For example, in practical applications, the bit width of the first target message can be 256 bits, wherein the bit width of the message header can be 1 bit, and the bit width of the message trailer can be 11 bits. In the following embodiments, the bit width of the first target message can be 256 bits, wherein the bit width of the message header can be 1 bit, the bit width of the message trailer can be 11 bits, and the bit width of the payload is 244 as an example.

[0137] Figure 7 is a schematic diagram of the structure of a target message provided by an embodiment of the present application, wherein the target message includes a message header, a payload, and a message trailer. In Figure 7, the message header has a bit width of 1 bit, the payload has a bit width of 244 bits, and the message trailer has a bit width of 11 bits as an example.

[0138] In one possible implementation, if the priority of the first valid data is higher and it cannot wait for other valid data for a long time, or, at the current moment, other valid data have been spliced ​​and no other valid data needs to be spliced, and the remaining bit width in the first payload excluding the bit width occupied by the first valid data is greater than the alignment bit width, since the bit width of the padding data is smaller than the alignment bit width, the padding data cannot be written entirely into the remaining bit width at this time, and virtual data needs to be written into part of the remaining bit width.

[0139] FIG8 is a flowchart of another data transmission method provided in an embodiment of the present application, the method comprising:

[0140] S801: Determine first valid data from a first bus channel, where the first valid data includes first data from the first bus channel.

[0141] S802: Determine a first payload according to the first valid data and the virtual data, wherein the first payload includes the first valid data, the padding data, and the virtual data concatenated in sequence, and the virtual data includes a virtual identifier, and the virtual identifier is used to indicate that the virtual data is invalid.

[0142] The virtual identifier can be used to indicate that the virtual data is invalid data. The bit width of the virtual identifier can be equal to the bit width of the channel identifier. In practical applications, the virtual identifier can be "CN:0", and the virtual data can also be called invalid data. The virtual data can be represented as VP.

[0143] S803: Encapsulate and send the first payload.

[0144] The data link layer encapsulates the first payload to obtain a first target message, which includes a message header, a first payload, and a message trailer.

[0145] In a possible embodiment, if the remaining bit width in the first payload excluding the bit width occupied by the first valid data is less than or equal to the bit width of the channel identifier, the padding data is written into the remaining bit width, wherein the first payload includes the first valid data and the padding data spliced ​​sequentially.

[0146] Figure 9 is a schematic diagram of the structure of a target message provided by the present application, which includes: a message header, a payload and a message trailer, wherein the payload includes first valid data, padding data and virtual data spliced ​​in sequence. The first valid data includes a first channel identifier "CN:1" and first data, and the virtual data includes a virtual identifier "CN:0" and virtual data. In Figure 9, the bit width of the first valid data is 12 bits, the bit width of the padding data is 20 bits, and the bit width of the virtual data is 212 bits, for example.

[0147] For ease of understanding, the data transmission method provided in this application is introduced and explained below in conjunction with Figures 10 and 11.

[0148] Figure 10 is a schematic diagram of the structure of another target message provided in an embodiment of the present application, wherein the target message includes: a message header, a payload, and a message tail, wherein the payload includes first valid data, padding data, second valid data, and padding data spliced ​​in sequence. The first valid data includes a first channel identifier and first data, and the second valid data includes a second channel identifier and second data. In Figure 10, the first channel identifier is "CN:1", the second channel identifier is "CN:2", the bit width of the first valid data and the bit width of the second valid data are both 104 bits, and the sum of the bit width of the first valid data and the bit width of the padding data is 128 bits.

[0149] Figure 11 is a schematic structural diagram of another target message provided in an embodiment of the present application, (a) in Figure 11 is a schematic structural diagram of the first target message, and (b) in Figure 11 is a schematic structural diagram of the second target message adjacent to the first target message. As can be seen from (a) in Figure 11, the first target message includes: a message header, a first payload and a message tail, wherein the first payload includes the first valid data, the padding data and part of the second valid data spliced ​​in sequence. The first valid data includes an identifier of the first channel and the first data, and the part of the second valid data includes a second channel identifier and part of the second data. As can be seen from (b) in Figure 11, the second target message includes: a message header, a second payload and a message tail, wherein the second payload includes the remaining data, padding data and third valid data of the second valid data spliced ​​in sequence except the part of the second valid data. 11 takes the first channel identified as “CN: 1”, the second channel identified as “CN: 2”, the first valid data having a bit width of 104 bits, and the second valid data having a bit width of 155 bits as an example. FIG10 does not show the third valid data.

[0150] Another data transmission method provided by an embodiment of the present application is described in detail below based on the system on chip shown in Figure 3. For a receiving-side bare die among the multiple bare die, a flow chart of the data transmission method is shown in Figure 12.

[0151] FIG12 is a flowchart of another data transmission method provided in an embodiment of the present application, the method comprising:

[0152] S120: Receive and parse the first target message to obtain a first payload.

[0153] The input / output interface receives the first target message from the input / output interface of the transmitting-side bare chip, and parses the first target message by the data link layer to obtain the first payload.

[0154] S121: Determine first valid data and at least part of second valid data according to the first payload.

[0155] The bus adapter determines the first valid data and at least a portion of the second valid data based on the first payload. Specifically, the bus adapter splits the first payload according to the alignment bit width to obtain the first valid data, padding data, and at least a portion of the second valid data.

[0156] In addition, the alignment bit width can be a sliding window bit width, and the window size of the sliding window bit width can be fixed. For example, the bus adapter performs a sliding window read on the first payload according to the alignment bit width (fixed bit) each time to obtain the first valid data, padding data, and at least a portion of the second valid data. The sliding window bit width can also be referred to as a sliding window read bit width. Compared to the bus adapter performing a sliding window read on the first payload one bit at a time under normal circumstances, this improves the efficiency of the receiving die in splitting the first payload; further, it improves the efficiency of the receiving die in processing messages.

[0157] Secondly, the alignment width can be pre-set. For example, the alignment width can be pre-set by the sending side bare chip, and the sending side bare chip sends the pre-set alignment width to the receiving side bare chip; or, the alignment width can be pre-set by the receiving side bare chip, and the receiving side bare chip sends the pre-set alignment width to the sending side bare chip; or, the alignment width can be pre-configured for the sending side bare chip and the receiving side bare chip. The embodiment of the present application does not make specific restrictions on this. The size of the alignment width can be determined according to actual needs and the experience of relevant technical personnel, and the present application does not make specific restrictions on this. In actual applications, the alignment width can generally be equal to 8 bits (bit), 16 bits, 32 bits, 64 bits or 128 bits. The following embodiments all take the alignment width of 32 bits as an example.

[0158] The first valid data includes a first channel identifier and first data, and at least part of the second valid data includes a second channel identifier and at least part of the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

[0159] S122: Send the first valid data to a first bus channel corresponding to the first valid data, and send at least a portion of the second valid data to a second bus channel corresponding to the second valid data.

[0160] Furthermore, before step S122, the method may include: the bus adapter determining, according to the first channel identifier and the second channel identifier, a sending priority of the first valid data and at least a portion of the second valid data.

[0161] Specifically, the first valid data and at least a portion of the second valid data are sent according to their sending priorities.

[0162] In a possible embodiment, if at least part of the second valid data is partial second valid data, a second target message adjacent to the first target message is received and parsed to obtain a second payload; based on the second payload, the remaining data in the second valid data other than the partial second valid data is determined; based on the remaining data and the partial second valid data, the second valid data is determined and sent.

[0163] Furthermore, before step S122, the method may include: deleting the first channel identifier in the first valid data and deleting the second channel identifier in at least part of the second valid data.

[0164] In a possible embodiment, the method further includes: determining the first valid data, the second valid data and at least part of the third valid data based on the first payload; sending the first valid data to the first bus channel corresponding to the first valid data, sending the second valid data to the second bus channel corresponding to the second valid data, and sending at least part of the third valid data to the third bus channel corresponding to the third valid data.

[0165] FIG13 is a flowchart of another data transmission method provided in an embodiment of the present application, the method comprising:

[0166] S130: Receive and parse the first target message to obtain a first payload.

[0167] S131: Determine first valid data according to the first payload.

[0168] S132: Send the first valid data to a first bus channel corresponding to the first valid data.

[0169] The embodiment of the present application provides a data transmission method, the method comprising: determining first valid data from a first bus channel, determining second valid data from a second bus channel; determining a first payload based on the first valid data and the second valid data, wherein the first payload includes the first valid data, padding data, and at least part of the second valid data spliced ​​in sequence, and the sum of the bit width of the first valid data and the bit width of the padding data is an integer multiple of the alignment bit width; encapsulating the first payload into a first target message, and sending the first target message. In this process, the first payload includes the first valid data, padding data, and at least part of the second valid data, so that there is no idle (remaining) bit width in the first payload, and when the first payload is encapsulated into the first target message and sent to the receiving side bare chip, the efficiency of data transmission is improved. On the other hand, after the receiving side bare chip receives the first target message, it can quickly obtain the first valid data and at least part of the second valid data according to the alignment bit width, reducing the processing delay of the receiving side bare chip and improving processing efficiency.

[0170] It is understandable that, in order to realize the above functions, the data transmission device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the steps of the data transmission methods of each example described in the embodiments herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0171] In the embodiment of the present application, the data transmission device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods.

[0172] In the case of dividing the functional modules according to their respective functions, FIG14 shows a possible structural diagram of a data transmission device involved in the above embodiment, which includes: an acquisition unit 100, a determination unit 101, an encapsulation unit 102, and a sending unit 103. The acquisition unit 100 is used to support the data transmission device in executing S501 of the above method embodiment; the determination unit 101 is used to support the data transmission device in executing S502 of the above method embodiment; the encapsulation unit 102 and the sending unit 103 are used to support the data transmission device in executing S503 of the above method embodiment.

[0173] In hardware implementation, the acquisition unit 100 can be the receiving module 401 shown in Figure 4, the determination unit 101 can be the splicing module / splitting module 404 shown in Figure 4, the encapsulation unit 102 can be the data link layer 332 shown in Figure 3, and the sending unit 103 can be the input / output interface 333 shown in Figure 3.

[0174] Figure 15 shows a possible structural diagram of a data transmission device involved in the above embodiment, which includes a receiving unit 201, a parsing unit 202, a determining unit 203, and a sending unit 204. The receiving unit 201 and the parsing unit 202 are used to support the data transmission device in executing S120 of the above method embodiment; the determining unit 203 is used to support the data transmission device in executing S121 of the above method embodiment; and the sending unit 204 is used to support the data transmission device in executing S122 of the above method embodiment.

[0175] In hardware implementation, the receiving unit 201 may be the receiving module 401 shown in FIG4 , the parsing unit 202 and the determining unit 203 may be the splicing module / splitting module 404 shown in FIG4 , and the sending unit 204 may be the input / output interface 333 shown in FIG3 .

[0176] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here. The device provided in the embodiment of the present application is used to perform the corresponding functions in the above embodiment, so it can achieve the same effect as the above method.

[0177] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0178] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0179] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing the device to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0180] In another aspect of the present application, a die is provided. The die includes a logic device, and the logic device is used to perform one or more steps S501 to S503 in the above method embodiment.

[0181] In another aspect of the present application, a die is provided. The die includes a logic device, and the logic device is used to perform one or more steps S801 to S803 in the above method embodiment.

[0182] In another aspect of the present application, a die is provided. The die includes a logic device, and the logic device is used to perform one or more steps S120 to S122 in the above method embodiment.

[0183] In another aspect of the present application, a die is provided. The die includes a logic device, and the logic device is used to perform one or more steps S130 to S132 in the above method embodiment.

[0184] Another aspect of the present application provides a system on chip, which includes a plurality of dies coupled to each other, the plurality of dies including a first die and a second die, the first die being used to perform one or more steps S501 to S503 in the above method embodiment, or the first die being used to perform one or more steps S801 to S803 in the above method embodiment; the second die being used to perform one or more steps S120 to S122 in the above method embodiment; or the second die being used to perform one or more steps S130 to S132 in the above method embodiment.

[0185] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are run on a data transmission device, the relevant steps in the above method embodiment are executed.

[0186] In another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is run on a computer device, the data transmission device executes the relevant steps in the above method embodiments.

[0187] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0188] The bit width of the target message mentioned in S503 and Figure 7 above can be 256 bits. This does not mean that the bit width of the target message is a fixed value of 256 bits. In actual products, the bit widths of the message header, payload, and message tail in the target message in Figure 7 can all have multiple length modes. For example, the bit width of the payload can be selected and set from a variety of preset bit width values. Correspondingly, the bit width of the message header is not limited to 1 bit in Figure 7, so that the message header can carry more indicator bits, such as an indicator bit for indicating the bit width mode of the payload. Assuming that there are 4 bit width modes to choose from for the bit width of the payload, only 2 bits of indicator bits are needed in the message header to indicate the bit width length of the payload in the target message. Specifically, in the first bit width mode, the payload width can be X bits, and the indicator bit can be "00" to indicate that the payload width in the current target message uses the first bit width mode, i.e., X bits. Similarly, in the second bit width mode, the payload width can be Y bits, and the corresponding indicator bit can be "01", where X and Y are integers and X is usually not equal to Y. And so on. The indicator bit "10" indicates that the payload uses the third bit width mode, and the indicator bit "11" indicates that the payload uses the fourth bit width mode.

[0189] In addition to the target message bit width, the bit widths of the various information bits mentioned above can also be set to other values. For example, the channel identifier bit width can be 5 bits; the data in the write address bus channel and the read address bus channel can be 107 bits wide; the data in the write data bus channel can be 157 bits wide; the data in the read data bus channel can be 143 bits wide; and the data in the write response bus channel can be 14 bits wide.

Claims

1. A data transmission method, characterized in that: The method comprises: Obtaining first valid data and second valid data, wherein the first valid data includes first data from a first bus channel, and the second valid data includes second data from a second bus channel; Determining a first payload according to the first valid data and the second valid data, wherein the first payload includes the first valid data, padding data, and at least part of the second valid data that are sequentially spliced ​​together; The first payload is encapsulated and sent.

2. The method according to claim 1, characterized in that The sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width.

3. The method according to claim 2, characterized in that The bit width of the padding data is smaller than the alignment bit width.

4. The method according to claim 2 or 3, characterized in that The alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits or 128 bits.

5. The method according to any one of claims 1 to 4, characterized in that The first valid data includes a first channel identifier and the first data, and the second valid data includes a second channel identifier and the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

6. The method according to claim 5, characterized in that The method further comprises: The sending priorities of the first valid data and the second valid data are determined according to the first channel identifier and the second channel identifier.

7. The method according to claim 5 or 6, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are both 4 bits.

8. The method according to any one of claims 1 to 7, characterized in that The determining the first payload according to the first valid data and the second valid data includes: If the bit width of the first payload is insufficient to carry the second valid data, only a portion of the second valid data is filled into the first payload.

9. The method according to claim 8, characterized in that The method further comprises: Filling the second payload with the remaining data of the second valid data except the part of the second valid data; The second payload is encapsulated and sent.

10. The method according to any one of claims 5 to 9, characterized in that: The determining the first payload according to the first valid data and the second valid data includes: If the remaining bit width of the first payload excluding the bit widths occupied by the first valid data, the padding data, and the second valid data is less than or equal to the bit width of the channel identifier, the padding data is written into the remaining bit width.

11. The method according to claim 10, characterized in that The method further comprises: If the remaining bit width is greater than the bit width of the channel identifier, obtaining third valid data, wherein the third valid data includes third data from a third bus channel; Determining the first payload according to the first valid data and the second valid data includes: determining the first payload according to the first valid data, the second valid data and the third valid data, wherein the The first payload includes the first valid data, the padding data, the second valid data, the padding data and at least part of the third valid data that are spliced ​​in sequence.

12. The method according to any one of claims 1 to 11, characterized in that The encapsulating and sending the first payload includes: Encapsulating the first payload to obtain a first target message, where the first target message includes a message header and a message trailer; Send the first target message.

13. The method according to claim 12, characterized in that The message header includes an indication bit for indicating a bit width mode of the first payload, wherein the first payload has different bit width lengths in different bit width modes.

14. The method according to claim 5 or 6, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are 5 bits.

15. A data transmission method, characterized in that: The method comprises: Obtaining first valid data, where the first valid data includes first data from a first bus channel; Determining a first payload according to the first valid data and the dummy data, wherein the first payload includes the first valid data, padding data, and the dummy data concatenated in sequence, and the dummy data includes a dummy identifier, and the dummy identifier is used to indicate that the dummy data is invalid; The first payload is encapsulated and sent.

16. A data transmission method, characterized in that: The method comprises: Receive and parse the first target message to obtain a first payload; determining, based on the first payload, first valid data and at least a portion of second valid data; The first valid data is sent to a first bus channel corresponding to the first valid data, and at least a portion of the second valid data is sent to a second bus channel corresponding to the second valid data.

17. The method according to claim 16, characterized in that The determining, according to the first payload, first valid data and at least part of second valid data includes: The first payload is split according to the alignment bit width to obtain the first valid data, padding data and at least part of the second valid data.

18. The method according to claim 17, characterized in that The sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width.

19. The method according to claim 15 or 16, characterized in that The bit width of the padding data is smaller than the alignment bit width.

20. The method according to any one of claims 17 to 19, characterized in that: The alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits or 128 bits.

21. The method according to any one of claims 16 to 20, characterized in that The first valid data includes a first channel identifier and first data, and at least part of the second valid data includes a second channel identifier and at least part of the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

22. The method according to claim 21, characterized in that The method further comprises: The sending priority of the first valid data and at least part of the second valid data is determined according to the first channel identifier and the second channel identifier.

23. The method according to claim 21 or 22, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are both 4 bits.

24. The method according to any one of claims 21 to 23, characterized in that Before sending the first valid data to a first bus channel corresponding to the first valid data and sending at least a portion of the second valid data to a second bus channel corresponding to the second valid data, the method further includes: The first channel identifier in the first valid data and the second channel identifier in at least part of the second valid data are deleted.

25. The method according to any one of claims 16 to 24, characterized in that: The sending at least part of the second valid data to a second bus channel corresponding to the second valid data includes: If at least part of the second valid data is part of the second valid data, receiving and parsing the second target message to obtain a second payload; determining, according to the second payload, remaining data in the second valid data excluding the portion of the second valid data; The second valid data is determined based on the remaining data and the portion of the second valid data and is sent.

26. The method according to any one of claims 16 to 25, characterized in that The determining, according to the first payload, first valid data and at least part of second valid data includes: determining, based on the first payload, the first valid data, the second valid data, and at least a portion of the third valid data; The first valid data is sent to a first bus channel corresponding to the first valid data, the second valid data is sent to a second bus channel corresponding to the second valid data, and at least part of the third valid data is sent to a third bus channel corresponding to the third valid data.

27. The method according to any one of claims 16 to 26, characterized in that The target message includes: a message header and a message tail.

28. The method according to claim 27, characterized in that The method further comprises: An indication bit is obtained from the message header, where the indication bit is used to indicate a bit width mode of the first payload, wherein the first payload has different bit width lengths in different bit width modes.

29. The method according to claim 21 or 22, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are 5 bits.

30. A data transmission method, characterized in that: The method comprises: Receive and parse the first target message to obtain a first payload; Determining first valid data according to the first payload, wherein the first payload includes the first valid data, padding data, and dummy data, and the dummy data includes a dummy identifier, and the dummy identifier is used to indicate that the dummy data is invalid; The first valid data is sent to a first bus channel corresponding to the first valid data.

31. A data transmission device, characterized in that: The device comprises: an acquiring unit, configured to acquire first valid data and second valid data, wherein the first valid data includes first data from a first bus channel, and the second valid data includes second data from a second bus channel; A determining unit, configured to determine a first payload according to the first valid data and the second valid data, wherein the first payload includes the first valid data, padding data, and at least part of the second valid data that are sequentially spliced ​​together. Effective data; an encapsulation unit, configured to encapsulate the first payload; A sending unit is used to send the encapsulated first payload.

32. The device according to claim 31, characterized in that The sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width.

33. The device according to claim 32, characterized in that The bit width of the padding data is smaller than the alignment bit width.

34. The device according to claim 31 or 32, characterized in that The alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits or 128 bits.

35. The device according to any one of claims 31 to 34, characterized in that The first valid data includes a first channel identifier and the first data, and the second valid data includes a second channel identifier and the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

36. The device according to claim 35, characterized in that The determining unit is further configured to: The sending priorities of the first valid data and the second valid data are determined according to the first channel identifier and the second channel identifier.

37. The device according to claim 35 or 36, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are both 4 bits.

38. The device according to any one of claims 31 to 37, characterized in that The determining unit is further configured to: If the bit width of the first payload is insufficient to carry the second valid data, only a portion of the second valid data is filled into the first payload.

39. The device according to claim 38, characterized in that The determining unit is further configured to fill the second payload with the remaining data of the second valid data except the portion of the second valid data; The encapsulation unit is further configured to encapsulate the second payload; The sending unit is further configured to send the encapsulated second payload.

40. The device according to any one of claims 35 to 39, characterized in that The determining unit is further configured to: If the remaining bit width of the first payload excluding the bit widths occupied by the first valid data, the padding data, and the second valid data is less than or equal to the bit width of the channel identifier, the padding data is written into the remaining bit width.

41. The device according to claim 40, characterized in that The acquiring unit is further configured to acquire third valid data if the remaining bit width is greater than or equal to the bit width of the channel identifier, wherein the third valid data includes third data from a third bus channel; The determination unit is further used to determine the first payload based on the first valid data, the second valid data and the third valid data, wherein the first payload includes the first valid data, padding data, the second valid data, padding data and at least part of the third valid data spliced ​​in sequence.

42. The device according to any one of claims 31 to 41, characterized in that The encapsulation unit encapsulates the first payload to obtain a first target message, where the first target message includes a message header and a message trailer. The sending unit sends the first target message.

43. The device according to claim 42, characterized in that The message header includes an indication bit for indicating a bit width mode of the first payload, wherein the first payload has different bit width lengths in different bit width modes.

44. The device according to claim 35 or 36, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are 5 bits.

45. A data transmission device, characterized in that The device comprises: an acquiring unit, configured to acquire first valid data, where the first valid data includes first data from a first bus channel; a determining unit, configured to determine a first payload based on the first valid data and the dummy data, wherein the first payload includes the first valid data, padding data, and the dummy data concatenated in sequence, and the dummy data includes a dummy identifier, and the dummy identifier is used to indicate that the dummy data is invalid; an encapsulation unit for encapsulating the first payload; A sending unit is used to send the encapsulated first payload.

46. ​​A data transmission device, characterized in that The device comprises: A receiving unit, configured to receive a first target message; a parsing unit, configured to parse the first target message to obtain a first payload; a determining unit, configured to determine first valid data and at least part of second valid data according to the first payload; The sending unit is configured to send the first valid data to a first bus channel corresponding to the first valid data, and send at least a portion of the second valid data to a second bus channel corresponding to the second valid data.

47. The device according to claim 46, characterized in that The determining unit is further configured to: The first payload is split according to the alignment bit width to obtain the first valid data, padding data and at least part of the second valid data.

48. The device according to claim 45, characterized in that The sum of the bit width of the first valid data and the bit width of the padding data is equal to an integer multiple of the alignment bit width.

49. The device according to claim 47 or 48, characterized in that The bit width of the padding data is smaller than the alignment bit width.

50. The device according to any one of claims 47 to 49, characterized in that The alignment bit width is equal to 8 bits, 16 bits, 32 bits, 64 bits or 128 bits.

51. The device according to any one of claims 47 to 50, characterized in that The first valid data includes a first channel identifier and first data, and at least part of the second valid data includes a second channel identifier and at least part of the second data, wherein the first channel identifier is used to indicate the first bus channel, and the second channel identifier is used to indicate the second bus channel.

52. The device according to claim 51, characterized in that The determining unit is further configured to: The sending priority of the first valid data and at least part of the second valid data is determined according to the first channel identifier and the second channel identifier.

53. The device according to claim 51 or 52, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are both 4 bits.

54. The device according to any one of claims 51 to 53, characterized in that The apparatus further includes a deletion unit, configured to: The first channel identifier in the first valid data and the second channel identifier in at least part of the second valid data are deleted.

55. The device according to any one of claims 46 to 54, characterized in that If at least part of the second valid data is part of the second valid data, the receiving unit is further configured to receive and parse the second target message to obtain a second payload; The determining unit is further configured to determine, based on the second payload, remaining data in the second valid data excluding the portion of the second valid data; The determining unit is further configured to determine the second valid data based on the remaining data and the portion of the second valid data; The sending unit is further configured to send the second valid data.

56. The device according to any one of claims 46 to 55, characterized in that The determining unit is further configured to determine the first valid data, the second valid data, and at least part of the third valid data based on the first payload; The sending unit is further used to send the first valid data to the first bus channel corresponding to the first valid data, send the second valid data to the second bus channel corresponding to the second valid data, and send at least part of the third valid data to the third bus channel corresponding to the third valid data.

57. The device according to any one of claims 46 to 56, characterized in that The target message includes: a message header and a message tail.

58. The device according to claim 57, characterized in that The parsing unit is further configured to obtain an indication bit from the message header, where the indication bit is configured to indicate a bit width mode of the first payload, wherein the first payload has different bit width lengths in different bit width modes.

59. The device according to claim 51 or 52, characterized in that The bit width of the first channel identifier and the bit width of the second channel identifier are both 5 bits.

60. A data transmission device, characterized in that The device comprises: A receiving unit, configured to receive and parse the first target message to obtain a first payload; a determining unit, configured to determine first valid data according to the first payload, wherein the first payload includes the first valid data, padding data, and dummy data, the dummy data includes a dummy identifier, and the dummy identifier is used to indicate that the dummy data is invalid; A sending unit is configured to send the first valid data to a first bus channel corresponding to the first valid data.

61. A system on chip, characterized in that The system on chip includes multiple dies coupled to each other, the multiple dies including a first die and a second die, the first die being used to execute the data transmission method according to any one of claims 1 to 14, or the first die being used to execute the data transmission method according to claim 15; the second die being used to execute the data transmission method according to any one of claims 16 to 27, or the second die being used to execute the data transmission method according to claim 30.

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