Medium laser accelerator micro-nano acceleration structure and preparation method

Abstract

The application provides a medium laser accelerator micro-nano acceleration structure preparation method, a wafer side wall is processed by using FIB, an ion beam is used to bombard a 5mm-long side, a 0.2mm-thick thickness is engraved, a smooth and flat plane can be obtained due to the parallelism between the ion beam and the thickness plane, and the problem of low efficiency is solved; a scribe line with a width of 3um is patterned by ultraviolet lithography, the depth of inductively coupled plasma deep silicon etching is greater than 40um, a grating hollow area is patterned by back alignment of ultraviolet lithography, the depth of inductively coupled plasma deep silicon etching is greater than 160um, the grating hollow area is positioned by ultraviolet lithography, the whole thickness is engraved by double-sided deep silicon etching, and a smooth and flat grating to-be-processed plane is obtained. The medium laser accelerator micro-nano acceleration structure preparation is performed at the high platform of the square hole obtained by etching the side and the back, and the shielding of electrons in the electron acceleration experiment is avoided; the whole processing procedure can obtain a small-size side micro-nano structure which can be put into a TEM pole piece, and the experimental requirements are met.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to a micro / nano acceleration structure for a dielectric laser accelerator and its fabrication method. Background Technology

[0002] Particle accelerators are crucial tools for exploring the microscopic world, widely used in industry, agriculture, medicine, and scientific research. Dielectric laser accelerators are currently recognized worldwide as one of the most promising miniaturization technologies for accelerators. By utilizing micro- and nano-scale dielectric structures to control the laser-driven light field, they can achieve small sizes. Furthermore, dielectric materials have a higher breakdown threshold than metals, resulting in higher acceleration gradients. One of the core technologies of dielectric laser accelerators is the fabrication of micro- and nano-accelerator structures. Different fabrication methods yield accelerator structures with varying degrees of practicality; therefore, it is necessary to select a suitable fabrication method for electron acceleration experiments conducted in TEM (Transient Electron Mechanics) equipment.

[0003] like Figure 1 As shown, the method for fabricating a dielectric laser accelerator disclosed in patent CN202111125969.8 is as follows: the acceleration region is formed by bonding two chips, and a grating is formed on both chips. The fabrication of the acceleration region includes the following steps: growing a first chip using vapor phase epitaxial deposition, which includes a first confinement layer and a top reflector; performing photoresist homogenization on the first confinement layer, followed by photolithography to obtain a preset mask to expose a position with a width and length equivalent to the acceleration channel; and performing wet or dry etching to create an etching trench with an etching depth of 0.35λ ± 0.05λ. The wavelength of the incident light is determined, and then the adhesive is removed, and positioning marks are made on the first confinement layer. A second chip is grown using vapor phase epitaxy, which includes a bottom mirror and an active region. A second confinement layer is grown on top of the active region, and a second grating with a depth of L is etched on the second confinement layer. Then, positioning marks are made on the second confinement layer, where L = 2(n-1) ± 0.1λ = 0.5λ ± 0.1λ, λ is the wavelength of the incident light, and n is the refractive index of the confinement layer. The first chip and the second chip are bonded according to the positioning marks to obtain an acceleration region containing the acceleration channel, wherein the acceleration channel has a grating on only one side. Existing technical solution two (Stanford doctoral dissertation), such as... Figure 2As shown, the accelerator equipment was fabricated on a 500 nm device layer at the Stanford Nanofabrication Facility (SNF) and the Stanford Nanofabrication Shared Facility (SNSF), with a 3 μm buried oxide insulator silicon wafer purchased from Soitec. A 330 nm thick ZEP-520A electron beam resist was patterned using a JEOL JBC-6300FS electron beam lithography tool, utilizing the accelerator, waveguide, and grating coupler structure. Electron beam writing involved immersion in dimethyl ether for 40 seconds, followed by immersion in a 25% methyl isobutyl ketone (25%) / 2-propanol (75%) solution for 30 seconds, and finally immersion in a 2-propanol bath for 30 seconds. Samples were subjected to reactive ion etching using a C2F6 breakthrough step, followed by BCl3 / Cl2 / O2 chemical master etching. Resistance was removed by overnight immersion in 1165 solution, followed by cleaning with a piranha solution (4:1 ratio of sulfuric acid and 30% hydrogen peroxide).

[0004] The shortcomings of existing fabrication methods are as follows: Current micro / nano lithography is a planar processing technique, typically involving etching, deposition, and growth on a wafer plane. Wafer areas are usually on the order of 10 cm² or larger. Regardless of whether a dicing-then-lithography or lithography-then-dicing approach is used, the planar dimensions of the chip containing the micro / nano accelerator structure are generally no less than 2 mm due to the clamping or fixing required for photoresist coating and dicing processes. Taking a grating as an example, in TEM electron acceleration experiments, electrons need to graze across the grating surface. Considering electron aggregation, positioning, and measurement stability, the length of the plane containing the grating surface must be less than 0.3 mm. Existing fabrication techniques do not meet this requirement. Using thinning methods commonly used in TEM sample preparation, such as mechanical grinding and chemical polishing, can easily damage the grating structure. Therefore, a fabrication method that directly prepares the sample to the dimensions required for TEM samples during micro / nano fabrication is needed.

[0005] The sample stage used in electron accelerator experiments is approximately 4mm x 5.5mm in size (e.g., ...). Figure 3 The blue area shows the white part, which is hollow to allow electrons to pass through. The green area is a schematic diagram of the small piece. The 5mm length ensures that the small piece is fixed on both sides and does not exceed the size limit. The 2mm width is to leave a gap for electrons to pass through. Summary of the Invention

[0006] In view of this, the present invention provides a micro / nano acceleration structure for a dielectric laser accelerator and a method for its fabrication.

[0007] A method for fabricating a dielectric laser accelerator micro / nano acceleration structure includes:

[0008] a. Cut a silicon wafer with a thickness of 0.2mm into rectangular silicon wafers with a height of 0.2mm;

[0009] b. Deposit a 2μm thick silicon oxide film on one side of a rectangular silicon wafer;

[0010] c. Define the side of the rectangular silicon wafer without silicon oxide film as the front side and the other side as the back side; perform ultraviolet lithography on the front side of the rectangular silicon wafer to form a scribe line 6 with a width of 3μm on the center line of the length direction.

[0011] d. Etch the scribing line 6 to a depth >40μm;

[0012] e. At the very center of the side of the rectangular silicon wafer coated with silicon oxide film, a square countersunk hole with a side length of 40μm is formed by ultraviolet photolithography, and a scribing line 7 is formed on the center line of the length direction, with an etching depth >160μm.

[0013] f. Crack the rectangular silicon wafer along the center line 6 and 7 to form a structure with two smooth and flat planes.

[0014] g. After the rectangular silicon wafer is split along the scribe line, there is a countersunk hole on one side of the square countersunk hole, and the other side of the countersunk hole is raised relative to the countersunk hole, thus forming a step. On this step, a focused ion beam dual-beam etching system is used to perform direct grating writing to obtain a micro-nano accelerated structure.

[0015] Preferably, the depth of the square countersunk hole is 20 μm.

[0016] Preferably, an inductively coupled plasma deep silicon lithography device is used.

[0017] Preferably, two small grooves are made on both sides of the etched grating position as positioning marks 5; when conducting experiments, the grating is positioned between these two positioning marks 5.

[0018] The present invention has the following beneficial effects:

[0019] This invention provides a method for fabricating micro / nano-accelerator structures for dielectric laser accelerators. The method utilizes FIB (fiber optic lithography) to process the wafer sidewalls. An ion beam bombards a 5mm long edge, etching through a 0.2mm thickness. Because the ion beam is parallel to the thickness plane, a smooth and flat surface is obtained, solving the problem of low efficiency. Ultraviolet (UV) lithography patterns 3μm wide scribe lines, and inductively coupled plasma (ICP) deep silicon etching (DSI) depths >40μm. UV lithography aligns the patterned grating cutout area with the back side, and ICP DSI etching depths >160μm. The grating cutout area is then positioned using UV lithography, and the entire thickness is etched through using double-sided DSI, resulting in a smooth and flat grating surface. The dielectric laser accelerator micro / nano-accelerator structure is fabricated on the raised platform of the square holes etched on the side and back sides, avoiding electron obstruction during electron acceleration experiments. The entire process yields small-sized side micro / nano-structures that can be placed in TEM pole pieces, meeting experimental requirements. Attached Figure Description

[0020] Figure 1 The dielectric laser accelerator structure disclosed in patent CN202111125969.8;

[0021] Figure 2 This is an etching process for a dielectric laser accelerator structure at Stanford University.

[0022] Figure 3 This is a schematic diagram showing the placement of the dielectric laser accelerator micro / nano acceleration structure of the present invention on an electron acceleration experimental sample stage;

[0023] Figure 4 This is a schematic diagram of the final structure of the dielectric laser accelerator micro / nano acceleration structure of the present invention;

[0024] Figures 5(a) and 5(b) show the front and back etching patterns of the silicon wafer in step ce, respectively.

[0025] Figure 6 The images show front views of the silicon wafers in Figures 5(a) and 5(b) after they have been separated into two halves.

[0026] Figure 7 The first half of the silicon wafer in Figure 5(a) and Figure 5(b) is shown with its side facing upwards.

[0027] Figure 8 The smooth surface formed by ion polishing and the two deposited markers.

[0028] Among them, 1-Electron acceleration experimental sample stage, 2-Micro-nano acceleration structure, 3-Square countersunk hole, 4-Raster etching area, 5-Positioning mark, 6-Scribble line on the front side of silicon wafer, 7-Scribble line on the back side of silicon wafer, 8-Deposited mark. Detailed Implementation

[0029] like Figure 4 As shown, this invention utilizes a relatively thin silicon wafer sidewall (approximately 0.2 mm) for structural etching. The back hollow area is a further thinning method. When the front side is deeply etched (>40 micrometers), the plane of the accelerated structure etching area will be tilted, and only the 40-micrometer portion will be etched. It is also necessary to ensure that after the accelerated structure is etched on the side, the etched area is still a protruding part. Therefore, a part of the back side needs to be hollowed out from bottom to top. The entire structure has a stepped structure when viewed from the side, and the surface above the step is the accelerated structure etching area. The positioning marks are two vertical lines etched through on both sides of the accelerated structure etching area. The purpose is to quickly locate the accelerated structure etching area under the observation of a transmission electron microscope.

[0030] A specific implementation scheme for the fabrication method of the dielectric laser accelerator micro / nano acceleration structure of the present invention is as follows:

[0031] a. As shown in Figure 5(a), a silicon wafer with a thickness of 0.2 mm is cut into a cuboid silicon wafer with a height of 0.2 mm. The subsequent processing of the grating structure is carried out on this thickness so that it can be directly placed on the TEM sample stage in the electron acceleration scheme (it cannot be too thick).

[0032] b. Deposit a 2μm thick silicon oxide film on the upper or lower surface of the rectangular silicon wafer;

[0033] c. As shown in Figure 5(a), the side of the rectangular silicon wafer without silicon oxide film is defined as the front side, and the other side is the back side; UV lithography is performed on the front side to form a scribe line 6 with a width of 3μm on the center line of the length direction.

[0034] d. The scribe line 6 is etched to a depth of >40μm using an inductively coupled plasma deep silicon etching device;

[0035] e. As shown in Figure 5(b), a square countersunk hole with a side length of 40 μm and a depth of approximately 20 μm is formed at the center of the back side of the silicon oxide film using ultraviolet lithography. A scribe line 7 is formed along the centerline of the length direction, and its etching depth is >160 μm using inductively coupled plasma deep silicon lithography. Thus, the total depth of the scribe line 6 and scribe line 7 exceeds the height of the cuboid silicon wafer by 0.2 mm, which is beneficial for wafer cutting. Now, a scribe line with a depth of 40 μm is etched on the front side, and then a scribe line and square hole with a depth of 160 μm are etched on the back side to penetrate the silicon wafer. This invention involves etching a thickness of 200 μm in two steps. Direct etching is not performed because it would break the surface during processing, thus avoiding damage to the smooth plane. The selection of the 40 μm side length of the square countersunk hole is related to the length of the grating to be processed. During electron acceleration experiments, this countersunk hole can be used to locate the position of the grating.

[0036] f. Cleave the rectangular silicon wafer along the center line at points 6 and 7 to form a structure with two smooth, flat planes, as shown. Figure 6 and Figure 7 As shown;

[0037] g, such as Figure 7 As shown, after the rectangular silicon wafer is split along the scribe line, due to the square countersinks etched on the back side, there is a countersink on one side of the fracture surface of the silicon wafer, and the other side is raised relative to the countersink, thus forming a step with a height of 40μm. On this step, a focused ion beam dual-beam etching system is used to perform direct grating writing.

[0038] It should be noted that the width of the scribe line 6 on the front side of the cuboid silicon wafer is larger than the width of the scribe line 7 on the back side, so the remaining part after etching on the front side can be seen when viewed from the front. Besides thinning the silicon wafer to form a protrusion, the square countersunk hole also provides positioning for the accelerating grating during electron acceleration experiments. The side length of the square countersunk hole is the same as the width of the grating, and the width of the scribe line on the front side is larger than the width of the scribe line on the back side. Figure 6 As shown, there is a groove when viewed from the front; this groove is the location of the accelerating grating. If the size of the square countersunk hole is too large (for example, by polishing the side directly with an ion polisher to create this square hole) or if the width of the grating to be etched later is smaller than the side length of the square hole, the square countersunk hole will not have a positioning effect. In this case, two additional 1μm wide grooves need to be made on both sides of the grating location as positioning marks 5. During the experiment, the grating will be positioned between these two positioning marks 5. The silicon wafer itself is not conductive. After applying conductive adhesive, it is placed in the sample chamber of the FIB equipment. The sample is observed through the electron beam to locate the position of positioning mark 5. The grating is then fabricated according to the layout, starting from the edge (the optimal position for electron beam focusing during electron acceleration experiments is at the edge).

[0039] The area of ​​ultraviolet lithography can be 10 cm in size, and multiple sets of samples can be made at the same time. Each set is about 4 mm * 5 mm in size. A set of samples is shown in Figure 5(a) and Figure 5(b), and can be separated into two pieces.

[0040] This invention also provides a method for preparing a smooth surface using an ion polishing instrument:

[0041] a. Obtain a small piece measuring 2mm*5mm*0.2mm;

[0042] b. Using an ion polisher, polish the 5mm thick surface of the 2mm*5mm small piece to obtain a polished surface with an area of ​​0.5mm*0.2mm and a depth of 1μm;

[0043] c. Locate the polished surface using electron beam observation, and use an ion beam to etch the grating near one edge;

[0044] d. Deposit two small dots with a diameter of 1 μm on both sides of the grating as markers for the location of the grating. (See etching diagram 8.) Figure 8 As shown:

[0045] The minimum size of the ion polisher is large, and the polished surface with an area of ​​0.5mm*0.2mm exceeds the field of view of the TEM. It is necessary to deposit growth positioning and alignment of markers, and the markers are easily obscured by roughness or dirt on the sample edges.

[0046] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a medium laser accelerator micro-nano acceleration structure, characterized in that, The method comprises the following steps: a. cutting a silicon wafer with a thickness of 0.2 mm into a cuboid silicon wafer with a height of 0.2 mm; b. coating a 2-μm-thick silicon oxide film on one side of the cuboid silicon wafer; c. defining the side without the silicon oxide film as the front side and the other side as the back side of the cuboid silicon wafer, and performing ultraviolet lithography on the front side to form a first scribing line (6) with a width of 3 μm on the middle line in the length direction; d. etching the first scribing line (6) to a depth of > 40 μm; e. performing ultraviolet lithography on the front center of the side of the cuboid silicon wafer coated with the silicon oxide film to form a square-shaped sink hole with a side length of 40 μm and a depth of 20 μm, and forming a second scribing line (7) on the middle line in the length direction, and etching the second scribing line (7) to a depth of > 160 μm; f. splitting the cuboid silicon wafer along the first scribing line (6) and the second scribing line (7) to form a structure with two smooth and flat surfaces; g. after splitting the cuboid silicon wafer along the scribing lines, one side edge of the square-shaped sink hole is concave, and the other side edge is convex relative to the sink hole, thereby forming a step, and performing grating direct writing on the step by using a focused ion beam double-beam etching system to obtain a micro-nano acceleration structure.

2. The method of claim 1, wherein the method further comprises: The etching of the first scribing line (6) and the second scribing line (7) is performed by using an inductively coupled plasma deep silicon etching device.

3. The method of claim 1, wherein the method further comprises: depositing a dielectric layer on the substrate; and patterning the dielectric layer to form a plurality of dielectric pillars on the substrate. Two small grooves are formed on both sides of the etched grating as positioning marks (5), and the grating is located between the two positioning marks (5) when the experiment is performed.

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