Deposition mask and method for manufacturing the same

Abstract

Disclosed are a deposition mask and a method for manufacturing the deposition mask, the method comprising: preparing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an upper silicon substrate, a lower silicon substrate and an insulating layer between the upper silicon substrate and the lower silicon substrate; forming a mask diaphragm having a plurality of openings by patterning the upper silicon substrate; forming a first protective layer on the upper silicon substrate and forming a second protective layer on the lower silicon substrate; forming a unit opening by patterning the lower silicon substrate; and removing the first protective layer and the second protective layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0131143 filed in the Korean Intellectual Property Office on September 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a deposition mask and a method of manufacturing the deposition mask. Background Art

[0004] Wearable devices that are in the form of glasses or helmets and focus images at a position close to the user's eyes are being developed. For example, the wearable device may be a head-mounted display (HMD) device or augmented reality (AR) glasses. Such wearable devices provide augmented reality (hereinafter referred to as "AR") screens (or images) or virtual reality (hereinafter referred to as "VR") screens (or images) to the user.

[0005] In order to allow users to use wearable devices (such as HMD devices and AR glasses) for a long time without dizziness, wearable devices should exhibit a display specification of at least about 2000 PPI (pixels per inch). In order to meet this standard, organic light emitting diode on silicon (OLEDoS) technology has emerged, which is a high-resolution small organic light emitting element display device. OLEDoS is a technology for setting an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is set.

[0006] In order to manufacture a high-resolution display device that exhibits about 2000 PPI or more, a high-resolution deposition mask is required. Silicon masks that can form masks with the precision of semiconductor processes are being studied and developed. A silicon mask is a mask that deposits an inorganic film pattern on a silicon substrate and allows the inorganic film pattern to act as a mask diaphragm. However, due to the thin mask diaphragm, the silicon mask is susceptible to stress. Summary of the invention

[0007] Embodiments of the present disclosure provide a deposition mask that is thin but has strong resistance to stress and a method of manufacturing the deposition mask by forming a mask spacer using some of a silicon layer included in a silicon-on-insulator (SOI) substrate.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a deposition mask includes: preparing a silicon-on-insulator (SOI) substrate, wherein the silicon-on-insulator (SOI) substrate includes an upper silicon substrate, a lower silicon substrate, and an insulating layer between the upper silicon substrate and the lower silicon substrate; forming a mask diaphragm having a plurality of openings by patterning the upper silicon substrate; forming a first protective layer on the upper silicon substrate and forming a second protective layer on the lower silicon substrate; forming a unit opening by patterning the lower silicon substrate; and removing the first protective layer and the second protective layer.

[0009] The insulating layer may include silicon oxide (SiO x ).

[0010] Patterning the upper silicon substrate may include forming a first photoresist pattern on the upper silicon substrate, forming a plurality of openings by using the first photoresist pattern, and removing the first photoresist pattern.

[0011] Forming the first protection layer and the second protection layer may include performing a thermal oxidation process on the upper silicon substrate and the lower silicon substrate, respectively.

[0012] The forming of the cell opening may include adjusting the relative relative humidity of the silicon oxide (SiO x ) and a KOH wet etching process with an etching ratio of silicon (Si) in the lower silicon substrate.

[0013] Removing the first protective layer and the second protective layer may include a stripping process using HF or a buffered oxide etchant (BOE).

[0014] The SOI substrate may include a plurality of cell regions and a mask rib region extending around the plurality of cell regions, and the method may further include forming a spacer by etching the upper silicon substrate in the mask rib region.

[0015] The spacer may have a height facing the substrate to be subjected to deposition.

[0016] The method may further include depositing a dummy inorganic film covering the mask membrane after removing the first protective layer and the second protective layer.

[0017] The dummy inorganic film may include silicon nitride (SiN x ). Depositing the dummy inorganic film may include adjusting a deposition thickness on a side of a mask shadow of the mask membrane so that a cross-section of a mask opening in the mask membrane has a regular tapered shape.

[0018] Forming the mask spacer may include forming a cross section of the mask spacer into an inverse tapered shape.

[0019] The inverse tapered shape of the cross section of the mask membrane may have a shape in which the thickness increases in an upward direction from the bottom surface.

[0020] According to an embodiment of the present disclosure, a deposition mask includes: a silicon-on-insulator (SOI) substrate, including an upper silicon substrate, a lower silicon substrate, and an insulating layer between the upper silicon substrate and the lower silicon substrate; a mask diaphragm formed by removing a portion of the upper silicon substrate in each of the cell regions of the SOI substrate; and a cell opening exposing the mask diaphragm from a rear direction in each of the cell regions.

[0021] The insulating layer may include silicon oxide (SiO x ). The SOI substrate may include a plurality of unit regions and a mask rib region extending around the plurality of unit regions, and the deposition mask may further include a spacer formed by removing a portion of the upper silicon substrate in the mask rib region. The spacer may have a height and face the substrate to be subjected to deposition.

[0022] The deposition mask may further include a dummy inorganic film covering the mask membrane.

[0023] The dummy inorganic film may include silicon nitride (SiN x ).

[0024] A cross section of the mask membrane may have an inverse tapered shape, and the inverse tapered shape may be a shape having a thickness increasing in an upward direction from a bottom surface.

[0025] According to an embodiment of the present disclosure, a thin but highly stress-resistant deposition mask is provided by forming a mask spacer using some of a silicon layer included in a silicon-on-insulator (SOI) substrate.

[0026] However, the aspects and features of the present disclosure are not limited to those set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the following detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1 is a perspective view of a head mounted display device according to an embodiment of the present disclosure;

[0029] Figure 2 yes Figure 1 An exploded perspective view of the head mounted display device shown in ;

[0030] Figure 3 is a perspective view of a head mounted display device according to an embodiment of the present disclosure;

[0031] Figure 4 is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0032] Figure 5 is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure;

[0033] Figure 6 is a perspective view of a mask according to an embodiment;

[0034] Figure 7 is a schematic plan view of a mask according to an embodiment of the present disclosure;

[0035] Figure 8 is a flow chart describing steps of a method of manufacturing a mask according to an embodiment of the present disclosure;

[0036] Figures 9 to 13 It is shown Figure 8 A cross-sectional view of the steps of the method for manufacturing a mask described in;

[0037] Fig.14 is a cross-sectional view showing steps of a method of patterning an upper silicon substrate according to an embodiment of the present disclosure;

[0038] Fig.15 is a schematic cross-sectional view of a deposition mask including spacers according to an embodiment; and

[0039] Fig.16 is a schematic cross-sectional view of a deposition mask including a dummy inorganic film according to an embodiment. DETAILED DESCRIPTION

[0040] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0041] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to another element or layer, or there may also be one or more intervening elements or layers. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled to or directly connected to the second element, or the first element may be indirectly coupled to or indirectly connected to the second element via one or more intervening elements.

[0042] In the accompanying drawings, for the clarity of explanation, the sizes of various elements, layers, etc. can be exaggerated. The same reference numerals represent the same elements. As described herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, when describing the embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure". When expressions such as "at least one of" and "any one of" are after a column of elements, the elements of the entire list are modified rather than the single elements in the list. For example, the expression "at least one of a, b and c" represents only a, only b, only c, a and b, a and c, b and c, a, b and c, all or their variations. As used herein, the terms "use (use)", "use (using)" and "use (used)" can be considered to be synonymous with the terms "utilize (utilize)", "utilize (utilizing)" and "utilized (utilized)" respectively. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent variations in measurements or calculations that those of ordinary skill in the art would recognize.

[0043] It should be understood that, although the terms first, second, third, etc. can be used in this article to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teaching of the exemplary embodiment, the first element, first component, first region, first layer or first section discussed below can be referred to as the second element, second component, second region, second layer or second section.

[0044] For ease of description, spatially relative terms such as "under", "below", "down", "above", "on" and the like may be used herein to describe the relationship of one element or feature to another (or some) element or feature as shown in the drawings. It should be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as being "under" or "under" other elements or features will then be oriented to be "above" or "on" other elements or features. Therefore, the term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly.

[0045] The terms used herein are for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "a kind of" are intended to also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when used in this specification, the terms "include", "include", "include" and / or "include" specify the existence of the features, wholes, steps, operations, elements and / or components set forth, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0046] The features of each of the various embodiments of the present disclosure may be partially combined with each other or completely combined with each other, and may be technically coordinated with each other differently, and the various embodiments may be implemented independently of each other, or may be implemented together in association with each other.

[0047] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view of a head mounted display device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 An exploded perspective view of the head-mounted display device shown in .

[0049] refer to Figure 1 and Figure 2 According to the embodiment, the head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device housing 110 and a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head band 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0050] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 spaced apart from each other in the X-axis direction is aligned with the reference Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, in understanding the reference Figure 4 and Figure 5 In the case where the description is applicable to the first display device 10_1 and the second display device 10_2, the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0051] The first optical member 151 may be disposed in the Z-axis direction between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed in the Z-axis direction between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0052] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 supports and fixes the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0053] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data (DATA), and may transmit the digital video data (DATA) to the first display device 10_1 and the second display device 10_2 through the connector.

[0054] The control circuit board 170 may transmit digital video data (DATA) associated with a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data (DATA) associated with a right-eye image optimized for the user's right eye to the second display device 10_2. In another embodiment, the control circuit board 170 may transmit the same digital video data (DATA) to the first display device 10_1 and the second display device 10_2.

[0055] The display device housing 110 accommodates the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170 and the connector. The housing cover 120 is configured to cover the opening surface (or opening side) of the display device housing 110, for example, the opening surface of the display device housing 110 defined by the X-axis direction and the Y-axis direction. The housing cover 120 may include a first eyepiece 131 for placing the user's left eye (or aligning with the user's left eye) and a second eyepiece 132 for placing the user's right eye (or aligning with the user's right eye). Although the first eyepiece 131 and the second eyepiece 132 are in Figure 1 and Figure 2 In the embodiment shown in FIG. 1 , the first eyepiece 131 and the second eyepiece 132 are separately provided, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into a single element.

[0056] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may view a virtual image of an image on the first display device 10_1 magnified by the first optical member 151 through the first eyepiece 131, and may view a virtual image of an image on the second display device 10_2 magnified by the second optical member 152 through the second eyepiece 132.

[0057] The head strap 140 fixes the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 remain consistent with the user's left eye and right eye, respectively (e.g., aligned with the user's left eye and right eye). By implementing a relatively light and small display device housing 110, the head mounted display device 1 may include (or may be implemented as) such as Figure 3 The eyeglass frames shown in, rather than e.g. Figure 1 The head strip 140 shown in FIG.

[0058] In addition, the head mounted display device 1 may further include a battery for power supply, an external memory slot for inserting an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a USB (Universal Serial Bus) terminal, a display port, or an HDMI (High Definition Multimedia Interface) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module, but the present disclosure is not limited thereto.

[0059] Figure 3 is a perspective view of a head mounted display device according to an embodiment of the present disclosure.

[0060] refer to Figure 3 The head mounted display device 1_1 according to the embodiment may be a glasses type display device having a relatively light and small display device housing 120_1. The head mounted display device 1_1 according to this embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, glasses temples 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0061] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, in understanding the reference Figure 4 and Figure 5 In the case where the description is applicable to the display device 10_3, the description of the display device 10_3 will be omitted.

[0062] The display device housing 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. The image displayed on the display device 10_3 may be magnified by the optical member 320, and the optical path of the image may be converted by the optical path conversion member 330 to be provided to the right eye of the user through the right eye lens 312. As a result, the user may view an augmented reality image with the right eye, which combines a virtual image displayed on the display device 10_3 and a real image observed through the right eye lens 312.

[0063] Despite Figure 3 In the embodiment shown in , the display device housing 120_1 is arranged at the right end of the support frame 350, but the embodiments of the present disclosure are not limited thereto. For example, the display device housing 120_1 may be arranged at the left end of the support frame 350. In such an embodiment, the image displayed on the display device 10_3 may be provided to the left eye of the user. In another embodiment, the display device housing 120_1 may be arranged at the left end and the right end of the support frame 350, respectively. In such an embodiment, the user may observe the image displayed on the display device 10_3 through both the left eye and the right eye.

[0064] Figure 4 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0065] refer to Figure 4 , the display device 10 according to the embodiment displays a moving image and / or a still image. The display device 10 according to this embodiment can be used by a portable electronic device such as a mobile phone, a smart phone, a tablet PC, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC). For example, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IOT) device. As another example, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0066] According to an embodiment, the display device 10 includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driver circuit 440 , and a power supply circuit 450 .

[0067] When viewed from the top, the display panel 410 may have a shape similar to a rectangular shape. For example, when viewed from the top, the display panel 410 may have a shape similar to a rectangle having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 410, the corner where the short side in the first direction DR1 intersects with the long side in the second direction DR2 may be rounded with a curvature (e.g., a predetermined curvature), or may be a right angle. When viewed from the top, the shape of the display panel 410 is not limited to a rectangular shape, but may be formed into a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. When viewed from the top, the shape of the display device 10 may follow (or may correspond to) the shape of the display panel 410, but embodiments of the present disclosure are not limited thereto.

[0068] The display panel 410 has a display area at which an image is displayed and a non-display area at which no image is displayed.

[0069] The display area includes a plurality of pixels, and each of the plurality of pixels includes a plurality of sub-pixels SP1, SP2, and SP3 (see, for example, Figure 5 ). The sub-pixels SP1, SP2 and SP3 include a plurality of pixel transistors. The pixel transistors are formed by a semiconductor process and may be disposed on a semiconductor substrate SSUB (see, for example, Figure 5 ). For example, the pixel transistor may be implemented as a complementary metal oxide semiconductor (CMOS) transistor.

[0070] The heat dissipation layer 420 may overlap the display panel 410 in a third direction DR3, which is a thickness direction of the display panel 410. The heat dissipation layer 420 may be disposed on one surface of the display panel 410, for example, on a rear surface of the display panel 410. The heat dissipation layer 420 releases heat generated in the display panel 410. The heat dissipation layer 420 may include a metal layer such as silver (Ag), copper (Cu), and aluminum (Al) having high thermal conductivity, or graphite.

[0071] The circuit board 430 may be electrically connected to a plurality of pads (not shown) in a pad region (not shown) of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board made of a flexible material, or may be a flexible film. Figure 44 shows the circuit board 430 in an unfolded state (or configuration), but the circuit board 430 may be bent. When the circuit board 430 is bent, one end of the circuit board 430 may be disposed on the rear surface of the display panel 410. The one end of the circuit board 430 may be opposite to the opposite end of the circuit board 430, which is connected to the pad in the pad area of ​​the display panel 410 by using a conductive adhesive member.

[0072] The driver circuit 440 may receive digital video data and a timing signal from the outside. The driver circuit 440 may generate a scan timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 in response to the timing signal.

[0073] The power supply circuit 450 may generate a plurality of panel driving voltages in response to a power supply voltage from the outside. For example, the power supply circuit 450 may generate a first power supply voltage (e.g., voltage “VSS”), a second power supply voltage (e.g., voltage “VDD”), and a third power supply voltage (e.g., voltage “VINT”) to be applied to the display panel 410.

[0074] Each of the driver circuit 440 and the power supply circuit 450 may be implemented as an integrated circuit (IC) and attached to a surface of the circuit board 430 .

[0075] Figure 5 is a cross-sectional view showing a portion of a display panel according to an embodiment of the present disclosure. For example, Figure 5 A cross-sectional structure of a portion of a display area including a plurality of sub-pixels SP1 , SP2 , and SP3 is shown.

[0076] refer to Figure 5 , the display panel 410 includes a semiconductor backplane SBP, an emission material backplane EBP, an emission material layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizer.

[0077] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the pixel transistors PTR, respectively.

[0078] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions (not shown) may be formed in the upper surface of the semiconductor substrate SSUB. The well region may be doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. In another embodiment, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0079] Each of the well regions has a source region SA associated with a source electrode of the pixel transistor PTR, a drain region DA associated with a drain electrode of the pixel transistor PTR, and a channel region CH between the source region SA and the drain region DA.

[0080] Each of the source region SA and the drain region DA may be doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the opposite side of the gate electrode GE.

[0081] Each of the plurality of well regions may further include a first low-concentration impurity region (not shown) disposed between the channel region CH and the source region SA and a second low-concentration impurity region (not shown) disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may have a lower impurity concentration than the source region SA. The second low-concentration impurity region may have a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, the length of the channel region CH of each of the pixel transistors PTR is increased, and therefore, punch-through and hot carrier phenomena due to a short channel may be mitigated or prevented.

[0082] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of, but not limited to, a silicon carbon nitride (SiCN)-based or silicon oxide (SiO x ) of inorganic film formation.

[0083] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of a silicon oxide (SiO x ) is formed as an inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0084] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole (e.g., an opening) passing through (or extending through) the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The contact terminal CTE may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy containing one or more of these.

[0085] The third semiconductor insulating film SINS3 may be disposed on a side surface of each of the contact terminals CTE. The upper surface of each of the contact terminals CTE may not be covered by the third semiconductor insulating film SINS3 but may be exposed. The third semiconductor insulating film SINS3 may be made of a silicon oxide (SiO x ) is formed as an inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0086] In some embodiments, a glass substrate or a polymer resin substrate (such as polyimide) may be used instead of the semiconductor substrate SSUB. In such an embodiment, the thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent (or unbendable), and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0087] The emission material back plate EBP includes the first metal layer ML1 to the eighth metal layer ML8, the reflective metal layers RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the emission material back plate EBP includes a plurality of interlayer dielectric films INS1 to INS8 disposed between the first metal layer ML1 to the eighth metal layer ML8 and interlayer dielectric films INS9 and INS10 disposed on the eighth metal layer ML8.

[0088] The first to eighth metal layers ML1 to ML8 implement the circuit of the first sub-pixel SP1 by connecting a plurality of contact terminals CTE exposed from (or by) the semiconductor backplane SBP.

[0089] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate (or extend through) the first interlayer insulating film INS1 and may be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and may be connected to the first vias VA1.

[0090] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may pass through the second interlayer insulating film INS2 to be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second vias VA2.

[0091] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may pass through the third interlayer insulating film INS3 to be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third vias VA3.

[0092] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may pass through the fourth interlayer insulating film INS4 to be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth vias VA4.

[0093] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may pass through the fifth interlayer insulating film INS5 to be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth vias VA5.

[0094] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may pass through the sixth interlayer insulating film INS6 to be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the sixth vias VA6.

[0095] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may pass through the seventh interlayer insulating film INS7 to be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh vias VA7.

[0096] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may pass through the eighth interlayer insulating film INS8 to be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth vias VA8.

[0097] The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be made of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) or an alloy containing one or more of these. The first through hole VA1 to the eighth through hole VA8 may be made of substantially the same material. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be made of a silicon oxide (SiO x ) is formed as an inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0098] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be respectively greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially equal.

[0099] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. The thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 may be substantially equal to the thickness of the eighth metal layer ML8.

[0100] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be made of a silicon oxide (SiO x ) is formed as an inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0101] Each of the ninth vias VA9 may pass through the ninth interlayer insulating film INS9 to be connected to the exposed eighth metal layer ML8. The ninth via VA9 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy containing one or more of these.

[0102] The first reflective electrode RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the ninth through hole VA9. The first reflective electrode RL1 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy including one or more of these.

[0103] The second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy containing one or more of these. For example, the second reflective electrode RL2 may be made of titanium nitride (TiN).

[0104] In the first sub-pixel SP1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in each of the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be determined based on the wavelength of the light of the first color and the distance between the emission material layer EML of the first sub-pixel SP1 and the fourth reflective electrode RL4, so that the light of the first color emitted from the emission material layer EML of the first sub-pixel SP1 is favorably reflected. The step layer STPL may be made of (but not limited to) a silicon carbon nitride (SiCN)-based material or a silicon oxide (SiO x ) of inorganic film formation.

[0105] In the first sub-pixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy containing one or more of these.

[0106] In various embodiments, at least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0107] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may reflect light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to provide appropriate light reflection. The fourth reflective electrode RL4 may be made of, but not limited to, aluminum (Al), a stack of aluminum and titanium (Ti / Al / Ti), a stack of aluminum and ITO (ITO / Al / ITO), silver (Ag), palladium (Pd), and an APC alloy (which is a copper (Cu) alloy), and a stack of an APC alloy and ITO (ITO / APC / ITO).

[0108] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be made of a silicon oxide (SiO x ) is formed as an inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0109] Each of the tenth through holes VA10 may pass through the tenth interlayer insulating film INS10 to be connected to the exposed ninth metal layer ML9. The tenth through hole VA10 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy containing one or more of these. Due to the step layer STPL, the thickness of the tenth through hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth through hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0110] The emission material layer EML may be disposed on the emission material back plate EBP. The emission material layer EML may include light emitting elements (not shown) and a pixel defining film PDL, each of the light emitting elements including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0111] The first electrode AND of each of the light emitting elements may be disposed on the tenth interlayer insulating film INS10 and may be connected to the tenth through hole VA10. The first electrode AND of each of the light emitting elements may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth through hole VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first through hole VA1 to the ninth through hole VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy containing one or more of these. For example, the first electrode AND of each of the light emitting elements may be made of titanium nitride (TiN).

[0112] The pixel defining film PDL may be partially disposed on the first electrode AND of each of the light emitting elements. The pixel defining film PDL may cover the edge of the first electrode AND of each of the light emitting elements. The pixel defining film PDL partitions the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0113] The first emission area EA1 may be defined as an area in the first sub-pixel SP1 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked on each other to emit light. The second emission area EA2 may be defined as an area in the second sub-pixel SP2 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked on each other to emit light. The third emission area EA3 may be defined as an area in the third sub-pixel SP3 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked on each other to emit light.

[0114] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be disposed on the edge of the first electrode AND of each of the light emitting elements, the second pixel definition film PDL2 may be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of a silicon oxide (SiO x ) is formed as an inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0115] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0116] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit different lights (e.g., emit lights of different colors). For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked on each other.

[0117] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic emission layer emitting light of a first color, and a first electron transport layer are sequentially stacked on each other. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic emission layer emitting light of a third color, and a second electron transport layer are sequentially stacked on each other. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic emission layer emitting light of a second color, and a third electron transport layer are sequentially stacked on each other.

[0118] The intermediate layer IL may cover the first electrode AND at (or in) the opening in the pixel defining film PDL, may cover the pixel defining film PDL between adjacent sub-pixels SP1 , SP2 , and SP3 , and may be partially disconnected.

[0119] According to an embodiment, leakage current and color crosstalk between adjacent sub-pixels SP1, SP2, and SP3 can be mitigated or prevented by disconnecting the intermediate layer IL between adjacent sub-pixels SP1, SP2, and SP3. Color crosstalk refers to a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is unintentionally turned on when the blue sub-pixel emits blue light. Because color crosstalk occurs due to leakage current, color crosstalk may occur if a blue sub-pixel and a red sub-pixel having a large voltage difference for driving the sub-pixel are adjacent to each other. For example, when a driving current is supplied to a light-emitting element of a blue sub-pixel to turn on the blue sub-pixel, some of the driving current may be transmitted to the red sub-pixel through at least some conductive layers of the intermediate layer IL as leakage current. If leakage current is generated, the red sub-pixel may be unintentionally turned on when the blue sub-pixel is turned on.

[0120] The number of the intermediate layers IL1, IL2 and IL3 emitting different light is not limited to Figure 5 For example, in another embodiment, the intermediate layer IL may include two intermediate layers. In such an embodiment, one of the two intermediate layers is substantially the same as the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic emission layer, a third organic emission layer, and a second electron transport layer. In such an embodiment, a charge generation layer may be provided between the two intermediate layers to provide electrons to one intermediate layer and charges to the other intermediate layer.

[0121] In addition, despite the Figure 5 In the embodiment shown in , the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 are all disposed in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the embodiments of the present disclosure are not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first emission area EA1, but not in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be disposed in the second emission area EA2, but not in the first emission area EA1 and the third emission area EA3. In addition, the third intermediate layer IL3 may be disposed in the third emission area EA3, but not in the first emission area EA1 and the second emission area EA2. In various embodiments, the first color filter CF1, the second color filter CF2 and the third color filter CF3 of the optical layer OPL may be omitted.

[0122] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of grooves (not shown). The second electrode CAT may be formed of a transparent conductive material (TCP) such as ITO and IZO capable of transmitting light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, light extraction efficiency may be improved by using a microcavity in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0123] The encapsulation layer TFE may be disposed on the emission material layer EML. The encapsulation layer TFE may include one or more inorganic films to reduce or prevent oxygen or moisture from penetrating into the emission material layer EML. In addition, the encapsulation layer TFE may include at least one organic film to protect the emission material layer EML from particles such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0124] The first inorganic encapsulation film TFE1 may be disposed on the second electrode CAT, the organic encapsulation film TFE2 may be disposed on the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 may be disposed on the organic encapsulation film TFE2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be formed of silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layers are alternately stacked on each other. The organic encapsulation film TFE2 may be a monomer. In another embodiment, the organic encapsulation film TFE2 may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0125] The adhesive layer ADL may adhere the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive and a transparent adhesive resin.

[0126] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0127] The first color filter CF1 may be consistent with the first emission area EA1 of the first subpixel SP1 (e.g., may be aligned with the first emission area EA1 of the first subpixel SP1). The first color filter CF1 may transmit light of a first color (e.g., light in a blue wavelength range). The blue wavelength range may be in the range of approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit light of a first color in the light emitted from the first emission area EA1.

[0128] The second color filter CF2 may be consistent with the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color (e.g., light in a green wavelength range). The green wavelength range may be in the range of approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 may transmit light of a second color in the light emitted from the second emission area EA2.

[0129] The third color filter CF3 may be consistent with the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color (e.g., light in a red wavelength range). The red wavelength range may be in the range of approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 may transmit light of a third color in the light emitted from the third emission area EA3.

[0130] Lenses LNS may be disposed on the first, second, and third color filters CF1, CF2, and CF3, respectively. Each of the lenses LNS may be a structure for increasing a ratio of light guided to the front side of the display device 10. Each of the lenses LNS may have an upwardly convex cross-sectional shape.

[0131] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) such that light travels in a third direction DR3 at an interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0132] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin such as polyimide. When the cover layer CVL is a glass substrate, it may be attached to the filling layer FIL. In such an embodiment, the filling layer FIL may adhere to the cover layer CVL. When the cover layer CVL is a glass substrate, it may be used as a packaging substrate. When the cover layer CVL is a polymer resin such as polyimide, it may be directly applied to the filling layer FIL.

[0133] A polarizer may be disposed on the surface of the cover layer CVL. The polarizer may be a structure for preventing visibility degradation due to reflection of external light. The polarizer may include a linear polarizer and a retardation film. For example, the retardation film may be a λ / 4 plate (quarter wave plate), but the embodiments of the present disclosure are not limited thereto. If visibility is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3 regardless of the reflection of external light, the polarizer may be omitted.

[0134] Figure 6 is a perspective view of a mask according to an embodiment. Figure 7 is a schematic plan view of a mask according to an embodiment of the present disclosure. Figure 6 In the stereogram of FIG. , one unit mask UM is separated from a plurality of unit masks. Figure 6 and Figure 7 The mask MK of the embodiment shown in FIG. 1 can be used for the above reference Figure 5 The process of depositing at least a portion of the intermediate layer IL of the display panel 410 is described. For example, the intermediate layer IL may emit different colors in the sub-pixels SP1, SP2, and SP3.

[0135] refer to Figure 6 and Figure 7 , the mask MK according to the embodiment may be a shadow mask in which the mask membrane MM is disposed on the silicon substrate 700. The mask MK may be referred to as a silicon mask.

[0136] According to an embodiment, the mask MK may include a silicon substrate 700 , and the mask membrane MM may be disposed on the silicon substrate 700 .

[0137] The silicon substrate 700 may be a silicon-on-insulator (SOI) substrate. The SOI substrate may be a silicon substrate including an upper silicon substrate, a lower silicon substrate, and an insulating layer disposed between the upper silicon substrate and the lower silicon substrate. The difference between the SOI substrate and a typical silicon wafer consisting only of a silicon single crystal is that the insulating layer is disposed between silicon single crystal layers (e.g., an upper silicon substrate and a lower silicon substrate). Such SOI substrates have strong resistance to process stress because they provide a defect-free silicon layer blocked by an insulating layer. One embodiment of the present disclosure processes the upper silicon substrate of such an SOI substrate to form a mask diaphragm MM, thereby providing a deposition mask that is thin but has strong resistance to stress, that is, the mask MK is also referred to as a "deposition mask". In the following description, reference numeral 700 refers to the SOI substrate.

[0138] In this application, the upper silicon substrate may be referred to as a “first silicon substrate” and the lower silicon substrate may be referred to as a “second silicon substrate.” Alternatively, the upper silicon substrate may be named “second silicon substrate” and the lower silicon substrate may be named “first silicon substrate.”

[0139] The mask membranes MM may be disposed in the cell regions 710 arranged in a matrix, and each of the cell regions 710 may be surrounded by the mask rib region 721 (eg, surrounded by the mask rib region 721 in a plan view).

[0140] The mask spacer MM may be a portion of the cell mask UM disposed in each of the plurality of cell regions 710. The mask spacer MM may be formed by patterning an upper silicon substrate.

[0141] The SOI substrate 700 may include a plurality of cell regions 710 and a mask frame region 720 excluding the plurality of cell regions 710. The mask frame region 720 may include a mask rib region 721 surrounding each cell region 710 and an outer frame region 722 disposed at the outermost position of the SOI substrate 700 (e.g., forming an outer periphery of the SOI substrate 700). The mask frame MF is disposed in the mask frame region 720, and the mask frame MF may include a mask rib surrounding the cell region 710.

[0142] The mask rib region 721 may separate the plurality of unit regions 710. For example, the plurality of unit regions 710 may be arranged in a matrix, and the mask rib region 721 may surround the unit regions 710.

[0143] A cell opening COP and a cell mask UM at least partially masking the cell opening COP may be located in each of the plurality of cell regions 710 of the SOI substrate 700 .

[0144] A plurality of unit openings COP may pass through (or extend through) the mask frame MF along the thickness direction (e.g., the third direction DR3) of the mask MK. The plurality of unit openings COP may be generated by removing a portion of the lower silicon substrate of the SOI substrate 700 from the back side (e.g., etching the lower silicon substrate of the SOI substrate 700).

[0145] Each unit mask UM may include a mask membrane MM, and the mask membrane MM may have a mask opening OP. Fig.13 ) may be arranged in a matrix in each unit mask UM, and the mask openings OP (see, for example Fig.13 ) may be located between the mask shadows 1020. For example, the mask shadows 1020 may be arranged to surround the mask opening OP (eg, extend around the periphery of the mask opening OP).

[0146] When the deposition material is deposited from a deposition source DS in a deposition machine (see, e.g. Fig.13 ) is evaporated, the mask shadow 1020 can be used as a blocking unit to mask the substrate undergoing deposition (e.g., the display panel 410 or the backplane substrate). Therefore, the deposition material generated by the deposition source DS can be deposited on the surface of the substrate undergoing deposition (e.g., the display panel 410 or the backplane substrate) through the mask opening OP in the mask membrane MM.

[0147] The mask opening OP in the mask film MM may be referred to as a hole or a mask hole. The mask opening OP may pass through the unit mask UM along a thickness direction (eg, third direction DR3) of the mask MK.

[0148] One unit mask UM may be used in a process of depositing one display panel 410. As used herein, the term "unit mask UM" may be used interchangeably with terms such as "mask unit UM."

[0149] Figure 8 is a flow chart describing the steps of a method of manufacturing a mask according to an embodiment of the present disclosure.

[0150] Figures 9 to 13 It is shown Figure 8 sectional views of steps of a method for manufacturing a mask described in .

[0151] In the following, reference Figures 8 to 14 , a method for manufacturing a mask according to an embodiment will be described. It should be noted that only some of the manufacturing processes of the mask will be described. Other processes for forming the elements described herein may be additionally performed before or after the manufacturing processes described below. In addition, the manufacturing processes of masks known in the art may be additionally performed before or after the manufacturing processes described below.

[0152] refer to Figure 8 and Fig. 9 In step 810, an SOI substrate 700 may be prepared (or provided). The SOI substrate 700 may be a silicon substrate including an upper silicon substrate 912, a lower silicon substrate 911, and an insulating layer 913 disposed between the upper silicon substrate 912 and the lower silicon substrate 911. The insulating layer 913 may include silicon oxide (SiO x ).

[0153] refer to Figure 8 and Fig.10 In step 820, the upper silicon substrate 912 may be patterned. The step of patterning the upper silicon substrate 912 includes: forming a first photoresist pattern PR1 on the upper silicon substrate 912, forming a plurality of openings 1011 in the upper silicon substrate 912 by using (or according to) the first photoresist pattern PR1, and removing the first photoresist pattern PR1.

[0154] In step 820, the upper silicon substrate 912 of the SOI substrate 700 is partially patterned in each cell region 710 to form a plurality of openings 1011. After the process according to step 820, the portion of the upper silicon substrate 912 remaining in each cell region 710 may serve as the mask diaphragm MM. For example, the portion of the upper silicon substrate 912 remaining in each cell region 710 may become a mask shadow 1020 of the mask diaphragm MM. After the process according to step 820, the plurality of openings 1011 formed in each cell region 710 may serve as the mask openings OP in the mask diaphragm MM.

[0155] refer to Figure 8 and Fig.11 In step 830, a first protective layer 1111 and a second protective layer 1112 are formed. The first protective layer 1111 may be an oxide film formed on the surface of the upper silicon substrate 912. The second protective layer 1112 may be an oxide film formed on the surface of the lower silicon substrate 911. For example, the step of forming the first protective layer 1111 and the second protective layer 1112 includes performing a thermal oxidation process on the upper silicon substrate 912 and the lower silicon substrate 911.

[0156] refer to Figure 8 and Fig.12 In step 840, the lower silicon substrate 911 is patterned. In step 840, the lower silicon substrate 911 is patterned in each cell region 710 by using the second photoresist pattern PR2 to form a cell opening COP. The step of forming the cell opening COP may include adjusting the silicon oxide (SiO x ) and a KOH wet etching with respect to an etching ratio of silicon (Si) included in the lower silicon substrate 911.

[0157] refer to Figure 8 and Fig.13, in step 850, the first protective layer 1111 and the second protective layer 1112 are removed. The step of removing the first protective layer 1111 and the second protective layer 1112 may include a stripping process using a wet chemical (e.g., HF or a buffered oxide etchant (BOE)). After removing the first protective layer 1111 and the second protective layer 1112, the SOI substrate 700 may become a silicon mask in which a portion of the upper silicon substrate 912 patterned in each cell region 710 serves as a mask diaphragm MM. For example, the mask diaphragm MM may include a mask shadow 1020 formed by the patterned upper silicon substrate 912 and a mask opening OP disposed between the mask shadows 1020. The mask diaphragm MM may be disposed to face the deposition source DS through a cell opening COP formed by (or formed in) the lower silicon substrate 911 patterned in each cell region 710.

[0158] Fig.14 are cross-sectional views showing steps of a method of patterning an upper silicon substrate according to an embodiment of the present disclosure.

[0159] According to an embodiment, the mask diaphragm MM formed by patterning the upper silicon substrate 912 may have an inverted tapered shape. For example, the cross section of the mask diaphragm MM may have an inverted tapered shape in which the thickness increases from the bottom surface (e.g., the surface facing the fourth direction DR4) toward the upper direction (e.g., the third direction DR3).

[0160] In order to make the mask membrane MM have a cross section of an inverted tapered shape, according to reference Figure 8 The process of step 820 described may form a plurality of mask openings OP, and may remove portions of the upper silicon substrate 912 (eg, etch the upper silicon substrate 912 ) such that each mask opening OP includes an undercut region.

[0161] According to the embodiment of the mask (for example, Figure 7 MK in FIG. 1020) can reduce the area of ​​the shadow region because the cross section of the mask membrane MM (e.g., the cross section of the mask shadow 1020) has an inverted cone shape. For example, the cone angle of the cross section of the mask shadow 1020 can be less than or equal to the deposition incident angle, which is the minimum angle from the deposition source DS to the mask opening OP, and therefore, the area of ​​the shadow region can be reduced.

[0162] Fig.15 is a schematic cross-sectional view of a deposition mask including a spacer according to an embodiment.

[0163] refer to Fig.15, the mask MK according to the embodiment may include a spacer 1511 having a height and facing the substrate undergoing deposition, that is, the spacer 1511 protrudes toward the substrate undergoing deposition. The substrate undergoing deposition may be a reference Figure 4 and Figure 5 A display panel 410 is described.

[0164] As described above, SOI substrate 700 includes a plurality of cell regions 710 and mask rib region 721 surrounding the plurality of cell regions 710. SOI substrate 700 may include spacers 1511 formed by removing portions of upper silicon substrate 912 in mask rib region 721 (eg, etching upper silicon substrate 912).

[0165] The spacer 1511 may be formed by removing a portion of the upper silicon substrate 912 (eg, etching the upper silicon substrate 912) in the mask rib region 721. The spacer 1511 generates tensile stress by physically contacting a substrate (eg, display panel 410) undergoing deposition and prevents the mask membrane MM from sagging.

[0166] Fig.16 is a schematic cross-sectional view of a deposition mask including a dummy inorganic film according to an embodiment.

[0167] According to an embodiment, the mask MK may have an additional inorganic film 1611 deposited on the surface of the mask diaphragm MM to prevent the mask diaphragm MM from sagging. For example, the inorganic film 1611 deposited on the surface of the mask diaphragm MM may be referred to as a "dummy inorganic film 1611", but the present disclosure is not limited thereto. For example, the dummy inorganic film 1611 may be represented by various terms such as "another inorganic film", "protective inorganic film", etc.

[0168] After the process of removing the first protective layer 1111 and the second protective layer 1112, for example, Figure 8 After step 850 , a process of depositing a dummy inorganic film 1611 is performed.

[0169] The dummy inorganic film 1611 may include silicon nitride (SiN x ), but the material of the dummy inorganic film 1611 is not limited thereto.

[0170] According to an embodiment, during the deposition process of the dummy inorganic film 1611, the cross section of the mask membrane MM may have an inverted tapered shape by adjusting the deposition thickness of the dummy inorganic film 1611. For example, a step of adjusting the deposition thickness on the side of the mask shadow 1020 of the mask membrane MM so that the cross section of the mask opening OP in the mask membrane MM has a regular tapered shape may be included.

[0171] According to an embodiment of the present disclosure, the mask spacer MM may be formed by using a portion of a silicon layer included in a silicon-on-insulator (SOI) substrate so that the mask spacer MM is thin but has strong resistance to stress.

[0172] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments described herein without departing substantially from the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense, rather than for a limiting purpose.

Claims

1. A method for manufacturing a deposition mask, the method comprising: preparing a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising an upper silicon substrate, a lower silicon substrate, and an insulating layer between the upper silicon substrate and the lower silicon substrate; forming a mask membrane having a plurality of openings by patterning the upper silicon substrate; forming a first protective layer on the upper silicon substrate and forming a second protective layer on the lower silicon substrate; forming a cell opening by patterning the lower silicon substrate; as well as The first protective layer and the second protective layer are removed.

2. The method according to claim 1, wherein: The insulating layer includes silicon oxide.

3. The method according to claim 1, wherein: Patterning the upper silicon substrate comprises: forming a first photoresist pattern on the upper silicon substrate; forming the plurality of openings by using the first photoresist pattern; and The first photoresist pattern is removed.

4. The method according to claim 3, wherein: Forming the first protection layer and the second protection layer includes performing a thermal oxidation process on the upper silicon substrate and the lower silicon substrate, respectively.

5. The method according to claim 3, wherein: Forming the cell opening includes a KOH wet etching process by adjusting an etching ratio with respect to silicon oxide in the second protection layer and silicon in the lower silicon substrate.

6. The method according to claim 5, wherein: Removing the first protective layer and the second protective layer includes a stripping process using HF or a buffered oxide etchant.

7. The method according to claim 1, wherein: The SOI substrate has a plurality of unit regions and a mask rib region extending around the plurality of unit regions, and The method further comprises forming a spacer by etching the upper silicon substrate in the mask rib region.

8. The method according to claim 7, wherein: The spacer has a height facing a substrate to be subjected to deposition.

9. The method according to claim 1, further comprising: After removing the first protective layer and the second protective layer, a dummy inorganic film covering the mask membrane is deposited.

10. The method according to claim 9, wherein: The dummy inorganic film includes silicon nitride.

11. The method according to claim 10, wherein: Depositing the dummy inorganic film includes adjusting a deposition thickness on a side of a mask shadow of the mask spacer so that a cross-section of a mask opening in the mask spacer has a tapered shape.

12. The method according to claim 1, wherein: Forming the mask spacer includes forming a cross section of the mask spacer into an inverted tapered shape.

13. The method according to claim 12, wherein: The inverse tapered shape of the cross section of the mask spacer has a shape in which a thickness increases from a bottom surface in an upward direction.

14. Deposition mask, comprising: A silicon-on-insulator substrate, comprising an upper silicon substrate, a lower silicon substrate and an insulating layer between the upper silicon substrate and the lower silicon substrate; a mask diaphragm formed by removing a portion of the upper silicon substrate in each of the cell regions of the silicon-on-insulator substrate; as well as A cell opening exposes the mask spacer from a rear direction in each of the cell regions.

15. The deposition mask according to claim 14, wherein: The insulating layer includes silicon oxide.

16. The deposition mask according to claim 14, wherein: The silicon-on-insulator substrate has a plurality of cell regions and a mask rib region extending around the plurality of cell regions, and Wherein, the deposition mask further includes a spacer formed by removing a portion of the upper silicon substrate in the mask rib region.

17. The deposition mask according to claim 16, wherein: The spacer has a height and faces a substrate to be subjected to deposition. 18 . The deposition mask of claim 14 , further comprising a dummy inorganic film covering the mask spacer.

19. The deposition mask according to claim 18, wherein: The dummy inorganic film includes silicon nitride.

20. The deposition mask according to claim 14, wherein: The cross section of the mask membrane has an inverted tapered shape, and Here, the inverted tapered shape is a shape having a thickness increasing from a bottom surface in an upward direction.

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