Satellite-borne large-area-array high-frame-frequency short-wave infrared detector data acquisition system

Abstract

The invention relates to a satellite-borne large-area-array high-frame-frequency short-wave infrared detector data acquisition system, which adopts a 1024 * 512 large-area-array short-wave infrared detector, designs a special acquisition circuit aiming at 8-path output of the 1024 * 512 large-area-array detector, and comprises the following steps: firstly, conditioning 8-path signals output by the detector through an analog front-end circuit; and after conditioning, synchronous sampling of eight paths of signals is carried out through three analog-to-digital sampling chips, so that the signals are synchronously input to the FPGA circuit, and the FPGA circuit rapidly generates a frame image. In other words, three analog-to-digital sampling chips supporting three-channel sampling and an FPGA circuit are selected as main control chips to complete 8-channel simultaneous reading of a 1024 * 512 large-area-array detector, the number of pixels is increased, the frame frequency is increased, meanwhile, the size, weight and power consumption of a data transmission link of the satellite-borne hyperspectral imager are reduced, and the image transmission quality is effectively guaranteed.

Description

Technical Field

[0001] The present application relates to the field of aerospace optical remote sensing imaging technology, and in particular to a satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system. Background Art

[0002] With the development of aerospace optical remote sensing imaging technology, the requirements for spatial resolution, spectral resolution and signal-to-noise ratio of satellite-borne hyperspectral imagers are constantly increasing. There is an urgent need to provide a satellite-borne infrared detector data acquisition system that can meet the new requirements. Summary of the invention

[0003] Based on this, it is necessary to provide a satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system.

[0004] The embodiment of the present application provides a satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system, comprising:

[0005] Short-wave infrared detector: the array size of the short-wave infrared detector is 1024*512. The short-wave infrared detector has 8 output terminals. The short-wave infrared detector is used to convert the received infrared radiation into an electrical signal under the drive of a driving signal.

[0006] An analog front-end circuit, wherein eight input terminals of the analog front-end circuit are respectively connected to eight output terminals of the short-wave infrared detector in a one-to-one correspondence, and the analog front-end circuit is used for conditioning electrical signals;

[0007] Three analog-to-digital sampling chips, each of which supports three-channel signal sampling, and the eight input terminals of the three analog-to-digital sampling chips are respectively connected to the eight output terminals of the analog-to-digital front-end circuit to synchronously receive the eight electrical signals output by the analog front-end circuit;

[0008] A temperature control feedback circuit, the temperature control feedback circuit is used to collect the temperature of the short-wave infrared detector and output a feedback signal representing the temperature;

[0009] The FPGA circuit is respectively connected to the eight output ends of the three analog-to-digital sampling chips, the output end of the temperature control feedback circuit, and the driving end of the short-wave infrared detector. The FPGA circuit is used to adjust the driving signal output to the short-wave infrared detector according to the feedback signal, and to generate and output an image to the data transmission subsystem based on the signal output by the analog-to-digital conversion circuit.

[0010] In one embodiment, the model of the analog-to-digital sampling chip is AD9826, and the register configuration of the analog-to-digital sampling chip is: input range 4V; internal reference enable; three-channel mode; input clamp voltage 4V; output mode two bytes; external bias OFFSET grounded.

[0011] In one embodiment, the satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system further includes:

[0012] The SRAM cache circuit is connected to the FPGA circuit, and the SRAM cache circuit is used to store images.

[0013] In one embodiment, the SRAM cache circuit uses 772 radiation-hardened SRAM modules B8CR1M39H.

[0014] In one embodiment, each output end of the short-wave infrared detector has a reference level output pin and a signal level output pin, and the analog front-end circuit includes:

[0015] 8 signal conditioning modules, the first input end of the signal conditioning module is correspondingly connected to the signal level output pin of the shortwave infrared detector, the second input end of the signal conditioning module is correspondingly connected to the reference level output pin of the shortwave infrared detector, and the output end of the signal conditioning module is correspondingly connected to the input end of the analog-to-digital sampling chip.

[0016] In one embodiment, the signal conditioning module includes:

[0017] A first voltage follower, wherein an input end of the first voltage follower corresponds to a signal level output pin of a short-wave infrared detector;

[0018] A second voltage follower, wherein an input end of the second voltage follower is connected to a reference level output pin of the short-wave infrared detector;

[0019] A differential circuit, wherein a first input end of the differential circuit is connected to an output end of a first voltage follower, a second input end of the differential circuit is connected to an output end of a second voltage follower, and an output end of the differential circuit is correspondingly connected to an input end of an analog-to-digital sampling chip.

[0020] In one embodiment, the temperature control feedback circuit includes:

[0021] A temperature feedback circuit, which is used to collect the temperature of the short-wave infrared detector;

[0022] The analog-to-digital sampling circuit has an input end connected to the output end of the temperature feedback circuit, and an output end of the analog-to-digital sampling circuit connected to the feedback end of the FPGA circuit.

[0023] In one embodiment, the temperature feedback circuit comprises:

[0024] Thermistor: The thermistor is arranged on the short-wave infrared detector to detect the temperature of the short-wave infrared detector;

[0025] A voltage divider circuit, wherein an input end of the voltage divider circuit is connected to an output end of the thermistor;

[0026] An instrument amplifier, wherein the input end of the instrument amplifier is connected to the output end of the voltage divider circuit, and the output end of the instrument amplifier is connected to the input end of the analog-to-digital sampling circuit.

[0027] In one embodiment, the gain and bias voltage of the instrumentation amplifier are configured based on the temperature impedance curve of the short-wave infrared detector so that the output signal of the instrumentation amplifier matches the range of the analog-to-digital sampling circuit.

[0028] In one embodiment, the FPGA circuit includes:

[0029] FPGA chip, the model of FPGA chip is XQ4VSX55-10FF1148M;

[0030] Refresh chip, the model of the refresh chip is JMRS01RH;

[0031] FLASH memory, the model of FLASH memory is JFM29LV641RH;

[0032] Among them, the refresh chip and FLASH memory are both connected to the FPGA chip to support on-orbit reconstruction of the FPGA chip.

[0033] In one embodiment, the satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system further includes:

[0034] A logic drive circuit, one end of the logic drive circuit is connected to the FPGA circuit, and the other end of the logic drive circuit is connected to the short-wave infrared detector to transmit the drive signal to the short-wave infrared detector.

[0035] In one embodiment, the satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system further includes:

[0036] The secondary power supply circuit is connected with the FPGA circuit and the short-wave infrared detector respectively.

[0037] The above-mentioned satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system adopts a 1024*512 large-array short-wave infrared detector, and designs a special acquisition circuit for the 8-channel output of the 1024*512 large-array detector. First, the 8-channel signal output by the detector is conditioned by the analog front-end circuit, and then the 8-channel signal is synchronously sampled by 3 analog-to-digital sampling chips after conditioning, so as to be synchronously input to the FPGA circuit, so that the FPGA circuit can quickly generate a frame image. That is, by selecting 3 analog-to-digital sampling chips supporting 3-channel sampling and FPGA circuit as the main control chip to complete the 8-channel simultaneous readout of the 1024*512 large-array detector, while increasing the number of pixels and the frame rate, the volume, weight and power consumption of the satellite-borne hyperspectral imager data transmission link are reduced, and the quality of image transmission is effectively guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is one of the structural schematic diagrams of a satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to an embodiment;

[0040] Figure 2 This is a second structural schematic diagram of a satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to an embodiment;

[0041] Figure 3 is a structural schematic diagram of a signal conditioning module according to an embodiment;

[0042] Figure 4 A circuit schematic diagram of a B54ACS164245SRHF chip according to a specific embodiment;

[0043] Figure 5 is a timing diagram of 11 driving signals in a specific embodiment;

[0044] Figure 6 A circuit schematic diagram of a radiation-resistant linear regulator RSW1201A according to a specific implementation method;

[0045] Figure 7 A circuit schematic diagram of a precision reference voltage chip AD580 according to a specific implementation method;

[0046] Figure 8 The schematic diagram of a circuit for realizing 8-way bias voltage generation based on a low-power operational amplifier LM158 is a specific implementation method. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It is understood that the terms "first", "second", etc. used in this application can be used to describe various elements in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. It is understood that the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have transmission of electrical signals or data with each other.

[0050] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0052] In one implementation, a satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system 100 is provided. Figure 1 As shown, the system 100 includes: a short-wave infrared detector 1, an analog front-end circuit 2, three analog-to-digital sampling chips 3, a temperature control feedback circuit 4, and an FPGA circuit 5.

[0053] Among them, the array size of the short-wave infrared detector 1 is 1024*512, and the short-wave infrared detector 1 has 8 output terminals. The short-wave infrared detector 1 is used to convert the received infrared radiation into an electrical signal under the drive signal. The 8 input terminals of the analog front-end circuit 2 are respectively connected to the 8 output terminals of the short-wave infrared detector 1 in a one-to-one correspondence, and the analog front-end circuit 2 is used to condition the electrical signal; each of the analog-to-digital sampling chips 3 supports three-channel signal sampling, and the 8 input terminals of the three analog-to-digital sampling chips 3 are respectively connected to the 8 output terminals of the analog-to-digital front-end circuit to synchronously receive the 8-channel electrical signals output by the analog front-end circuit 2; the temperature control feedback circuit 4 is used to collect the temperature of the short-wave infrared detector 1 and output a feedback signal representing the temperature. The FPGA circuit 5 is respectively connected to the eight output ends of the three analog-to-digital sampling chips 3, the output end of the temperature control feedback circuit 4, and the driving end of the short-wave infrared detector 1, and the FPGA circuit 5 is used to adjust the driving signal output to the short-wave infrared detector 1 according to the feedback signal, and generate and output an image to the data transmission subsystem 100 based on the signal output by the analog-to-digital conversion circuit.

[0054] The response band of the short-wave infrared detector 1 is 1635-1655 nm, and the pixel size is 30 um.

[0055] Specifically, the data acquisition system of the large-array high-frame-rate short-wave infrared detector 1 on board adopts a 1024*512 large-array short-wave infrared detector 1, and designs a special acquisition circuit for the 8-channel output of the 1024*512 large-array detector. First, the 8-channel signal output by the detector is conditioned by the analog front-end circuit 2, and then the 8-channel signal is synchronously sampled by three analog-to-digital sampling chips 3 after conditioning, so as to be synchronously input to the FPGA circuit 5, so that the FPGA circuit 5 can quickly generate a frame image. That is, by selecting three analog-to-digital sampling chips 3 supporting 3-channel sampling and the FPGA circuit 5 as the main control chip to complete the 8-channel simultaneous readout of the 1024*512 large-array detector, while increasing the number of pixels and the frame rate, the volume, weight and power consumption of the data transmission link of the onboard hyperspectral imager are reduced, and the quality of image transmission is effectively guaranteed.

[0056] The satellite-borne large-array high-frame-rate short-wave infrared detector 1 data acquisition system provided in the embodiment of the present application uses a short-wave infrared detector 1 with 1024*512 pixels, adopts 8 channels for simultaneous readout, and the maximum pixel readout rate can reach 20MHz, and the maximum frame rate is 250Hz. This solves the problem of the satellite-borne hyperspectral imager short-wave infrared detector 1 data acquisition system in the traditional technology, which has a small number of pixels, slow readout speed, and low frame rate.

[0057] In one embodiment, the model of the analog-to-digital sampling chip 3 is AD9826, and the register configuration of the analog-to-digital sampling chip 3 is: input range 4V; internal reference enable; three-channel mode; input clamp voltage 4V; output mode two bytes; external bias OFFSET grounded.

[0058] Among them, the analog-to-digital sampling chip 3 is used to convert the analog signal output by the short-wave infrared detector 1 output by the analog front-end circuit 2 into a digital signal, and transmit it to the FPGA circuit 5 for image processing. The analog-to-digital sampling chip 3 can use the 3-channel, 16-bit high-speed analog-to-digital converter AD9826 of AD Company. Three AD9826s are used to collect the 8-channel analog signals output by the short-wave infrared detector 1, and the AD9826 register is set to: input range 4V; internal reference enable; three-channel mode; input clamp 4V; output mode two bytes. The external bias OFFSET is grounded. Under this AD9826 setting, the AD9826 gain G can be set to 23 (17H), and Gain=1.437 can be obtained. Then the analog voltage output by the short-wave infrared detector 1 is gained to 0.201~3.932, which can reach the full scale of the analog-to-digital sampling chip 3. When it is close to the full scale, it can help improve the measurement accuracy.

[0059] In one embodiment, Figure 2 As shown, the satellite-borne large-array high-frame-rate short-wave infrared detector 1 data acquisition system also includes: an SRAM cache circuit 6.

[0060] The SRAM cache circuit 6 is connected to the FPGA circuit 5 , and the SRAM cache circuit 6 is used to store the image.

[0061] The size of one frame of image output by the short-wave infrared detector 1 is about 8.4 Mbit. The storage space of the FPGA circuit 5 is limited. By adding the SRAM cache circuit 6, the data storage capacity in the process of data reception and processing can be improved.

[0062] In one embodiment, the SRAM cache circuit 6 uses 772 radiation-hardened SRAM modules B8CR1M39H.

[0063] The radiation-resistant reinforced SRAM module of Institute 772 - B8CR1M39H, has 40 signal input pins, a capacity of 40Mbit, a write time of only 20ns, and can write 40bit of data at a time, which can support the large-capacity cache requirements of 8 simultaneous outputs of short-wave infrared detectors.

[0064] In one embodiment, each output end of the short-wave infrared detector 1 has a reference level output pin and a signal level output pin, and the analog front-end circuit 2 includes: 8 signal conditioning modules.

[0065] The first input end of the signal conditioning module is correspondingly connected to the signal level output pin of the short-wave infrared detector 1, the second input end of the signal conditioning module is correspondingly connected to the reference level output pin of the short-wave infrared detector 1, and the output end of the signal conditioning module is correspondingly connected to the input end of the analog-to-digital sampling chip 3.

[0066] The analog output signal of the short-wave infrared detector 1 is read out in parallel by 8 differential channels, and its output adopts the correlated double sampling technology, that is, each channel consists of a reference level output pin and a signal level output pin, and its effective signal is the difference between the reference level and the signal level, which can effectively eliminate the noise generated during reset and improve the output signal reliability of the short-wave infrared detector 1. On this basis, with the 8-channel signal conditioning module, each signal conditioning module receives and conditions 1 channel output of the short-wave infrared detector 1 to output the conditioned analog signal to the corresponding analog sampling chip.

[0067] In one embodiment, Figure 3 As shown, the signal conditioning module includes: a first voltage follower 211 , a second voltage follower 212 , and a differential circuit 213 .

[0068] The input end of the first voltage follower 211 is connected to the signal level output pins (Vout1_N, Vout2_N, Vout3_N, Vout4_N, Vout5_N, Vout6_N, Vout7_N, Vout8_N, Figure 3 Only one Vout1_N is given as an example); the input end of the second voltage follower 212 is connected to the reference level output pins (Vout1_P, Vout2_P, Vout3_P, Vout4_P, Vout5_P, Vout6_P, Vout7_P, Vout8_P, Figure 3 Only one Vout1_P is given as an example); a first input end of the differential circuit 213 is connected to the output end of the first voltage follower 211, a second input end of the differential circuit 213 is connected to the output end of the second voltage follower 212, and an output end of the differential circuit 213 is correspondingly connected to an input end of the analog-to-digital sampling chip 3.

[0069] The reference level output range of the reference level output pin of the short-wave infrared detector 1 is 2.2~2.4V, and the signal level output range of the signal level output pin is 0.4~2.4V. Therefore, the effective signal level range after differential is -0.2~2.0V, and the detector output impedance is greater than 10KΩ. The first voltage follower and the second voltage follower can be selected to follow the signal level and reference level output by the short-wave infrared detector 1 respectively, and then the effective signal level range of the short-wave infrared detector 1 is reversed through the differential circuit. When the parameter A of the differential circuit is 11.8 / 10=1.18, the effective signal level range of the short-wave infrared detector 1 can be reversed to 0.14~2.736V (effective signal level Vout=(Vout_N-Vout_P)*A+2.5V=0.14~2.736V), which is close to the full scale of the analog-to-digital sampling chip 3, which is conducive to improving the measurement accuracy.

[0070] Optionally, the signal conditioning module can use AD8042 chip, a rail-to-rail dual-channel operational amplifier from AD Corporation. Since the short-wave infrared detector 1 uses 8 channels for simultaneous readout, 8 pieces of AD8042 are required to simultaneously condition the 8 channels of signals of the short-wave infrared detector 1. Figure 3 Only the signal conditioning module corresponding to the output of one short-wave infrared detector 1 is shown, and the signal conditioning modules of the remaining 7 analog output signals are the same and will not be described in detail here.

[0071] Among them, Figure 3 As shown, a filtering circuit can be set at the 5V voltage input end of the differential circuit and the voltage follower, for example, a filtering circuit formed by connecting C1, C2, C3, C4, C5, and C6 in series and parallel to improve the stability and reliability of the signal conditioning module.

[0072] In one embodiment, the temperature control feedback circuit 4 includes: a temperature feedback circuit 41 and an analog-to-digital sampling circuit 42 .

[0073] The temperature feedback circuit 41 is used to collect the temperature of the shortwave infrared detector 1 ; the input end of the analog-to-digital sampling circuit 42 is connected to the output end of the temperature feedback circuit 41 , and the output end of the analog-to-digital sampling circuit 42 is connected to the feedback end of the FPGA circuit 5 .

[0074] Under this circuit architecture, the FPGA circuit 5 can adjust the driving signal loaded to the short-wave infrared detector 1 in real time according to the acquired temperature of the short-wave infrared detector 1 to achieve high-precision temperature control of the short-wave infrared detector 1.

[0075] In one embodiment, the analog-to-digital sampling circuit 42 can use TI's 8-channel, 12-bit, serial output analog-to-digital converter ADC128S102. The signal output by the short-wave infrared detector 1 is converted by ADC128S102 and then input to the FPGA circuit 5 for collection. The PID control algorithm inside the FPGA circuit 5 is used to calculate and generate a driving signal, thereby realizing high-precision temperature control of the short-wave infrared detector 1.

[0076] In one embodiment, the temperature feedback circuit 41 includes: a thermistor, a voltage divider circuit, and an instrument amplifier.

[0077] Wherein, the thermistor is arranged on the short-wave infrared detector 1 to detect the temperature of the short-wave infrared detector 1; the input end of the voltage divider circuit is connected to the output end of the thermistor; the input end of the instrument amplifier is connected to the output end of the voltage divider circuit, and the output end of the instrument amplifier is connected to the input end of the analog-to-digital sampling circuit 42.

[0078] The temperature feedback circuit 41 realizes bias elimination and amplification of the temperature feedback voltage signal output by the short-wave infrared detector 1. The temperature feedback circuit 41 can be implemented by building an instrument amplifier using TI's Q-class operational amplifier device LM158AJ. The thermistor signal output by the short-wave infrared detector 1 is connected to a voltage divider circuit to match the input requirements of the instrument amplifier. After amplification by the instrument amplifier, it is input to the analog-to-digital sampling circuit 42 for analog-to-digital conversion. The digital signal representing the temperature of the short-wave infrared detector 1 is transmitted to the FPGA circuit 5 to provide a data basis for the FPGA circuit 5 to adjust the output drive signal, thereby ensuring the working temperature stability of the short-wave infrared detector 1.

[0079] In one embodiment, the gain and bias voltage of the instrument amplifier are configured based on the temperature impedance curve of the short-wave infrared detector 1, so that the output signal of the instrument amplifier matches the range of the analog-to-digital sampling circuit 42. According to the temperature impedance curve, the gain and bias voltage of the instrument amplifier are adjusted so that they can meet the full range of the analog-to-digital sampling circuit 42 (such as the 3.3V range of ADC128S102) within the temperature fluctuation range, thereby improving the measurement accuracy.

[0080] In one embodiment, the FPGA circuit 5 includes: an FPGA chip, a refresh chip, and a FLASH memory.

[0081] Among them, the model of the FPGA chip is XQ4VSX55-10FF1148M; the model of the refresh chip is JMRS01RH; the model of the FLASH memory is JFM29LV641RH, and the refresh chip and the FLASH memory are both connected to the FPGA chip to support on-orbit reconstruction of the FPGA chip.

[0082] The FPGA chip uses Xilinx's military-grade product XQ4VSX55-10FF1148M, which is an SRAM-type FPGA with 55296 logic units, 640 I / O ports, and a maximum system operating frequency of 500MHz. In order to enhance the adaptability of the FPGA chip to the space environment, the domestically produced Fudan Micro's radiation-resistant refresh chip JMRS01RH and Reset Micro's 64-megahertz radiation-resistant FLASH memory JFM29LV641RH are selected for on-orbit reconstruction of the FPGA. Among them, JMRS01RH can regularly detect the SEFI state of the FPGA and refresh the FPGA, reducing the cumulative effect of single particles, which is an important solution to improve the single-particle performance of SRAM-type FPGAs.

[0083] The various circuit components provided in the embodiments of the present application all adopt components in the aerospace catalog and can be applied to short-wave infrared detection in aerospace scenarios.

[0084] In one embodiment, in one embodiment, the satellite-borne large-array high-frame-rate short-wave infrared detector 1 data acquisition system further includes:

[0085] A logic driving circuit 7 , one end of the logic driving circuit 7 is connected to the FPGA circuit 5 , and the other end of the logic driving circuit 7 is connected to the short-wave infrared detector 1 , so as to transmit a driving signal to the short-wave infrared detector 1 .

[0086] The 11 driving signals required by the short-wave infrared detector 1 are generated by the FPGA circuit 5. The aerospace-grade radiation-resistant bidirectional transceiver B54ACS164245SRHF chip bus driver from the 772 Institute can be selected and input to the short-wave infrared detector 1. The implementation principle of the B54ACS164245SRHF chip can be as follows: Figure 4 shown.

[0087] based on Figure 4 Under the chip pins shown, the column clock signal (CLKCOL), row clock signal (CLKROW), row trigger clock signal (STROW), row and column trigger signal (STROWCOL), column op amp trigger signal (STCOLOP), column trigger signal (STCOL), reset signal (RESET), SH1 signal, SH2 signal, SELCAP signal, and SEL128 signal are input, and the amplitude of the drive signal is required to be 0-3.3V.

[0088] The timing diagram of 11 driving signals is as follows: Figure 5 As shown, under this timing, the short-wave infrared detector 1 can be driven to perform infrared detection.

[0089] In one embodiment, the satellite-borne large-array high-frame-rate short-wave infrared detector 1 data acquisition system further includes: a secondary power supply circuit 8. The secondary power supply circuit 8 is connected to the FPGA circuit 5 and the short-wave infrared detector 1 respectively.

[0090] The secondary power supply circuit 8 is responsible for providing the operating voltage of the FPGA circuit 5 and the short-wave infrared detector 1 to meet their power supply requirements.

[0091] In one embodiment, the secondary power supply circuit 8 provides 10 bias voltages to meet the power supply requirements of the satellite-borne large-array high-frame-rate short-wave infrared detector 1 data acquisition system. The current and voltage requirements of various power supplies required for its operation are shown in Table 1:

[0092] Table 1

[0093]

[0094] In one embodiment, the generation of 10 bias voltages can be specifically performed by selecting Figure 6 The radiation-resistant linear regulator RSW1201A shown in the figure generates a 3.3V bias voltage. The AD580 precision reference voltage chip from AD can be used to convert the +5V voltage obtained after the secondary power supply conversion to +2.5V (such as Figure 7 As shown in Figure 1), the low-power operational amplifier LM158 from Texas Instruments is used to divide the 2.5V voltage to obtain the remaining 8 bias voltages required by the detector, such as Figure 8 shown.

[0095] In one embodiment, the FPGA circuit 5 is also connected to a refrigeration device via a refrigeration control output interface 9 to control a working device of the refrigeration device, and cooperates with the adjustment of the driving signal to achieve precise temperature control of the short-wave infrared detector 1 .

[0096] In one embodiment, the FPGA circuit 5 is also connected to the CAN bus 10, and the CAN bus 10 is connected to the data management subsystem to achieve communication between the FPGA circuit 5 and the data management subsystem.

[0097] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0098] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system, characterized in that: include: A short-wave infrared detector, wherein the array size of the short-wave infrared detector is 1024*512, the short-wave infrared detector has 8 output terminals, and the short-wave infrared detector is used to convert the received infrared radiation into an electrical signal under the drive of a driving signal; An analog front-end circuit, wherein eight input terminals of the analog front-end circuit are respectively connected to eight output terminals of the short-wave infrared detector in a one-to-one correspondence, and the analog front-end circuit is used to condition the electrical signal; Three analog-to-digital sampling chips, each of which supports three-channel signal sampling, and the eight input terminals of the three analog-to-digital sampling chips are respectively connected to the eight output terminals of the analog-to-digital front-end circuit to synchronously receive the eight electrical signals output by the analog front-end circuit; A temperature control feedback circuit, the temperature control feedback circuit is used to collect the temperature of the short-wave infrared detector and output a feedback signal representing the temperature; The FPGA circuit is respectively connected to the eight output ends of the three analog-to-digital sampling chips, the output end of the temperature control feedback circuit, and the driving end of the short-wave infrared detector, and the FPGA circuit is used to adjust the driving signal output to the short-wave infrared detector according to the feedback signal, and generate and output an image to the data transmission subsystem based on the signal output by the analog-to-digital conversion circuit.

2. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 1 is characterized in that: The model of the analog-to-digital sampling chip is AD9826, and the register configuration of the analog-to-digital sampling chip is: input range 4V; internal reference enable; three-channel mode; input clamp voltage 4V; output mode two bytes; external bias OFFSET grounded.

3. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 1 is characterized in that: Also includes: An SRAM cache circuit is connected to the FPGA circuit, and the SRAM cache circuit is used to store the image.

4. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 3 is characterized in that: The SRAM cache circuit adopts the radiation-resistant reinforced SRAM module B8CR1M39H from 772 Institute.

5. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 1 is characterized in that: Each output end of the short-wave infrared detector has a reference level output pin and a signal level output pin, and the analog front-end circuit includes: 8 signal conditioning modules, the first input end of the signal conditioning module is correspondingly connected to the signal level output pin of the short-wave infrared detector, the second input end of the signal conditioning module is correspondingly connected to the reference level output pin of the short-wave infrared detector, and the output end of the signal conditioning module is correspondingly connected to the input end of the analog-to-digital sampling chip.

6. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 5 is characterized in that: The signal conditioning module comprises: A first voltage follower, wherein an input end of the first voltage follower is correspondingly connected to a signal level output pin of the short-wave infrared detector; A second voltage follower, wherein an input end of the second voltage follower is correspondingly connected to a reference level output pin of the short-wave infrared detector; A differential circuit, wherein the first input end of the differential circuit is connected to the output end of the first voltage follower, the second input end of the differential circuit is connected to the output end of the second voltage follower, and the output end of the differential circuit is correspondingly connected to an input end of the analog-to-digital sampling chip.

7. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 1 is characterized in that: The temperature control feedback circuit comprises: A temperature feedback circuit, wherein the temperature feedback circuit is used to collect the temperature of the short-wave infrared detector; An analog-to-digital sampling circuit, wherein the input end of the analog-to-digital sampling circuit is connected to the output end of the temperature feedback circuit, and the output end of the analog-to-digital sampling circuit is connected to the feedback end of the FPGA circuit.

8. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 7 is characterized in that: The temperature feedback circuit comprises: a thermistor, wherein the thermistor is arranged on the short-wave infrared detector to detect the temperature of the short-wave infrared detector; A voltage divider circuit, wherein an input end of the voltage divider circuit is connected to an output end of the thermistor; An instrument amplifier, wherein the input end of the instrument amplifier is connected to the output end of the voltage divider circuit, and the output end of the instrument amplifier is connected to the input end of the analog-to-digital sampling circuit.

9. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to claim 8 is characterized in that: The gain and bias voltage of the instrument amplifier are configured based on the temperature impedance curve of the short-wave infrared detector so that the output signal of the instrument amplifier matches the range of the analog-to-digital sampling circuit.

10. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to any one of claims 1 to 9, characterized in that: The FPGA circuit comprises: FPGA chip, the model of the FPGA chip is XQ4VSX55-10FF1148M; A refresh chip, the model of which is JMRS01RH; FLASH memory, the model of the FLASH memory is JFM29LV641RH; Wherein, the refresh chip and the FLASH memory are both connected to the FPGA chip to support on-track reconstruction of the FPGA chip.

11. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to any one of claims 1 to 9, characterized in that: Also includes: A logic drive circuit, one end of which is connected to the FPGA circuit, and the other end of which is connected to the short-wave infrared detector, so as to transmit the drive signal to the short-wave infrared detector.

12. The satellite-borne large-array high-frame-rate short-wave infrared detector data acquisition system according to any one of claims 1 to 9, characterized in that: Also includes: A secondary power supply circuit is connected to the FPGA circuit and the short-wave infrared detector respectively.

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