Space-borne large-aperture high-frame-rate short-wave infrared detector data acquisition system

Abstract

The application relates to a kind of spaceborne large array high frame frequency short wave infrared detector data acquisition systems, using 1024*512 large array short wave infrared detector, and special collection circuit is designed for 8-way output of 1024*512 large array detector, first, the 8-way signal output by detector is conditioned through analog front-end circuit, after conditioning, 8-way signal is synchronously sampled through three analog-digital sampling chips, to be synchronously input to FPGA circuit, so that FPGA circuit quickly generates frame image. That is, by selecting three analog-digital sampling chips supporting 3-channel sampling, FPGA circuit as master control chip to complete 8-channel simultaneous readout of 1024*512 large array detector, while improving the number of pixels and increasing frame frequency, the volume, weight and power consumption of the spaceborne hyperspectral imager data transmission link are reduced, and the quality of image transmission is effectively guaranteed.

Description

Technical Field

[0001] This application relates to the field of aerospace optical remote sensing imaging technology, and in particular to a data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector. Background Technology

[0002] With the development of aerospace optical remote sensing imaging technology, the requirements for the spatial resolution, spectral resolution and signal-to-noise ratio of spaceborne hyperspectral imagers are constantly increasing, and there is an urgent need to provide a data acquisition system for spaceborne infrared detectors that can meet the new requirements. Summary of the Invention

[0003] Therefore, it is necessary to provide a data acquisition system for a spaceborne large-area array high-frame-rate shortwave infrared detector.

[0004] This application provides a data acquisition system for a spaceborne large-area array high-frame-rate shortwave infrared detector, comprising:

[0005] The shortwave infrared detector has an array size of 1024*512 and eight output terminals. It is used to convert the received infrared radiation into electrical signals under the drive signal.

[0006] The analog front-end circuit has eight input terminals that are connected one-to-one with the eight output terminals of the shortwave infrared detector. The analog front-end circuit is used to condition the electrical signal.

[0007] Three analog-to-digital sampling chips, each supporting three-channel signal sampling, with the eight input terminals of the three chips respectively connected to the eight output terminals of the analog-to-digital front-end circuit to synchronously receive eight electrical signals output from the analog front-end circuit;

[0008] Temperature control feedback circuit: The temperature control feedback circuit is used to collect the temperature of the shortwave infrared detector and output a feedback signal characterizing the temperature.

[0009] The FPGA circuit is connected to the eight outputs of three analog-to-digital sampling chips, the output of the temperature control feedback circuit, and the drive terminal of the short-wave infrared detector. The FPGA circuit is used to adjust the drive signal output to the short-wave infrared detector according to the feedback signal, and to generate and output an image to the data transmission subsystem based on the signal output from the analog front-end circuit.

[0010] In one embodiment, the analog-to-digital sampling chip is model AD9826, and the registers of the analog-to-digital sampling chip are configured as follows: input range 4V; internal reference enable; three-channel mode; input clamp voltage 4V; output mode two bytes; external bias OFFSET grounded.

[0011] In one embodiment, the data acquisition system for a spaceborne large-area array high-frame-rate shortwave infrared detector further includes:

[0012] The SRAM cache circuit is connected to the FPGA circuit and is used to store images.

[0013] In one embodiment, the SRAM cache circuit employs a radiation-hardened SRAM module B8CR1M39H.

[0014] In one embodiment, each output of the shortwave infrared detector has a reference level output pin and a signal level output pin, and the analog front-end circuit includes:

[0015] Eight signal conditioning modules are provided. The first input terminal of the signal conditioning module is connected to the signal level output pin of the shortwave infrared detector, the second input terminal of the signal conditioning module is connected to the reference level output pin of the shortwave infrared detector, and the output terminal of the signal conditioning module is connected to the input terminal of the analog-to-digital sampling chip.

[0016] In one embodiment, the signal conditioning module includes:

[0017] The first voltage follower has its input terminal connected to the signal level output pin of the shortwave infrared detector.

[0018] The second voltage follower is connected to the reference level output pin of the shortwave infrared detector.

[0019] The differential circuit has its first input terminal connected to the output terminal of the first voltage follower, its second input terminal connected to the output terminal of the second voltage follower, and its output terminal connected to one input terminal of the analog-to-digital sampling chip.

[0020] In one embodiment, the temperature control feedback circuit includes:

[0021] Temperature feedback circuit, used to collect the temperature of the shortwave infrared detector;

[0022] The analog-to-digital sampling circuit has its input connected to the output of the temperature feedback circuit, and its output connected to the feedback of the FPGA circuit.

[0023] In one embodiment, the temperature feedback circuit includes:

[0024] A thermistor is placed on a short-wave infrared detector to detect the temperature of the short-wave infrared detector.

[0025] A voltage divider circuit is used, with its input terminal connected to the output terminal of a thermistor.

[0026] The instrumentation amplifier's input is connected to the output of the voltage divider circuit, and its output is connected to the input of the analog-to-digital sampling circuit.

[0027] In one embodiment, the gain and bias voltage of the instrumentation amplifier are configured based on the temperature impedance curve of the shortwave infrared detector so that the output signal of the instrumentation amplifier is matched with the range of the analog-to-digital sampling circuit.

[0028] In one embodiment, the FPGA circuit includes:

[0029] The FPGA chip is model XQ4VSX55-10FF1148M.

[0030] The refresh chip is model JMRS01RH.

[0031] The FLASH memory is model JFM29LV641RH;

[0032] Both the refresh chip and the FLASH memory are connected to the FPGA chip to support on-orbit reconfiguration of the FPGA chip.

[0033] In one embodiment, the data acquisition system for a spaceborne large-area array high-frame-rate shortwave infrared detector further includes:

[0034] The logic driver circuit has one end connected to the FPGA circuit and the other end connected to the shortwave infrared detector to transmit the drive signal to the shortwave infrared detector.

[0035] In one embodiment, the data acquisition system for a spaceborne large-area array high-frame-rate shortwave infrared detector further includes:

[0036] The secondary power supply circuit is connected to both the FPGA circuit and the shortwave infrared detector.

[0037] The aforementioned spaceborne large-area array high-frame-rate shortwave infrared detector data acquisition system employs a 1024*512 large-area array shortwave infrared detector. A dedicated acquisition circuit is designed for the eight outputs of the 1024*512 large-area array detector. First, the eight output signals are conditioned by an analog front-end circuit. Then, the conditioned signals are synchronously sampled by three analog-to-digital sampling chips and input to the FPGA circuit, enabling the FPGA circuit to quickly generate frame images. In other words, by selecting three analog-to-digital sampling chips supporting three-channel sampling and the FPGA circuit as the main control chip, the system achieves simultaneous readout of eight channels from the 1024*512 large-area array detector. This increases the pixel count and frame rate while reducing the size, weight, and power consumption of the spaceborne hyperspectral imager data transmission link, effectively ensuring the quality of image transmission. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is one of the structural schematic diagrams of a data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to an embodiment;

[0040] Figure 2 This is a second schematic diagram of the structure of a spaceborne large-area array high frame rate shortwave infrared detector data acquisition system according to one embodiment;

[0041] Figure 3 This is a schematic diagram of the structure of a signal conditioning module according to one embodiment;

[0042] Figure 4 The circuit schematic of the B54ACS164245SRHF chip is shown in a specific embodiment.

[0043] Figure 5 The timing diagram shows the 11 drive signals in a specific embodiment.

[0044] Figure 6 The circuit schematic of the radiation-resistant linear regulator RSW1201A is shown in a specific embodiment.

[0045] Figure 7 The circuit schematic of the precision reference voltage chip AD580 is shown in a specific implementation.

[0046] Figure 8 This is a circuit schematic diagram of an implementation of an 8-channel bias voltage generation based on a low-power operational amplifier LM158. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It is understood that the terms "first," "second," etc., used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have the transmission of electrical signals or data between them.

[0050] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0052] In one implementation, a data acquisition system 100 for a spaceborne large-area array high-frame-rate shortwave infrared detector is provided, such as... Figure 1 As shown, the system 100 includes: a shortwave infrared detector 1, an analog front-end circuit 2, three analog-to-digital sampling chips 3, a temperature control feedback circuit 4, and an FPGA circuit 5.

[0053] The shortwave infrared detector 1 has an array size of 1024*512 and eight output terminals. It converts received infrared radiation into electrical signals under the drive of a driving signal. The eight input terminals of the analog front-end circuit 2 are connected one-to-one with the eight output terminals of the shortwave infrared detector 1, and the analog front-end circuit 2 is used to condition the electrical signals. Each analog-to-digital sampling chip 3 supports three-channel signal sampling, and the eight input terminals of the three analog-to-digital sampling chips 3 are respectively connected to the eight output terminals of the analog-to-digital front-end circuit to synchronously receive the eight electrical signals output by the analog front-end circuit 2. The temperature control feedback circuit 4 is used to acquire the temperature of the shortwave infrared detector 1 and output a feedback signal characterizing the temperature. The FPGA circuit 5 is connected to the eight output terminals of the three analog-to-digital sampling chips 3, the output terminal of the temperature control feedback circuit 4, and the driving terminal of the short-wave infrared detector 1. The FPGA circuit 5 is used to adjust the driving signal output to the short-wave infrared detector 1 according to the feedback signal, and to generate and output an image to the data transmission subsystem 100 based on the signal output by the analog front-end circuit.

[0054] Among them, the shortwave infrared detector 1 has a response band of 1635-1655nm and a pixel size of 30um.

[0055] Specifically, the data acquisition system of the spaceborne large-area array high-frame-rate shortwave infrared detector 1 adopts a 1024*512 large-area array shortwave infrared detector 1. A dedicated acquisition circuit is designed for the 8 outputs of the 1024*512 large-area array detector. First, the 8 output signals of the detector are conditioned by the analog front-end circuit 2. After conditioning, the 8 signals are synchronously sampled by three analog-to-digital sampling chips 3 and input synchronously to the FPGA circuit 5, enabling the FPGA circuit 5 to quickly generate frame images. That is, by selecting three analog-to-digital sampling chips 3 supporting 3-channel sampling and the FPGA circuit 5 as the main control chips to complete the simultaneous readout of the 8 channels of the 1024*512 large-area array detector, the number of pixels and the frame rate are increased while the size, weight, and power consumption of the data transmission link of the spaceborne hyperspectral imager are reduced, effectively ensuring the quality of image transmission.

[0056] The data acquisition system for the spaceborne large-area array high-frame-rate short-wave infrared detector 1 provided in this application embodiment uses a 1024*512 pixel short-wave infrared detector 1, employs 8 channels for simultaneous readout, achieves a maximum readout rate of 20MHz, and a maximum frame rate of 250Hz. This solves the problems of limited pixel count, slow readout speed, and low frame rate in traditional spaceborne hyperspectral imager short-wave infrared detector 1 data acquisition systems.

[0057] In one embodiment, the analog-to-digital sampling chip 3 is model AD9826, and the registers of the analog-to-digital sampling chip 3 are configured as follows: input range 4V; internal reference enable; three-channel mode; input clamp voltage 4V; output mode two-byte; external bias OFFSET grounded.

[0058] The analog-to-digital sampling chip 3 converts the analog signal output from the shortwave infrared detector 1 from the analog front-end circuit 2 into a digital signal and transmits it to the FPGA circuit 5 for image processing. The analog-to-digital sampling chip 3 can be an AD9826, a 3-channel, 16-bit high-speed analog-to-digital converter from Analog Devices. Three AD9826 chips are used to acquire the eight analog signals output from the shortwave infrared detector 1. The AD9826 register is set as follows: input range 4V; internal reference enabled; three-channel mode; input clamp 4V; output mode two bytes. The external bias OFFSET is grounded. With this AD9826 setting, the AD9826 gain G can be set to 23 (17H), resulting in Gain = 1.437. This amplifies the analog voltage output from the shortwave infrared detector 1 to 0.201–3.932, reaching the full scale of the analog-to-digital sampling chip 3. Approaching full scale improves measurement accuracy.

[0059] In one embodiment, such as Figure 2 As shown, the data acquisition system of the spaceborne large-area array high frame rate shortwave infrared detector 1 also includes: SRAM cache circuit 6.

[0060] The SRAM cache circuit 6 is connected to the FPGA circuit 5, and the SRAM cache circuit 6 is used to store the image.

[0061] The shortwave infrared detector 1 outputs an image frame of approximately 8.4 Mbit. Since the storage space of the FPGA circuit 5 is limited, the data storage capacity during data reception and processing can be improved by adding an SRAM cache circuit 6.

[0062] In one embodiment, the SRAM cache circuit 6 employs a radiation-hardened SRAM module B8CR1M39H.

[0063] The radiation-hardened SRAM module B8CR1M39H has 40 signal input pins, a capacity of 40Mbit, a write time of only 20ns, and can write 40 bits of data at a time. It can support the large-capacity buffer requirements of 8 simultaneous outputs from shortwave infrared detectors.

[0064] In one embodiment, each output terminal of the shortwave infrared detector 1 has a reference level output pin and a signal level output pin, and the analog front-end circuit 2 includes 8 signal conditioning modules.

[0065] The first input terminal of the signal conditioning module is connected to the signal level output pin of the shortwave infrared detector 1, the second input terminal of the signal conditioning module is connected to the reference level output pin of the shortwave infrared detector 1, and the output terminal of the signal conditioning module is connected to the input terminal of the analog-to-digital sampling chip 3.

[0066] The analog output signal of the shortwave infrared detector 1 is read out in parallel from eight differential channels. Its output employs correlated double sampling technology, meaning each channel consists of a reference level output pin and a signal level output pin. The effective signal is the difference between the reference level and the signal level. This effectively eliminates noise generated during reset and improves the reliability of the shortwave infrared detector 1's output signal. Furthermore, in conjunction with eight signal conditioning modules, each module receives and conditions one output channel of the shortwave infrared detector 1 to output a conditioned analog signal to the corresponding analog sampling chip.

[0067] In one embodiment, such as Figure 3 As shown, the signal conditioning module includes: a first voltage follower 211, a second voltage follower 212, and a differential circuit 213.

[0068] The input terminal of the first voltage follower 211 is connected to the signal level output pins (Vout1_N, Vout2_N, Vout3_N, Vout4_N, Vout5_N, Vout6_N, Vout7_N, Vout8_N) of the shortwave infrared detector 1. Figure 3 (Only one path, Vout1_N, is given as an example); the input of the second voltage follower 212 is connected to the reference level output pins (Vout1_P, Vout2_P, Vout3_P, Vout4_P, Vout5_P, Vout6_P, Vout7_P, Vout8_P) of the shortwave infrared detector 1. Figure 3 (Only one Vout1_P is given as an example); the first input terminal of the differential circuit 213 is connected to the output terminal of the first voltage follower 211, the second input terminal of the differential circuit 213 is connected to the output terminal of the second voltage follower 212, and the output terminal of the differential circuit 213 is connected to one input terminal of the analog-to-digital sampling chip 3.

[0069] The reference level output pin of the shortwave infrared detector 1 outputs a reference level range of 2.2–2.4V, and the signal level output pin outputs a signal level range of 0.4–2.4V. Therefore, the effective signal level range after differential is -0.2–2.0V, and the detector output impedance is greater than 10KΩ. A first voltage follower and a second voltage follower can be used to follow the signal level and reference level output by the shortwave infrared detector 1, respectively. Then, through a differential circuit, the effective signal level range of the shortwave infrared detector 1 is inverted. When the parameter A of the differential circuit is 11.8 / 10 = 1.18, the effective signal level range of the shortwave infrared detector 1 can be inverted to 0.14–2.736V (effective signal level Vout = (Vout_N - Vout_P)*A + 2.5V = 0.14–2.736V), which is close to the full-scale range of the analog-to-digital sampling chip 3, thus improving measurement accuracy.

[0070] Optionally, the signal conditioning module can use the AD8042 rail-to-rail dual-channel operational amplifier chip from Analog Devices. Since the shortwave infrared detector 1 uses 8 simultaneous readouts, 8 AD8042 chips are needed to simultaneously condition the 8 signals from the shortwave infrared detector 1. Figure 3 Only the signal conditioning module corresponding to the output of one shortwave infrared detector 1 is shown. The signal conditioning modules for the other 7 analog output signals are the same and will not be described in detail here.

[0071] Among them, such as Figure 3 As shown, a filter circuit can be set at the 5V voltage input terminal of the differential circuit and voltage follower, for example, a filter circuit formed by connecting C1, C2, C3, C4, C5, and C6 in series and parallel, to improve the stability and reliability of the signal conditioning module.

[0072] In one embodiment, the temperature control feedback circuit 4 includes a temperature feedback circuit 41 and an analog-to-digital sampling circuit 42.

[0073] The temperature feedback circuit 41 is used to collect the temperature of the shortwave infrared detector 1; the input terminal of the analog-to-digital sampling circuit 42 is connected to the output terminal of the temperature feedback circuit 41, and the output terminal of the analog-to-digital sampling circuit 42 is connected to the feedback terminal of the FPGA circuit 5.

[0074] Under this circuit architecture, the FPGA circuit 5 can adjust the driving signal applied to the short-wave infrared detector 1 in real time according to the acquired temperature of the short-wave infrared detector 1, so as to achieve high-precision temperature control of the short-wave infrared detector 1.

[0075] In one embodiment, the analog-to-digital sampling circuit 42 can be a TI 8-channel, 12-bit, serial output analog-to-digital converter ADC128S102. The signal output by the shortwave infrared detector 1 is converted from analog to digital by the ADC128S102 and then input to the FPGA circuit 5 for acquisition. The PID control algorithm inside the FPGA circuit 5 is used to calculate and generate a drive signal, thereby realizing high-precision temperature control of the shortwave infrared detector 1.

[0076] In one embodiment, the temperature feedback circuit 41 includes a thermistor, a voltage divider circuit, and an instrumentation amplifier.

[0077] The thermistor is mounted on the short-wave infrared detector 1 to detect the temperature of the short-wave infrared detector 1; the input terminal of the voltage divider circuit is connected to the output terminal of the thermistor; the input terminal of the instrumentation amplifier is connected to the output terminal of the voltage divider circuit, and the output terminal of the instrumentation amplifier is connected to the input terminal of the analog-to-digital sampling circuit 42.

[0078] The temperature feedback circuit 41 performs bias elimination and amplification on the temperature feedback voltage signal output by the shortwave infrared detector 1. The temperature feedback circuit 41 can be implemented by building an instrumentation amplifier using the TI Q-level operational amplifier device LM158AJ. The thermistor signal output by the shortwave infrared detector 1 is connected to the voltage divider circuit to match the input requirements of the instrumentation amplifier. After being amplified by the instrumentation amplifier, it is input to the analog-to-digital sampling circuit 42 for analog-to-digital conversion. The digital signal representing the temperature of the shortwave infrared detector 1 is then transmitted to the FPGA circuit 5, providing data for the FPGA circuit 5 to adjust the output drive signal and ensuring the operating temperature stability of the shortwave infrared detector 1.

[0079] In one embodiment, the gain and bias voltage of the instrumentation amplifier are configured based on the temperature impedance curve of the shortwave infrared detector 1, so that the output signal of the instrumentation amplifier matches the range of the analog-to-digital sampling circuit 42. According to the temperature impedance curve, the gain and bias voltage of the instrumentation amplifier are adjusted so that they can meet the full-scale range of the analog-to-digital sampling circuit 42 (e.g., the 3.3V range of the ADC128S102) within the temperature fluctuation range, thereby improving measurement accuracy.

[0080] In one embodiment, the FPGA circuit 5 includes: an FPGA chip, a refresh chip, and a FLASH memory.

[0081] The FPGA chip is model XQ4VSX55-10FF1148M; the refresh chip is model JMRS01RH; and the FLASH memory is model JFM29LV641RH. Both the refresh chip and the FLASH memory are connected to the FPGA chip to support on-orbit reconfiguration of the FPGA chip.

[0082] The FPGA chip selected is the Xilinx XQ4VSX55-10FF1148M, a military-grade product. This SRAM-based FPGA has 55,296 logic cells, 640 I / O ports, and a maximum system operating frequency of 500MHz. To enhance the FPGA's space environment adaptability, the domestically produced Fudan Microelectronics radiation-hardened refresh chip JMRS01RH and the reset micro 64M radiation-hardened FLASH memory JFM29LV641RH were used for on-orbit reconfiguration of the FPGA. The JMRS01RH can periodically detect and refresh the FPGA's SEFI status, reducing the cumulative effect of single-event events (SEE), and is an important solution for improving the SEE performance of SRAM-based FPGAs.

[0083] The circuit devices provided in this application are all from the aerospace catalog and can be applied to short-wave infrared detection in aerospace scenarios.

[0084] In one embodiment, the data acquisition system of the spaceborne large-area array high frame rate shortwave infrared detector 1 further includes:

[0085] The logic driving circuit 7 is connected at one end to the FPGA circuit 5 and at the other end to the shortwave infrared detector 1 to transmit the driving signal to the shortwave infrared detector 1.

[0086] The 11 drive signals required by the shortwave infrared detector 1 are generated by the FPGA circuit 5. These signals can be driven by an aerospace-grade radiation-hardened bidirectional transceiver chip, the B54ACS164245SRHF, and then input to the shortwave infrared detector 1. The implementation principle of the B54ACS164245SRHF chip is as follows: Figure 4 As shown.

[0087] based on Figure 4 The chip pins shown input column clock signal (CLKCOL), row clock signal (CLKROW), row trigger clock signal (STROW), row and column trigger signal (STROWCOL), column operational amplifier trigger signal (STCOLOP), column trigger signal (STCOL), reset signal (RESET), SH1 signal, SH2 signal, SELCAP signal, and SEL128 signal. The amplitude of the drive signal is required to be 0-3.3V.

[0088] The timing diagram of the 11 drive signals is as follows: Figure 5 As shown, under this timing, the shortwave infrared detector 1 can be driven to perform infrared detection.

[0089] In one embodiment, the data acquisition system of the spaceborne large-area array high-frame-rate shortwave infrared detector 1 further includes a secondary power supply circuit 8. The secondary power supply circuit 8 is connected to both the FPGA circuit 5 and the shortwave infrared detector 1.

[0090] The secondary power supply circuit 8 is responsible for providing the operating voltage to the FPGA circuit 5 and the shortwave infrared detector 1 to meet their power supply requirements.

[0091] In one embodiment, the secondary power supply circuit 8 provides 10 bias voltages to meet the power supply requirements of the data acquisition system of the spaceborne large-area array high-frame-rate shortwave infrared detector 1. The current and voltage requirements of the various power supplies required for its operation are shown in Table 1.

[0092] Table 1

[0093]

[0094] In one embodiment, the generation of 10 bias voltages can be specifically achieved by selecting, for example... Figure 6 The radiation-resistant linear regulator RSW1201A shown generates a 3.3V bias voltage. An Analog Devices (AD) precision reference voltage chip AD580 can be used to convert the +5V voltage obtained from the secondary power supply to +2.5V (e.g., ...). Figure 7 As shown), by using the low-power operational amplifier LM158 from Texas Instruments (TI), the 2.5V is divided to obtain the remaining 8 bias voltages required by the detector, such as... Figure 8 As shown.

[0095] In one embodiment, the FPGA circuit 5 is also connected to the cooling device through the cooling control output interface 9 to control the working device of the cooling device and, in conjunction with the adjustment of the drive signal, to achieve precise temperature control of the shortwave infrared detector 1.

[0096] In one embodiment, the FPGA circuit 5 is also connected to the CAN bus 10, which is connected to the data management subsystem to enable communication between the FPGA circuit 5 and the data management subsystem.

[0097] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector, characterized in that, include: A shortwave infrared detector, the array size of which is 1024*512, has 8 output terminals, and is used to convert received infrared radiation into electrical signals under the drive signal. An analog front-end circuit is provided, wherein the eight input terminals of the analog front-end circuit are respectively connected to the eight output terminals of the shortwave infrared detector, and the analog front-end circuit is used to condition the electrical signal. Three analog-to-digital sampling chips, each supporting three-channel signal sampling, with the eight input terminals of the three analog-to-digital sampling chips respectively connected to the eight output terminals of the analog-to-digital front-end circuit to synchronously receive the eight electrical signals output by the analog front-end circuit; A temperature control feedback circuit is used to acquire the temperature of the shortwave infrared detector and output a feedback signal characterizing the temperature. The FPGA circuit is connected to the eight output terminals of the three analog-to-digital sampling chips, the output terminal of the temperature control feedback circuit, and the driving terminal of the short-wave infrared detector. The FPGA circuit is used to adjust the driving signal output to the short-wave infrared detector according to the feedback signal, and to generate and output an image to the data transmission subsystem based on the signal output by the analog front-end circuit.

2. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 1, characterized in that, The analog-to-digital sampling chip is model AD9826, and its registers are configured as follows: input range 4V; internal reference enable; three-channel mode; input clamp voltage 4V; output mode two bytes; external bias OFFSET grounded.

3. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 1, characterized in that, Also includes: An SRAM cache circuit is connected to the FPGA circuit and is used to store the image.

4. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 3, characterized in that, The SRAM cache circuit uses a radiation-hardened SRAM module B8CR1M39H.

5. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 1, characterized in that, Each output of the shortwave infrared detector has a reference level output pin and a signal level output pin. The analog front-end circuit includes: Eight signal conditioning modules are provided. The first input terminal of each signal conditioning module is connected to the signal level output pin of the shortwave infrared detector, the second input terminal of each signal conditioning module is connected to the reference level output pin of the shortwave infrared detector, and the output terminal of each signal conditioning module is connected to the input terminal of the analog-to-digital sampling chip.

6. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 5, characterized in that, The signal conditioning module includes: A first voltage follower, the input of which is connected to the signal level output pin of the shortwave infrared detector; The second voltage follower is connected to the reference level output pin of the shortwave infrared detector. A differential circuit, wherein the first input terminal of the differential circuit is connected to the output terminal of the first voltage follower, the second input terminal of the differential circuit is connected to the output terminal of the second voltage follower, and the output terminal of the differential circuit is correspondingly connected to one input terminal of the analog-to-digital sampling chip.

7. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 1, characterized in that, The temperature control feedback circuit includes: A temperature feedback circuit is used to collect the temperature of the shortwave infrared detector. An analog-to-digital sampling circuit is provided, wherein the input terminal of the analog-to-digital sampling circuit is connected to the output terminal of the temperature feedback circuit, and the output terminal of the analog-to-digital sampling circuit is connected to the feedback terminal of the FPGA circuit.

8. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 7, characterized in that, The temperature feedback circuit includes: A thermistor is disposed on the short-wave infrared detector to detect the temperature of the short-wave infrared detector; A voltage divider circuit, wherein the input terminal of the voltage divider circuit is connected to the output terminal of the thermistor; An instrumentation amplifier, the input of which is connected to the output of the voltage divider circuit, and the output of which is connected to the input of the analog-to-digital sampling circuit.

9. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to claim 8, characterized in that, The gain and bias voltage of the instrumentation amplifier are configured based on the temperature impedance curve of the shortwave infrared detector so that the output signal of the instrumentation amplifier matches the range of the analog-to-digital sampling circuit.

10. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to any one of claims 1-9, characterized in that, The FPGA circuit includes: FPGA chip, the model of which is XQ4VSX55-10FF1148M; A refresh chip, the model of which is JMRS01RH; The FLASH memory is model JFM29LV641RH; The refresh chip and the FLASH memory are both connected to the FPGA chip to support on-orbit reconfiguration of the FPGA chip.

11. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to any one of claims 1-9, characterized in that, Also includes: A logic driving circuit is provided, one end of which is connected to the FPGA circuit, and the other end of which is connected to the shortwave infrared detector, so as to transmit the driving signal to the shortwave infrared detector.

12. The data acquisition system for a spaceborne large-area array high frame rate shortwave infrared detector according to any one of claims 1-9, characterized in that, Also includes: A secondary power supply circuit is provided, which is connected to both the FPGA circuit and the shortwave infrared detector.

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