Test circuits, methods, apparatus, equipment, media, and products for power semiconductors

Abstract

This invention relates to the field of power semiconductor test circuit technology, and particularly to a power semiconductor test circuit, method, apparatus, device, medium, and product. The circuit includes a DC power supply and a device under test (DUT), wherein the DUT includes a first DUT and a second DUT; a first terminal of the first DUT is connected to the positive terminal of the DC power supply, and a second terminal of the first DUT is connected to the first terminal of the second DUT; the second terminal of the second DUT is connected to the negative terminal of the DC power supply; and the circuit is capable of accurately measuring the switching losses of the power semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor testing technology, and particularly to a power semiconductor testing circuit, method, apparatus, device, medium, and product. Background Technology

[0002] Datasheets for power semiconductor devices provide turn-on and turn-off energies, values ​​obtained from tests based on specific electrical parameters. However, in practical applications, due to differences in application scenarios and specific design requirements, the switching voltage / current, drive resistance, and drive voltage of power semiconductor devices are difficult to maintain consistency with the datasheets. Continuing to use the turn-on and turn-off energies from the datasheets for calculations will result in significant deviations in the calculated switching losses, potentially leading to the burnout of the power semiconductor device. This presents a technical problem in the field: the difficulty in measuring the switching losses of power semiconductor devices. Summary of the Invention

[0003] This invention provides a test circuit, method, apparatus, device, medium, and product for power semiconductors, solving the technical problem of the difficulty in measuring the switching losses of power semiconductor devices.

[0004] In a first aspect, the present invention provides a test circuit for a power semiconductor, the circuit comprising: a DC power supply and a device under test (DUT), wherein the DUT comprises a first DUT and a second DUT; a first terminal of the first DUT is connected to the positive terminal of the DC power supply, a second terminal of the first DUT is connected to the first terminal of the second DUT; and a second terminal of the second DUT is connected to the negative terminal of the DC power supply.

[0005] In some embodiments, the circuit further includes: an input capacitor, an inductor, and an output capacitor; the input capacitor is connected in parallel to both ends of a DC power supply; the first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor; the second end of the output capacitor is connected to the negative terminal of the DC power supply.

[0006] In some embodiments, the device under test includes a metal-oxide-semiconductor field-effect transistor and an insulated-gate bipolar transistor.

[0007] In a second aspect, the present invention provides a power semiconductor testing method based on a power semiconductor test circuit according to any of the above aspects, the method comprising: obtaining the equivalent series resistance of the test circuit; driving the test circuit based on a preset driving signal to make the test circuit work in a preset mode; acquiring the electrical parameters of the test circuit in the preset mode; and calculating the turn-off loss of the device under test based on the electrical parameters.

[0008] In some embodiments, the step of driving the test circuit based on a preset driving signal includes: turning on a first device under test (DUT) of the test circuit at time zero based on the preset driving signal, turning off the first DUT of the test circuit at a second time based on the preset driving signal; turning on a second DUT of the test circuit at a second time based on the preset driving signal, and turning off the second DUT of the test circuit at a fourth time based on the preset driving signal.

[0009] In some embodiments, the step of calculating the turn-off loss of the device under test (DUT) based on electrical parameters includes: calculating the input power of the test circuit based on the current and voltage of the DC power supply in the test circuit; calculating the line loss of the test circuit and the conduction loss of the DUT based on the line current in the test circuit, the current of the DUT, and the equivalent series resistance of the test circuit; and subtracting the input power from the line loss of the test circuit and the conduction loss of the DUT to obtain the turn-off loss of the DUT.

[0010] Thirdly, the present invention provides a power semiconductor testing apparatus based on a power semiconductor testing circuit according to any of the above aspects. The apparatus includes: an acquisition module for acquiring the equivalent series resistance of the test circuit; a driving module for driving the test circuit based on a preset driving signal to make the test circuit work in a preset mode; a data acquisition module for acquiring the electrical parameters of the test circuit in the preset mode; and a calculation module for calculating the turn-off loss of the device under test based on the electrical parameters.

[0011] Fourthly, the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any of the above-described power semiconductor testing methods.

[0012] Fifthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the power semiconductor testing method of any of the above aspects.

[0013] In a sixth aspect, the present invention provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the power semiconductor testing method according to any of the above aspects.

[0014] This invention provides a test circuit, method, apparatus, device, medium, and product for power semiconductors. The circuit includes a DC power supply and a device under test (DUT). The DUT includes a first DUT and a second DUT. A first terminal of the first DUT is connected to the positive terminal of the DC power supply, and a second terminal of the first DUT is connected to the first terminal of the second DUT. A second terminal of the second DUT is connected to the negative terminal of the DC power supply. This invention enables accurate measurement of the switching losses of power semiconductor devices. Attached Figure Description

[0015] The invention will now be described in more detail with reference to embodiments and the accompanying drawings:

[0016] Figure 1 This is a schematic diagram of a test circuit for power semiconductors provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a power semiconductor testing method provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of a power semiconductor testing device provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the test waveform of the power semiconductor provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of a circuit with ESR provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of a test circuit for the first mode of a power semiconductor provided in an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of a test circuit for the second mode of a power semiconductor provided in an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of the test circuit for the third mode of power semiconductors provided in an embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of a test circuit for the fourth mode of a power semiconductor provided in an embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of the IGBT test circuit provided in an embodiment of the present invention;

[0026] Figure 11 This is a schematic diagram of the IGBT test waveform provided in an embodiment of the present invention.

[0027] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention and to fully understand and implement the process of how the present invention uses technical means to solve technical problems and achieve corresponding technical effects, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The embodiments of the present invention and the various features therein can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0031] Datasheets for power semiconductor devices provide turn-on and turn-off energies, values ​​obtained from tests based on specific electrical parameters. However, in practical applications, due to differences in application scenarios and specific design requirements, the switching voltage / current, drive resistance, and drive voltage of power semiconductor devices are difficult to maintain consistency with the datasheets. Continuing to use the turn-on and turn-off energies from the datasheets for calculations will result in significant deviations in the calculated switching losses, potentially leading to the burnout of the power semiconductor device. This presents a technical problem in the field: the difficulty in measuring the switching losses of power semiconductor devices.

[0032] The technical solution of this application will be described below with reference to specific embodiments.

[0033] Example 1

[0034] Figure 1 This is a schematic diagram of a test circuit for power semiconductors provided in an embodiment of the present invention. Figure 1 As shown in the technical solution of this embodiment, a test circuit for power semiconductors is provided. The circuit includes a DC power supply and a device under test (DUT). The DUT includes a first DUT and a second DUT. A first terminal of the first DUT is connected to the positive terminal of the DC power supply, and a second terminal of the first DUT is connected to the first terminal of the second DUT. The second terminal of the second DUT is connected to the negative terminal of the DC power supply.

[0035] The technical problem this embodiment aims to solve is how to construct a test circuit for measuring the switching losses of power semiconductor devices. In the field of power semiconductor device switching loss testing, a suitable test circuit is needed to perform subsequent testing work, which is the basis for accurately measuring switching losses.

[0036] The technical solution of this embodiment constructs the main body of the test circuit by setting up a DC power supply and a device under test (DUT). The DUT is divided into a first DUT and a second DUT. The first terminal of the first DUT is connected to the positive terminal of the DC power supply, and its second terminal is connected to the first terminal of the second DUT. The second terminal of the second DUT is connected to the negative terminal of the DC power supply. This connection method provides the basic architecture for the subsequent construction of the complete test circuit and the testing of switching losses of power semiconductor devices, and is the core part of the entire test circuit.

[0037] The technical solution of this embodiment first clarifies the basic architecture of the main test circuit, providing a foundational framework for subsequent additions of other components to complete the test circuit. For example, in a complete test circuit, subsequently added components such as input capacitors, inductors, and output capacitors can all be connected based on this main architecture. This main architecture enables accurate measurement of the switching losses of power semiconductor devices. Without this basic circuit structure, a complete test environment cannot be established. Moreover, this simple main architecture is easily applicable to different types of power semiconductor devices, including metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), all of which can be tested based on this architecture. This facilitates the unified construction of a basic architecture across various power semiconductor device testing scenarios, improving testing efficiency and providing a stable foundation for subsequent more complex test circuit designs and test method applications.

[0038] Example 2

[0039] Based on the above embodiments, the circuit further includes: an input capacitor, an inductor, and an output capacitor; the input capacitor is connected in parallel to both ends of the DC power supply; the first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor; the second end of the output capacitor is connected to the negative terminal of the DC power supply.

[0040] The technical problem this embodiment aims to solve is how to construct a complete test circuit for measuring the switching losses of power semiconductor devices. After constructing the main body of the test circuit, other components need to be added to form a complete test circuit in order to achieve comprehensive testing of the switching losses of power semiconductor devices.

[0041] The technical solution of this embodiment constructs a complete test circuit by adding an input capacitor, an inductor, and an output capacitor to the above embodiment. The input capacitor is connected in parallel to both ends of the DC power supply to stabilize the input voltage; the first end of the inductor is connected to the second end of the first device under test, and the second end is connected to the first end of the output capacitor; the second end of the output capacitor is connected to the negative terminal of the DC power supply to stabilize the output voltage. The addition of these components improves the test circuit, enabling it to better simulate actual operating conditions and providing a complete circuit environment for accurately measuring the switching losses of power semiconductor devices.

[0042] The technical solution of this embodiment, by adding these components, forms a complete test circuit. The input capacitor filters out high-frequency noise in the power supply, ensuring the stability of the input voltage, which is crucial for accurately measuring the switching losses of power semiconductor devices. Unstable input voltage can lead to measurement deviations. The inductor acts as a filter and energy storage unit in the circuit; it can be adjusted according to the required device turn-off current value, allowing the test circuit to better simulate current changes under actual operating conditions. The output capacitor stabilizes the output voltage, ensuring the stability of the test circuit output. This complete test circuit can more accurately simulate the working environment of power semiconductor devices in practical applications, thereby more accurately measuring their switching losses. Moreover, this complete test circuit structure has good versatility, adapting to the testing needs of different power semiconductor devices. By reasonably adjusting the parameters of each component, switching loss tests can be performed on various types of power semiconductor devices.

[0043] Example 3

[0044] Based on the above embodiments, the device under test includes a metal-oxide-semiconductor field-effect transistor and an insulated-gate bipolar transistor.

[0045] The technical problem this embodiment aims to solve is how to construct a test circuit for measuring the switching losses of various power semiconductor devices. In the testing of power semiconductor devices, a test circuit that can be applied to various different types of devices is needed to meet the requirements of different application scenarios.

[0046] The technical solution of this embodiment, by limiting the devices under test to include metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), constructs a test circuit capable of measuring the switching losses of various power semiconductor devices. Based on the previously constructed test circuit, both the main circuit structure and the various added components are compatible with these two common power semiconductor devices, thereby enabling the measurement of switching losses for different types of devices.

[0047] The technical solution of this embodiment, firstly, improves the versatility of the test circuit. In the application of power semiconductor devices, metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs) are two very common types of devices, and circuits capable of testing their switching losses have high practical value. This test circuit can adapt to different device characteristics; for example, MOSFETs have bidirectional conductivity, while IGBTs have unidirectional conductivity, and the test circuit can perform corresponding tests according to their characteristics. Through such a test circuit, different types of power semiconductor devices can be compared and evaluated under the same test environment, providing a more accurate reference for device selection and application.

[0048] Example 4

[0049] Figure 2 This is a schematic diagram of a power semiconductor testing method provided in an embodiment of the present invention, as shown below. Figure 2 As shown, in the technical solution of this embodiment, a test method for power semiconductors based on the test circuit of any of the power semiconductors in the above embodiments is provided. The method includes: obtaining the equivalent series resistance of the test circuit; driving the test circuit based on a preset driving signal to make the test circuit work in a preset mode; collecting the electrical parameters of the test circuit in the preset mode; and calculating the turn-off loss of the device under test based on the electrical parameters.

[0050] The technical problem to be solved in this embodiment is how to test the turn-off loss of power semiconductors based on the test circuit of the above embodiment? After having the test circuit, a complete test method is needed to effectively test the turn-off loss of power semiconductors.

[0051] The technical solution of this embodiment obtains the equivalent series resistance of the test circuit, drives the test circuit based on a preset drive signal to make the test circuit work in a preset mode, collects the electrical parameters of the test circuit in the preset mode, and finally calculates the turn-off loss of the device under test based on these electrical parameters. The equivalent series resistance can be obtained by testing with testing equipment or by referring to the technical specifications provided by the supplier. The preset drive signal is used to control the turn-on and turn-off of the devices in the test circuit. The preset mode is a different operating state divided according to the operating characteristics of the test circuit. The electrical parameters include voltage, current, and other parameters, which are key to calculating the turn-off loss.

[0052] The technical solution of this embodiment, through this testing method, can systematically test the turn-off loss of power semiconductor devices. Obtaining the equivalent series resistance takes into account the influence of the resistive characteristics of each component in the circuit on the turn-off loss, making the test results more accurate. Based on the preset drive signal and preset mode of operation, the working process of the test circuit can be precisely controlled, simulating the switching process of the power semiconductor device under actual operating conditions. The collection of electrical parameters provides a data foundation for subsequent calculations. Through reasonable calculation of these parameters, the turn-off loss of the device under test can be accurately obtained. This testing method has high accuracy and can effectively avoid the deviation in turn-off loss calculation caused by improper testing methods. In practical applications, this helps to more accurately evaluate the performance of power semiconductor devices in specific application scenarios, providing accurate data support for subsequent work such as thermal design, thereby avoiding over-design or under-design problems caused by inaccurate turn-off loss evaluation, and improving the reliability and economy of the entire power semiconductor device application system.

[0053] Example 5

[0054] Based on the above embodiments, the step of driving the test circuit based on a preset driving signal includes: turning on the first device under test (DUT) of the test circuit at time zero based on the preset driving signal, turning off the first DUT of the test circuit at time two based on the preset driving signal; turning on the second DUT of the test circuit at time two based on the preset driving signal, and turning off the second DUT of the test circuit at time four based on the preset driving signal.

[0055] The technical problem this embodiment aims to solve is how to drive the test circuit. In the process of testing the switching losses of power semiconductor devices, it is necessary to clarify how to turn the devices in the test circuit on and off according to a specific time sequence to ensure the accuracy of the test.

[0056] The technical solution of this embodiment drives the test circuit by turning on the first device under test (DUT) at time zero based on a preset drive signal, and turning off the first DUT at time two; turning on the second DUT at time two, and turning off the second DUT at time four. These specific time points control the turn-on and turn-off sequence of the two DUTs, enabling the test circuit to operate according to a predetermined working mode.

[0057] The technical solution of this embodiment, with its precise driving method, ensures that the operating state of the test circuit meets expectations, simulating the switching process of power semiconductor devices under actual operating conditions. By turning the device on and off at specific times, the current and voltage in the circuit can change according to the designed waveform, thereby providing an accurate working environment for subsequent electrical parameter acquisition and turn-off loss calculation.

[0058] Example 6

[0059] Based on the above embodiments, the step of calculating the turn-off loss of the device under test (DUT) based on electrical parameters includes: calculating the input power of the test circuit based on the current and voltage of the DC power supply in the test circuit; calculating the line loss of the test circuit and the conduction loss of the DUT based on the line current in the test circuit, the current of the DUT, and the equivalent series resistance of the test circuit; and subtracting the input power from the line loss of the test circuit and the conduction loss of the DUT to obtain the turn-off loss of the DUT.

[0060] The technical problem this embodiment aims to solve is how to obtain the turn-off loss of the device under test (DUT). After driving the test circuit and acquiring the electrical parameters, an effective calculation method is needed to obtain the accurate turn-off loss of the DUT.

[0061] The technical solution of this embodiment calculates the input power of the test circuit based on the current and voltage of the DC power supply in the test circuit. Based on the current in the lines of the test circuit, the current of the device under test (DUT), and the equivalent series resistance of the test circuit, it calculates the line loss of the test circuit and the conduction loss of the DUT. Then, it subtracts the line loss and conduction loss from the input power to obtain the turn-off loss of the DUT. This embodiment considers various power loss factors in the circuit and accurately calculates the turn-off loss using the law of conservation of energy.

[0062] The calculation method of this embodiment can accurately obtain the turn-off loss of the device under test. By considering factors such as input power, line loss, and conduction loss, it avoids errors that may be caused by simple calculations. In practical applications, this accurate turn-off loss calculation result is crucial for the performance evaluation and application of power semiconductor devices. For example, in the design of power electronic converters, accurate turn-off loss can help engineers better perform thermal design and avoid over- or under-design caused by inaccurate turn-off loss assessment. This helps improve the efficiency and reliability of the converter and extend the lifespan of power semiconductor devices. Moreover, this calculation method has high accuracy and strong versatility, and is applicable to different types of power semiconductor devices and different test circuit structures, providing reliable technical support for the testing and application of power semiconductor devices.

[0063] Example 7

[0064] Figure 3 This is a schematic diagram of the structure of a power semiconductor testing device provided in an embodiment of this application, as shown below. Figure 3 As shown, in the technical solution of this embodiment, a power semiconductor testing device based on the power semiconductor testing circuit of any of the above embodiments is provided. The device includes: an acquisition module for acquiring the equivalent series resistance of the test circuit; a driving module for driving the test circuit based on a preset driving signal to make the test circuit work in a preset mode; a data acquisition module for acquiring the electrical parameters of the test circuit in the preset mode; and a calculation module for calculating the turn-off loss of the device under test based on the electrical parameters.

[0065] The technical problem this embodiment aims to solve is how to construct a test circuit for measuring the switching losses of power semiconductor devices. In the field of power semiconductor device switching loss testing, a suitable test circuit is needed to perform subsequent testing work, which is the basis for accurately measuring switching losses.

[0066] The technical solution of this embodiment constructs the main body of the test circuit by setting up a DC power supply and a device under test (DUT). The DUT is divided into a first DUT and a second DUT. The first terminal of the first DUT is connected to the positive terminal of the DC power supply, and its second terminal is connected to the first terminal of the second DUT. The second terminal of the second DUT is connected to the negative terminal of the DC power supply. This connection method provides the basic architecture for the subsequent construction of the complete test circuit and the testing of switching losses of power semiconductor devices, and is the core part of the entire test circuit.

[0067] The technical solution of this embodiment first clarifies the basic architecture of the main test circuit, providing a foundational framework for subsequent additions of other components to complete the test circuit. For example, in a complete test circuit, subsequently added components such as input capacitors, inductors, and output capacitors can all be connected based on this main architecture. This main architecture enables accurate measurement of the switching losses of power semiconductor devices. Without this basic circuit structure, a complete test environment cannot be established. Moreover, this simple main architecture is easily applicable to different types of power semiconductor devices, including metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), all of which can be tested based on this architecture. This facilitates the unified construction of a basic architecture across various power semiconductor device testing scenarios, improving testing efficiency and providing a stable foundation for subsequent more complex test circuit designs and test method applications.

[0068] Example 8

[0069] In this embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of any of the power semiconductor testing methods described in the above embodiments. In this embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements the steps of any of the power semiconductor testing methods described in the above embodiments. In this embodiment, a computer program product is provided, including a computer program. When executed by a processor, the computer program implements the steps of any of the power semiconductor testing methods described in the above embodiments.

[0070] The processor may include, but is not limited to, one or more processors or microprocessors. Each processor may be implemented as an Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), controller, microcontroller, microprocessor, or other electronic component, for performing the methods in the above embodiments. The computer-readable storage medium may be implemented by any type of volatile or non-volatile storage device or a combination thereof, and may include, but is not limited to, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (e.g., hard disk, floppy disk, solid-state drive, removable disk, CD-ROM, DVD-ROM, Blu-ray disc, etc.).

[0071] Computer-readable storage media may also store at least one computer-executable program / instruction, such as computer-readable instructions. Computer-readable storage media include, but are not limited to, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Computer-readable storage media may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, a non-transitory computer-readable storage medium may be connected to a computing device such as a computer, and then, when the computing device executes the computer-readable instructions stored on the computer-readable storage medium, the various methods described above can be performed.

[0072] In addition, the computer device may also include (but is not limited to) a data bus, an input / output (I / O) bus, a display, and input / output devices (e.g., a keyboard, mouse, speakers, etc.). The processor can communicate with external devices via the I / O bus through a wired or wireless network. In one embodiment, the at least one computer-executable instruction may also be compiled into or comprise a software product / computer program product, wherein one or more computer-executable instructions, when executed by the processor, perform the steps of the various functions and / or methods in the embodiments described herein.

[0073] Example 9

[0074] Based on the above embodiments, this embodiment provides an application example.

[0075] This application example relates to power conversion technology, specifically a power semiconductor device. Power semiconductor devices, as the foundation of power electronics technology, are used in power electronic converters to convert and control electrical energy by controlling the switching on and off of these devices. With the development of power electronics technology and the widespread application of third-generation wide-bandgap semiconductor devices, the operating frequency of power semiconductor devices is increasing, leading to higher switching losses and more severe heat generation. Accurately assessing the switching losses of power semiconductor devices has become a key challenge and a hot topic in current power electronic converter design.

[0076] Currently, the datasheets for power semiconductor devices such as MOSFETs and IGBTs all provide the device's turn-on energy E. on and shut-off energy E off These values ​​are obtained based on specific switching voltage / current, drive resistance (on / off), and drive voltage (on / off) tests. However, in practical applications, due to differences in application scenarios and specific design requirements, it is difficult to keep the device's switching voltage / current, drive resistance, and drive voltage consistent with the datasheet. Continuing to use the E values ​​from the datasheet would be inappropriate. on and E off Calculations of switching losses can lead to significant deviations in the calculated results, potentially causing device burnout. This invention proposes a method and circuit for testing the turn-off loss of power semiconductor devices. The switching voltage / current, drive resistance, and drive voltage of the semiconductor device in the test circuit are configured according to specific design requirements to ensure that the tested switching conditions are completely consistent with the actual switching conditions. This allows for accurate measurement of the turn-off energy E generated during the device's turn-off process. off Perform precise measurements.

[0077] The actual turn-off voltage / current, drive resistance, and drive voltage of semiconductor devices used in applications differ from those in the device datasheet, resulting in discrepancies between the actual turn-off energy E stated in the datasheet and the actual turn-off voltage / current. off The results of loss calculations vary greatly. This application example proposes a method and circuit for testing turn-off losses, which completely simulates the actual switching conditions of the device. It can accurately measure the device's E under actual operating conditions. off This improves the accuracy of device turn-off energy calculation.

[0078] The test circuit of this invention adopts a half-bridge structure, with a Buck circuit topology and an open-circuit output. The drive signals of Q1 and Q2 are complementary (ignoring the dead-time effect), and both have a percentage and open-circuit ratio of 0.5. Therefore, the output voltage V can be obtained. o =V in / 2. Circuit diagram see Figure 1The descriptions of each component are shown in Table 1.

[0079] Table 1 Device Description

[0080]

[0081] The operating waveform of the test circuit is shown below. Figure 4 The descriptions and settings of each physical quantity are as follows:

[0082] ——V gs The preset drive signals for the devices under test (DUTs) Q1 / Q2 are provided, and their drive voltage amplitude and drive resistance are consistent with the parameters of the specific design. The drive signals for Q1 and Q2 are complementary (ignoring the dead time effect) and account for 50% of the empty space D.

[0083] ——V ds When the drain-sink voltage of Q1 / Q2 is 1, the switching transistor is turned on, V ds Approximately equal to 0; when the switching transistor is turned off, V ds =V in Among them, V in This is the DC input power supply voltage. By adjusting the input power supply voltage, it can be ensured that it is consistent with the operating voltage of the specific design.

[0084] ——i Q1 and i Q2 These are the collector currents of Q1 and Q2, respectively.

[0085] ——i L This represents the inductor current.

[0086] ——T s To test the switching cycle of the circuit, f s To test the switching frequency of the circuit, f s =1 / T s In specific settings, minimize the impact of high-frequency skin effect and proximity effect of ESR (equivalent series resistance) in the circuit.

[0087] —I m The maximum inductor current, which is also the turn-off current of the semiconductor device, is determined by changing the switching period T. s And the filter inductance L, ensuring that this value is consistent with the turn-off current of the specific design.

[0088] Depend on Figure 4It can be seen that when the first device under test (DUT) Q1 and the second device under test (DUT) Q2 are turned on (the first DUT Q1 is turned on at time t0 and time t5, and the second DUT Q2 is turned on at time t2), the device current is freewheeled by the body diode, thus achieving zero-voltage turn-on, meaning that the turn-on loss of both is zero. The turn-off of both the first DUT Q1 and the second DUT Q2 is hard turn-off (the first DUT Q1 is turned off at time t2, and the second DUT Q2 is turned off at time t4), and the turn-off current is always within the maximum inductor current I. m That is, the turn-off losses of the two are equal and not zero; the conduction time of the first device under test Q1 and the second device under test Q2 are equal, and the current passing through them is equal to half of the inductor current, that is, the conduction losses of the two are equal.

[0089] To accurately assess the switching losses of switching devices, the equivalent series resistance (ESR) of the circuit connection parameters and the equivalent ESR of the devices themselves are evaluated. (Circuit diagram shown) Figure 5 The resistors are described below:

[0090] ——R DS The on-resistance of the first device under test (DUT) Q1 and the second device under test (DUT) Q2 were obtained from the technical specifications provided by the supplier.

[0091] ——R Cin The ESR of the input capacitor can be obtained by testing with testing equipment or by consulting the technical specifications provided by the supplier.

[0092] ——R Co The ESR of the output capacitor can be obtained by testing with testing equipment or by consulting the technical specifications provided by the supplier.

[0093] ——R L The ESR of the filter inductor L can be obtained by testing with testing equipment or by consulting the technical specifications provided by the supplier.

[0094] ——R pcb1 ESR of the cable connecting the input capacitor to the first device under test Q1 / the second device under test Q2. The connection can be a printed circuit board (PCB), a composite busbar, or a cable, and can be obtained by testing equipment.

[0095] ——R pcb2 ESR of the connection cable between the output capacitor and the first device under test Q1 / second device under test Q2. The connection can be PCB, composite busbar and cable, and can be obtained by testing equipment.

[0096] Combination Figure 4 control waveform and Figure 5The circuit model is used to analyze the operating modes of the circuit. Based on the circuit's operating characteristics, a single cycle (t1~t5) can be divided into four operating modes, from the first mode to the fourth mode, as follows: Figure 6 , Figure 7 , Figure 8 , Figure 9 As shown, where t0 = 0, t1 = T s / 4, t2=T s / 2, t3=3T s / 4, t4 = T s t5 = 5T s / 4.

[0097] First mode (t1~t2): First device under test Q1 is turned on, second device under test Q2 is turned off, and the voltage applied across the inductor is V. in -V o =V in / 2, the inductor current increases linearly, and reaches its maximum value at time t2. See the current loop diagram. Figure 6 .

[0098] Second mode (t2~t3): At time t2, the first device under test (DUT) Q1 is turned off, and the turn-off current of the first DUT Q1 is I. m There is a turn-off loss P off The current is commutated from the body diode of the first device under test (DUT) Q1 to the body diode of the second DUT Q2. At this time, the second DUT Q2 is turned on, and the second DUT Q2 is turned on at zero voltage. The turn-on loss P on It is zero. At this time, the voltage applied across the inductor is -V. o =-V in / 2, the inductor current is from I m The inductor current decreases linearly, reaching zero at time t3. The current loop is shown below. Figure 7 .

[0099] Third mode (t3~t4): The first device under test (DUT) Q1 is off, the second DUT Q2 is on, and the inductor is at -V in At a voltage of / 2, after the inductor current crosses zero, it continues to decrease. At time t4, the inductor current reaches its maximum value in the reverse direction. The current loop is shown below. Figure 8 .

[0100] Fourth mode (t4~t5): At time t4, the second device under test (DUT) Q2 is turned off, and the turn-off current of the second DUT Q2 at this time is I. m There is a turn-off loss, and it is related to the turn-off loss P of the first device under test Q1 in the second mode. offCompletely identical; the current is commutated from the second device under test (DUT) Q2 to the body diode of the first DUT Q1, at which point the first DUT Q1 is turned on, and the first DUT Q1 is turned on at zero voltage, with zero turn-on loss. At this time, the voltage applied across the inductor is V. in -V o =V in / 2, the inductor current is from -I m As the linear line increases, the inductor current reaches zero at time t5. The current loop is shown below. Figure 9 .

[0101] Measurement and design of device current.

[0102] The current values ​​of each device can be obtained through measurement instruments or calculated. Based on the above analysis, combined with the waveform, and according to D=0.5, the current of each device is calculated as follows:

[0103] —The effective current values ​​of the switching transistors / first device under test Q1 and second device under test Q2 are equal, calculated as follows:

[0104]

[0105] —Filter inductor L and output capacitor C o The effective values ​​of the currents are equal, and the calculation is as follows:

[0106]

[0107] —Input capacitor C in The effective value of the current is calculated as follows:

[0108]

[0109] I in This is the output current of the power supply, which can be read directly from the power supply device or measured directly by a current testing device.

[0110] Measurement and calculation of device losses.

[0111] The losses of each component can be obtained through testing with measuring instruments or calculated. Based on the above analysis, combined with the waveform, and according to D=0.5, the losses of each component are calculated as follows:

[0112] —Input capacitor losses:

[0113] P Cin =i Cin_RMS 2 *R Cin (Equation 4)

[0114] — Output capacitor losses:

[0115] PCo =i Co_RMS 2 *R Co (Equation 5)

[0116] —The filter inductor is an air-core inductor with zero core loss; the only loss is winding loss, which can be obtained through magnetic simulation software or by calculation.

[0117] P L =i L_RMS 2 *R L (Equation 6)

[0118] Connection losses mainly originate from the connecting cables (PCB, composite busbars, or cables), primarily in the form of R... pcb1 and R pcb2 The resulting losses are calculated as follows:

[0119] P pcb =i Q_RMS 2 *R pcb1 +i L_RMS 2 *R pcb2 (Equation 7)

[0120] —The losses generated by semiconductor devices consist of conduction losses P con and P off It consists of two parts, and the P of the two devices con and P off Same. P off It is difficult to calculate accurately the loss we are looking for. The loss P generated by a single device... Q The calculation is as follows:

[0121] P Q =P con +P off (Equation 8)

[0122] P con =i Q_RMS 2 *R DS (Equation 9)

[0123] —Power P generated by the power source in It can be read directly from the power supply, or it can be calculated as follows:

[0124] P in =V in *I in (Equation 10)

[0125] According to the law of conservation of energy, the losses generated by all components and connecting cables in the circuit are supplied by the power source, therefore:

[0126] P in =P Cin +P Co +P L +P pcb +2P Q (Equation 11)

[0127] Substituting equation 8 into equation 11, we get:

[0128] P in =P Cin +P Co +P L +P pcb +2(P con +P off (Equation 12)

[0129] Then P off We can obtain:

[0130]

[0131] The formula for calculating the turn-off loss of semiconductor devices is:

[0132] P off =E off *f s (Equation 14)

[0133] By combining Equations 13 and 14, the turn-off energy of the semiconductor device can be finally obtained:

[0134]

[0135] Equation 15 represents the semiconductor device turn-off energy E off The final calculation formula is based on the turn-off energy of the specific device application. The test conditions, such as the driving voltage amplitude, driving resistance, and voltage and current at turn-on and turn-off times, can be kept consistent with actual operating conditions, thus ensuring the accuracy of the calculation. In subsequent applications, there is no need to consult the device's datasheet; the E value obtained using this method can be used directly. off By multiplying by the actual switching frequency, the turn-off loss of the device can be accurately calculated, thereby avoiding over- and under-design in subsequent thermal design.

[0136] The basic testing methods and principles remain the same when the semiconductor device is replaced with an IGBT. The main changes are as follows:

[0137] 1) Changes in test circuit: The test circuit based on IGBT is as follows: Figure 10 As shown, the first device under test Q1 and the second device under test Q2 are IGBTs, and VD1 and VD2 are freewheeling diodes.

[0138] 2) The operating waveform has changed: IGBT passes through Figure 4 The forward current of the first device under test (DUT) Q1 / the second device under test (DUT) Q2 is measured by the diode through... Figure 4 The reverse current of the first device under test (DUT) Q1 / the second device under test (DUT) Q2 is modified as follows: Figure 11 As shown.

[0139] 3) In working mode Figure 7 and Figure 9 The circuit path has changed: MOSFETs have bidirectional conductivity, so the current can still continue to pass through the MOSFET after the direction of reversal; IGBTs have unidirectional conductivity, and the current freewheels through their anti-parallel diodes after the direction of reversal.

[0140] 4) The current calculation has changed: the IGBT and anti-parallel diode circuit together constitute the original MOSFET current.

[0141] —The effective value of the IGBT current is calculated using Equation 16, with the instantaneous value set as i. Q (t), can be found in the reference. Figure 11 The calculations will not be elaborated here.

[0142]

[0143] —The effective value of the diode current is calculated using Equation 17, with the instantaneous value set as i. VD (t), can be found in the reference. Figure 11 The calculations will not be elaborated here.

[0144]

[0145] 5) The calculation of losses in semiconductor switching devices has changed: the original single MOSFET loss has been changed to IGBT loss and diode loss.

[0146] —The losses generated by the IGBT are due to the conduction loss P con and P off It consists of two parts, and the P of the two devices con and P off Same. P off It is difficult to calculate accurately the loss we are looking for. The loss P generated by a single IGBT is... Q The calculation is as follows, and P con The instantaneous value of the conduction current i can be used to determine the conduction current. Q (t) and its corresponding on-state voltage drop V ce The product is shown in Equation 19, where the time interval from t1 to t2 is T. s / 4.

[0147] P Q =P con +Poff (Equation 18)

[0148]

[0149] —Diode losses: Reverse recovery loss is zero; only conduction loss exists. P VD The instantaneous value of the conduction current i can be used to determine the conduction current. VD (t) and its corresponding on-state voltage drop V F The product is obtained, where the time from t0 to t1 is T. s / 4.

[0150]

[0151] Finally, the IGBT's turn-off energy was calculated:

[0152]

[0153] This method can accurately test the turn-off energy E of semiconductor devices in specific applications. off This enables accurate calculation of the turn-off loss of semiconductor devices, avoiding over- or under-design of thermal due to inaccurate loss assessment.

[0154] In the embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0155] It should be noted that, in this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element limited by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0156] While the embodiments disclosed in this invention are as described above, the above content is merely for the purpose of facilitating understanding of this invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this invention; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A test method for power semiconductors based on a test circuit for power semiconductors, characterized in that, The circuit includes: a DC power supply and a device under test (DUT), wherein the DUT includes a first DUT and a second DUT; The first terminal of the first device under test is connected to the positive terminal of the DC power supply, and the second terminal of the first device under test is connected to the first terminal of the second device under test. The second terminal of the second device under test is connected to the negative terminal of the DC power supply; The circuit also includes: an input capacitor, an inductor, and an output capacitor; The input capacitor is connected in parallel across the DC power supply. The first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor. The second terminal of the output capacitor is connected to the negative terminal of the DC power supply; The method includes: Obtain the equivalent series resistance of the test circuit; The test circuit is driven by a preset driving signal, so that the test circuit works in a preset mode. Collect the electrical parameters of the test circuit under the preset mode; The turn-off loss of the device under test is calculated based on the electrical parameters. The step of calculating the turn-off loss of the device under test based on the electrical parameters includes: The input power of the test circuit is calculated based on the current and voltage of the DC power supply in the test circuit. Based on the current in the lines of the test circuit, the current of the device under test, and the equivalent series resistance of the test circuit, calculate the line loss of the test circuit and the conduction loss of the device under test. The input power is subtracted from the line loss of the test circuit and the conduction loss of the device under test to obtain the turn-off loss of the device under test.

2. The testing method for power semiconductors according to claim 1, characterized in that, The step of driving the test circuit based on a preset driving signal includes: The first device under test (DUT) turns on the test circuit at time zero based on a preset drive signal, and turns off the test circuit at time two based on the preset drive signal. The second device under test (DUT) is turned on at the second moment based on a preset drive signal, and the second DUT is turned off at the fourth moment based on the preset drive signal.

3. The testing method for power semiconductors according to claim 1, characterized in that, The device under test includes a metal-oxide-semiconductor field-effect transistor and an insulated-gate bipolar transistor.

4. A power semiconductor testing device based on a power semiconductor testing circuit, characterized in that, The circuit includes: a DC power supply and a device under test (DUT), wherein the DUT includes a first DUT and a second DUT; The first terminal of the first device under test is connected to the positive terminal of the DC power supply, and the second terminal of the first device under test is connected to the first terminal of the second device under test. The second terminal of the second device under test is connected to the negative terminal of the DC power supply; The circuit also includes: an input capacitor, an inductor, and an output capacitor; The input capacitor is connected in parallel across the DC power supply. The first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor. The second terminal of the output capacitor is connected to the negative terminal of the DC power supply; The device includes: An acquisition module is used to acquire the equivalent series resistance of the test circuit; The driving module is used to drive the test circuit based on a preset driving signal, so that the test circuit works in a preset mode; The acquisition module is used to acquire the electrical parameters of the test circuit under a preset mode; The calculation module is used to calculate the turn-off loss of the device under test based on the electrical parameters. The calculation of the turn-off loss of the device under test based on the electrical parameters includes: The input power of the test circuit is calculated based on the current and voltage of the DC power supply in the test circuit. Based on the current in the lines of the test circuit, the current of the device under test, and the equivalent series resistance of the test circuit, calculate the line loss of the test circuit and the conduction loss of the device under test. The input power is subtracted from the line loss of the test circuit and the conduction loss of the device under test to obtain the turn-off loss of the device under test.

5. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the test method for the power semiconductor according to any one of claims 1 to 3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the test method for the power semiconductor according to any one of claims 1 to 3.

7. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the test method for the power semiconductor according to any one of claims 1 to 3.

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