Doppler radar echo signal processing method based on FPGA

Abstract

This invention discloses a Doppler radar echo signal processing method based on FPGA, mainly addressing the problems of poor real-time performance, long lock-out time, and low reliability in existing Doppler radar speed measurement. The implementation scheme is as follows: When the radar locks on, the sampled signal undergoes Hilbert transform and mixing to complete digital down-conversion processing; then, it is filtered, decimated, and truncated to form a Doppler frequency shift signal and the Doppler frequency shift difference signal between adjacent speed measurement cycles, which are output to the DSP. The DSP performs automatic gain control and tracking threshold judgment based on its input signal. When the radar loses lock, an FFT transform is added to the sampled signal, and the output sampled signal frequency is transmitted to the DSP to determine the accurate frequency sweep range, reducing the radar lock-out time. This invention improves the real-time performance of digital signal processing, reduces the Doppler radar lock-out time, and meets the requirements of new platforms for high real-time performance, short lock-out time, and high reliability of Doppler radar data, and can be used for Doppler radar speed measurement.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing, and specifically relates to a Doppler radar echo signal processing method that can be used for Doppler radar speed measurement. Background Technology

[0002] With the rapid development of Doppler radar platforms, the requirements for the real-time performance of Doppler radar data are becoming increasingly stringent, and the requirements for reliability are also becoming increasingly strict. Traditional Doppler radar digital signal processing technology based on DSP (Digital Signal Processor) can no longer adapt to the rapid development of the platform.

[0003] Due to limitations in the development of domestic integrated circuit technology, traditional Doppler radar digital signal processing is mostly based on DSP platforms. The high signal sampling rate results in a large amount of data to be processed in real time by DSPs, long processing time, large output delay, and poor real-time performance. However, with the rapid development of domestic integrated circuit technology, digital signal processing technology based on programmable logic arrays (FPGAs) has shown its characteristics of good real-time performance and high speed.

[0004] Existing Doppler radar platforms are faster and more mobile, and face increasingly complex electromagnetic environments. This requires Doppler radar to have a wider speed measurement range, stronger ability to filter clutter signals, and faster ability to track signals after loss. Traditional DSP-based digital signal processing methods for Doppler radar are no longer sufficient for these applications.

[0005] Patent document CN110058221A discloses a low-speed speed measurement method for Doppler radar. It improves the tracking capability of low-speed speed measurement signals by adopting hardware modifications such as absorbing waves, increasing antenna isolation, and improving the intermediate frequency filtering curve of analog signals. However, it is prone to losing lock when the external environment changes, such as at the boundary between land and water or when there is external interference. Moreover, when the lock is lost, the DSP rescanning time is too long, which reduces the time for outputting effective data and makes it impossible for the radar to track quickly and effectively after the radar loses lock.

[0006] Therefore, under the new circumstances, there is an urgent need for a Doppler radar digital signal processing method with good real-time performance, high reliability, and strong anti-interference capability. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of the prior art by proposing an FPGA-based Doppler echo signal processing method to enhance the real-time performance of radar echo signal processing, improve the radar's ability to suppress interference signals, reduce radar lock-off time, and enhance the reliability of output data.

[0008] The technical approach of this invention is as follows: Based on FPGA integrated circuit technology, the sampled Doppler radar echo signal is processed using the real-time performance and fast response characteristics of FPGA digital signal processing, thereby enhancing the real-time performance of radar digital signal processing. According to the mobility characteristics of different mounting platforms, filtering of the Doppler frequency shift difference signal between adjacent velocity measurement cycles removes interference signals entering from complex electromagnetic environments, enhancing the anti-interference capability of the Doppler radar and improving the reliability of output data. After radar lock-up, FPGA-based FFT processing is added to quickly calculate a coarse Doppler frequency shift signal, narrowing the DSP's frequency sweep range when the Doppler signal is lost, and reducing the radar lock-up time.

[0009] Based on the above ideas, the technical solution of the present invention includes the following:

[0010] Technical Solution 1:

[0011] A method for processing echo signals during Doppler radar lock-on based on FPGA, characterized in that it includes:

[0012] S1) During a speed measurement cycle, when the radar locks on, the intermediate frequency sampling signal of this speed measurement cycle is subjected to Hilbert transform, and two orthogonal intermediate frequency signals containing Doppler frequency shift are output. Then, the two orthogonal intermediate frequency signals containing Doppler frequency shift are subjected to low-pass filtering, and the two orthogonal Doppler frequency shift signals are retained. After decimation and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP.

[0013] S2) The DSP calculates the signal energy based on the amplitude of the Doppler frequency shift signal and performs automatic gain control of the radar intermediate frequency signal;

[0014] S3) During this speed measurement cycle, the frequency control word calibrated from the DSP in the previous speed measurement cycle is received. The frequency control word controls the DDS signal generator inside the FPGA to generate two orthogonal intermediate frequency (IF) signals containing the Doppler frequency shift signal from the previous speed measurement cycle. These two orthogonal IF signals containing the Doppler frequency shift signal from the previous speed measurement cycle are then mixed with the IF sampling signal of this speed measurement cycle to form two orthogonal IF signals containing the Doppler frequency shift difference signal from two adjacent speed measurement cycles. These two signals are then subjected to low-pass filtering, data extraction, and data truncation to form two orthogonal Doppler frequency shift difference signals from adjacent speed measurement cycles, which are then transmitted to the DSP.

[0015] S4) During this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word for the next speed measurement cycle.

[0016] S5) During this speed measurement cycle, based on the characteristics of the Doppler frequency shift change between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals. The signals after secondary low-pass filtering are extracted and truncated, the amplitude of the main spectrum signal in the band is calculated, and transmitted to the DSP.

[0017] S6) During this speed measurement cycle, the DSP uses the amplitude of the in-band main spectrum signal to calculate the energy of the main spectrum signal and performs radar signal tracking threshold determination to ensure stable tracking.

[0018] S7) Repeat steps S1)-S6) above for each velocity measurement cycle when the radar locks on, to complete the processing of the echo signal when the Doppler radar locks on. Steps S1), S3) and S5) are all completed on the FPGA platform.

[0019] Technical Solution 2:

[0020] A method for processing echo signals when Doppler radar loses lock, based on FPGA, characterized by comprising:

[0021] (1) When the radar loses lock during a speed measurement cycle, the intermediate frequency sampling signal in this speed measurement cycle is subjected to FFT operation, and the calculation result is transmitted to the DSP to determine the upper and lower limits of the frequency sweep, narrow the frequency sweep range, reduce the frequency sweep time, and enhance the rapid tracking capability after the radar loses lock.

[0022] (2) During this speed measurement cycle, the intermediate frequency sampling signal of the radar during this speed measurement cycle is subjected to Hilbert transformation, and two orthogonal intermediate frequency signals containing Doppler frequency shift are output. Then, the two orthogonal intermediate frequency signals containing Doppler frequency shift are subjected to low-pass filtering, and the two orthogonal Doppler frequency shift signals are retained. After decimation and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP.

[0023] (3) During this speed measurement cycle, the DSP calculates the signal energy based on the amplitude of the Doppler frequency shift signal and performs automatic gain control of the radar intermediate frequency signal;

[0024] (4) During this speed measurement cycle, the frequency control word calibrated from the previous speed measurement cycle is received from the DSP. The frequency control word controls the DDS signal generator inside the FPGA to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle. Then, the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are mixed with the intermediate frequency sampling signal of this speed measurement cycle to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signal of two adjacent speed measurement cycles. Then, the two signals are low-pass filtered, data extracted and data trunculated to form two orthogonal Doppler frequency shift difference signals of adjacent speed measurement cycles and transmitted to the DSP.

[0025] (5) During this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word for the next speed measurement cycle.

[0026] (6) During this speed measurement cycle, based on the characteristics of the Doppler frequency shift change between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals. The signals after secondary low-pass filtering are extracted and truncated, the amplitude of the main spectrum signal in the band is calculated, and transmitted to the DSP.

[0027] (7) During this speed measurement cycle, the DSP uses the amplitude of the in-band main spectrum signal to calculate the energy of the main spectrum signal and performs radar signal tracking threshold determination to ensure stable tracking.

[0028] (8) Repeat steps (1)-(7) above for each velocity measurement cycle when the radar loses lock to complete the processing of the echo signal when the Doppler radar loses lock. Steps (1), (2), (4) and (6) are all completed on the FPGA platform.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] Firstly, since the present invention completes the down-conversion, low-pass filtering and signal amplitude calculation of the intermediate frequency sampling signal on the FPGA platform, it can meet the requirements of the new platform for strong real-time digital signal processing.

[0031] Secondly, this invention enhances the radar's adaptability to the motion characteristics of new mounting platforms and complex electromagnetic environments by filtering the Doppler frequency shift difference signal between adjacent velocity measurement cycles after digital down-conversion.

[0032] Thirdly, when encountering radar lock-off, this invention introduces an FPGA-based FFT processing method, which utilizes the advantages of FPGA parallel processing to calculate the approximate signal frequency range, reduce the frequency sweep range of the DSP, decrease the radar lock-off time, and enhance the reliability of the radar. Attached Figure Description

[0033] Figure 1 This is a flowchart illustrating the implementation of Embodiment 1 of the present invention;

[0034] Figure 2 This is a flowchart illustrating the implementation of Embodiment 2 of the present invention;

[0035] Figure 3 This is the amplitude-frequency response curve of the first low-pass filter fir_1 in this embodiment of the invention;

[0036] Figure 4 This is the amplitude-frequency response curve of the second low-pass filter fir_2 in this embodiment of the invention;

[0037] Figure 5 This is the amplitude-frequency response curve of the third low-pass filter fir_3 in this embodiment of the invention. Detailed Implementation

[0038] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to the described embodiments.

[0039] The radar measures speed in cycles, with each cycle lasting the same amount of time.

[0040] During normal operation, the radar receives echo signals, amplifies them at intermediate frequency, performs AD sampling, and then performs digital signal processing on the intermediate frequency sampled signals. The processing results are then output to the DSP for calculation, and the speed information is output. At this point, the radar locks onto the target.

[0041] When the echo information received by the radar is weak, or the Doppler frequency shift difference between adjacent velocity measurement cycles is too large and does not conform to the actual movement characteristics of the platform, the amplitude output after digital signal processing will not meet the locking requirements, resulting in the radar losing lock.

[0042] This invention provides different embodiments of the echo signal processing methods for the two scenarios of radar lock-on and radar loss of lock-on.

[0043] Example 1: Doppler radar echo signal processing method during normal radar tracking and locking.

[0044] Reference Figure 1 The implementation steps of this example include the following:

[0045] Step 1: Perform Hilbert transform on the sampled signal, calculate the amplitude of the Doppler frequency shift signal, and output it to the DSP.

[0046] The sampling signal is an intermediate frequency analog signal that has been converted into an intermediate frequency sampling signal through AD sampling, and its form is as follows:

[0047] s(n)=Asin[2π(f0+f d )Δ t [n+ω0],

[0048] Where A is the amplitude of the intermediate frequency sampling signal, f0 is the carrier frequency, and f d The frequency of the Doppler frequency shift signal is... ω is the sampling time, ω0 is the initial phase, and n is the number of sampling points, which is a non-negative integer.

[0049] This step includes:

[0050] 1.1) Within one speed measurement cycle, perform a Hilbert transform on the intermediate frequency sampling signal s(n) to obtain two orthogonal intermediate frequency signals sn.I (n) and s Q (n):

[0051] s I (n)=Asin[2π(f0+f d )Δ t n+ω0]cos(2πf0Δ t n)

[0052] s Q (n)=Asin[2π(f0+f d )Δ t n+ω0]sin(2πf0Δ t n)

[0053] Among them, s I (n) represents the I-channel intermediate frequency signal, s Q (n) represents the intermediate frequency signal of the Q channel;

[0054] Then, according to the product-to-sum formula, the two orthogonal intermediate frequency signals above are transformed into the following form:

[0055]

[0056] 1.2) Filter coefficients are generated using MATLAB and combined with the filter IP core built into the FPGA to form the first low-pass filter fir_1. Its amplitude-frequency response is shown in [reference needed]. Figure 3 ,from Figure 3 It can be seen that the passband cutoff frequency of this low-pass filter is 8kHz;

[0057] 1.3) The two orthogonal intermediate frequency signals are low-pass filtered using a low-pass filter fir_1 to form two filtered orthogonal Doppler frequency shift signals s. If (n) and s Qf (n):

[0058]

[0059] Among them, s If (n) represents the I-channel Doppler frequency shift signal, s Qf (n) represents the Q-channel Doppler frequency shift signal;

[0060] 1.4) The two filtered quadrature Doppler frequency shift signals are decimated by a factor of 8 to form the two decimated quadrature Doppler frequency shift signals as follows:

[0061]

[0062] 1.5) According to s Id (n) and s Qd (n) Calculate the signal amplitude A from the two extracted quadrature Doppler frequency shift signals:

[0063]

[0064] 1.6) Steps 1.1)-1.5) are completed on the FPGA platform, and then the signal amplitude A is output to the DSP. The signal energy is calculated on the DSP platform to perform automatic gain control of the radar intermediate frequency signal.

[0065] Step 2: The quadrature Doppler frequency shift difference signal is subjected to a low-pass filter, and two quadrature Doppler frequency shift difference signals are output to the DSP.

[0066] 2.1) The DDS signal generator generates two orthogonal intermediate frequency signals p, each containing the Doppler frequency shift signal from the previous speed measurement cycle, based on the frequency control word sent by the DSP. I (n) and p Q (n):

[0067] p I (n)=cos[2π(f0+f d )Δ t n]

[0068] p Q (n)=sin[2π(f0+f d )Δ t n].

[0069] Where, p I (n) represents the intermediate frequency signal of channel I, p Q (n) represents the Q-channel intermediate frequency signal, f0 is the carrier frequency, and f d The frequency of the Doppler frequency shift signal from the previous velocity measurement cycle. is the sampling time, and n is the number of sampling points, whose value is a non-negative integer;

[0070] 2.2) Let the difference in Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle be Δ. f The intermediate frequency sampling signal for this speed measurement cycle is transformed into: p(n)=Asin[2π(f0+f d +Δ f )Δ t [n+ω1];

[0071] 2.3) Mix the two orthogonal intermediate frequency (IF) signals containing the Doppler frequency shift signal from the previous speed measurement cycle with the IF sampling signal p(n) of the current speed measurement cycle, and then convert them into two orthogonal IF signals p(n) containing the Doppler frequency shift difference signal from adjacent speed measurement cycles using the product-sum-difference formula. I1 (n) and p Q1 (n):

[0072]

[0073] Where, p I1 (n) represents the I-channel Doppler frequency shift difference signal, p Q1 (n) is the Q-channel Doppler frequency shift difference signal, A is the signal amplitude, and ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement cycle;

[0074] 2.4) Filter coefficients are generated using MATLAB and combined with the filter IP core built into the FPGA to form a second low-pass filter, fir_2. Its amplitude-frequency response is shown in [reference needed]. Figure 4 ,from Figure 4 It can be seen that the passband cutoff frequency of this low-pass filter is 15kHz;

[0075] 2.5) Use low-pass filter fir_2 to perform low-pass filtering on the two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signal, forming two filtered orthogonal Doppler frequency shift difference signals p. If1 (n) and p Qf1 (n):

[0076]

[0077] Where, p If1 (n) represents the I-channel Doppler frequency shift difference signal after the first filtering, p Qf1 (n) is the Q-channel Doppler frequency shift difference signal after the first filtering;

[0078] 2.6) The two filtered quadrature Doppler frequency shift difference signals are decimated and truncated by a factor of 8 to form the difference signal p between the two decimated quadrature Doppler frequency shift difference signals. Id1 (n) and p Qd1 (n):

[0079]

[0080] Where, p Id1 (n) represents the I-channel Doppler frequency shift difference signal after the first extraction, p Qd1 (n) is the Q-channel Doppler frequency shift difference signal after the first extraction;

[0081] 2.7) The two decimated and truncated quadrature Doppler frequency shift difference signals are output to the DSP and the subsequent low-pass filter fir_3 for secondary low-pass filtering, respectively;

[0082] 2.8) Steps 2.1)-2.7) are completed on the FPGA platform. Then, the two extracted and truncated quadrature Doppler frequency shift difference signals are output to the DSP. Frequency and phase discrimination are performed on the DSP platform to calculate the frequency of the Doppler frequency shift difference signal, which is used to calibrate the frequency control word for the next speed measurement cycle.

[0083] Step 3, for p Id1 (n) and p Qd1 (n) Perform a second low-pass filter to reduce the filter bandwidth, filter out possible interference, and output the Doppler frequency shift difference signal amplitude to the DSP.

[0084] 3.1) Filter coefficients were generated using MATLAB and imported into the FPGA's built-in IP core FIR filter to form a third low-pass filter, fir_3. Its amplitude-frequency response is shown in [reference needed]. Figure 5 ,from Figure 5 It can be seen that the passband cutoff frequency of this low-pass filter is 500Hz;

[0085] 3.2) For p Id1 (n) and p Qd1 (n) Whether there is interference between the two signals, perform secondary low-pass filtering on each of the two cases to form two quadrature Doppler frequency shift difference signals p after secondary low-pass filtering. If2 (n) and p Qf2 (n):

[0086] If there is no interference signal, then for p Id1 (n) and p Qd1 (n) After the two signals undergo secondary low-pass filtering, the change in their main spectrum amplitude is negligible, resulting in the two quadrature Doppler frequency shift difference signals p after secondary low-pass filtering. If2 (n) and p Qf2 (n):

[0087]

[0088] Where, p If2 (n) represents the I-channel Doppler frequency shift difference signal after the second filtering, p Qf2 (n) represents the Q-channel Doppler frequency shift difference signal after the second filtering, where A is the signal amplitude and Δ is the signal value. f This represents the difference in Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle. Where n is the sampling time, n is the number of sampling points, and ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement cycle;

[0089] If interference signals are present, the interference signals will be added to transform the two orthogonal signals p after primary filtering, decimation, and truncation. Id1 (n) and p Qd1 (n) is transformed into the following orthogonal signal p with interference. Idn1 (n) and p Qdn1 (n):

[0090]

[0091] Where, p Idn1(n) represents the I-channel Doppler frequency shift difference signal after the interference signal is added, p Qdn1 (n) represents the Q-channel Doppler frequency shift difference signal after the interference signal is added, f noise For the frequency of the interference signal;

[0092] Then, the two orthogonal signals p after the interference signal is added... Idn1 (n) and p Qdn1 (n) After the second low-pass filtering, the filtering frequency is f noise The interference signal is converted into two quadrature Doppler frequency shift difference signals p after secondary filtering. If2 (n) and p Qf2 (n):

[0093]

[0094] Where, p If2 (n) represents the I-channel Doppler frequency shift difference signal after the second filtering, p Qf2 (n) is the Q-channel Doppler frequency shift difference signal after the second filtering;

[0095] 3.3) For p If2 (n) and p Qf2 (n) Two orthogonal signal data are decimated and truncated by a factor of 8 to form two orthogonal signals p after secondary decimation and truncation. Id2 (n) and p Qd2 (n):

[0096]

[0097] Where, p Id2 (n) represents the difference in Doppler frequency shift between the second decimation and truncation of the I-channel signal, p Qd2 (n) is the Q-channel Doppler frequency shift difference signal after the second extraction and truncation;

[0098] 3.4) Calculate the amplitude A of the two quadrature signals after secondary filtering:

[0099]

[0100] 3.5) Steps 3.1)-3.4) are completed on the FPGA platform. The result A is output to the DSP. The main spectrum signal energy is calculated on the DSP platform, and the radar signal tracking threshold is determined to ensure stable tracking.

[0101] Step 4: Repeat steps 1-3 for each radar lock-on speed measurement cycle to complete the processing of the echo signal when the Doppler radar locks on.

[0102] Example 2: Doppler radar echo signal processing method when radar lock is lost.

[0103] Reference Figure 2 The implementation steps of this example include the following:

[0104] Step 1: Calculate the intermediate frequency sampling signal frequency when the radar loses lock.

[0105] The sampling signal is an intermediate frequency analog signal that has been converted into an intermediate frequency sampling signal through AD sampling, and its form is as follows:

[0106] s(n)=Asin[2π(f0+f d )Δ t [n+ω0],

[0107] Where A is the amplitude of the intermediate frequency sampling signal, f0 is the carrier frequency, and f d The frequency of the Doppler frequency shift signal is... ω is the sampling time, ω0 is the initial phase, and n is the number of sampling points, which is a non-negative integer.

[0108] Within a speed measurement cycle, when the radar loses lock, the frequency calculation of the intermediate frequency (IF) sampled signal for that cycle is initiated by the DSP sending an "out-of-lock" signal to activate the FFT transformation. The FPGA then performs the FFT operation using its built-in IP core based on the received IF sampled signal data, calculating the IF sampled signal frequency f0+f. d Where f0 is the carrier frequency, f d The frequency of the Doppler shift signal;

[0109] The calculated results are then transmitted to the DSP to determine the upper and lower limits of the frequency sweep, narrow the frequency sweep range, reduce the radar lock-out time, and enhance the rapid tracking capability after the radar lock-out.

[0110] Step 2: During this speed measurement cycle, perform Hilbert transform on the intermediate frequency sampling signal of the radar during this speed measurement cycle to output two orthogonal intermediate frequency signals containing Doppler frequency shift. Then, perform low-pass filtering on the two orthogonal intermediate frequency signals containing Doppler frequency shift, retain the two orthogonal Doppler frequency shift signals, perform decimation and truncation, calculate the amplitude of the Doppler frequency shift signal, and transmit it to the DSP.

[0111] The relevant implementation formula for this step is the same as step 1 in Example 1.

[0112] Step 3: During this speed measurement cycle, the frequency control word calibrated from the previous speed measurement cycle is received from the DSP. This frequency control word controls the DDS signal generator inside the FPGA to generate two orthogonal intermediate frequency (IF) signals containing the Doppler frequency shift signal from the previous speed measurement cycle. These two IF signals are then mixed with the IF sampling signal of the current speed measurement cycle to form two orthogonal IF signals containing the Doppler frequency shift difference signal from two adjacent speed measurement cycles. These two signals are then subjected to low-pass filtering, data decimation, and data truncation to form two orthogonal Doppler frequency shift difference signals from two adjacent speed measurement cycles, which are transmitted to the DSP. The DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word for the next speed measurement cycle.

[0113] The relevant implementation formula for this step is the same as step 2 in Example 1.

[0114] Step four: During this speed measurement cycle, based on the characteristics of the Doppler frequency shift change between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals. The signals after secondary low-pass filtering are decimated and truncated, and the amplitude of the in-band main spectrum signal is calculated and transmitted to the DSP. The DSP uses the amplitude of the in-band main spectrum signal to calculate the main spectrum signal energy and performs radar signal tracking threshold determination to ensure stable tracking.

[0115] The relevant implementation formula for this step is the same as step 3 in Example 1.

[0116] Step 5: Repeat steps 1 to 4 above for each speed measurement cycle when the radar loses lock, to complete the processing of the echo signal when the Doppler radar locks.

[0117] The above descriptions are merely two specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. For example, the number of FFT transform points may be increased or decreased according to the required range of frequency sweeping, the Doppler frequency shift difference filtering characteristics may be adjusted for interference signals, and the decimation factor may be changed to meet the data processing needs of the back-end DSP. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

[0118] It should be noted that the step numbers in the specification and claims of this invention are only for the purpose of clearly describing the embodiments of this invention and facilitating understanding, and their order is not limited.

Claims

1. A method for processing echo signals during Doppler radar lock-on based on FPGA, characterized in that, include: S1) During a speed measurement cycle, when the radar locks on, the intermediate frequency sampling signal of this speed measurement cycle is subjected to Hilbert transform, and two orthogonal intermediate frequency signals containing Doppler frequency shift are output. Then, the two orthogonal intermediate frequency signals containing Doppler frequency shift are subjected to low-pass filtering, and the two orthogonal Doppler frequency shift signals are retained. After decimation and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP. S2) The DSP calculates the signal energy based on the amplitude of the Doppler frequency shift signal and performs automatic gain control of the radar intermediate frequency signal; S3) During this speed measurement cycle, the frequency control word calibrated from the DSP in the previous speed measurement cycle is received. The frequency control word controls the DDS signal generator inside the FPGA to generate two orthogonal intermediate frequency (IF) signals containing the Doppler frequency shift signal from the previous speed measurement cycle. These two orthogonal IF signals containing the Doppler frequency shift signal from the previous speed measurement cycle are then mixed with the IF sampling signal of this speed measurement cycle to form two orthogonal IF signals containing the Doppler frequency shift difference signal from two adjacent speed measurement cycles. These two signals are then subjected to low-pass filtering, data extraction, and data truncation to form two orthogonal Doppler frequency shift difference signals from adjacent speed measurement cycles, which are then transmitted to the DSP. S4) During this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word for the next speed measurement cycle. S5) During this speed measurement cycle, based on the characteristics of the Doppler frequency shift change between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals. The signals after secondary low-pass filtering are extracted and truncated, the amplitude of the main spectrum signal in the band is calculated, and transmitted to the DSP. S6) During this speed measurement cycle, the DSP uses the amplitude of the in-band main spectrum signal to calculate the energy of the main spectrum signal and performs radar signal tracking threshold determination to ensure stable tracking. S7) Repeat steps S1)-S6) above for each velocity measurement cycle when the radar locks on, to complete the processing of the echo signal when the Doppler radar locks on. Steps S1), S3) and S5) are all completed on the FPGA platform.

2. The method according to claim 1, characterized in that, The process of performing a Hilbert transform on the intermediate frequency sampled signal within one speed measurement cycle includes the following: 2a) Let the intermediate frequency sampling signal be s(n)=Asin[2π(f0+f d )Δ t Perform a Hilbert transform on [n+ω0] to obtain two orthogonal intermediate frequency signals s. I (n) and s Q (n): s I (n)=Asin[2π(f0+f d )D t n+ω0]cos(2πf0Δ t n) s Q (n)=Asin[2π(f0+f d )D t n+ω0]sin(2πf0Δ t n) Among them, s I (n) represents the I-channel intermediate frequency signal, s Q (n) represents the Q-channel intermediate frequency signal, A represents the amplitude of the intermediate frequency sampling signal, f0 represents the carrier frequency, and f d The frequency of the Doppler frequency shift signal is... Where n is the sampling time, n is the number of sampling points, and ω0 is the initial phase; 2b) According to the product-to-sum formula, the two orthogonal intermediate frequency signals above are transformed into the following form:

3. The method according to claim 1, characterized in that, The step of low-pass filtering, decimation, and truncation of the two orthogonal intermediate frequency signals within the current speed measurement cycle, followed by calculating the signal amplitude, includes the following: 3a) Use MATLAB software to generate filter coefficients, and combine them with the filter IP core built into the FPGA to form the first low-pass filter fir_1; 3b) The two orthogonal intermediate frequency signals are low-pass filtered using the first low-pass filter fir_1 to form two filtered orthogonal Doppler frequency shift signals s. If (n) and s Qf (n): Among them, s If (n) represents the I-channel Doppler frequency shift signal, s Qf (n) represents the Q-channel Doppler frequency shift signal, A is the amplitude of the intermediate frequency sampled signal, and f d The frequency of the Doppler frequency shift signal is... Where n is the sampling time, n is the number of sampling points, and ω0 is the initial phase; 3c) Decrease and truncate the two filtered quadrature Doppler frequency shift signals by a factor of 8 to form two decrelated and truncate quadrature Doppler frequency shift signals s. Id (n) and s Qd (n): Among them, s Id (n) represents the decimated and truncated I-channel Doppler frequency shift signal, s Qd (n) represents the Q-channel Doppler frequency shift signal after extraction and truncation; 3d) According to s Id (n) and s Qd (n) Calculate the signal amplitude A from the two extracted and truncated quadrature Doppler frequency-shifted signals:

4. The method according to claim 1, characterized in that, During the current speed measurement cycle, the DDS generates two orthogonal intermediate frequency (IF) signals containing the Doppler frequency shift of the previous speed measurement cycle, which are then mixed, low-pass filtered, decimated, and truncated with the IF sampling signal of the current speed measurement cycle, including the following: 4a) The DDS generates two orthogonal intermediate frequency signals p, each containing the Doppler frequency shift signal from the previous speed measurement cycle, based on the frequency control word sent by the DSP. I (n) and p Q (n): p I (n)=cos[2π(f0+f d )D t [n] p Q (n)=sin[2π(f0+f d )D t [n] Where, p I (n) represents the intermediate frequency signal of channel I, p Q (n) represents the Q-channel intermediate frequency signal, f0 is the carrier frequency, and f d The frequency of the Doppler frequency shift signal from the previous velocity measurement cycle. Where n is the sampling time and n is the number of sampling points; 4b) Assume the difference in Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle is Δ f Then the intermediate frequency sampling signal for this speed measurement cycle becomes p(n)=Asin[2π(f0+f d +Δ f )Δ t [n+ω1]; Mix the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal from the previous speed measurement cycle with the intermediate frequency sampling signal p(n) of the current speed measurement cycle, and then convert them into two orthogonal intermediate frequency signals p containing the Doppler frequency shift difference signal from adjacent speed measurement cycles using the product-difference formula. I1 (n) and p Q1 (n): Where, p I1 (n) represents the I-channel Doppler frequency shift difference signal, p Q1 (n) is the Q-channel Doppler frequency shift difference signal, A is the signal amplitude, and ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement cycle; 4c) Use MATLAB software to generate filter coefficients, and combine them with the filter IP core built into the FPGA to form a second low-pass filter fir_2; 4d) The two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signal are low-pass filtered using the second low-pass filter fir_2 to form two filtered orthogonal Doppler frequency shift difference signals p. If1 (n) and p Qf1 (n): Where, p If1 (n) represents the I-channel Doppler frequency shift difference signal after the first filtering, p Qf1 (n) is the Q-channel Doppler frequency shift difference signal after the first filtering; 4e) The two filtered quadrature Doppler frequency shift difference signals are decimated and truncated by a factor of 8 to form two decimated and truncated quadrature Doppler frequency shift difference signals p. Id1 (n) and p Qd1 (n): Where, p Id1 (n) represents the I-channel Doppler frequency shift difference signal after the first extraction, p Qd1 (n) is the Q-channel Doppler frequency shift difference signal after the first extraction.

5. The method according to claim 1, characterized in that, During this speed measurement cycle, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering, signal extraction and truncation, and the in-band main spectrum signal amplitude is calculated, including the following: 5a) Use MATLAB software to generate filter coefficients, import them into the FPGA's built-in IP core FIR filter to form the third low-pass filter fir_3; 5b) Use the third low-pass filter fir_3 to perform low-pass filtering on the two orthogonal Doppler frequency shift difference signals to form two filtered orthogonal Doppler frequency shift difference signals; If there is no interference signal, then for p Id1 (n) and p Qd1 (n) After the two signals undergo secondary filtering, the change in their main spectrum amplitude is negligible, resulting in the two quadrature Doppler frequency shift difference signals p after secondary filtering. If2 (n) and p Qf2 (n): Where, p If2 (n) represents the I-channel Doppler frequency shift difference signal after the second filtering, p Qf2 (n) represents the Q-channel Doppler frequency shift difference signal after the second filtering, where A is the signal amplitude and Δ is the signal value. f This represents the difference in Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle. Where n is the sampling time, n is the number of sampling points, and ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement cycle; If interference signals are present, the interference signals will be added to transform the two orthogonal signals p after primary filtering, decimation, and truncation. Id1 (n) and p Qd1 (n) is transformed into the following orthogonal signal p with interference. Idn1 (n) and p Qdn1 (n): Where, p Idn1 (n) represents the I-channel Doppler frequency shift difference signal after the interference signal is added, p Qdn1 (n) represents the Q-channel Doppler frequency shift difference signal after the interference signal is added, f noise For the frequency of the interference signal; After a second low-pass filter is applied to the two orthogonal signals after the interference signal is added, the filtering frequency is f. noise The interference signal is converted into two quadrature Doppler frequency shift difference signals p after secondary filtering. If2 (n) and p Qf2 (n): Where, p If2 (n) represents the I-channel Doppler frequency shift difference signal after the second filtering, p Qf2 (n) is the Q-channel Doppler frequency shift difference signal after the second filtering; 5c) for p If2 (n) and p Qf2 (n) Two orthogonal signal data are decimated and truncated by a factor of 8 to form two orthogonal signals p after secondary decimation and truncation. Id2 (n) and p Qd2 (n): Where, p Id2 (n) represents the difference in Doppler frequency shift between the second decimation and truncation of the I-channel signal, p Qd2 (n) is the Q-channel Doppler frequency shift difference signal after the second extraction and truncation; 5d) Calculate the amplitude A of the two quadrature signals after secondary filtering:

6. A method for processing echo signals when Doppler radar loses lock based on FPGA, characterized in that, include: (1) When the radar loses lock during a speed measurement cycle, the intermediate frequency sampling signal in this speed measurement cycle is subjected to FFT operation, and the calculation result is transmitted to the DSP to determine the upper and lower limits of the frequency sweep, narrow the frequency sweep range, reduce the frequency sweep time, and enhance the rapid tracking capability after the radar loses lock. (2) During this speed measurement cycle, the intermediate frequency sampling signal of the radar during this speed measurement cycle is subjected to Hilbert transformation, and two orthogonal intermediate frequency signals containing Doppler frequency shift are output. Then, the two orthogonal intermediate frequency signals containing Doppler frequency shift are subjected to low-pass filtering, and the two orthogonal Doppler frequency shift signals are retained. After decimation and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP. (3) During this speed measurement cycle, the DSP calculates the signal energy based on the amplitude of the Doppler frequency shift signal and performs automatic gain control of the radar intermediate frequency signal; (4) During this speed measurement cycle, the frequency control word calibrated from the previous speed measurement cycle is received from the DSP. The frequency control word controls the DDS signal generator inside the FPGA to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle. Then, the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are mixed with the intermediate frequency sampling signal of this speed measurement cycle to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signal of two adjacent speed measurement cycles. Then, the two signals are low-pass filtered, data extracted and data trunculated to form two orthogonal Doppler frequency shift difference signals of adjacent speed measurement cycles and transmitted to the DSP. (5) During this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word for the next speed measurement cycle. (6) During this speed measurement cycle, based on the characteristics of the Doppler frequency shift change between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals. The signals after secondary low-pass filtering are extracted and truncated, the amplitude of the main spectrum signal in the band is calculated, and transmitted to the DSP. (7) During this speed measurement cycle, the DSP uses the amplitude of the in-band main spectrum signal to calculate the energy of the main spectrum signal and performs radar signal tracking threshold determination to ensure stable tracking. (8) Repeat steps (1)-(7) above for each velocity measurement cycle when the radar loses lock to complete the processing of the echo signal when the Doppler radar loses lock. Steps (1), (2), (4) and (6) are all completed on the FPGA platform.

7. The method according to claim 6, characterized in that, Within one velocity measurement cycle, the intermediate frequency sampled signal when the radar loses lock is subjected to FFT operation, including the following: 7a) When the Doppler signal is lost, the DSP sends an "unlocked" signal to activate the FFT transform; 7b) The FPGA receives the intermediate frequency (IF) sampling signal data and uses its built-in IP core to perform FFT operations based on the received IF sampling signal data to calculate the IF sampling signal frequency f0+f d Where f0 is the carrier frequency, f d The frequency of the Doppler shift signal is denoted as .

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