Monolithic integrated photoelectric fusion interconnection chip and preparation method thereof

Abstract

The invention provides a monolithic integrated photoelectric fusion interconnection chip and a preparation method thereof, relates to the technical field of photoelectric integration, and can solve the problems of low integration level, low bandwidth and low energy efficiency of an interconnection chip prepared in the prior art. The method comprises: a substrate; the dielectric layer is arranged on one side of the substrate; the protective layer is arranged on one side, far away from the substrate, of the dielectric layer; wherein at least one functional module is arranged in the protective layer, at least part of the functional module comprises a plurality of silicon core layers and at least one first metal layer, the silicon core layer represents at least one light path device and / or at least one circuit device, and the first metal layer represents a signal transmission contact. Any two adjacent layers in the multiple silicon core layers and the at least one first metal layer are electrically connected through a second metal layer. An optical device and an electric device are prepared in an overlapped mode through the multiple silicon core layers, the chip area is greatly reduced, and the integration level, the bandwidth and the energy efficiency of the chip are improved.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic integration technology, and in particular to a monolithic integrated optoelectronic fusion interconnection chip and a preparation method thereof. Background Art

[0002] With the rapid development of new-generation information technologies such as artificial intelligence, machine learning, and high-performance computing, the demand for interconnected bandwidth and energy efficiency for data movement is increasing exponentially.

[0003] However, the existing packaging and integration technology based on discrete optoelectronic chips not only limits the chip scale, but also causes significant deterioration in key performance, resulting in low integration, bandwidth and energy efficiency of the prepared interconnected chips. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention provides a monolithically integrated optoelectronic fusion interconnection chip and a method for manufacturing the same.

[0005] One aspect of the present invention provides a monolithic integrated optoelectronic fusion interconnection chip, comprising: a substrate; a dielectric layer, arranged on one side of the substrate; a protective layer, arranged on a side of the dielectric layer away from the substrate; wherein at least one functional module is arranged in the protective layer, at least part of the functional modules include multiple silicon core layers and at least one first metal layer, the silicon core layer is characterized as at least one optical path device and / or at least one circuit device, the first metal layer is characterized as a contact for signal transmission, and any two adjacent layers in the multiple silicon core layers and the at least one first metal layer are electrically connected through a second metal layer.

[0006] According to an embodiment of the present invention, the projections of any two layers of multi-layer silicon core layers electrically connected by the same second metal layer on the substrate at least partially overlap.

[0007] According to an embodiment of the present invention, the optical path device includes: a passive optical waveguide device, an electro-optic modulator and a photodetector; and the circuit device is implemented based on a driving circuit and a transimpedance amplifier circuit.

[0008] According to an embodiment of the present invention, the passive optical waveguide device includes: an optical waveguide, a grating coupler, an end coupler, a directional coupler, a multimode interferometer, a mode spot converter, a polarization beam rotation combiner, a polarization beam rotation splitter, a phase shifter and a microring resonator.

[0009] According to an embodiment of the present invention, the circuit device is implemented based on a MOS tube.

[0010] According to an embodiment of the present invention, the circuit device also includes: at least one of a communication circuit and a control circuit; wherein the communication circuit is used to control the working state of at least one of the driving circuit and the transimpedance amplifier circuit, and the control circuit is used to control the on and off of the driving circuit and the transimpedance amplifier circuit.

[0011] According to an embodiment of the present invention, a single silicon core layer also represents at least one of a corresponding electro-optic modulator array, a photodetector array, a driver circuit array and a transimpedance amplifier circuit array, each of which is composed of at least one of a plurality of electro-optic modulators, a plurality of photodetectors, a plurality of driving circuits and a plurality of transimpedance amplifier circuits.

[0012] According to an embodiment of the present invention, the number of channels of the array corresponding to two adjacent silicon core layers electrically connected by the same second metal layer is consistent.

[0013] According to an embodiment of the present invention, two adjacent silicon core layers electrically connected by the same second metal layer are both optical path devices, and the projections of the two optical path devices on the substrate at least partially overlap to achieve transmission of optical signals.

[0014] Another aspect of the present invention provides a method for preparing a monolithic integrated optoelectronic fusion interconnection chip, comprising: forming a dielectric layer on one side of a substrate; forming a protective layer on a side of the dielectric layer away from the substrate; using at least one of waveguide etching, doping and metal epitaxial technology to form at least one functional module in the protective layer, at least part of the functional modules include multiple silicon core layers and at least one first metal layer, the silicon core layer is characterized by at least one optical path device and / or at least one circuit device, the first metal layer is characterized by a contact for signal transmission, and any two adjacent layers of the multiple silicon core layers and the at least one first metal layer are electrically connected through the second metal layer; wherein the first metal layer and the second metal layer are obtained based on a through-hole process and metal deposition.

[0015] The present invention adopts a multi-layer silicon core layer to overlap the optical path device and the circuit device, which can greatly reduce the chip area and improve the chip integration, bandwidth and energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram shows a structure of a monolithic integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention;

[0018] Figure 2 A schematic diagram showing the structure of various functional modules of a monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the front view of the array structure of the monolithic integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention is shown;

[0020] Figure 4A schematic diagram showing a top view of an array of a monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention;

[0021] Figure 5 The flowchart of the method for preparing the monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention is schematically shown.

[0022] [Description of Reference Numerals]

[0023] 1-substrate; 2-dielectric layer; 3-protective layer; 4-functional module; 41-silicon core layer; 411-first silicon core layer; 412-second silicon core layer; 42-first metal layer; 43-second metal layer. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0025] It should be noted that in the drawings or descriptions, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form new solutions without conflict, and in the drawings, the shape or thickness of the embodiments can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are in a form known to ordinary technicians in the relevant technical field. In addition, although demonstrations of parameters containing specific values ​​may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0026] Unless there are technical obstacles or contradictions, the above-mentioned various embodiments of the present invention can be freely combined to form other embodiments, and these other embodiments are all within the protection scope of the present invention.

[0027] Although the present invention is described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to exemplify the preferred embodiments of the present invention and should not be construed as limiting the present invention. The size ratios in the drawings are merely illustrative and should not be construed as limiting the present invention.

[0028] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general disclosed concept.

[0029] The present invention can be prepared, for example, based on a CMOS-compatible SOI platform process. The CMOS-compatible SOI platform process has a low cost, and can realize the preparation of a low-cost, high-integration, and large-scale scalable monolithic integrated optoelectronic fusion interconnection chip. In addition, the present invention realizes the monolithic integration of optical chips and electrical chips, and further extends it to heterogeneous heterogeneous process platforms, which can truly realize the fusion integration of monolithic all-optoelectronic devices including light sources, and has a commercial application foundation and prospects while achieving high integration.

[0030] Figure 1 The structure of a monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention is schematically shown. Figure 2 The structure diagram of various functional modules of the monolithic integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention is schematically shown.

[0031] According to an embodiment of the present invention, Figure 1 As shown, the present invention provides a monolithic integrated optoelectronic fusion interconnection chip, comprising: a substrate 1. A dielectric layer 2, which is arranged on one side of the substrate 1. A protective layer 3, which is arranged on the side of the dielectric layer 2 away from the substrate 1. Among them, at least one functional module 4 is arranged in the protective layer 3, and at least part of the functional modules 4 includes a multi-layer silicon core layer 41 and at least one first metal layer 42, the silicon core layer 41 is characterized as at least one optical path device and / or at least one circuit device, the first metal layer 42 is characterized as a contact for signal transmission, and any two adjacent layers in the multi-layer silicon core layer 41 and the at least one first metal layer 42 are electrically connected through the second metal layer 43.

[0032] In some embodiments, the substrate 1 may be, for example, a silicon substrate. The dielectric layer 2 may be, for example, a silicon dioxide buried oxide layer grown on a silicon substrate using SOI technology, which is used to reduce parasitic capacitance and improve device performance. The protective layer 3 may be, for example, a silicon dioxide cladding layer. The functional module 4 may be, for example, a device structure composed of a silicon core layer 41, a first metal layer 42, and a second metal layer 43 according to actual needs. The circuit device and / or optical path device represented by the silicon core layer 41 may be, for example, any type and any number of related devices. The materials of the first metal layer 42 and the second metal layer 43 may be, for example, copper and aluminum.

[0033] It is understandable that the present invention can combine the structures in the functional module 4 in different ways according to different practical needs.

[0034] In some embodiments, Figure 2As shown, the silicon core layer 41 may be, for example, a first silicon core layer 411 and a second silicon core layer 412 distributed on two different horizontal planes. With the difference of the circuit devices and / or optical devices implemented in the first silicon core layer 411 and the second silicon core layer 412, the monolithic integrated optoelectronic fusion interconnection chip of the present invention may have a variety of different structures and functions.

[0035] For example, Figure 2 As shown in the module A in FIG. 1 , the present invention may include, from bottom to top: a substrate 1, a dielectric layer 2, a first silicon core layer 411, a second metal layer 43, a second silicon core layer 412, a second metal layer 43, a first metal layer 42, and a protective layer 3. The first silicon core layer 411 may be, for example, a circuit device, and the second silicon core layer 412 may be, for example, an electro-optic modulator. The electro-optic modulator and the circuit device transmit electrical signals through the second metal layer 43, and the electro-optic modulator transmits electrical signals to the outside through the second metal layer 43 and the first metal layer 42.

[0036] For example, Figure 2 As shown in the B module in the figure, the present invention may further include from bottom to top: substrate 1, dielectric layer 2, first silicon core layer 411, second metal layer 43, second silicon core layer 412, second metal layer 43, first metal layer 42 and protective layer 3. The first silicon core layer 411 may be, for example, an electro-optic modulator, the second silicon core layer 412 may be, for example, a circuit device, the circuit device and the electro-optic modulator transmit electrical signals through the second metal layer 43, and the circuit device transmits electrical signals to the outside through multiple layers of the second metal layer 43 and multiple layers of the first metal layer 42.

[0037] For example, Figure 2 As shown in the C module in the figure, the present invention may further include from bottom to top: substrate 1, dielectric layer 2, first silicon core layer 411, second metal layer 43, first metal layer 42, second metal layer 43, first metal layer 42 and protective layer 3. The first silicon core layer 411 may be, for example, a circuit device, and the circuit device transmits electrical signals to the outside through multiple layers of second metal layers 43 and multiple layers of first metal layers 42.

[0038] For example, Figure 2 As shown in the D module in the figure, the present invention may further include from bottom to top: substrate 1, dielectric layer 2, first silicon core layer 411, second metal layer 43, first metal layer 42, second metal layer 43, first metal layer 42 and protective layer 3. The first silicon core layer 411 may be, for example, an electro-optic modulator, which transmits electrical signals to the outside through multiple layers of second metal layers 43 and multiple layers of first metal layers 42.

[0039] For example, Figure 2As shown in the E module in FIG. 1 , the present invention may further include from bottom to top: a substrate 1, a dielectric layer 2, a first silicon core layer 411, a second metal layer 43, a first metal layer 42, a second metal layer 43, a first metal layer 42 and a protective layer 3. The first silicon core layer 411 may be, for example, a photodetector, which transmits electrical signals to the outside through multiple layers of the second metal layer 43 and multiple layers of the first metal layer 42.

[0040] For example, Figure 2 As shown in the F module in the figure, the present invention may further include from bottom to top: a substrate 1, a dielectric layer 2, a second silicon core layer 412, a second metal layer 43, a first metal layer 42 and a protective layer 3. The second silicon core layer 412 may be, for example, a circuit device, and the circuit device transmits electrical signals to the outside through the second metal layer 43 and the first metal layer 42.

[0041] For example, Figure 2 As shown in the G module in the figure, the present invention may further include from bottom to top: a substrate 1, a dielectric layer 2, a second silicon core layer 412, a second metal layer 43, a first metal layer 42 and a protective layer 3. The second silicon core layer 412 may be, for example, an electro-optic modulator, which transmits electrical signals to the outside through the second metal layer 43 and the first metal layer 42.

[0042] For example, Figure 2 As shown in the H module in FIG. 1 , the present invention may further include from bottom to top: a substrate 1, a dielectric layer 2, a second silicon core layer 412, a second metal layer 43, a first metal layer 42 and a protective layer 3. The second silicon core layer 412 may be, for example, a photodetector, which transmits electrical signals to the outside through the second metal layer 43 and the first metal layer 42.

[0043] By integrating optical devices and circuit devices in a single chip, the preparation of discrete optoelectronic chips is realized, which significantly reduces the packaging complexity, avoids the bonding structure introduced by different packaging methods, and significantly improves the interconnection bandwidth, integration and energy efficiency density of the chip. At the same time, by interconnecting optical devices and electrical devices at close distances, the signal transmission loss caused by the back-end process is avoided, parasitic parameters are reduced, and the system bandwidth is increased, which has the advantages of ultra-high-speed and efficient transmission.

[0044] According to an embodiment of the present invention, the projections of any two layers of multi-layer silicon core layers electrically connected by the same second metal layer on the substrate at least partially overlap.

[0045] In some embodiments, Figure 1 As shown, the two silicon core layers 41 are respectively prepared with optical circuit components and circuit components and are connected through the second metal layer 43. The optical circuit components and circuit components are completely or partially overlapped in a plane parallel to the substrate 1.

[0046] By overlapping the optical path devices and circuit devices with multiple silicon core layers, the integration can be further increased by more than double compared to a single silicon core layer, greatly improving the bandwidth density and energy efficiency density of the chip, greatly reducing the chip area and improving the integration, and breaking the inherent bottlenecks of interconnection bandwidth and energy efficiency. The cost and process difficulty are greatly reduced, and the parasitic parameters introduced by the package are eliminated, so that the preparation of a monolithic integrated optoelectronic fusion interconnection chip with low cost, low difficulty, high integration, high bandwidth and high energy efficiency can be achieved. According to an embodiment of the present invention, the optical path device includes: a passive optical waveguide device, an electro-optical modulator and a photodetector. The circuit device is implemented based on a driving circuit and a transimpedance amplifier circuit.

[0047] In some embodiments, the electro-optic modulator may be, for example, a Mach-Zehnder electro-optic modulator and a micro-ring modulator. The photodetector may be, for example, a silicon germanium detector. The driver circuit and the transimpedance amplifier circuit are circuits for equalizing, gaining, and amplifying electrical signals input from outside the chip.

[0048] It is understandable that the present invention can select different optical path components and circuit components according to actual needs.

[0049] By preparing different optical path devices and circuit devices on the silicon core layer, different functional requirements of the chip can be met.

[0050] According to an embodiment of the present invention, the passive optical waveguide device includes: an optical waveguide, a grating coupler, an end coupler, a directional coupler, a multimode interferometer, a mode spot converter, a polarization beam rotation combiner, a polarization beam rotation splitter, a phase shifter and a microring resonator.

[0051] Passive optical waveguide devices refer to optical waveguide components that can work normally without external energy drive.

[0052] In some embodiments, the optical path device can transmit optical signals to the outside through a grating coupler or an end face coupler, for example. It is understandable that the present invention can select corresponding passive optical waveguide devices according to actual needs.

[0053] By selecting different passive optical waveguide components, different functional requirements of the chip can be met.

[0054] According to an embodiment of the present invention, the circuit device is implemented based on a MOS tube.

[0055] In some embodiments, for example, MOS tubes may be used to implement the driving circuit and the transimpedance amplifier circuit.

[0056] The circuit device realized by the MOS tube has many advantages such as high speed, low power consumption, high reliability, easy integration and strong adaptability, and can significantly improve the performance of the chip of the present invention.

[0057] According to an embodiment of the present invention, the circuit device further comprises: at least one of a communication circuit and a control circuit, wherein the communication circuit is used to control the working state of at least one of the driving circuit and the transimpedance amplifier circuit, and the control circuit is used to control the on and off of the driving circuit and the transimpedance amplifier circuit.

[0058] The communication circuit in the present invention is a circuit for controlling the working state of at least one of the driving circuit and the transimpedance amplifier circuit. The control circuit is a circuit for controlling the on and off of the driving circuit and the transimpedance amplifier circuit.

[0059] In some embodiments, the communication circuit controls the working state of at least one of the driving circuit and the transimpedance amplifier circuit, for example, it may be the amplification factor of at least one of the controlling driving circuit and the transimpedance amplifier circuit, and for example, it may be the equalization and gain effect of at least one of the controlling driving circuit and the transimpedance amplifier circuit.

[0060] By arranging a communication circuit and a control circuit outside a driving circuit and a transimpedance amplifier circuit, the needs of various circuit devices can be met and the performance of the circuit devices can be improved.

[0061] Figure 3 The schematic diagram shows a front view of the array structure of a monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention. Figure 4 The schematic diagram shows a top view of the array structure of a monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention.

[0062] According to an embodiment of the present invention, a single silicon core layer also represents at least one of a corresponding electro-optic modulator array, a photodetector array, a driver circuit array and a transimpedance amplifier circuit array, each of which is composed of at least one of a plurality of electro-optic modulators, a plurality of photodetectors, a plurality of driving circuits and a plurality of transimpedance amplifier circuits.

[0063] In some embodiments, a monolithic integrated optoelectronic fusion interconnection chip applicable to optical communications is provided. Figure 3 and Figure 4 As shown, the silicon core layer 41 may be, for example, a first silicon core layer 411 and a second silicon core layer 412 distributed on two different horizontal planes.

[0064] The first silicon core layer 411 can be characterized as an electro-optic modulator array and a photodetector array composed of multiple electro-optic modulators and multiple photodetectors, respectively. The second silicon core layer 412 can be characterized as a driver array and a transimpedance amplifier array composed of multiple driver circuits and multiple transimpedance amplifiers, respectively.

[0065] The driver array corresponds to the electro-optic modulator array, forming a transmitter module, and the transresistor amplifier array corresponds to the photodetector array, forming a receiver module.

[0066] The working mode of the transmitting end module can be, for example: the external light source enters the silicon optical waveguide of the first silicon core layer 411 through the passive coupling structure, and is transmitted to the electro-optic modulator array of the first silicon core layer 411 through the silicon optical waveguide. The electrical signal enters the driver circuit array through the first metal layer 42 and the second metal layer 43, and after being processed by the driver circuit array, enters the corresponding electro-optic modulator array through the second metal layer 43. The electro-optic modulator array modulates the electrical signal on the optical signal, and outputs the modulated optical signal to the outside of the chip through the silicon optical waveguide and the passive coupling structure.

[0067] The working mode of the receiving end module includes: the external optical modulation signal enters the silicon optical waveguide of the first silicon core layer 411 through the passive coupling structure, and is transmitted to the photodetector array of the first silicon core layer 411 through the silicon optical waveguide. The electrical signal converted by the photodetector array enters the corresponding transimpedance amplifier circuit array through the second metal layer 43, and is output to the outside of the chip through the second metal layer 43 and the first metal layer 42 after being processed by the transimpedance amplifier circuit array.

[0068] The external light source may be, for example, a broad spectrum light source or a pulse light source. The passive coupling structure may be, for example, a grating coupler or an end face coupler. The electrical signal input into the driver circuit array may be, for example, a non-return-to-zero code signal, a four-level pulse amplitude modulation signal, or a signal in another format.

[0069] By combining a variety of optical path devices and circuit devices into corresponding arrays, the integration of the chip and its parallel processing capabilities can be significantly improved.

[0070] According to an embodiment of the present invention, the number of channels of the array corresponding to two adjacent silicon core layers electrically connected by the same second metal layer is consistent.

[0071] In the present invention, the number of channels refers to the number of independent paths for transmitting electrical signals or optical signals. For example, in a multi-channel electro-optical modulator array, each electro-optical modulator may correspond to an independent optical signal channel. It is understood that the number of array channels may be set according to actual conditions.

[0072] By keeping the number of channels in the silicon core layer consistent with the array, the chip layout is optimized. The same number of channels also facilitates synchronous control, ensuring that the devices in the array can work together and improving chip performance.

[0073] According to an embodiment of the present invention, two adjacent silicon core layers electrically connected by the same second metal layer are both optical path devices, and the projections of the two optical path devices on the substrate at least partially overlap to achieve transmission of optical signals.

[0074] In some embodiments, two adjacent silicon core layers 41 electrically connected by the same second metal layer 43 may be, for example, two different optical path devices, and the overlapping area formed by the projection of the passive optical waveguide parts in the above two different optical path devices on the substrate 1 is called a waveguide coupling area. The above two different passive waveguide devices may, for example, transmit optical signals through the waveguide coupling area. It is understandable that the silicon core layer 41 of the present invention may select any suitable signal transmission mode according to actual conditions, for example, electrical signal transmission may be performed through the second metal layer 43, optical signal transmission may be performed through the waveguide coupling area, or no signal transmission may be performed.

[0075] The optical devices are overlapped and prepared by multiple silicon core layers, which greatly improves the integration of the chip.

[0076] Figure 5 The flowchart of the method for preparing the monolithically integrated optoelectronic fusion interconnection chip according to an embodiment of the present invention is schematically shown.

[0077] Another aspect of the present invention provides a method for preparing a monolithic integrated optoelectronic fusion interconnection chip, such as Figure 5 As shown, for example, operations S510 to S530 are included.

[0078] In operation S510 , a dielectric layer is formed on one side of a substrate.

[0079] In operation S520 , a protection layer is formed on a side of the dielectric layer away from the substrate.

[0080] In operation S530, at least one functional module is formed in the protective layer by using at least one of waveguide etching, doping and metal epitaxy technology, at least part of the functional module includes a multi-layer silicon core layer and at least one first metal layer, the silicon core layer is characterized by at least one optical path device and / or at least one circuit device, the first metal layer is characterized by a contact for signal transmission, and any two adjacent layers in the multi-layer silicon core layer and the at least one first metal layer are electrically connected through the second metal layer. The first metal layer and the second metal layer are obtained based on a through-hole process and metal deposition.

[0081] In some embodiments, for example, a waveguide etching technique may be used to integrate silicon-based passive optical waveguide devices on the silicon core layer 41 .

[0082] For another example, a CMOS circuit may be integrated on the silicon core layer 41 by using waveguide etching and doping technology.

[0083] For another example, a silicon-based electro-optic modulator may be integrated on the silicon core layer 41 by using waveguide etching, doping, and metal epitaxy techniques.

[0084] For another example, waveguide etching, doping, and metal epitaxy techniques may be used to integrate germanium silicon photodetectors on the silicon core layer 41 .

[0085] For another example, metal deposition and through-hole process technology may be used to form metal electrodes inside the protective layer 3 and to form through-holes on the surface of the protective layer 3 .

[0086] The details not included in the product embodiment section are similar to those in the device embodiment section. Please refer to the device embodiment section and will not be repeated here.

[0087] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present invention. The attached method provides the elements of various steps in an exemplary order and is not intended to be limited to a specific order or hierarchy.

[0088] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present invention. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the present invention. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.

[0089] In the foregoing detailed description, various features are grouped together in a single embodiment to simplify the invention. This disclosure method should not be interpreted as reflecting such an intention.

[0090] In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification, the word is covered in a manner similar to the term "including", as explained by "including," used as a transitional word. The use of any term "or" in the specification is intended to mean "non-exclusive or".

[0091] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A monolithic integrated optoelectronic fusion interconnection chip, characterized in that: include: Substrate (1); A dielectric layer (2) is arranged on one side of the substrate (1); A protective layer (3) is arranged on a side of the dielectric layer (2) away from the substrate (1); At least one functional module (4) is arranged in the protective layer (3), at least part of the functional modules (4) includes multiple silicon core layers (41) and at least one first metal layer (42), the silicon core layer (41) is characterized as at least one optical path device and / or at least one circuit device, the first metal layer (42) is characterized as a contact point for signal transmission, and any two adjacent layers of the multiple silicon core layers (41) and the at least one first metal layer (42) are electrically connected via a second metal layer (43).

2. The monolithic integrated optoelectronic fusion interconnection chip according to claim 1, characterized in that: The projections of any two layers of the multi-layer silicon core layers (41) electrically connected by the same second metal layer (43) on the substrate (1) at least partially overlap.

3. The monolithic integrated optoelectronic fusion interconnection chip according to claim 1, characterized in that: The optical path device comprises: Passive optical waveguide devices, electro-optic modulators, and photodetectors; The circuit device is realized based on a driving circuit and a transimpedance amplifier circuit.

4. The monolithic integrated optoelectronic fusion interconnection chip according to claim 3, characterized in that: The passive optical waveguide device comprises: Optical waveguides, grating couplers, end couplers, directional couplers, multimode interferometers, spot mode converters, polarization beam rotation combiners, polarization beam rotation splitters, phase shifters and microring resonators.

5. The monolithic integrated optoelectronic fusion interconnection chip according to claim 3, characterized in that: The circuit device is implemented based on MOS tube.

6. The monolithic integrated optoelectronic fusion interconnection chip according to claim 3, characterized in that: The circuit device further comprises: at least one of a communication circuit and a control circuit; The communication circuit is used to control the working state of at least one of the driving circuit and the transimpedance amplifier circuit, and the control circuit is used to control the on and off of the driving circuit and the transimpedance amplifier circuit.

7. The monolithic integrated optoelectronic fusion interconnection chip according to claim 3, characterized in that: The single silicon core layer (41) also features a corresponding electro-optic modulator array, a photodetector array, a driver circuit array, and a transimpedance amplifier circuit array, each of which is composed of at least one of a plurality of the electro-optic modulators, a plurality of the photodetectors, a plurality of the drive circuits, and a plurality of the transimpedance amplifier circuits.

8. The monolithic integrated optoelectronic fusion interconnection chip according to claim 7, characterized in that: The number of channels in the array corresponding to two adjacent silicon core layers (41) electrically connected by the same second metal layer (43) is consistent.

9. The monolithic integrated optoelectronic fusion interconnection chip according to claim 3, characterized in that: Two adjacent silicon core layers (41) electrically connected by the same second metal layer (43) are both optical path devices, and the projections of the two optical path devices on the substrate (1) at least partially overlap to achieve transmission of optical signals.

10. A method for preparing a monolithic integrated optoelectronic fusion interconnection chip, characterized in that: include: forming a dielectric layer (2) on one side of the substrate (1); forming a protective layer (3) on a side of the dielectric layer (2) away from the substrate (1); At least one of waveguide etching, doping and metal epitaxy techniques is used to form at least one functional module (4) in the protective layer (3), at least part of the functional module (4) comprises a multi-layer silicon core layer (41) and at least one first metal layer (42), the silicon core layer (41) is characterized as at least one optical path device and / or at least one circuit device, the first metal layer (42) is characterized as a contact point for signal transmission, and any two adjacent layers of the multi-layer silicon core layer (41) and the at least one first metal layer (42) are electrically connected via a second metal layer (43); The first metal layer (42) and the second metal layer (43) are obtained based on a through-hole process and metal deposition.

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