Hardware acceleration method, device, equipment and medium

Abstract

The present invention relates to a hardware acceleration method, device, equipment and medium. The method comprises: obtaining a read-write command issued by a host; parsing the read-write command to obtain a parsing command; judging whether the parsing command is a read command; if it is a read command, judging whether the parsing command is a sequential read command; if it is a sequential read command, applying for a buffer from a read cache management engine, and constructing a pre-read command, carrying a buffer address and an LBA address; according to the pre-read command, caching data in a read cache buffer; submitting the parsing command to the read cache management engine for processing; judging whether the parsing command hits the cache data of the current read cache buffer; if it hits, directly returning the corresponding data from the read cache buffer to the host, and marking the command completion. The present invention improves the pertinence and efficiency of processing, shortens the response time of commands and the transmission delay of data, and improves the overall performance of the system.

Description

Technical Field

[0001] The present invention relates to the field of hardware acceleration technology, and in particular to hardware acceleration methods, devices, equipment and media. Background Art

[0002] Solid-state drives (SSDs) have rapidly become popular in the personal computer (PC) market due to their high-speed data read and write capabilities and high reliability, and have gradually replaced traditional mechanical hard disks (HDDs). SSDs use flash memory technology (such as NAND flash memory) to significantly increase data access speeds, providing users with a smoother experience. However, as the interface rate continues to increase, the performance ceiling of SSDs has also increased, but in the consumer market, cost constraints are a factor that cannot be ignored.

[0003] Consumer-grade SSDs are often limited by cost control and are often unable to be equipped with sufficient computing and memory resources for complex performance optimization. Therefore, under limited resource conditions, how to effectively improve the performance of SSDs has become an urgent problem to be solved. In typical user scenarios, sequential reading and repeated reading of data are the two most common situations.

[0004] 1. Sequential read scenario: In this scenario, users usually access a series of data blocks continuously. If the SSD can identify this data access mode in advance and preload the data blocks that the host is about to access in the disk, it can significantly reduce the command delay time and improve data transmission efficiency. However, existing SSDs often lack intelligent prediction and preloading mechanisms for this sequential read mode, resulting in a certain delay in the data access process.

[0005] 2. Repeated read scenario: When a user reads the same data block multiple times, if each read requires reloading the data from the NAND flash memory, it will cause a large delay. In order to reduce this delay, some SSDs have introduced a cache mechanism to temporarily store data in memory for quick access. However, existing cache strategies are often not smart enough to effectively identify and cache data blocks that users frequently access, thus limiting performance improvements.

[0006] In view of the above limitations, it is urgent to propose an optimization method for consumer-grade SSDs, aiming to intelligently identify and accelerate typical user usage scenarios under limited computing and memory resources. Summary of the invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a hardware acceleration method, device, equipment and medium.

[0008] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0009] In a first aspect, this embodiment provides a hardware acceleration method, comprising the following steps:

[0010] Get the read and write commands issued by the host;

[0011] Parse the read and write commands to obtain parsed commands;

[0012] Determine whether the parsed command is a read command;

[0013] If the parsed command is a read command, determining whether the parsed command is a sequential read command;

[0014] If the parsed command is a sequential read command, the read cache management engine is requested to allocate a buffer, and a pre-read command is constructed, carrying the buffer address and the LBA address;

[0015] According to the pre-read command, the data is cached in the read cache buffer;

[0016] Submit the parsing command to the read cache management engine for processing;

[0017] Determine whether the parsing command hits the cache data in the current read cache buffer;

[0018] If the parsed command hits the cache data in the current read cache buffer, the corresponding data is directly returned to the host from the read cache buffer and the command is marked as completed.

[0019] Its further technical solution is: after the step of determining whether the parsing command hits the cache data of the current read cache buffer, it also includes: if the parsing command does not hit the cache data of the current read cache buffer, then mark the command node corresponding to the parsing command and allocate an available read cache buffer address.

[0020] Its further technical solution is: after marking the command node corresponding to the parsed command and allocating the available read cache buffer address, it also includes: reading the corresponding data according to the parsed command and returning it to the host, and saving the data to the read cache buffer at the same time.

[0021] Its further technical solution is: after the step of judging whether the parsed command is a read command, it also includes: if the parsed command is not a read command, the parsed command is a write command, and the corresponding buffer data is invalidated.

[0022] In a second aspect, the present embodiment provides a hardware acceleration device, including: an acquisition unit, a parsing unit, a first judgment unit, a second judgment unit, an application construction unit, a cache unit, a submission processing unit, a third judgment unit and a return marking unit;

[0023] The acquisition unit is used to obtain the read and write commands sent by the host;

[0024] The parsing unit is used to parse the read and write commands to obtain parsed commands;

[0025] The first determination unit is used to determine whether the parsed command is a read command;

[0026] The second determination unit is configured to determine whether the parsed command is a sequential read command if the parsed command is a read command;

[0027] The application construction unit is used to apply for a buffer from the read cache management engine if the parsed command is a sequential read command, and to construct a pre-read command, carrying a buffer address and an LBA address;

[0028] The cache unit is used to cache data in a read cache buffer according to a pre-read command;

[0029] The submission processing unit is used to submit the parsing command to the read cache management engine for processing;

[0030] The third judgment unit is used to judge whether the parsing command hits the cache data of the current read cache buffer;

[0031] The return marking unit is used to return the corresponding data directly from the read cache buffer to the host if the parsed command hits the cache data in the current read cache buffer, and mark the command completed.

[0032] Its further technical solution is: the device also includes: a tag allocation unit, which is used to mark the command node corresponding to the parsed command and allocate an available read cache buffer address if the parsed command does not hit the cache data of the current read cache buffer.

[0033] A further technical solution is as follows: the device further comprises: a return saving unit, which is used to read the corresponding data according to the parsing command and return it to the host, and at the same time save the data into the read cache buffer.

[0034] A further technical solution is as follows: the device further comprises: an invalidation unit, which is used to invalidate the corresponding buffer data if the parsed command is not a read command and the parsed command is a write command.

[0035] In a third aspect, this embodiment provides a computer device, which includes a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the hardware acceleration method as described above is implemented.

[0036] In a fourth aspect, this embodiment provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the hardware acceleration method as described above can be implemented.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows: by acquiring and parsing the read and write commands issued by the host, the read commands can be intelligently identified, and further distinguished as to whether they are sequential read commands, so that the SSD can adopt different processing strategies for different types of read commands, thereby improving the pertinence and efficiency of the processing; in addition, for the identified sequential read commands, by applying for a buffer from the read cache management engine and constructing a pre-read command, data is read from the NAND flash memory in advance and cached in the read cache buffer. This mechanism effectively reduces the delay in subsequent data access, because when the host requests the data again, it can be directly obtained from the cache without accessing the NAND flash memory again; in addition, by judging whether the parsed command hits the cached data in the current read cache buffer, the host's data request can be responded to quickly. Once hit, the data will be directly returned to the host from the read cache buffer and the command will be marked as completed, which greatly shortens the command response time and data transmission delay, and improves the overall performance of the system.

[0038] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 This is a schematic diagram of an application scenario of a typical read command SSD internal processing in the prior art;

[0041] Figure 2 A schematic diagram of an application scenario of a typical SSD user access command feature in the prior art;

[0042] Figure 3 A schematic diagram of a process flow of a hardware acceleration method provided by an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of an application scenario of the hardware acceleration method provided by an embodiment of the present invention;

[0044] Figure 5 A schematic block diagram of a hardware acceleration device provided by an embodiment of the present invention;

[0045] Figure 6 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0048] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0049] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0050] See also Figure 1 The schematic diagram of the application scenario of a typical read command SSD internal processing in the prior art is shown as follows:

[0051] The host submits a read command to the front-end module of the SSD; the SSD front-end module divides the command into mapping units (typically 4KB); submits an operation request to the buffer management module to allocate a read buffer; submits an operation request to the mapping table management module; the mapping table management module is responsible for converting the logical address into a NAND physical address; submits an operation request to the back-end module, and the back-end module initiates a NAND read request based on the physical address; waits for the NAND read operation request to be completed, at which time the data will be loaded into the NANDCacheRegist (NAND memory cache); after the data is ready, start the data transmission from the NANDCacheRegistry to the host.

[0052] From the front-end module, through a series of internal software processing, to NAND reading, a long processing delay is required, so the performance will be lower.

[0053] See also Figure 2 The following is a schematic diagram of an application scenario of a typical SSD user access command feature in the prior art:

[0054] In chronological order, the host sends some read and write commands one after another; read commands RD_0, RD_1, RD_2... are adjacent and access continuous LBA intervals; read command RD_X accesses the same LBA interval as RD_1 (LBA 16-31); read commands RD_Y and RD_Z are not adjacent, but access the same LBA interval (LBA 128-255)

[0055] In this scenario, commands RD_0 / RD_1 / RD_2... form a sequential read stream. The SSD needs to see the command before initiating internal reads, which results in a large delay. Furthermore, RD_X and RD_1 read the same LBA interval; RD_Y and RD_Z also read the same LBA interval. RD_X / RD_Z also need to initiate NAND reads inside the SSD, which results in a large delay.

[0056] See also Figure 3 to Figure 4 In the specific embodiment shown, the present invention discloses a hardware acceleration method, comprising the following steps:

[0057] S1, obtain the read and write commands issued by the host;

[0058] Specifically, when the host needs to read or write data in the SSD, it constructs the corresponding read and write commands according to the communication protocol and sends them to the SSD through the interface. The command receiving module inside the SSD is responsible for monitoring the data transmission on the interface. Once it detects that a read or write command has been issued, it immediately captures and stores these commands. By directly obtaining the read and write commands issued by the host, the SSD can quickly respond to the host's data requests, which reduces the delay in data transmission and improves the overall performance of the system. In addition, by directly obtaining commands, the SSD can use its own computing and storage resources more effectively, which avoids unnecessary waste of resources and improves the overall efficiency and performance of the system.

[0059] S2, parsing the read and write commands to obtain parsed commands;

[0060] Specifically, parsing the read and write commands includes two methods: command format parsing and state machine parsing. Among them, command format parsing includes:

[0061] First, in the communication protocol between the SSD and the host, the format of the read and write commands is clearly defined, including the command's start bit, length, check code, and specific opcode and data address information. When the SSD receives the read and write commands sent by the host, it will first store them in the internal command buffer. The parsing module inside the SSD will match the format of the read and write commands stored in the command buffer according to the predefined command format, and ensure that the received command is complete and valid by comparing the command's start bit, length, check code and other information. After confirming that the command is valid, the parsing module will further extract the opcode (indicating whether it is a read operation or a write operation) and the data address (indicating the location of the data to be read or written in the SSD) in the command. Based on the extracted opcode and data address, the parsing module will generate the corresponding parsing command and pass it to the subsequent processing module.

[0062] Among them, state machine-based analysis includes:

[0063] A state machine is designed inside the SSD to process read and write commands in different states. The state machine includes idle state, receiving state, parsing state, and completion state. When the SSD receives a read or write command, the state machine switches from the idle state to the receiving state. In the receiving state, the state machine gradually receives and stores each part of the command according to the format and length of the command. After receiving the entire command, the state machine switches to the parsing state. In the parsing state, the state machine parses the command according to predefined rules and extracts information such as the opcode and data address. Then, the state machine updates to the completion state based on the parsing results and generates the corresponding parsing command.

[0064] More specifically, through a parsing method based on a command format or a state machine, the SSD can quickly identify and parse the read and write commands issued by the host, which reduces the delay in command processing and improves the overall performance of the system. The predefined command format and state machine design ensure that the SSD can accurately parse the read and write commands issued by the host, which avoids problems such as data read and write errors or system crashes caused by command parsing errors. The command format-based parsing method can flexibly adapt to different communication protocols and command formats, which makes the SSD compatible with a variety of hosts and storage devices, improving the versatility and scalability of the system. Through efficient parsing methods, the SSD can more effectively utilize its own computing and storage resources, which avoids unnecessary waste of resources and improves the overall efficiency and performance of the system.

[0065] S3, determining whether the parsed command is a read command;

[0066] Specifically, judging the parsed command includes two methods: judging based on the operation code and judging based on the command type field; wherein judging based on the operation code includes:

[0067] In the communication protocol between the SSD and the host, the opcodes of the read and write commands are clearly defined. Read commands and write commands correspond to different opcodes. In the previous steps, the parsed command has been obtained by parsing the read and write commands. This parsed command contains the opcode extracted from the original command. The judgment module inside the SSD will obtain the opcode in the parsed command and match it with the predefined read command opcode. If the match is successful, that is, the opcode is consistent with the read command opcode, the judgment module will output a signal or flag indicating that the parsed command is a read command. If the match is unsuccessful, the parsed command is judged to be another type of command (such as a write command).

[0068] Among them, judgment based on the command type field includes:

[0069] In some communication protocols, read and write commands may contain a clear command type field to indicate whether the command is a read command or a write command. In the process of parsing the read and write commands to obtain the parsed command, this command type field is also extracted. The judgment module compares the value of the extracted command type field with the predefined read command type field value. If the field values ​​are equal, the parsed command is judged to be a read command; if not, it is judged to be another type of command.

[0070] More specifically, through the judgment method based on the opcode or command type field, the SSD can accurately identify the read command issued by the host, which avoids problems such as data read and write errors or system abnormalities caused by command judgment errors. Once the judgment module determines that the parsed command is a read command, the SSD can immediately enter the processing flow of the read command, which reduces unnecessary processing steps and delays and improves the response speed and overall performance of the system. Since the judgment module makes judgments based on the predefined opcode or command type field, when the communication protocol or command format changes, only the predefined information in the judgment module needs to be updated, which enables the SSD to flexibly adapt to different communication protocols and host types. Through an efficient judgment method, the SSD can determine the type of parsed command more quickly and take corresponding processing measures, which reduces the system's resource consumption and improves the overall efficiency and performance of the system.

[0071] S4, if the parsed command is a read command, determine whether the parsed command is a sequential read command; if the parsed command is not a sequential read command, jump to step S7;

[0072] Specifically, the determination and parsing of commands include two methods: determination based on address continuity and command queue analysis; wherein the determination based on address continuity includes:

[0073] First, the received command is parsed by the parser to confirm that it is a read command. The starting address and read length of the target data are extracted from the parsed read command, and a register or variable is set up to record the end address of the last read command. The starting address of the current read command is compared with the end address of the last read command to check whether there is continuity (for example, whether the current starting address is equal to the last end address plus 1). If the addresses are continuous and meet other possible sequential read conditions (such as consistent read length, etc.), it is judged as a sequential read command. If the addresses are not continuous or do not meet other sequential read conditions, it is judged as a non-sequential read command.

[0074] Among them, the command queue analysis includes:

[0075] A command queue is maintained inside the SSD to store pending read and write commands. The received commands are parsed and added to the command queue, and the commands in the queue are traversed to find the latest read command. The arrangement and interval of the read commands in the command queue are analyzed to identify whether there is a continuous read command sequence, and to check whether the target addresses of these continuous read commands are arranged in ascending order, and whether the interval between each command is less than a certain threshold (indicating that they are issued continuously in a short period of time). If the above conditions are met, it is judged as a sequential read command sequence; otherwise, it is judged as a non-sequential read command.

[0076] More specifically, after accurately identifying sequential read commands, the SSD can optimize its internal data processing flow, such as using prefetch or cache strategies, to reduce read latency and increase data transfer rates. For sequential read operations, the SSD can adjust its power management strategy to reduce unnecessary energy consumption, which is particularly important in mobile or embedded devices. By optimizing the processing of sequential read operations, the SSD can better meet the needs of the host system and improve overall system performance, especially when processing large data block read tasks. When users perform continuous data read operations (such as video playback, file copying, etc.), sequential read optimization can significantly reduce waiting time and improve user experience. Accurately identifying sequential read commands provides a basis for SSDs to implement more advanced data management strategies (such as data compression, deduplication, etc.), which helps to further improve storage efficiency and performance.

[0077] S5, if the parsed command is a sequential read command, apply for a buffer from the read cache management engine, and construct a pre-read command, carrying the buffer address and LBA address;

[0078] Specifically, the read cache management engine includes two modes: buffer application and pre-reading command construction based on the read cache management engine and optimization of pre-reading strategy and dynamic buffer management; wherein, the buffer application and pre-reading command construction based on the read cache management engine includes:

[0079] Receive and parse the command sent by the host, and identify the command as a sequential read command. According to the read length and data characteristics of the sequential read command (such as data block size, access mode, etc.), apply for a buffer of appropriate size from the read cache management engine. The read cache management engine allocates one or more free buffers based on the current cache usage and strategy, and returns the buffer address to the requester. Construct a pre-read command based on the starting LBA address, read length, and requested buffer address of the sequential read command. In addition to basic read and write instructions, the pre-read command must also clearly specify the LBA address range of the target data block and the buffer address where the data should be stored. Send the constructed pre-read command to the data processing module (such as the flash memory controller) inside the SSD for execution. The data processing module reads data from the storage medium according to the pre-read command and stores it in the specified buffer.

[0080] Among them, optimizing the pre-reading strategy and dynamic buffer management includes:

[0081] Dynamically adjust the pre-reading strategy based on the history of sequential read commands, the current system load, and the characteristics of the storage medium; for example, when a frequent sequential read pattern is detected, the pre-reading depth can be increased (that is, more data blocks are read in advance) to improve the hit rate of subsequent reads. The read cache management engine dynamically adjusts the size and number of buffers based on the current cache usage and future pre-reading needs; for example, when the cache usage rate is high, some infrequently used buffers can be released for new pre-reading commands; when the cache usage rate is low, the number of buffers can be increased to store more pre-read data. Combine pre-reading strategies and dynamic buffer management to build more efficient pre-reading commands. Issue and execute optimized pre-reading commands to ensure that data can be accurately stored in the specified buffer, while reducing unnecessary cache replacement and data migration overhead.

[0082] More specifically, by constructing and executing pre-read commands, data blocks that may be read later can be loaded into the cache in advance, thereby shortening the read latency and improving data access speed. The dynamic buffer management strategy can dynamically adjust the usage of cache resources according to actual needs and system load to avoid waste and overuse of cache resources. Efficient pre-read strategies and cache management can significantly improve the response speed and stability of SSDs when processing sequential read tasks. By reducing unnecessary storage media access and data transmission overhead, the overall energy consumption of SSDs can be reduced. When processing a large number of sequential read tasks (such as video playback, file decompression, etc.), users can experience faster response speeds and a smoother user experience.

[0083] S6, according to the pre-read command, cache the data in the read cache buffer;

[0084] Specifically, data caching includes two methods: directly caching pre-read data and optimizing cache strategy and data consistency. Among them, directly caching pre-read data includes:

[0085] When the SSD receives a pre-read command, the command contains the LBA (logical block address) of the data block to be read and the expected buffer address. The flash controller or other data processing module of the SSD reads the corresponding data block from the storage medium (such as NAND flash memory) according to the LBA address in the pre-read command. The read data block is directly transferred to the read cache buffer specified in the pre-read command. During the transmission process, data decoding, error correction (ECC) and necessary format conversion may be involved to ensure data consistency and integrity. The read cache management engine is responsible for maintaining the mapping relationship between the data blocks in the cache and the LBA addresses. When new data blocks are cached, the management engine updates the mapping table for subsequent quick access to these data blocks. When the host requests access to the cached data block, the SSD finds the location of the data block in the cache by querying the mapping table and reads the data directly from the cache instead of accessing the storage medium again.

[0086] Among them, optimizing cache strategy and data consistency includes:

[0087] According to the workload characteristics of the SSD, the performance of the storage medium, and the access pattern of the host, formulate a suitable cache strategy; for example, the LRU (Least Recently Used) algorithm can be used to manage the data blocks in the cache so that the data blocks that are least likely to be accessed again can be replaced in time when the cache space is insufficient. When the data is cached in the read cache buffer, the version number and verification information (such as ECC check code) of the data are recorded at the same time. When the data block in the storage medium is updated, the SSD will check the data block version in the cache to ensure that the data in the cache is updated when necessary to maintain consistency. According to the access pattern and pre-reading strategy of the host, the number and type of data blocks in the cache are dynamically adjusted; for example, when a frequent sequential read pattern is detected, the number and range of pre-read data blocks in the cache can be increased to improve the hit rate of subsequent reads.

[0088] More specifically, by caching data blocks in the read cache buffer, the number of accesses to the storage medium can be significantly reduced, thereby reducing read latency and increasing data access speed. A suitable cache strategy can ensure that the data blocks in the cache are the most likely to be accessed by the host, thereby optimizing the efficiency of cache space usage. By recording the version number and verification information of the data, and updating the data in the cache when necessary, it can be ensured that the data in the cache is consistent with the data in the storage medium. When processing large amounts of data reading tasks, users can experience faster response speeds and a smoother user experience. By reducing the number of accesses to the storage medium, the overall energy consumption of the SSD can be reduced, which is particularly important in mobile or embedded devices.

[0089] S7, submitting the parsing command to the read cache management engine for processing;

[0090] Specifically, the parsing command submission includes two methods: basic process and command submission and optimization strategy and dynamic adjustment. Among them, the basic process and command submission include:

[0091] The SSD controller first receives data access commands from the host, which may include multiple types such as read, write, and delete. The command parsing module in the controller parses the received commands and identifies key information such as the command type, target address (such as LBA address), and data length. Based on the parsed command information, it is determined whether the command is a read operation and whether it is possible to benefit from the read cache. If the command meets the conditions for using the read cache (such as the command is a sequential read, the random read hit rate is high, the data block size matches the cache block size, etc.), it is marked as a command that needs to be processed by the read cache management engine. The parsed command and its related information (such as the target LBA address, data length, expected data transmission speed, etc.) are submitted to the read cache management engine. The read cache management engine decides whether to provide data directly from the cache or whether to read data from the storage medium and update the cache based on the cache policy (such as LRU, LFU, etc.) and the current cache status (such as cache hit rate, cache space usage, etc.). If the target data is already in the cache, the read cache management engine will read the data directly from the cache and return it to the host through the controller. If the target data is not in the cache, the read cache management engine triggers the operation of reading the data from the storage medium, and caches the data after the data is read, and then returns it to the host.

[0092] Among them, optimization strategies and dynamic adjustments include:

[0093] Dynamically adjust the cache strategy according to the workload characteristics of the SSD, the performance of the storage medium, and the access mode of the host. For example, in the sequential read mode, the pre-read depth can be increased to cache the data blocks that may be accessed later in the read cache in advance. In the random read mode, the cache replacement algorithm can be optimized to improve the cache hit rate. Different commands are assigned different priorities according to the urgency of the command and the data access mode. High-priority commands are processed first to ensure fast access to key data. For low-priority commands, the processing can be appropriately delayed or the data can be read directly from the storage medium when the cache resources are tight. The size of the read cache is dynamically adjusted according to the current system memory usage, the read and write speed of the storage medium, and the access requirements of the host. When the system memory is sufficient and the host access speed requirement is high, the size of the read cache can be increased to improve the cache hit rate; when the system memory is tight or the host access speed requirement is not high, the size of the read cache can be reduced to release memory resources.

[0094] More specifically, by submitting the parsed commands to the read cache management engine for processing, the data in the cache can be fully utilized to improve the reading speed and reduce the number of storage medium accesses and delays. Dynamic cache strategies and command priority management can ensure that cache resources are used efficiently and avoid cache pollution and waste. By dynamically adjusting the cache size and strategy, it can adapt to different workloads and host access patterns, improving the flexibility and adaptability of the system. Reducing the number of storage medium accesses can reduce the overall energy consumption of the SSD, which is especially important in mobile or embedded devices. When processing large amounts of data reading tasks, users can experience faster response times and a smoother user experience.

[0095] S8, determining whether the parsing command hits the cache data in the current read cache buffer;

[0096] Specifically, judging whether the parsed command hits the cache data of the current read cache buffer includes two methods: cache hit judgment based on tag comparison and optimized cache hit judgment strategy; wherein, cache hit judgment based on tag comparison includes:

[0097] The SSD controller receives and parses the data access command from the host, extracting key information from the command, such as the logical block address (LBA) and data length of the target data. The read cache management engine in the controller maintains a cache tag table, which records the LBA address and corresponding data status (such as valid, invalid, or dirty) of the data block cached in the current read cache buffer. The target LBA address in the parsed command is compared with the entries in the cache tag table one by one to find out whether there is a matching cache data block. If an entry that completely matches the target LBA address is found in the cache tag table, and the data status of the entry is valid, it is judged as a cache hit. If no matching entry is found, or the data status of the entry found is invalid or dirty (indicating that the data has been modified but has not been written back to the storage medium), it is judged as a cache miss. In the case of a cache hit, the target data block is directly read from the read cache buffer and returned to the host through the controller. In the case of a cache miss, the operation of reading data from the storage medium is triggered, and after the data is read, it is cached in the read cache buffer (if the cache space allows), and then returned to the host.

[0098] Among them, the optimization cache hit judgment strategy includes:

[0099] According to the host's access pattern and history, a prefetch algorithm is used to predict the data blocks that may be accessed in the future, and cache them in advance in the read cache buffer. The prefetch algorithm can increase the probability of cache hits and reduce cache misses. A multi-level cache structure is used, such as L1 cache and L2 cache, where L1 cache is faster but smaller in capacity, and L2 cache is slower but larger in capacity; when the parsed command does not hit in the L1 cache, it can continue to search in the L2 cache to improve the overall cache hit rate. According to the cache replacement algorithm (such as LRU, LFU, etc.) and the current workload characteristics, the data blocks in the cache are dynamically adjusted to optimize the cache hit rate; for example, in sequential read mode, a more aggressive prefetch and cache replacement strategy can be used to increase the number and hit rate of consecutive data blocks in the cache.

[0100] More specifically, accurate cache hit judgment can fully utilize the data in the read cache buffer and reduce the number of accesses to the storage medium, thereby increasing the data reading speed. The optimized cache hit judgment strategy can reduce unnecessary cache replacement and data migration operations and improve the efficiency of cache resource utilization. The use of a multi-level cache structure and a dynamic cache replacement strategy can adapt to different workloads and host access patterns, improving the flexibility and adaptability of the system. Reducing the number of accesses to the storage medium can reduce the overall energy consumption of the SSD, which is particularly important in mobile or embedded devices. When processing large amounts of data reading tasks, users can experience faster response speeds and a smoother user experience.

[0101] S9: If the parsed command hits the cache data in the current read cache buffer, the corresponding data is directly returned from the read cache buffer to the host, and the command is marked as completed.

[0102] Specifically, directly returning corresponding data from the read cache buffer to the host and marking the command completed includes two methods: basic process and hit processing and optimized hit processing process; wherein the basic process and hit processing include:

[0103] The SSD controller receives and parses the data read command from the host, extracts key information such as the logical block address (LBA) and data length of the target data. The read cache management engine in the controller searches for matching cache data blocks in the current read cache buffer based on the parsed command information. If a cache data block that completely matches the target LBA address is found in the read cache buffer, and the status of the data block is valid (i.e., not marked as invalid or dirty), it is judged as a cache hit. In the case of a cache hit, the read cache management engine directly reads the corresponding data block from the cache and returns it to the host through the SSD controller. At the same time as the data is returned to the host, the SSD controller or read cache management engine marks the data read command as completed, which usually involves updating the command queue or status register to indicate that the processing of the command has been completed and the corresponding data has been successfully transmitted to the host. Once the command is marked as completed, the SSD controller can continue to process the next command in the queue, or enter an idle state to wait for a new command to arrive.

[0104] The optimization hit processing flow includes:

[0105] In order to further improve the processing speed of cache hits, a fast path processing mechanism can be designed. When the parsed command hits the cache, the data is directly transferred from the read cache buffer to the host through the fast path without passing through other processing modules in the controller, which can reduce the delay of data transmission and improve the overall response speed of the system. If the target data blocks of multiple data read commands are all located in the read cache buffer, and these commands can be merged for processing (such as reading multiple data blocks continuously), command merging and batch processing technology can be used. By merging these commands, the processing overhead of the controller and the read cache management engine can be reduced, and the efficiency of data transmission can be improved. When processing cache hits, it is necessary to ensure that the data in the cache is consistent with the data in the storage medium. If the data in the storage medium is updated during the cache hit (for example, due to the execution of another write command), appropriate measures (such as delaying the return of data, updating the data in the cache, etc.) need to be taken to maintain the consistency of the cache.

[0106] More specifically, by returning cache hit data directly from the read cache buffer, the number of storage medium accesses and data transmission delays can be significantly reduced, thereby increasing data read speed. The cache hit processing flow is more efficient, which can reduce the processing overhead of the controller and read cache management engine and improve the utilization efficiency of system resources. Fast path processing and command merging and batch processing technology can further shorten the response time of data reads and improve the overall response speed of the system.

[0107] In one embodiment, after the step of determining whether the parsing command hits the cache data of the current read cache buffer, it also includes: S10, if the parsing command does not hit the cache data of the current read cache buffer, marking the command node corresponding to the parsing command and allocating an available read cache buffer address.

[0108] Specifically, marking and allocating available read cache buffer addresses at the command node corresponding to the parsed command includes two methods: a cache miss processing flow and an optimized miss processing strategy; wherein the cache miss processing flow includes:

[0109] The SSD controller receives and parses the data read command from the host, extracts key information such as the logical block address (LBA) and data length of the target data. The read cache management engine in the controller searches the current read cache buffer for matching cache data blocks based on the parsed command information. If no cache data block matching the target LBA address is found in the read cache buffer, or the cache data block found is invalid or dirty (indicating that the data has been modified but not yet written back to the storage medium), it is judged as a cache miss. In the case of a cache miss, the read cache management engine finds the command node corresponding to the parsed command in the command queue or command processing tree, and sets a miss flag on the node. This miss flag is used to track the processing status of the command in the future to ensure that the data can be correctly returned to the host after it is read from the storage medium and cached in the read cache buffer. The read cache management engine searches the read cache buffer for available cache space and allocates one or more consecutive address blocks to the missed command. These address blocks will be used to store the data blocks read from the storage medium. While allocating the address, the read cache management engine will also update the corresponding cache tag table to record the mapping relationship between the newly allocated address block and the target LBA address. Once the read cache buffer address is allocated, the SSD controller will trigger the operation of reading the target data block from the storage medium. After the data is read, the controller will write the data block to the previously allocated read cache buffer address and update the status information of the cache tag table to mark the data block as valid.

[0110] Among them, the optimization miss handling strategy includes:

[0111] When the read cache buffer space is insufficient, an appropriate cache replacement strategy needs to be adopted to make room for new miss commands. Common cache replacement strategies include Least Recently Used (LRU) and Least Frequently Used (LFU). The SSD controller can dynamically select an appropriate replacement strategy to optimize the cache hit rate based on the current workload characteristics and cache usage. For data read commands with high priority or urgency, the SSD controller can take special measures to speed up their processing when the cache misses; for example, the read cache buffer address can be preferentially allocated to these commands, or the relevant data blocks can be read from the storage medium in advance through a prefetch algorithm. The SSD controller can dynamically adjust the size of the read cache buffer according to the actual needs and performance goals of the system. When a large number of data read tasks need to be processed, the size of the read cache buffer can be increased to improve the cache hit rate; when resources are tight, the buffer size can be reduced to release other resources.

[0112] More specifically, by allocating the read cache buffer address and triggering the data read and cache operation when a miss occurs, it is possible to ensure that data can be efficiently read and returned to the host even if a cache miss occurs. By adopting an appropriate cache replacement strategy and command priority processing mechanism, the space resources of the read cache buffer can be maximized to improve the cache hit rate and overall performance. The function of dynamically adjusting the read cache buffer size can adapt the SSD to different workloads and performance requirements, improving the flexibility and scalability of the system. By optimizing the miss processing process, the delay time of data reading can be reduced and the system response speed can be improved, thereby bringing a better user experience.

[0113] In one embodiment, after marking the command node corresponding to the parsed command and allocating the available read cache buffer address, the method further includes: S11, reading the corresponding data according to the parsed command and returning it to the host, and saving the data to the read cache buffer at the same time.

[0114] Specifically, reading the corresponding data according to the parsed command and returning it to the host and saving the data to the read cache buffer at the same time includes two methods: data reading and cache synchronization processing and optimizing data reading and cache flow; wherein, data reading and cache synchronization processing includes:

[0115] The SSD controller receives and parses the data read command from the host and executes the previous steps, including marking misses at the command node and allocating available read cache buffer addresses. Once the read cache buffer address is allocated, the SSD controller triggers the operation of reading the target data block from the storage medium (such as NAND flash memory). This usually involves sending a read command to the storage medium controller and waiting for the data to be read out. When the data is successfully read from the storage medium, the SSD controller immediately returns the data block to the host through an interface (such as SATA, PCIe, etc.) to meet the host's data request. At the same time, the controller also writes the data block to the previously allocated read cache buffer address to cache the data. This step is to enable subsequent possible read requests for the same data to be directly obtained from the cache, reducing the number of accesses to the storage medium. After the data is written to the cache, the SSD controller updates the cache tag table or corresponding metadata, marks the data block as valid, and records the mapping relationship between its logical block address (LBA) and the cache address. After the data is returned to the host and the cache update is completed, the SSD controller marks the data read command as completed and removes or updates its status information from the command queue.

[0116] The optimization of data reading and caching processes includes:

[0117] In order to further improve the efficiency of data reading and caching, the SSD controller can use a pre-fetch algorithm to predict and read adjacent data blocks in advance while reading the target data block. These adjacent data blocks can be cached in the read cache buffer for subsequent possible read requests. At the same time, the SSD controller can be designed as a multi-channel or multi-core architecture to achieve parallel reading and cache processing of data and reduce processing delays. The SSD controller can intelligently manage the use of the read cache buffer according to the access mode of the data and the request mode of the host; for example, for frequently accessed data blocks, they can be kept in the cache for a longer time; for less frequently accessed data blocks, they can be replaced in time to free up space. During the data reading and caching process, if a storage medium failure or data transmission error occurs, the SSD controller needs to adopt appropriate error handling mechanisms, such as retrying reading, data recovery, or reading from backup. At the same time, the controller also needs to ensure the consistency and integrity of the data in the cache to avoid data corruption or loss.

[0118] More specifically, by returning the data directly to the host after reading it from the storage medium and caching it in the read cache buffer at the same time, the delay time of data reading can be significantly reduced and the response speed of the system can be improved. The data blocks in the cache can be used multiple times, reducing the number of accesses to the storage medium and reducing the energy consumption and wear of the system. At the same time, the intelligent cache management strategy can further optimize the efficiency of cache use, improve the cache hit rate and overall performance. By adopting pre-fetch algorithms and parallel processing technology, the risk of system crashes and data loss caused by storage medium failures or data transmission errors can be reduced. At the same time, the error handling and recovery mechanism can ensure that the system can quickly recover and continue to work when encountering abnormal situations.

[0119] In one embodiment, after the step of determining whether the parsed command is a read command, the method further includes: S12, if the parsed command is not a read command, the parsed command is a write command, and the corresponding buffer data is invalidated.

[0120] Specifically, parsing a command as a write command and invalidating the corresponding buffer data includes two methods: command parsing and buffer processing flow and optimizing write command processing and cache management; wherein the command parsing and buffer processing flow includes:

[0121] The SSD controller receives a command from the host and first determines whether the command is a read command. This step usually involves parsing the command format and content to identify the command type (read / write) and the logical block address (LBA) of the target data. If the parsing result shows that the command is not a read command, the command is assumed to be a write command (in most storage systems, the command type is usually read or write, so this judgment is reasonable). Once a write command is identified, the SSD controller will check whether there are data blocks corresponding to the target LBA address in the current read / write cache buffer. If so, these data blocks are considered outdated or invalid because the write command will update the content of these data blocks. For the data blocks corresponding to the target LBA address found, the SSD controller will mark them as invalid, which usually involves updating the cache tag table or corresponding metadata to indicate that these data blocks no longer contain valid data. The invalidation operation ensures that when there are subsequent read requests for these addresses, the system will not mistakenly read outdated data from the cache. After completing the invalidation of the buffer data, the SSD controller will execute the write command to write the data from the host to the storage medium (such as NAND flash memory). If the data block involved in the write command already exists in the cache (that is, it has been read and cached before), the controller may update the data block in the cache first and then write it back to the storage medium. But usually, in order to avoid data inconsistency, the write operation bypasses the cache and writes directly to the storage medium, and updates the cache status (such as marking it as dirty or invalid) after the write operation is completed. In some cases, in order to maintain cache consistency, the SSD controller may read the new data block back from the storage medium and cache it in the read / write cache buffer after the write operation is completed (this depends on the cache policy and write-back policy). At the same time, the controller also needs to update the cache tag table or metadata to reflect the latest status of the data blocks in the storage medium and cache.

[0122] Among them, optimizing write command processing and cache management includes:

[0123] To reduce the number of write operations and the wear of the storage media, the SSD controller can use write merging and compression technology, which involves merging multiple small write operations into a large write operation and compressing the data to reduce the storage space occupied. When performing write merging and compression, the controller needs to ensure that the data blocks in the cache are consistent with the data blocks in the storage media to avoid data loss or inconsistency. The SSD controller can use different write-back strategies to manage the data blocks in the cache; for example, a write-through strategy can be used, that is, the write operation is directly written to the storage media without passing through the cache; or a write-back strategy can be used, that is, the write operation first updates the data block in the cache and then writes it back to the storage media when appropriate. The choice of write-back strategy depends on factors such as the system's performance requirements, reliability requirements, and the characteristics of the storage media. When processing write commands, the SSD controller needs to ensure cache consistency. This includes updating the cache tag table and metadata after the write operation is completed, and reading new data blocks from the storage media and caching them in the cache when necessary. To avoid data inconsistency, the controller can also use some additional mechanisms, such as double write or checksum.

[0124] More specifically, by invalidating the corresponding buffer data and directly executing the write command, unnecessary cache access and write operations can be reduced, and the efficiency of write operations can be improved. Invalidating obsolete data blocks can free up cache space for new data blocks and optimize cache usage efficiency. By ensuring data consistency between the cache and the storage medium, system crashes and data corruption caused by data loss or inconsistency can be avoided.

[0125] See also Figure 4 Schematic diagram of application scenarios of the hardware acceleration method shown;

[0126] Pre-reading engine: monitors the host's read and write commands to determine whether there is a sequential read scenario; if so, initiates pre-loading of sequential reads; for example, the host's three consecutive read commands read LBA 0-127, LBA 128-255, and LBA 256-383 in sequence, and these LBAs are all sequential; before the subsequent read command comes, the pre-reading engine can first initiate a read of LBA 384-511 to cache the data in memory.

[0127] The read cache management engine mainly includes the following functions:

[0128] Manage the allocation and recycling of read cache buffers;

[0129] When the host command is a read, a check is made based on the LBA address to see if the data cached in the buffer is hit; if so, the data is directly returned from the buffer to the host without having to load the data from the NAND in the traditional way.

[0130] When the host command is a write command, a check is made based on the LBA address to see if the data cached in the buffer is hit; if it is hit, the corresponding buffer data is invalidated (its latest data is carried in the current write command).

[0131] For non-hit read commands, determine whether they need to be added to the read cache and mark the corresponding command node (save_to_rc=1, indicating that when the corresponding read command reads data from NAND and returns it to the host, the data is also backed up to the memory allocated to the read cache); and when it needs to be saved to the read cache, allocate an available read cache buffer address (save_address).

[0132] Command reporting, responsible for reporting the command information received by the hardware to the firmware, including the following types:

[0133] Host reads and writes, and performs NAND reads and writes according to the traditional path;

[0134] Host reads (into RC), the command (save_to_rc=1, and carries the allocated save_address), this command not only performs NAND read and returns to the host, but also saves the data into the read cache buffer at the same time.

[0135] Command request queue, software and hardware interaction interface, the command reporting module writes command information into the queue, and the software obtains the command from it for execution.

[0136] The read cache buffer and data buffer are organized to store user data according to a certain granularity (such as LPA, 4KB; LPA 0 corresponds to LBA 0-7; LPA 1 corresponds to LBA 8-15...).

[0137] During this process, sequential reads can be recognized by the hardware engine and NAND reads can be initiated in advance to load the data into the read cache buffer. For repeated reads, they are also backed up in the read cache buffer when they are first read out and returned to the host. When the host subsequently reads the corresponding data, it is recognized by the hardware engine as a hit in the read cache and can be quickly returned to the host from the memory, greatly reducing the command response delay.

[0138] By acquiring and parsing the read and write commands sent by the host, the present invention can intelligently identify the read commands and further distinguish whether they are sequential read commands, so that the SSD can adopt different processing strategies for different types of read commands, thereby improving the pertinence and efficiency of processing; in addition, for the identified sequential read commands, by applying for a buffer from the read cache management engine and constructing a pre-read command, data is read from the NAND flash memory in advance and cached in the read cache buffer. This mechanism effectively reduces the delay in subsequent data access, because when the host requests these data again, they can be directly obtained quickly from the cache without accessing the NAND flash memory again; in addition, By judging whether the parsed command hits the cache data in the current read cache buffer, the host's data request can be responded to quickly. Once it hits, the data will be directly returned to the host from the read cache buffer and the command will be marked as completed, which greatly shortens the command response time and data transmission delay, and improves the overall performance of the system; in addition, for repeated read operations, when the data is read out for the first time and returned to the host, it will be backed up in the read cache buffer, so that when the host requests the same data again, the hardware engine can quickly identify the hit read cache, and directly return the data from the memory, avoiding the additional delay caused by repeated reading of NAND flash memory. In addition, the entire acceleration process is implemented at the hardware level, without relying on the host's CPU resources, which not only reduces the burden on the host, but also makes the acceleration effect more significant and stable; at the same time, due to the introduction of hardware acceleration, SSD can maintain higher throughput and lower latency when processing a large number of read and write requests.

[0139] See also Figure 5 As shown, the present invention also discloses a hardware acceleration device, including: an acquisition unit 10, a parsing unit 20, a first judgment unit 30, a second judgment unit 40, an application construction unit 50, a cache unit 60, a submission processing unit 70, a third judgment unit 80 and a return marking unit 90;

[0140] The acquisition unit 10 is used to obtain the read and write commands sent by the host;

[0141] The parsing unit 20 is used to parse the read and write commands to obtain parsed commands;

[0142] The first determination unit 30 is used to determine whether the parsed command is a read command;

[0143] The second determination unit 40 is configured to determine whether the parsed command is a sequential read command if the parsed command is a read command;

[0144] The application construction unit 50 is used to apply for a buffer from the read cache management engine if the parsed command is a sequential read command, and to construct a pre-read command, carrying a buffer address and an LBA address;

[0145] The cache unit 60 is used to cache data in a read cache buffer according to a pre-read command;

[0146] The submission processing unit 70 is used to submit the parsing command to the read cache management engine for processing;

[0147] The third judgment unit 80 is used to judge whether the parsing command hits the cache data of the current read cache buffer;

[0148] The return marking unit 90 is used to return the corresponding data directly from the read cache buffer to the host if the parsed command hits the cache data in the current read cache buffer, and mark the command completed.

[0149] In one embodiment, the device further includes: a tag allocation unit 100, which is used to mark the command node corresponding to the parsed command and allocate an available read cache buffer address if the parsed command does not hit the cache data of the current read cache buffer.

[0150] In one embodiment, the device further includes: a return saving unit 110, which is used to read corresponding data according to the parsed command and return it to the host, and save the data to the read cache buffer at the same time.

[0151] In one embodiment, the apparatus further comprises: an invalidation unit 120, configured to invalidate corresponding buffer data if the parsed command is not a read command, then the parsed command is a write command.

[0152] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned hardware acceleration device and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.

[0153] The hardware acceleration device can be implemented in the form of a computer program. Figure 6 Runs on the computer device shown.

[0154] See also Figure 6 , Figure 6 is a schematic block diagram of a computer device provided in an embodiment of the present application; the computer device 500 may be a terminal or a server, wherein the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of multiple servers.

[0155] See also Figure 6The computer device 500 includes a processor 502 , a memory and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0156] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, and when the program instructions are executed, the processor 502 may execute a hardware acceleration method.

[0157] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500 .

[0158] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a hardware acceleration method.

[0159] The network interface 505 is used to communicate with other devices over the network. Figure 6 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0160] The processor 502 is used to run the computer program 5032 stored in the memory to implement the following steps:

[0161] Obtain the read and write commands issued by the host; parse the read and write commands to obtain the parsed commands; determine whether the parsed command is a read command; if the parsed command is a read command, determine whether the parsed command is a sequential read command; if the parsed command is a sequential read command, apply for a buffer from the read cache management engine, and construct a pre-read command, carrying the buffer address and LBA address; according to the pre-read command, cache the data in the read cache buffer; submit the parsed command to the read cache management engine for processing; determine whether the parsed command hits the cached data of the current read cache buffer; if the parsed command hits the cached data of the current read cache buffer, directly return the corresponding data from the read cache buffer to the host, and mark the command completed.

[0162] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0163] It can be understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.

[0164] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions, and the program instructions, when executed by a processor, can implement the above-mentioned hardware acceleration method. The storage medium stores a computer program, wherein the computer program includes program instructions, and the program instructions, when executed by a processor, can implement the above-mentioned method. The program instructions include the following steps:

[0165] Obtain the read and write commands issued by the host; parse the read and write commands to obtain the parsed commands; determine whether the parsed command is a read command; if the parsed command is a read command, determine whether the parsed command is a sequential read command; if the parsed command is a sequential read command, apply for a buffer from the read cache management engine, and construct a pre-read command, carrying the buffer address and LBA address; according to the pre-read command, cache the data in the read cache buffer; submit the parsed command to the read cache management engine for processing; determine whether the parsed command hits the cached data of the current read cache buffer; if the parsed command hits the cached data of the current read cache buffer, directly return the corresponding data from the read cache buffer to the host, and mark the command completed.

[0166] The storage medium may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk, etc., which are computer-readable storage media that can store program codes.

[0167] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0168] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or skipped.

[0169] The steps in the method of the embodiment of the present invention can be adjusted in order, combined and deleted according to actual needs. The units in the device of the embodiment of the present invention can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0170] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention.

[0171] The above embodiments are preferred implementation schemes of the present invention. In addition, the present invention may also be implemented in other ways. Any obvious replacement without departing from the concept of the present technical solution is within the protection scope of the present invention.

Claims

1. A hardware acceleration method, characterized in that: The following steps are involved: Get the read and write commands issued by the host; Parse the read and write commands to obtain parsed commands; Determine whether the parsed command is a read command; If the parsed command is a read command, determining whether the parsed command is a sequential read command; If the parsed command is a sequential read command, the read cache management engine is requested to allocate a buffer, and a pre-read command is constructed, carrying the buffer address and the LBA address; According to the pre-read command, the data is cached in the read cache buffer; Submit the parsing command to the read cache management engine for processing; Determine whether the parsing command hits the cache data in the current read cache buffer; If the parsed command hits the cache data in the current read cache buffer, the corresponding data is directly returned to the host from the read cache buffer and the command is marked as completed.

2. The hardware acceleration method according to claim 1, characterized in that: After the step of determining whether the parsing command hits the cache data of the current read cache buffer, the method further includes: if the parsing command does not hit the cache data of the current read cache buffer, marking the command node corresponding to the parsing command and allocating an available read cache buffer address.

3. The hardware acceleration method according to claim 2, characterized in that: After the step of marking the command node corresponding to the parsed command and allocating the available read cache buffer address, the method further includes: reading the corresponding data according to the parsed command and returning it to the host, and simultaneously saving the data to the read cache buffer.

4. The hardware acceleration method according to claim 1, characterized in that: After the step of determining whether the parsed command is a read command, the method further includes: if the parsed command is not a read command, the parsed command is a write command, and the corresponding buffer data is invalidated.

5. A hardware acceleration device, characterized in that: include: An acquisition unit, a parsing unit, a first judgment unit, a second judgment unit, an application construction unit, a cache unit, a submission processing unit, a third judgment unit and a return marking unit; The acquisition unit is used to obtain the read and write commands sent by the host; The parsing unit is used to parse the read and write commands to obtain parsed commands; The first determination unit is used to determine whether the parsed command is a read command; The second determination unit is configured to determine whether the parsed command is a sequential read command if the parsed command is a read command; The application construction unit is used to apply for a buffer from the read cache management engine if the parsed command is a sequential read command, and to construct a pre-read command, carrying a buffer address and an LBA address; The cache unit is used to cache data in a read cache buffer according to a pre-read command; The submission processing unit is used to submit the parsing command to the read cache management engine for processing; The third judgment unit is used to judge whether the parsing command hits the cache data of the current read cache buffer; The return marking unit is used to return the corresponding data directly from the read cache buffer to the host if the parsed command hits the cache data in the current read cache buffer, and mark the command completed.

6. The hardware acceleration device according to claim 5, characterized in that: The device further comprises: a tag allocation unit, which is used for marking a command node corresponding to the parsed command and allocating an available read cache buffer address if the parsed command does not hit the cache data of the current read cache buffer.

7. The hardware acceleration device according to claim 6, characterized in that: The device also includes: a return saving unit, which is used to read corresponding data according to the parsing command and return it to the host, and save the data to the read cache buffer at the same time.

8. The hardware acceleration device according to claim 5, characterized in that: The device further comprises: an invalidation unit, which is used for invalidating corresponding buffer data if the parsed command is not a read command and the parsed command is a write command.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the hardware acceleration method according to any one of claims 1 to 4 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the hardware acceleration method according to any one of claims 1 to 4 is implemented.

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