Data storage system and method emulating eeprom using flash

Abstract

The application relates to a data storage system and method using FLASH to simulate EEPROM, which is improved based on the existing hardware implementation method of the same kind of FLASH to simulate EEPROM, a digital circuit controller for simulating EEPROM function is designed by using FLASH and SRAM and other storage devices, the hardware method is used to realize the function of simulating EEPROM, and the data storage structure is improved and the digital circuit control method is more precise, such as introducing state information, adopting a 'ping-pong operation' to manage the alternately executed internal backup transfer operation and the write operation corresponding to the external host, designing a 'background recycling' management mechanism to recycle the data blocks of the simulated EEPROM in the background, and introducing an abnormal management mechanism to diagnose and manage the abnormality, so that the performance loss of the hardware implementation of using FLASH to simulate EEPROM is greatly reduced, and the utilization rate of the storage resource is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of data storage technology, and relates to a data storage system and method that uses FLASH to simulate EEPROM. Background Technology

[0002] Currently, the two most commonly used non-volatile memories in integrated circuit design are EEPROM (Electrically Erasable Programmable Read-Only Memory) and FLASH (Flash Memory). EEPROM has advantages such as a high number of erase / write cycles and flexible byte-by-byte read / write capabilities, but it also has disadvantages such as low resource utilization and high read / write latency. Therefore, it is suitable for storage scenarios with small amounts of data that require frequent and flexible updates. FLASH has advantages such as high resource utilization and low read / write latency, but it also has disadvantages such as a lower number of erase / write cycles and the inability to erase byte-by-byte. FLASH generally can only erase large amounts of data in sectors, and after a write operation, the next write operation can only be performed after the erase operation is completed. Therefore, it is suitable for storage scenarios with large amounts of data that require fast read / write operations.

[0003] In practical integrated circuit design, due to process limitations (e.g., the semiconductor foundry's process technology does not support EEPROM), or for design cost and performance considerations (e.g., wanting to combine the advantages of EEPROM and FLASH), FLASH-based EEPROM emulation technology is often used. There are generally two methods for using FLASH to emulate EEPROM: software implementation and hardware implementation. The overall design concepts are largely similar. Existing hardware implementations of similar types using FLASH to emulate EEPROM typically utilize FLASH storage space several times the capacity of the target emulated EEPROM and SRAM (Static Random Access Memory) of the same capacity, combined with an emulated EEPROM controller circuit to implement the FLASH-emulated EEPROM function. Its design architecture divides the FLASH storage space into several emulated EEPROM data blocks (i.e., FLASH BANKs), with each FLASH BANK having a capacity equal to the target emulated EEPROM capacity. However, traditional hardware implementation methods that use FLASH to simulate EEPROM still suffer from significant performance loss and low storage resource utilization in scenarios such as FLASH BANK "page flipping" and large amounts of effective data in the simulated EEPROM. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a data storage system that uses FLASH to simulate EEPROM and a data storage management method that uses FLASH to simulate EEPROM, which can significantly reduce the performance loss of hardware implementation using FLASH to simulate EEPROM and effectively improve the storage resource utilization of FLASH memory.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, a data storage system using FLASH to simulate EEPROM is provided, including a simulated EEPROM controller, SRAM and FLASH memory;

[0007] The capacity of each simulated EEPROM data block in the FLASH memory is greater than the target simulated EEPROM capacity. The data structure of each simulated EEPROM data block includes a first type of address bits and a second type of address bits. The first type of address bits is used to store the status information of the simulated EEPROM data block, including erase status flag, backup status flag, write status flag and transfer status flag. The second type of address bits is used to store the simulated EEPROM data, the simulated EEPROM data address and the data validity status.

[0008] When the data space of the simulated EEPROM data block in the current FLASH memory is full and the backup transfer operation of the next simulated EEPROM data block has not been completed, the simulated EEPROM controller performs a backup transfer operation when there is no simulated EEPROM write operation request initiated by an external host. The simulated EEPROM data is continuously read from the SRAM address by address and written into the storage space of the empty simulated EEPROM data block in the FLASH memory. When there is a simulated EEPROM write operation request initiated by an external host, the write operation and backup transfer operation corresponding to the simulated EEPROM write operation request initiated by the external host are executed alternately.

[0009] The simulated EEPROM controller is also used for background recycling of simulated EEPROM data blocks that have been filled in the FLASH memory and have not participated in simulated EEPROM data writing or backup transfer operations. During the system power-on initialization phase, the simulated EEPROM controller performs diagnosis and anomaly management based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data when restoring simulated EEPROM data from the simulated EEPROM data blocks to SRAM.

[0010] On the other hand, a data storage management method using FLASH to simulate EEPROM is also provided, applied to the aforementioned data storage system using FLASH to simulate EEPROM. This data storage management method using FLASH to simulate EEPROM includes the following steps:

[0011] When the data space of the simulated EEPROM data block in the current FLASH memory is full and the backup transfer operation of the next simulated EEPROM data block has not been completed, in the absence of a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller performs a backup transfer operation that continuously reads the simulated EEPROM data from the SRAM address by address and writes it into the storage space of the empty simulated EEPROM data block in the FLASH memory.

[0012] When the data space of the simulated EEPROM data block in the current FLASH storage is full and the backup and transfer operation of the next simulated EEPROM data block has not been completed, when there is a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller alternately executes the write operation and backup and transfer operation corresponding to the simulated EEPROM write operation request initiated by the external host.

[0013] The simulated EEPROM controller performs background recycling of simulated EEPROM data blocks that have been filled in the FLASH memory and have not participated in simulated EEPROM data writing or backup transfer operations.

[0014] During the system power-on initialization phase, when restoring simulated EEPROM data from the simulated EEPROM data block to SRAM, diagnosis and anomaly management are performed based on the status information of the simulated EEPROM data block and the backed-up simulated EEPROM data.

[0015] One of the above technical solutions has the following advantages and beneficial effects:

[0016] The aforementioned data storage system and method using FLASH to simulate EEPROM significantly improves upon existing FLASH-based EEPROM hardware implementation methods. It utilizes FLASH and SRAM storage devices to design and implement a digital circuit controller that simulates EEPROM functionality. This hardware implementation achieves the simulated EEPROM function. Furthermore, through an improved data storage structure and more refined digital circuit control methods, such as introducing status information like erase, backup, write, and transfer flags, it employs a "ping-pong" management system to alternately execute internal backup / transfer operations with corresponding write operations from the external host. A "background reclamation" management mechanism is also designed to reclaim simulated EEPROM data blocks in the FLASH memory that are already full and have not participated in simulated EEPROM data writing or backup / transfer operations. Simultaneously, an anomaly management mechanism is introduced during the system power-on initialization phase, during the recovery of simulated EEPROM data from the simulated EEPROM data blocks to SRAM. This mechanism diagnoses and manages anomalies based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data. This significantly reduces the performance loss associated with hardware implementation of FLASH-based EEPROM and effectively improves the utilization rate of storage resources. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of an existing hardware implementation that uses FLASH to simulate EEPROM;

[0019] Figure 2 This is a schematic diagram of the hardware implementation of a data storage system that uses FLASH to simulate EEPROM in one embodiment;

[0020] Figure 3 This is a schematic diagram illustrating a "ping-pong operation" simulating EEPROM data backup and transfer in one embodiment;

[0021] Figure 4 This is a schematic diagram of the data structure simulating an EEPROM data block in one embodiment;

[0022] Figure 5 This is a schematic diagram of the workflow of a data storage system that uses FLASH to simulate EEPROM in one embodiment;

[0023] Figure 6 This is a flowchart illustrating a data storage management method that uses FLASH to simulate EEPROM in one embodiment. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0025] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in the specification and appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] like Figure 1The diagram illustrates a conventional FLASH-based simulated EEPROM hardware implementation. The overall data access process for the simulated EEPROM is as follows: When the device is powered off, the simulated EEPROM data and its corresponding simulated EEPROM address are stored in the FLASH memory. When the device is powered on, the simulated EEPROM controller first reads the simulated EEPROM data stored in the FLASH memory one by one and, based on its simulated EEPROM address, restores and writes it back to the corresponding simulated EEPROM address space in the SRAM. When an external host performs a read access to the simulated EEPROM, it directly reads the corresponding simulated EEPROM data from the corresponding simulated EEPROM read access address in the SRAM. When an external host performs a write operation to the simulated EEPROM, it first updates the simulated EEPROM write operation address space in the SRAM with the write data. Then, the simulated EEPROM controller, based on whether the current write operation has changed the simulated EEPROM data at the current write operation address, writes the updated simulated EEPROM data and its corresponding simulated EEPROM address together into the corresponding FLASH BANK memory space, so that the simulated EEPROM data can be restored after the device is powered off / on.

[0028] Because FLASH memory has the characteristic that after a write operation, the next write operation can only be performed after the erase operation is completed, the simulated EEPROM controller needs to divide the FLASH storage space into simulated EEPROM data blocks (such as...). Figure 1 The EEPROM controller manages the write and erase operations of FLASH BANK0 to FLASH BANK7. When the current FLASH BANK's storage space is full, if a new simulated EEPROM write operation from an external host is detected, the controller must first erase the next FLASH BANK. Then, it traverses the simulated EEPROM data in the SRAM, backing up and transferring the valid data (not all-binary 1 data; all-binary 1 data is the default data after memory initialization and does not need to be saved) along with its corresponding simulated EEPROM address to the next FLASH BANK's storage space. This allows for simulated EEPROM data recovery after power failure and restoration. Only then can the controller respond to new simulated EEPROM write operations from external hosts, updating the new simulated EEPROM write data to the simulated EEPROM write operation address space in the SRAM, and writing the updated simulated EEPROM data and its corresponding simulated EEPROM address to the corresponding FLASH BANK's storage space for further recovery after power failure and restoration.

[0029] In current hardware designs for implementing FLASH-based EEPROM functionality, a common problem is the "page-turning" phenomenon. This means that after a FLASH sector is fully programmed, time-consuming operations such as erasing sectors and transferring backup data are required before new simulated EEPROM write operations can proceed. This phenomenon makes simulated EEPROM write operations extremely time-consuming and unstable. Furthermore, the larger the amount of valid data in the simulated EEPROM, the more frequent the "page-turning" phenomenon becomes, exacerbating the time-consuming and unstable impact of simulated EEPROM write operations. Simultaneously, most of the FLASH storage space is used to store simulated EEPROM backup data, resulting in low resource utilization.

[0030] Specifically, at the specific operating clock frequency used in the example, the erase operation of the FLASH BANK typically takes milliseconds, and the data write operation of the FLASH BANK typically takes microseconds. However, the time taken for large-scale data write operations will increase exponentially, eventually reaching tens of milliseconds. Therefore, when a "page-turning" phenomenon occurs, the external host's write operation needs to wait for the erase operation of all data blocks (sectors) of the FLASH BANK and the FLASH write operation of all valid simulated EEPROM data to complete. The access latency is enormous, tens or even hundreds of times that of simulated EEPROM write operations during normal operation. As the target simulated EEPROM data capacity increases, more simulated EEPROM data needs to be backed up and transferred with each "page turning" phenomenon, resulting in greater access latency. Furthermore, as the amount of effective data in the simulated EEPROM increases, the remaining available data space in the new FLASH BANK after the "page turning" backup and transfer operation will decrease, making the "page turning" phenomenon more frequent. In extreme cases, when the simulated EEPROM is full of effective data, the storage space utilization of the FLASH BANK may be extremely low, leading to an extreme scenario where every simulated EEPROM write operation triggers the "page turning" phenomenon.

[0031] In one embodiment, such as Figure 2As shown, a data storage system using FLASH to simulate EEPROM is provided, including a simulated EEPROM controller, SRAM, and FLASH memory. The capacity of each simulated EEPROM data block in the FLASH memory is larger than the target simulated EEPROM capacity. The data structure of each simulated EEPROM data block includes a first type of address bits and a second type of address bits. The first type of address bits is used to store the status information of the simulated EEPROM data block, including an erase status flag, a backup status flag, a write status flag, and a transfer status flag. The second type of address bits is used to store the simulated EEPROM data, the simulated EEPROM data address, and the data validity status. When the data space of the simulated EEPROM data block in the current FLASH memory is full and the backup transfer operation of the next simulated EEPROM data block has not been completed, the simulated EEPROM controller performs a backup transfer operation when there is no simulated EEPROM write operation request initiated by an external host. This operation reads the simulated EEPROM data continuously from the SRAM address by address and writes it into the storage space of an empty simulated EEPROM data block in the FLASH memory. When there is a simulated EEPROM write operation request initiated by an external host, the write operation and backup transfer operation corresponding to the simulated EEPROM write operation request initiated by the external host are executed alternately.

[0032] The simulated EEPROM controller is also used for background recycling of simulated EEPROM data blocks that have been filled in the FLASH memory and have not participated in simulated EEPROM data writing or backup transfer operations. During the system power-on initialization phase, the simulated EEPROM controller performs diagnosis and anomaly management based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data when restoring simulated EEPROM data from the simulated EEPROM data blocks to SRAM.

[0033] Understandable. Figure 2 In the diagram, A0 represents the sequential erasure of all FLASH BANKs in the current FLASH memory bank when the data backup and transfer operation of the first FLASH BANK in the next FLASH memory bank is completed. A2 represents FLASH BANK status management, and A3 represents the rotation of FLASH BANK numbers in response to external host simulated EEPROM write operations.

[0034] In this embodiment, a new structure for dividing the storage space of the simulated EEPROM and FLASH BANK is designed, along with a new management and control method for erasing FLASH BANK and backing up and transferring simulated EEPROM data. This aims to minimize the performance loss of simulated EEPROM access caused by the "page turning" phenomenon in existing FLASH simulated EEPROM hardware implementation methods, reduce the low utilization rate of storage space resources as the amount of effective data in the simulated EEPROM increases, and significantly improve the shortcomings of frequent "page turning" phenomena.

[0035] This embodiment improves the partitioning structure of the simulated EEPROM data blocks (FLASH BANK) in the FLASH storage space based on existing FLASH simulated EEPROM hardware implementation methods. Specifically, the capacity of the simulated EEPROM data blocks (FLASH BANK) in the FLASH storage space is changed from being equal to the target simulated EEPROM capacity to being larger than the target simulated EEPROM capacity. For example... Figure 2 Each FLASH BANK has a capacity twice that of the target simulated EEPROM. This improved design ensures that when the simulated EEPROM is full of valid data, even after the FLASH BANK's storage space is occupied by simulated EEPROM data backup and transfer during "page turning," there is still sufficient storage space available for new simulated EEPROM write operations to save new data. This avoids frequent "page turning," effectively preventing the main storage space resources of the FLASH BANK from being wasted on frequent "page turning" for simulated EEPROM data backup and transfer, thus improving resource utilization.

[0036] Next, based on the existing FLASH emulation EEPROM hardware implementation method, the scheme for emulation EEPROM data backup and transfer during "page turning" is improved. Specifically, in this embodiment, when the data space of the emulation EEPROM data block in the current FLASH memory is full and the next emulation EEPROM data block backup and transfer operation has not been completed, when there is no emulation EEPROM write operation request initiated by an external host, the emulation EEPROM data is continuously read from the SRAM address by address and then written into the new (empty) FLASH BANK storage space to complete the emulation EEPROM data backup and transfer operation; when there is an emulation EEPROM write operation request initiated by an external host, the write operation request initiated by the external host needs to perform a write operation on the FLASH BANK, which will conflict with the requirement of the emulation EEPROM data backup operation to perform a write operation on the FLASH BANK. Therefore, the emulation EEPROM data backup and transfer operation is no longer performed continuously, but instead, the write operation requests of these two types of FLASH BANK are handled as follows. Figure 3The "ping-pong operation" management shown refers to the alternation between simulated EEPROM write operations initiated by the external host and simulated EEPROM data backup and transfer operations. Based on the ratio between the FLASH BANK capacity and the target simulated EEPROM capacity, each specific simulated EEPROM data backup and transfer operation is controlled to be executed two or more times. This ensures that the simulated EEPROM data backup and transfer operations are completed as quickly and promptly as possible, avoiding the situation where the FLASH BANK storage space is already full due to simulated EEPROM write operations initiated by the external host before the simulated EEPROM data backup and transfer operation is completed.

[0037] For example, when the FLASH BANK capacity is greater than twice the target simulated EEPROM capacity, the ratio of simulated EEPROM write operations and simulated EEPROM data backup and transfer operations initiated by the external host can be set to 1:1, executed alternately. When the FLASH BANK capacity is less than twice the target simulated EEPROM capacity, the aforementioned ratio needs to be set to 1:2; when the FLASH BANK capacity is less than 1.5 times the target simulated EEPROM capacity, the aforementioned ratio needs to be set to 1:3. The goal is to successfully complete the backup and transfer of all simulated EEPROM data with the maximum effective data volume within a single FLASH BANK. This can be understood as allocating the FLASH BANK capacity according to the aforementioned ratio to the simulated EEPROM write operation data and simulated EEPROM data backup and transfer operation data initiated by the external host. The data space allocated to the simulated EEPROM data backup and transfer operation data must be greater than the capacity of the target simulated EEPROM; otherwise, it will be impossible to complete the backup and transfer of all simulated EEPROM data with the maximum effective data volume within the FLASH BANK.

[0038] By improving the scheme for simulating EEPROM data backup and transfer during "page turning", the huge delay in the existing method, which requires waiting for all simulated EEPROM data backup and transfer to be completed before responding to new external host simulated EEPROM write operations, is distributed across multiple external host simulated EEPROM write operations. In the worst-case scenario, the delay of external host simulated EEPROM write operations is controlled within the total time of several FLASH BANK write operations, based on the actual size of the write operation data.

[0039] The aforementioned data storage system using FLASH to simulate EEPROM significantly improves upon existing FLASH-based EEPROM hardware implementation methods. It utilizes FLASH and SRAM storage devices to design a digital circuit controller that simulates EEPROM functionality. This hardware implementation achieves the simulated EEPROM function. Furthermore, through an improved data storage structure and more refined digital circuit control methods, such as introducing erase, backup, write, and transfer status flags, it employs a "ping-pong" management system to alternately execute internal backup / transfer operations with corresponding write operations from the external host. A "background reclamation" management mechanism is also designed to reclaim simulated EEPROM data blocks in the FLASH memory that are already full and have not participated in simulated EEPROM data writing or backup / transfer operations. Simultaneously, an anomaly management mechanism is introduced during the system power-on initialization phase, when restoring simulated EEPROM data from simulated EEPROM data blocks to SRAM. This mechanism diagnoses and manages anomalies based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data. This significantly reduces the performance loss associated with hardware implementation using FLASH to simulate EEPROM and effectively improves the utilization rate of storage resources.

[0040] In one embodiment, the values ​​of the erase status flag and the backup status flag both include specific valid values, as well as a count value that is initially all 1s and decrements with each update. The values ​​of the write status flag and the transfer status flag both include specific valid values. The erase status flag is used to detect whether the erase status of its associated simulated EEPROM data block is valid. The value of the erase status flag is updated and written by the simulated EEPROM controller immediately after each background recycling and erase of its associated simulated EEPROM data block. The backup status flag is used to locate and determine the associated simulated EEPROM data block that is currently valid for backup. The value of the backup status flag is updated and written by the simulated EEPROM controller when a backup and transfer operation of valid simulated EEPROM data is completed on its associated simulated EEPROM data block. The write status flag is used to determine whether a simulated EEPROM data write operation has been performed on the currently associated simulated EEPROM data block since the last background recycling and erase. The value of the write status flag is written by the simulated EEPROM controller after the previous simulated EEPROM data block is full and before enabling a new simulated EEPROM data block for external host simulated EEPROM data write operations. The transfer status flag is used to determine whether the current simulated EEPROM data block has undergone a backup and transfer operation after the last background recycling and erasure. The value of the transfer status flag is written by the simulated EEPROM controller after the previous simulated EEPROM data block is full, before enabling a new simulated EEPROM data block and performing a backup and transfer operation.

[0041] It is understandable that this embodiment improves the FLASH BANK erasure management method based on existing FLASH emulation EEPROM hardware implementation methods. This embodiment provides a FLASH BANK "background recycling" management mechanism, which can use two or more independent FLASH memory banks (it should be noted that this design can also be applied when using only one FLASH memory bank, but the "background recycling" function cannot be implemented; therefore, when a "page turning" phenomenon occurs, the performance loss due to the delay in waiting for the FLASH memory bank's emulation EEPROM data block erasure operation will be unavoidable). When all FLASH BANKs in the corresponding FLASH memory bank are full and not involved in emulation EEPROM data writing or emulation EEPROM data backup management, the emulation EEPROM controller performs parallel erasure operations. After erasure, "recycling" is achieved, and the FLASH BANK can be reused for FLASH write operations. Since the currently "recycled" FLASH BANK does not participate in the emulation EEPROM function implementation, this background "recycling" operation is performed in parallel with the normal emulation EEPROM function, effectively eliminating the huge performance loss caused by waiting for FLASH BANK erasure operations in existing methods.

[0042] It is understood that this embodiment also provides a new data structure, state management mechanism and exception management mechanism for the FLASH simulated EEPROM data block (FLASH BANK) storage space, enabling the system to cope with the impact of abnormal power loss on the simulated EEPROM function during simulated EEPROM write operations or simulated EEPROM data backup and transfer processes performed by an external host.

[0043] The data structure is optional. In each FLASH memory, the data bit width of the simulated EEPROM data block is at least greater than the sum of the simulated EEPROM address bit width, data bit width, and data validity status information bit width. This is used to store the simulated EEPROM data and its corresponding address information, as well as the data validity status (a specific valid value, which can be set according to usage requirements). For example... Figure 4 As shown, the storage space of 4 addresses (referred to as first-class address bits, and correspondingly, the remaining address bits are referred to as second-class address bits (in some implementations, the first-class address bits are, for example, but not limited to, the first 4 address bits of the simulated EEPROM data block)) in each FLASH BANK is used to store the status information of the FLASH BANK, including erase status flag, backup status flag, write status flag and transfer status flag.

[0044] Status Management Mechanism: Based on the control requirements of the simulated EEPROM, four status flags are defined for each FLASH BANK: erase status flag, backup status flag, write status flag, and transfer status flag. The erase and backup status flags are composed of a specific valid value and a counter value that is initially all 1s and decrements with each update. The write and transfer status flags are also specific valid values.

[0045] The erase status flag is used to detect whether the erase status is valid: the control logic ensures that the count values ​​of the erase status flags of each FLASH BANK are continuous and their differences are not too large. The erase status flag is updated and written immediately after each FLASH BANK "background recycling" erase is completed.

[0046] The backup status flag is used to locate and determine the currently valid FLASH BANK for backup: the FLASH BANK with the smallest backup status flag count contains valid analog EEPROM data. This data is then combined with the write status flag of the next FLASH BANK to determine if it also contains valid analog EEPROM data. During system power-on initialization, the recovery of analog EEPROM data can begin from the currently used FLASH BANK. The backup status flag is updated and written when all valid data in the analog EEPROM has been backed up and transferred.

[0047] The write status flag is used to determine whether the current FLASH BANK has undergone a simulated EEPROM data write operation since the last "background recycling" erase. Combined with the backup status flag of the previous FLASH BANK, it can be determined whether the current FLASH BANK contains valid simulated EEPROM data. A valid value is written to the write status flag after the previous FLASH BANK is full, and before a new FLASH BANK is started to perform simulated EEPROM data write operations on the external host.

[0048] The transfer status flag is used to determine whether a simulated EEPROM data backup and transfer operation has been performed on the current FLASH BANK since the last "background recycling" erase. This helps in determining the status of the simulated EEPROM data backup. A valid value is written to the transfer status flag after the previous FLASH BANK is full, before a new FLASH BANK is enabled and a simulated EEPROM data backup and transfer operation is performed.

[0049] Anomaly management mechanism: During the system power-on initialization phase, when restoring simulated EEPROM data from FLASH BANK to SRAM, the status flags of all FLASH BANKs and the backed-up simulated EEPROM data are first diagnosed. If an anomaly is detected, it will be reported.

[0050] Because a power outage during FLASH writing can lead to data errors, these anomalies can be categorized into two main types: The first type is minor anomalies (power-off anomalies): These occur when a power outage occurs during the writing process, causing errors in the FLASH BANK status flag or the simulated EEPROM data. In this case, only the data from the last simulated EEPROM write operation is lost; the remaining data can still be recovered. The second type is severe anomalies: These occur when a power outage during the writing process detects errors in the FLASH BANK status flag or the simulated EEPROM data that do not conform to the system's established standard flow control logic. This type of anomaly indicates that the simulated EEPROM data is unreliable or that the simulated EEPROM function is malfunctioning and unusable.

[0051] In one embodiment, when the simulated EEPROM controller performs diagnostics and anomaly management, if a minor anomaly is detected, the simulated EEPROM controller performs an emergency recovery operation or an emergency backup operation based on the anomaly diagnosis status flag. A minor anomaly is a situation where the status flag of a simulated EEPROM data block is detected during system power-on or a power outage occurs during the writing of simulated EEPROM data, resulting in an abnormality in the status flag or simulated EEPROM data.

[0052] Specifically, if a minor anomaly is detected, the analog EEPROM controller will perform the following operations based on the specific diagnosis: (1) "Emergency Recycling" operation: Perform an "emergency recycling" erase operation on the FLASH BANK whose erase status flag is diagnosed as abnormal. (2) "Emergency Backup" operation: Restore the analog EEPROM data from the FLASH BANK to the SRAM, erase all other FLASH BANKs that do not store valid analog EEPROM data, and urgently back up and transfer the analog EEPROM data from the SRAM to a new FLASH BANK. After all the analog EEPROM data has been urgently backed up and transferred, it will be put back into use.

[0053] In one embodiment, when the simulated EEPROM controller performs diagnostics and anomaly management, if a serious anomaly is detected, the simulated EEPROM controller reports the corresponding diagnostic information. A serious anomaly is defined as a situation where, during system power-up, the status flag bit of the simulated EEPROM data block is detected, or the simulated EEPROM data contains information that does not conform to the system's standard flow control logic.

[0054] It is understandable that if a serious anomaly is detected, the simulated EEPROM controller will report the corresponding diagnostic information for the serious anomaly.

[0055] In one embodiment, when the simulated EEPROM controller performs diagnostics and anomaly management, if two or more simulated EEPROM data blocks have abnormal erase states, a critical anomaly is reported. If only one simulated EEPROM data block has an abnormal erase state and the count value of the erase state flag bit of the adjacent previous simulated EEPROM data block is not the minimum value, a critical anomaly is reported. If only one simulated EEPROM data block has an abnormal erase state and the count value of the erase state flag bit of the adjacent previous simulated EEPROM data block is the minimum value, a power-down anomaly is reported, and an emergency recovery operation is performed on the simulated EEPROM data block with the abnormal erase state. If no simulated EEPROM data blocks have abnormal erase states, or only one simulated EEPROM data block has an abnormal erase state, and the difference between the maximum and minimum count values ​​of the erase state flag bits of all valid simulated EEPROM data blocks is greater than or equal to a set value, a critical anomaly is reported. For example, Figure 2 In the example shown, when using 4 FLASH BANKs, this setting can be 4, meaning the setting can be selected as the number of FLASH BANKs used.

[0056] Understandable, with Figure 2 Taking the system structure of the four FLASH BANKs shown as an example, the specific diagnostic content of the exception management mechanism is introduced:

[0057] The abnormal diagnosis process for the erase status flag bit includes: (1) If there are two or more FLASH BANKs with abnormal erase status, a serious abnormality is reported. (2) If there is only one FLASH BANK with abnormal erase status and the count value of the erase status flag bit of its previous FLASH BANK is not the minimum value, a serious abnormality is reported. (3) If there is only one FLASH BANK with abnormal erase status and the count value of the erase status flag bit of its previous FLASH BANK is the minimum value, a power failure abnormality is reported and an "emergency recovery" operation is performed. (4) If there are no FLASH BANKs with abnormal erase status or only one FLASH BANK with abnormal erase status, and the difference between the maximum and minimum count values ​​of the erase status flag bits of all valid FLASH BANKs (i.e., FLASH BANKs with no abnormal erase status) is greater than or equal to 4, a serious abnormality is reported. (5) If there are no abnormalities as described above, it is normal.

[0058] In one embodiment, when the simulated EEPROM controller performs diagnostics and anomaly management, if it detects that no simulated EEPROM data block has a valid backup status, a serious anomaly is reported. If three or more simulated EEPROM data blocks have abnormal backup statuses, a serious anomaly is reported. If two simulated EEPROM data blocks have abnormal backup statuses, and the previous simulated EEPROM data block whose current backup status flag count is at its minimum value also has an abnormal backup status, a serious anomaly is reported. If two simulated EEPROM data blocks have abnormal backup statuses, and the previous simulated EEPROM data block whose current backup status flag count is at its minimum value also has a valid backup status, a power failure anomaly is reported, and an emergency backup operation is performed. If only one simulated EEPROM data block has an abnormal backup status, and the simulated EEPROM data block with the abnormal backup status is neither the previous nor the next simulated EEPROM data block whose current backup status flag count is at its minimum value, a serious anomaly is reported. If only one simulated EEPROM data block has an abnormal backup status, and that simulated EEPROM data block is the preceding or following simulated EEPROM data block whose current backup status flag count is at its minimum, a power failure anomaly is reported and an "emergency backup" operation is performed. If the write status flag or transfer status flag of the simulated EEPROM data block whose current backup status flag count is at its minimum is invalid, a serious anomaly is reported.

[0059] Specifically, the abnormal diagnosis process for the backup status flag bit includes: (1) If no FLASH BANK has a valid backup status, a serious abnormality is reported. (2) If three or more FLASH BANKs have abnormal backup statuses, a serious abnormality is reported. (3) If two FLASH BANKs have abnormal backup statuses and the previous FLASH BANK with the current backup status flag bit count of the minimum value has an abnormal backup status, a serious abnormality is reported. (4) If two FLASH BANKs have abnormal backup statuses and the previous FLASH BANK with the current backup status flag bit count of the minimum value has a valid backup status, a power failure abnormality is reported and an "emergency backup" operation is performed. (5) If only one FLASH BANK has an abnormal backup status, and this FLASH BANK is not the previous or next FLASH BANK of the FLASH BANK with the current backup status flag bit count of the minimum value, a serious abnormality is reported. (6) If only one FLASH BANK has an abnormal backup status, and that FLASH BANK is the previous or next FLASH BANK of the FLASH BANK whose current backup status flag count is the minimum, then a power failure abnormality is reported, and an "emergency backup" operation is performed. (7) If the write status flag or transfer status flag of the FLASH BANK whose current backup status flag count is the minimum is invalid, then a serious abnormality is reported. (8) If there are no abnormalities as described above, then it is normal.

[0060] In one embodiment, when a simulated EEPROM data block with the minimum count value of the current backup status flag is determined to be a valid backup simulated EEPROM data block, if the currently valid backup simulated EEPROM data block is not full, the simulated EEPROM controller performs data recovery and inspection from the currently valid backup simulated EEPROM data block. If the currently valid backup simulated EEPROM data block is full, and the write status flag or transfer status flag of the next simulated EEPROM data block is not the default value after the erase operation, the simulated EEPROM controller reports a power failure and performs an emergency backup operation. If the currently valid backup simulated EEPROM data block is full, and the write status flag of the next simulated EEPROM data block is the default value after the erase operation, the simulated EEPROM controller performs data recovery and inspection from the currently valid backup simulated EEPROM data block. During the simulated EEPROM data recovery process, the simulated EEPROM controller traverses all data spaces of the valid backup simulated EEPROM data blocks and checks the data validity status. If there is a phenomenon where only the last valid address data is abnormal, the simulated EEPROM controller reports a power failure and performs an emergency backup operation. If there is a phenomenon where data is abnormal at addresses other than the last valid address, the simulated EEPROM controller reports a serious abnormality.

[0061] Specifically, when determining that the FLASH BANK with the minimum count value of the current backup status flag is the valid backup FLASH BANK, the process of diagnosing the simulated EEPROM data stored in its backup includes: (1) If the current valid backup FLASH BANK is not full, then only data recovery and inspection need to be performed from the current valid backup FLASH BANK. (2) If the current valid backup FLASH BANK is full, and the write status flag or transfer status flag of the next FLASH BANK is the default value after the non-erase operation (binary all 1), then it indicates that the next FLASH BANK may have experienced an abnormal power failure during the simulated EEPROM data backup and transfer process. At this time, the valid backup FLASH BANK contains the next FLASH BANK, and the simulated EEPROM controller needs to report the power failure abnormality and perform an "emergency backup" operation. (3) If the current valid backup FLASH BANK is full, and the write status flag of the next FLASH BANK is the default value after the erase operation (binary all 1), then only data recovery and inspection need to be performed from the current valid backup FLASH BANK. (4) During the simulated EEPROM data recovery process, all data spaces of the valid backup FLASH BANK are traversed and the data validity status is checked. If there is a phenomenon where only the last valid address data is abnormal (the data of subsequent addresses are all default values ​​after the erase operation (binary all 1)), the simulated EEPROM controller reports a power failure and performs an "emergency backup" operation; if there is a phenomenon where there is not the last valid address data abnormal, the simulated EEPROM controller reports a serious abnormality.

[0062] like Figure 5 The diagram illustrates the workflow of a data storage system that uses FLASH to simulate EEPROM. This improved design has been verified through extensive EDA (Electronic Design Automation) tool simulations and FPGA prototype verification. The simulation results are consistent with the design expectations. Compared with traditional hardware implementation methods, it greatly amortizes the performance loss caused by the "page turning" phenomenon, making the "page turning" phenomenon almost imperceptible. This significantly reduces the low resource utilization caused by frequent "page turning" when the effective data volume of the simulated EEPROM increases.

[0063] In one embodiment, a data storage management method using FLASH to simulate EEPROM is provided, applied to the aforementioned data storage system using FLASH to simulate EEPROM, such as... Figure 6 As shown, the data storage management method using FLASH to simulate EEPROM described above may include the following steps S10 to S16:

[0064] S10, when the data space of the simulated EEPROM data block in the current FLASH memory is full and the backup transfer operation of the next simulated EEPROM data block has not been completed, in the absence of a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller performs a backup transfer operation that continuously reads the simulated EEPROM data from the SRAM address by address and writes it into the storage space of the empty simulated EEPROM data block in the FLASH memory.

[0065] S12, when the data space of the simulated EEPROM data block in the current FLASH storage is full and the backup and transfer operation of the next simulated EEPROM data block has not been completed, when there is a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller alternately executes the write operation and backup and transfer operation corresponding to the simulated EEPROM write operation request initiated by the external host.

[0066] S14, the simulated EEPROM data blocks in the FLASH memory that have been filled and have not participated in the simulated EEPROM data writing or backup transfer operation are recycled in the background by the simulated EEPROM controller.

[0067] S16, during the process of restoring the simulated EEPROM data from the simulated EEPROM data block to SRAM during the system power-on initialization phase, diagnosis and anomaly management are performed based on the status information of the simulated EEPROM data block and the backed-up simulated EEPROM data.

[0068] The aforementioned data storage management method using FLASH to simulate EEPROM significantly improves upon existing FLASH-based EEPROM hardware implementations. It utilizes FLASH and SRAM storage devices to design a digital circuit controller that simulates EEPROM functionality. This hardware implementation achieves the simulated EEPROM function. Furthermore, through an improved data storage structure and more refined digital circuit control methods, such as introducing erase, backup, write, and transfer status flags, it employs a "ping-pong" management system to alternately execute internal backup / transfer operations with corresponding write operations from the external host. A "background reclamation" management mechanism is also designed to reclaim simulated EEPROM data blocks in the FLASH memory that are already full and have not participated in simulated EEPROM data writing or backup / transfer operations. Simultaneously, an anomaly management mechanism is introduced during the system power-on initialization phase, when restoring simulated EEPROM data from simulated EEPROM data blocks to SRAM. This mechanism diagnoses and manages anomalies based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data. This significantly reduces the performance loss associated with hardware implementations using FLASH to simulate EEPROM and effectively improves the utilization rate of storage resources.

[0069] For specific limitations on the data storage management method of using FLASH to simulate EEPROM, please refer to the corresponding limitations of the data storage system using FLASH to simulate EEPROM mentioned above, which will not be repeated here.

[0070] It should be understood that, although Figure 6 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 6 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0071] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented in hardware through digital integrated circuit design or FPGA digital circuit design, etc. When the digital integrated circuit is working, the processes including the embodiments of the above methods can be implemented. Any references to memory, storage, database, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A data storage system using FLASH to simulate EEPROM, characterized in that, This includes an analog EEPROM controller, SRAM, and FLASH memory. The capacity of each simulated EEPROM data block in the FLASH memory is greater than the target simulated EEPROM capacity. The data structure of each simulated EEPROM data block includes a first type of address bits and a second type of address bits. The first type of address bits is used to store the status information of the simulated EEPROM data block, including erase status flag, backup status flag, write status flag and transfer status flag. The second type of address bits is used to store the simulated EEPROM data, the simulated EEPROM data address and the data validity status. When the simulated EEPROM data block space in the current FLASH memory is full and the backup transfer operation of the next simulated EEPROM data block is not completed, the simulated EEPROM controller performs a backup transfer operation in which simulated EEPROM data is continuously read from SRAM address by address and written into the storage space of an empty simulated EEPROM data block in the FLASH memory when there is no simulated EEPROM write operation request initiated by an external host. When there is a simulated EEPROM write operation request initiated by an external host, the write operation corresponding to the simulated EEPROM write operation request initiated by the external host is executed alternately with the backup transfer operation. The simulated EEPROM controller is also used to perform background recycling of simulated EEPROM data blocks that have been filled in the FLASH memory and have not participated in simulated EEPROM data writing or backup transfer operations. During the process of restoring simulated EEPROM data from the simulated EEPROM data blocks to SRAM during the system power-on initialization phase, the simulated EEPROM controller performs diagnosis and anomaly management based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data.

2. The data storage system using FLASH to simulate EEPROM according to claim 1, characterized in that, The values ​​of the erase status flag and the backup status flag both include specific valid values, as well as a count value that is initially all 1s and decrements with each update. The values ​​of the write status flag and the transfer status flag both include specific valid values. The erase status flag is used to detect whether the erase status of the corresponding analog EEPROM data block is valid. The value of the erase status flag is updated and written by the analog EEPROM controller immediately after each background recycling and erasure of the corresponding analog EEPROM data block. The backup status flag is used to find and determine the simulated EEPROM data block to which the current backup is valid. The value of the backup status flag is updated and written by the simulated EEPROM controller when the backup and transfer operation of valid simulated EEPROM data is completed on the corresponding simulated EEPROM data block. The write status flag is used to determine whether the current simulated EEPROM data block has been written to after the last background recycling and erasure. The value of the write status flag is written by the simulated EEPROM controller after the previous simulated EEPROM data block is full and before enabling a new simulated EEPROM data block to perform simulated EEPROM data writing operations on the external host. The transfer status flag is used to determine whether the current simulated EEPROM data block has undergone a backup and transfer operation after the last background recycling and erasure. The value of the transfer status flag is written by the simulated EEPROM controller after the previous simulated EEPROM data block is full, before enabling a new simulated EEPROM data block and performing a backup and transfer operation on the simulated EEPROM data.

3. The data storage system using FLASH to simulate EEPROM according to claim 1 or 2, characterized in that, When the simulated EEPROM controller performs diagnosis and anomaly management, if a minor anomaly is detected, the simulated EEPROM controller performs an emergency recovery operation or an emergency backup operation based on the anomaly diagnosis based on the status flag bit. The minor anomaly refers to a situation where the status flag of the simulated EEPROM data block is detected during system power-on or a power failure occurs during the writing of simulated EEPROM data, resulting in an abnormality in the status flag or simulated EEPROM data.

4. The data storage system using FLASH to simulate EEPROM according to claim 3, characterized in that, When the simulated EEPROM controller performs diagnosis and anomaly management, if a serious anomaly is detected, the simulated EEPROM controller reports the diagnostic information corresponding to the serious anomaly. The serious anomaly is a situation where, during system power-up, the status flag bit of the simulated EEPROM data block is detected, or the simulated EEPROM data does not conform to the system's standard flow control logic.

5. The data storage system using FLASH to simulate EEPROM according to claim 4, characterized in that, When the simulated EEPROM controller performs diagnosis and anomaly management, if there are two or more simulated EEPROM data blocks with abnormal erase status, a serious anomaly will be reported. If only one simulated EEPROM data block has an abnormal erase status and the count value of the erase status flag bit of the adjacent previous simulated EEPROM data block is not the minimum value, then a serious abnormality is reported. If only one simulated EEPROM data block has an abnormal erase status and the count value of the erase status flag bit of the adjacent simulated EEPROM data block is the minimum value, then a power failure is reported and an emergency recovery operation is performed on the simulated EEPROM data block with the abnormal erase status. If there is no abnormal erase status of the simulated EEPROM data block or only one abnormal erase status of the simulated EEPROM data block, and the difference between the maximum and minimum values ​​of the count values ​​of the erase status flag bits of all valid simulated EEPROM data blocks is greater than or equal to the set value, then a serious abnormality is reported.

6. The data storage system using FLASH to simulate EEPROM according to claim 4, characterized in that, When the simulated EEPROM controller performs diagnosis and anomaly management, if it detects that no simulated EEPROM data block has a valid backup status in all simulated EEPROM data blocks, it will report a serious anomaly. If three or more simulated EEPROM data blocks have abnormal backup status, a serious anomaly should be reported. If there are two simulated EEPROM data blocks with abnormal backup status, and the previous simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag has an abnormal backup status, then a serious abnormality should be reported. If there are two simulated EEPROM data blocks with abnormal backup status, and the backup status of the previous simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag is valid, then a power failure abnormality is reported and an emergency backup operation is performed. If there is only one simulated EEPROM data block with an abnormal backup status, and the simulated EEPROM data block with the abnormal backup status is not the previous or next simulated EEPROM data block of the simulated EEPROM data block with the minimum current backup status flag count, then a serious abnormality is reported. If there is only one simulated EEPROM data block with an abnormal backup status, and the simulated EEPROM data block with the abnormal backup status is the previous or next simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag bit, then a power failure abnormality is reported and an "emergency backup" operation is performed. If the write status flag or transfer status flag of the simulated EEPROM data block whose current backup status flag count is at its minimum value is invalid, a serious anomaly will be reported.

7. The data storage system using FLASH to simulate EEPROM according to claim 4, characterized in that, When a simulated EEPROM data block whose current backup status flag count is at its minimum is determined to be a valid backup simulated EEPROM data block, if the current valid backup simulated EEPROM data block is not full, the simulated EEPROM controller performs data recovery and inspection from the current valid backup simulated EEPROM data block. If the current valid backup simulated EEPROM data block is full, and the write status flag or transfer status flag of the next simulated EEPROM data block is not the default value after the erase operation, then the simulated EEPROM controller reports a power failure and performs an emergency backup operation. If the current valid backup simulated EEPROM data block is full, and the write status flag of the next simulated EEPROM data block is the default value after the erase operation, then the simulated EEPROM controller performs data recovery and inspection from the current valid backup simulated EEPROM data block. During the simulated EEPROM data recovery process, the simulated EEPROM controller traverses all data spaces of the valid backup simulated EEPROM data blocks and checks the data validity status. If there is a phenomenon where only the last valid address data is abnormal, the simulated EEPROM controller reports a power failure and performs an emergency backup operation. If there is a phenomenon where data is abnormal at addresses other than the last valid address, the simulated EEPROM controller reports a serious abnormality.

8. The data storage system using FLASH to simulate EEPROM according to claim 3, characterized in that, The first type of address bits is the first 4 address bits of the simulated EEPROM data block.

9. The data storage system using FLASH to simulate EEPROM according to claim 3, characterized in that, In each of the FLASH memory blocks, the data bit width of the simulated EEPROM data block is at least greater than the sum of the simulated EEPROM address bit width, data bit width, and data valid status information bit width.

10. A data storage management method using FLASH to simulate EEPROM, characterized in that, The data storage management method for using FLASH to simulate EEPROM, applicable to any one of claims 1 to 9, comprises the following steps: When the data space of the simulated EEPROM data block in the current FLASH memory is full and the backup transfer operation of the next simulated EEPROM data block has not been completed, in the absence of a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller performs a backup transfer operation that continuously reads the simulated EEPROM data from the SRAM address by address and writes it into the storage space of the empty simulated EEPROM data block in the FLASH memory. When the data space of the simulated EEPROM data block in the current FLASH storage is full and the backup and transfer operation of the next simulated EEPROM data block has not been completed, when there is a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller alternately executes the write operation corresponding to the simulated EEPROM write operation request initiated by the external host and the backup and transfer operation. The simulated EEPROM controller performs background recycling of simulated EEPROM data blocks that have been filled in the FLASH memory and have not participated in simulated EEPROM data writing or backup transfer operations. During the system power-on initialization phase, when restoring simulated EEPROM data from the simulated EEPROM data block to SRAM, diagnosis and anomaly management are performed based on the status information of the simulated EEPROM data block and the backed-up simulated EEPROM data.

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