Dynamic instruction conversion memory access optimization method based on data pre-alignment

Abstract

The invention discloses a dynamic instruction conversion memory access optimization method based on data pre-alignment, which comprises the following steps of: pre-constructing a memory mapping table of a mapping relationship from an x86-segment base address to an ARM page table base address in an ARM system, and when an executable file is loaded and executed in a dynamic instruction conversion mode, establishing a data information table; obtaining initialized and uninitialized global variables and static variables, respectively establishing a first variable table and a second variable table, and completing instruction conversion and static pre-alignment of instructions and variables for the statically distributed memory according to the memory mapping table, the data information table, the first variable table and the second variable table; for the dynamically distributed memory, instruction conversion and dynamic pre-alignment of instructions and variables are completed according to a memory mapping table, and finally, related instructions are combined into batch data transmission instructions based on address continuity of a memory space to further optimize memory access, so that memory access optimization during instruction conversion is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to a dynamic instruction conversion memory access optimization method based on data pre-alignment. Background Art

[0002] When dynamically converting x86 programs to ARM multi-core systems for execution, memory access efficiency becomes one of the key factors affecting program execution performance. Since x86 systems and ARM systems have significant differences in memory access mode, memory layout, and instruction execution methods, when programs run across architectures, they will have poor performance or even failures due to low memory access efficiency. Summary of the invention

[0003] In view of this, the present invention provides a dynamic instruction conversion memory access optimization method based on data pre-alignment, which realizes efficient memory access when running programs across architectures in a dynamic instruction conversion manner.

[0004] The present invention provides a method for optimizing memory access by dynamic instruction conversion based on data pre-alignment, which specifically comprises the following steps: Step 1: Build a memory mapping table from the x86 segment base address to the ARM page table base address in the ARM system, load and execute the executable file through dynamic instruction conversion, form a first variable table by initialized variables in global variables and static variables, and form a second variable table by uninitialized variables; establish a data information table to save the instruction name and variable name and the corresponding ARM start address, data length and aligned ARM target address; Step 2: parse the current instruction to be converted to obtain the x86 segment base address and the offset address within the x86 segment corresponding to the instruction and operand. If there is a corresponding entry in the memory mapping table, obtain the ARM page table base address; otherwise, assign the ARM page table base address to the x86 segment base address and add it to the memory mapping table; Step 3: Calculate the ARM start address of the instruction and variable according to the ARM page table base address and the offset address in the x86 segment. If the corresponding ARM target address exists in the data information table, execute step 4. If there is a corresponding table entry, execute step 5. Otherwise, execute step 6. Step 4: When the variable belongs to the first variable table, the instruction and the variable alignment operation are executed according to the ARM target address, and the initial value of the variable is copied to the aligned buffer in sequence; when it belongs to the second variable table, the instruction alignment operation is executed; the current instruction to be converted is converted into an ARM instruction with the same function using the ARM target address as the operand; Step 5, calculate the ARM target address of the instruction and variable and save it to the data information table, convert the current instruction to be converted into an ARM instruction with the same function using the ARM target address as an operand; Step 6: Construct a first ARM instruction for checking whether the variable address is aligned, a second ARM instruction with the result of the first ARM instruction as a jump condition, and a third ARM instruction with address alignment, and convert the current instruction to be converted into an ARM instruction sequence consisting of an ARM instruction with the same function, the first ARM instruction, the second ARM instruction, and the third ARM instruction.

[0005] Furthermore, the memory mapping table is stored in a memory space with lower access latency in the ARM system.

[0006] Furthermore, the table entries of the memory mapping table are represented as 64-bit data, wherein the lower 32 bits store the ARM page table base address and the upper 32 bits store the x86 segment base address.

[0007] Furthermore, it also includes: taking the instructions within the backward setting range of the converted ARM instructions or ARM instruction sequence as the instruction optimization area, if there are multiple memory data transfer instructions with continuous memory space as operands in the instruction optimization area, then merging these memory data transfer instructions into instructions for batch data transfer to the continuous memory space; otherwise, the instructions in the instruction optimization area are kept unchanged.

[0008] Furthermore, it also includes: adding a data prefetch instruction before the converted ARM instruction or ARM instruction sequence.

[0009] Furthermore, it also includes: when the ARM system captures a data abort exception and the exception address corresponds to data in the first variable table or the second variable table, the ARM start address and data length in the exception information are saved in the data information table, and then the execution of the program is terminated.

[0010] Furthermore, when the executable file has a complete symbol table, the data information table is constructed before the executable file is loaded and executed.

[0011] Furthermore, the memory space with lower access latency is obtained in the following manner: Step 1.1, initialize the SysTick timer to generate an interrupt every 1ms; Step 1.2, perform multiple memory read and write operations on the addresses in the memory space under test with the set value as the step length, calculate the number of clock cycles consumed by the operation by recording the value of the SysTick timer before and after the operation, and obtain the access time; Step 1.3: The address with the shortest access time is the starting address of the memory space with lower access latency.

[0012] Furthermore, the memory space with lower access latency is a tightly coupled memory. Beneficial Effects

[0013] The present invention pre-builds a memory mapping table of the mapping relationship between the x86 segment base address and the ARM page table base address in the ARM system, establishes a data information table when loading and executing an executable file in a dynamic instruction conversion mode, obtains initialized and uninitialized global variables and static variables to respectively establish a first variable table and a second variable table, completes instruction conversion and static pre-alignment of instructions and variables for statically allocated memory according to the memory mapping table, the data information table, the first variable table and the second variable table, completes instruction conversion and dynamic pre-alignment of instructions and variables for dynamically allocated memory according to the memory mapping table, and finally merges related instructions into batch data transmission instructions based on the address continuity of the memory space to further optimize memory access, thereby realizing memory access optimization while performing instruction conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic flow chart of a method for optimizing dynamic instruction conversion and memory access based on data pre-alignment provided by the present invention. DETAILED DESCRIPTION

[0015] The present invention is described in detail below with reference to the accompanying drawings and with reference to the embodiments.

[0016] The invention provides a dynamic instruction conversion memory access optimization method based on data pre-alignment, the core idea of ​​which is: pre-building a memory mapping table of the mapping relationship between an x86 segment base address and an ARM page table base address in an ARM system, establishing a data information table when loading and executing an executable file in a dynamic instruction conversion mode, acquiring initialized and uninitialized global variables and static variables to respectively establish a first variable table and a second variable table, completing instruction conversion and static pre-alignment of instructions and variables for statically allocated memory according to the memory mapping table, the data information table, the first variable table and the second variable table, completing instruction conversion and dynamic pre-alignment of instructions and variables for dynamically allocated memory according to the memory mapping table, and finally merging related instructions into batch data transmission instructions based on the address continuity of the memory space to further optimize memory access, thereby realizing memory access optimization while performing instruction conversion.

[0017] The present invention provides a method for optimizing dynamic instruction conversion memory access based on data pre-alignment, the specific process is as follows: Figure 1 As shown, the specific steps include: Step 1: Pre-build a memory mapping table in the ARM system to implement the mapping of the x86 segment base address to the ARM page table base address, and save the memory mapping table in a memory space with lower access latency in the ARM system.

[0018] Among them, the table entries of the memory mapping table can be represented by 64-bit data, the lower 32 bits are used to save the ARM page table base address, and the upper 32 bits are used to save the x86 segment base address, thereby realizing the simulation of the logical segment memory management method in the x86 architecture in the ARM system.

[0019] Specifically, the memory space with lower access latency in the ARM system is obtained by executing the constructed access time test program. The execution process of the access time test program includes: Step 1.1, initialize the SysTick timer to generate an interrupt every 1ms; Step 1.2, perform multiple memory read and write operations on the addresses in the memory space under test with the set value as the step length, calculate the number of clock cycles consumed by the operation by recording the value of the SysTick timer before and after the operation, and obtain the access time; Step 1.3: The address with the shortest access time is the starting address of the memory space with lower access latency in the ARM system.

[0020] Step 2: Load and execute the executable file through dynamic instruction conversion in the ARM system, obtain the initialized global variables and static variables in the executable file to establish a first variable table, obtain the uninitialized global variables and static variables therein to establish a second variable table; establish a data information table to save the instruction name and its ARM start address, data length and aligned ARM target address, as well as the variable name and its ARM start address, data length and aligned ARM target address, wherein the ARM start address and the ARM target address are both ARM virtual addresses.

[0021] If the executable file has a complete symbol table, the data information table can be constructed before the executable file is loaded and executed.

[0022] Step 3, obtain the current instruction to be converted, parse the x86 segment base address and the offset address within the x86 segment corresponding to the instruction and operand of the current instruction to be converted, use the obtained x86 segment base address to search in the memory mapping table, if there is a table entry containing the x86 segment base address, obtain the ARM page table base address corresponding to the x86 segment base address; otherwise, assign a new ARM page table base address to the x86 segment base address, and add the mapping relationship between the x86 segment base address and the ARM page table base address to the memory mapping table.

[0023] In the x86 architecture, the address where instructions are stored is related to the system's working mode and the program's memory layout. Usually, instructions are stored in the address range corresponding to the code segment. For example, in the real mode, a simple segmented memory management is used. The memory is divided into multiple logical segments, each segment is identified by a segment register, and the code segment is pointed to by the code segment register CS. The CS register stores the upper 16 bits of the segment base address, and the default lower 4 bits are 0. The base address of the code segment can be obtained by shifting the CS value left by 4 bits (equivalent to multiplying by 16). The offset address of the instruction is provided by the instruction pointer register IP. The physical address of the instruction in the memory can be determined by the combination of CS and IP.

[0024] The storage address of the operand depends on the type of operand, the system's operating mode, and the specific needs of the program. For example, in the real mode, the data segment is pointed to by the data segment register DS. DS stores the upper 16 bits of the segment base address, and the lower 4 bits default to 0. The base address of the data segment can be obtained by shifting the value of DS left by 4 bits. Most common data operands are stored in the data segment by default, and the physical address of the operand can be located by combining DS with the offset address within the segment.

[0025] Step 4. According to the ARM page table base address and the offset address in the x86 segment obtained in step 3, calculate the ARM starting address of the instruction and variable in the current instruction to be converted; according to the instruction name and its ARM starting address, the variable name and its ARM starting address, find out whether there is a corresponding table entry in the data information table. If so, it means that the variable is a statically allocated variable, and when the ARM target address exists in the table entry, execute step 5; when the ARM target address does not exist in the table entry, execute step 6; otherwise, it means that the variable is a dynamically allocated variable and execute step 7.

[0026] Step 5, read the ARM target address of the instruction and the ARM target address of the variable, when the variable belongs to the first variable table, perform the alignment operation of the instruction and the variable according to the ARM target address of the instruction and the variable, and then copy the initial value of the variable to the aligned buffer according to the corresponding ARM target address execution order; when the variable belongs to the second variable table, only perform the alignment operation of the instruction according to the ARM target address of the instruction; convert the current instruction to be converted into an ARM instruction with the same function using the ARM target address as the operand, and then execute step 8.

[0027] Step 6: According to the ARM starting addresses of the instructions and variables in the current instruction to be converted, the alignment addresses of the instructions and variables are calculated as the ARM target addresses respectively, and the instruction name and variable name and their corresponding ARM starting address, data length and ARM target address are saved in the data information table. After the current instruction to be converted is converted into an ARM instruction with the same function and the ARM target address as the operand, step 8 is executed.

[0028] In order to further improve the reliability of instruction conversion execution, the present invention adds an exception handling mechanism. When the ARM system captures a data termination exception and the exception address corresponds to data in the first variable table or the second variable table, the ARM starting address and data length in the exception information are saved in the data information table, and then the execution of the program is terminated.

[0029] Step 7, construct a calculation instruction for checking whether the variable address is aligned, record it as the first ARM instruction, construct a jump instruction based on the result of the first ARM instruction, record it as the second ARM instruction, construct an instruction group for address alignment, record it as the third ARM instruction, and convert the current instruction to be converted into an ARM instruction sequence consisting of an ARM instruction with the same function, the first ARM instruction, the second ARM instruction and the third ARM instruction.

[0030] Step 8: The instructions in the backward setting range of the converted ARM instructions or ARM instruction sequences are used as the instruction optimization area. If there are multiple memory data transfer instructions with continuous memory space as operands in the instruction optimization area, these memory data transfer instructions are merged into instructions for batch data transfer to the continuous memory space; otherwise, the instructions in the instruction optimization area are kept unchanged.

[0031] In order to further reduce memory access latency, the present invention can also add a data prefetch instruction before the converted ARM instruction or ARM instruction sequence to prefetch memory data that may need to be processed by the ARM instruction or ARM instruction sequence into the cache in advance.

[0032] Step 9: If the executable file is executed and the conversion is completed, then the process ends; otherwise, proceed to step 3. Example

[0033] In this embodiment, a dynamic instruction conversion memory access optimization method based on data pre-alignment provided by the present invention is adopted to achieve optimized execution of an x86 architecture executable file on an ARM system, including the following steps: S1. Establish and dynamically update the memory mapping table during the instruction conversion process to ensure the effective conversion of memory addresses. The specific steps are as follows: S1.1. Build the basic architecture of memory mapping table. In ARM system, in order to realize the memory address conversion from x86 to ARM, a memory mapping table is created.

[0034] S1.2. Save the memory mapping table in the tightly coupled memory (TCM).

[0035] Because the memory mapping table will be accessed frequently, it is necessary to create a memory mapping table in a specific area of ​​the memory to improve the access performance of the memory mapping table. Tightly-Coupled Memory (TCM) is tightly connected to the CPU, has extremely low access latency, and can complete data read and write operations within one clock cycle. It is usually used to store code and data with extremely high real-time requirements. By measuring the memory access latency, it is judged that the access latency of the memory space is significantly lower, even nearly an order of magnitude lower. In order to accurately measure the latency, the SysTick timer is used for measurement in this embodiment.

[0036] The sample code is as follows: / / Define test parameters #defineTEST_LOOPS10000 #defineTEST_ADDRESS_START0x00000000 #defineTEST_ADDRESS_END0x40000000 #defineTEST_STEP0x1000 / / Initialize SysTick timer voidSysTick_Init(void){ SysTick->LOAD=SystemCoreClock / 1000-1 / / / / 1ms interruption SysTick->VAL=0 / / SysTick->CTRL=SysTick_CTRL_CLKSOURCE_Msk|SysTick_CTRL_ENABLE_Msk / / } / / Read the value of the SysTick timer uint32_tSysTick_Read(void){ returnSysTick->VAL / / } / / Measure memory access time uint32_tmeasure_access_time(uint32_taddress){ uint32_tstart_time,end_time / / volatileuint32_t*ptr=(volatileuint32_t*)address / / start_time = SysTick_Read() / / for(int i = 0 / / i <TEST_LOOPS / / i++){ *ptr=i / / / / write operation volatileuint32_ttemp=*ptr / / / / Read operation } end_time = SysTick_Read() / / if(end_time>start_time){ return(SysTick->LOAD+1)-(end_time-start_time) / / }else{ returnstart_time-end_time / / } } intmain(void){ SysTick_Init() / / uint32_tmin_time = UINT32_MAX / / uint32_ttcm_address = 0 / / for(uint32_taddress=TEST_ADDRESS_START / / address <TEST_ADDRESS_END / / address+=TEST_STEP){ uint32_ttime=measure_access_time(address) / / if(time <min_time){ min_time=time / / tcm_address=address / / } } / / Output possible TCM addresses printf("Possible TCM starting address: 0x%08X\n",tcm_address) / / while(1){ / / Main loop } } The specific steps include: S1.2.1, SysTick timer initialization: SysTick_Init function is used to initialize the SysTick timer so that it generates an interrupt every 1ms.

[0037] S1.2.2, Measure memory access time: measure_access_time function is used to measure the time taken to perform multiple memory read and write operations on a specified address. By recording the value of the SysTick timer before and after the operation, the number of clock cycles consumed by the operation is calculated.

[0038] S1.2.3. Traverse the address range: In the main function, start from TEST_ADDRESS_START, traverse to TEST_ADDRESS_END with TEST_STEP as the step size, and call the measure_access_time function to measure each address.

[0039] S1.2.4. Find the fastest access address: record the minimum access time min_time and the corresponding address tcm_address, which is the starting address of TCM (recorded as TCM_START_ADDRESS).

[0040] S1.3 is completed in the kernel. The kernel's memory address page table (TLB) is searched for an area within the TCM memory range that is unallocated and has a data length that meets the requirements of the memory mapping table. If such an area exists, a TLB page table entry is constructed in the kernel, and the physical address of this page table entry points to this area. The virtual address is used as the user-state address of the memory mapping table. If such an area does not exist, a normal memory allocation function is called in user mode to allocate the memory mapping table.

[0041] Each entry in the memory map table contains the mapping information between the x86 segment base address and the corresponding ARM page table base address. The following is a sample of some assembly code to create and initialize the memory map table: LDRr0,=0x80000000 / / Assume that the x86 segment base address is stored in r1 and the ARM target physical address is stored in r2 STRr1,[r0] STRr2,[r0,#4] S2. Dynamically update the memory mapping table. When a new x86 segment base address is encountered during runtime, the memory mapping table needs to be dynamically updated. The update process can be implemented through the search and update functions. First, check whether the mapping of the x86 segment base address already exists in the memory mapping table. If not, a new ARM page table base address is allocated and added to the memory mapping table; if it exists, the corresponding ARM page table base address is updated considering the possible address relocation. The following is an assembly code example for searching and updating the memory mapping table: / / r3 stores the x86 segment base address to be found LDRr0,=0x80000000 lookup_loop: LDRr4,[r0] CMPr4,r3 BEQfound ADDr0,r0,#8 BNElookup_loop / / Not found, assign new ARM physical address / / Assume that r5 is used to store the newly allocated ARM physical address STRr3,[r0] STRr5,[r0,#4] Bdone Found: / / Found, can update / / Assume that the updated ARM physical address is r6 STRr6,[r0,#4] done: Existing address conversion methods may only use simple linear mapping or fixed offset mapping, which lacks flexibility. The memory mapping table in the present invention adopts a dynamic update mechanism, which can flexibly adjust the mapping relationship according to the actual needs of the program when it is running, support more complex memory management scenarios, and improve the adaptability and scalability of memory address conversion. At the same time, the memory mapping table is stored in an independent memory area and adopts a specific data structure, which is convenient for management and updating.

[0042] S3: Perform static pre-alignment and dynamic runtime alignment on memory data to ensure the alignment of memory access. The specific steps are as follows: S3.1. Static pre-alignment.

[0043] The .data segment of the ELF file is used to store initialized global variables and static variables, and the .bss segment stores uninitialized global variables and static variables.

[0044] At the beginning of dynamic instruction conversion, for known global data and static data, memory alignment is performed on initialized global data and static data based on the data information table, and address offset processing is performed on the corresponding instructions. For uninitialized global data and static data, only address offset processing is performed on the corresponding instructions. The specific steps are as follows: S3.1.1, when the program is loaded, if the program has a complete symbol table, the data information table is constructed based on the symbol table. If the data information table is not empty, execute S3.1.2, otherwise execute S3.1.3.

[0045] S3.1.2. Align the data in the .data or .bss segment based on the data information table. The specific steps are as follows: Perform alignment processing on initialized global data and static data, and record the target address to the corresponding item. Then, copy the initialized data recorded in the data information table to the aligned buffer in the alignment order. Perform alignment processing on uninitialized global data and static data, and only need to record the target address to the corresponding item.

[0046] S3.1.3. If the operand of the current instruction to be converted is data in the .data or .bss segment, the corresponding aligned address is searched in the data information table according to the original offset of the data; if found, the operand is changed to the aligned address. If not found, an alignment exception may occur during execution.

[0047] If a data abort exception (DataAbortException) is captured and the exception address is data in the .data or .bss segment, the starting address and data length in the exception information are recorded in the data information table and the program execution ends.

[0048] S3.2. Dynamic runtime alignment.

[0049] For memory dynamically allocated at runtime, dynamic alignment checking and adjustment is performed on each memory access. When using the LDR or STR instruction, the AND instruction is used to check whether the address is aligned. If it is not aligned, the address is adjusted. In addition, for unaligned memory access, padding or reorganization operations can be used to ensure aligned access. The following is an assembly code example for dynamic runtime alignment: / / Assume that the data address is stored in r4 LDRr5,[r4] / / Check if it is 4-byte aligned ANDr6,r4,#0x3 CMPr6,#0 BN Eunaligned / / Address has been aligned, continue processing Bdone unaligned: / / Misaligned, adjust ADDr4,r4,#4 LDRr5,[r4] / / Handle unaligned data, which may need to be reorganized according to the data type / / Assuming the data is a 32-bit integer, you can combine the front and back bytes LDRBr7,[r4,#-1] LDRBr8,[r4,#-2] LDRBr9,[r4,#-3] LSLr7,r7,#24 LSLr8,r8,#16 LSLr9,r9,#8 ORRr5,r5,r7 ORRr5,r5,r8 ORRr5,r5,r9 done: Different from the existing methods that only perform memory alignment processing at compile time, the dynamic runtime alignment method of the present invention can handle the alignment problem of dynamically allocated memory at runtime. At the same time, it combines data reorganization technology to effectively handle the access of misaligned data, avoid the performance overhead caused by misalignment, and ensure the efficiency of memory access and data integrity.

[0050] S4. Based on pre-alignment, optimize memory access instructions, select the optimal instructions and perform pre-fetch optimization.

[0051] When converting x86 memory access instructions to ARM instructions, for continuous memory access, traverse the memory start address and data length accessed by continuous LDR / STR instructions. If the concatenation results in a continuous address space, merge the memory areas accessed by continuous LDR / STR instructions, and use LDM and STM instructions to load and store data in batches, rather than using LDR and STR instructions multiple times. The following is an assembly code example for batch data processing using LDM and STM: / / Assume that the data address range to be loaded starts from r0 and the data length is 16 bytes LDMr0,{r1-r4} / / Store data STMr5,{r6-r9} For different data types and sizes, choose appropriate load and store instructions, such as LDRB for bytes, LDRH for halfwords, and LDR for words.

[0052] S5. Prefetch optimization.

[0053] Use ARM's prefetch instructions (such as PLD) to prefetch the memory data that may be accessed into the cache in advance. According to the program's execution flow and branch prediction information, predict future memory accesses and prefetch data to reduce memory access latency. The following is an assembly code example of prefetch optimization: / / Assume that the next address to be accessed is stored in r10 PLD[r10] / / Subsequent execution code LDRr11,[r10] Existing instruction conversions often only focus on the basic function conversion of instructions, while the present invention selects the best instruction combination according to the characteristics of the ARM architecture through instruction selection optimization, thereby improving the parallelism of memory access and data transmission efficiency. At the same time, the introduction of prefetch optimization makes it possible to actively reduce memory access latency and utilize the prefetch function of the ARM core to improve overall performance.

[0054] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic instruction conversion memory access optimization method based on data pre-alignment, characterized in that: The specific steps include: Step 1: Build a memory mapping table from the x86 segment base address to the ARM page table base address in the ARM system, load and execute the executable file through dynamic instruction conversion, form a first variable table by initialized variables in global variables and static variables, and form a second variable table by uninitialized variables; establish a data information table to save the instruction name and variable name and the corresponding ARM start address, data length and aligned ARM target address; Step 2: parse the current instruction to be converted to obtain the x86 segment base address and the offset address within the x86 segment corresponding to the instruction and operand. If there is a corresponding entry in the memory mapping table, obtain the ARM page table base address; otherwise, assign the ARM page table base address to the x86 segment base address and add it to the memory mapping table; Step 3: Calculate the ARM start address of the instruction and variable according to the ARM page table base address and the offset address in the x86 segment. If the corresponding ARM target address exists in the data information table, execute step 4. If there is a corresponding table entry, execute step 5. Otherwise, execute step 6. Step 4: When the variable belongs to the first variable table, the instruction and the variable alignment operation are executed according to the ARM target address, and the initial value of the variable is copied to the aligned buffer in sequence; When belonging to the second variable table, an instruction alignment operation is performed; the current instruction to be converted is converted into an ARM instruction with the same function and the ARM target address as an operand; Step 5, calculate the ARM target address of the instruction and variable and save it to the data information table, convert the current instruction to be converted into an ARM instruction with the same function using the ARM target address as an operand; Step 6: Construct a first ARM instruction for checking whether the variable address is aligned, a second ARM instruction with the result of the first ARM instruction as a jump condition, and a third ARM instruction with address alignment, and convert the current instruction to be converted into an ARM instruction sequence consisting of an ARM instruction with the same function, the first ARM instruction, the second ARM instruction, and the third ARM instruction.

2. The dynamic instruction conversion memory access optimization method according to claim 1, characterized in that: The memory mapping table is stored in a memory space with lower access latency in the ARM system.

3. The dynamic instruction conversion memory access optimization method according to claim 1, characterized in that: The table entries of the memory mapping table are represented as 64-bit data, wherein the lower 32 bits store the ARM page table base address and the upper 32 bits store the x86 segment base address.

4. The dynamic instruction conversion memory access optimization method according to claim 1, characterized in that: Also includes: The instructions in the backward setting range of the converted ARM instructions or ARM instruction sequences are taken as the instruction optimization area. If there are multiple memory data transfer instructions with continuous memory space as operands in the instruction optimization area, these memory data transfer instructions are merged into instructions for batch data transfer to the continuous memory space; otherwise, the instructions in the instruction optimization area are kept unchanged.

5. The dynamic instruction conversion memory access optimization method according to claim 1, characterized in that: Also includes: A data prefetch instruction is added before the converted ARM instruction or ARM instruction sequence.

6. The dynamic instruction conversion memory access optimization method according to claim 1, characterized in that: Also includes: When the ARM system captures a data abort exception and the exception address corresponds to data in the first variable table or the second variable table, the ARM start address and data length in the exception information are saved in the data information table, and then the execution of the program ends.

7. The dynamic instruction conversion memory access optimization method according to claim 1, characterized in that: When the executable file has a complete symbol table, the data information table is built before the executable file is loaded and executed.

8. The dynamic instruction conversion memory access optimization method according to claim 2, characterized in that: The memory space with lower access latency is obtained as follows: Step 1.1, initialize the SysTick timer to generate an interrupt every 1ms; Step 1.2, perform multiple memory read and write operations on the addresses in the memory space under test with the set value as the step length, calculate the number of clock cycles consumed by the operation by recording the value of the SysTick timer before and after the operation, and obtain the access time; Step 1.3: The address with the shortest access time is the starting address of the memory space with lower access latency.

9. The dynamic instruction conversion memory access optimization method according to claim 8, characterized in that: The memory space with lower access latency is a tightly coupled memory.

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