Task allocation method and related device

Abstract

The invention discloses a task allocation method and a related device, is applied to a bare ARM processor carrying a plurality of kernels, and belongs to the technical field of task processing.The method comprises the steps that a target interrupt request which is sent by a PC terminal and carries at least one task needing to be processed by the kernels is received; placing a task carried by the target interrupt request into a corresponding task queue; and sequentially distributing the tasks in the task queue to different idle kernels for processing. By applying the embodiment of the invention, the working efficiency of the ARM processor can be improved.

Description

Technical Field

[0001] The present application belongs to the field of task processing technology, and in particular to a task allocation method and related devices. Background Art

[0002] ARM processors are a series of 32-bit and 64-bit RISC (Reduced Instruction Set Computing) processors, which are widely used in embedded systems, mobile devices, smart phones, tablet computers, digital televisions, automotive electronics, network equipment and other fields.

[0003] In order to improve the efficiency of task processing, multiple cores are installed on the ARM processor to process tasks in parallel. In the case of multiple cores, the task processing is generally scheduled by the operating system added to the ARM processor. For example, the LINUX operating system is transplanted on the ARM processor, and the LINUX system uses multi-threading to manage multiple cores. Because the LINUX system is relatively large, it will cause the task processing speed to slow down, which will affect the performance of the ARM processing and greatly reduce the work efficiency of the ARM processor. Summary of the invention

[0004] The purpose of this application is to provide a task allocation method and related devices, aiming to improve the working efficiency of ARM processors.

[0005] An embodiment of the present application provides a task allocation method, which is applied to a bare metal ARM processor equipped with multiple cores, and the method includes:

[0006] Receive a target interrupt request from the PC carrying at least one task to be processed by the kernel;

[0007] Put the task carried by the target interrupt request into the corresponding task queue;

[0008] The tasks in the task queue are assigned to different idle cores for processing in turn.

[0009] Optionally, when there is an interrupt request being processed when the target interrupt request is received, the method further includes:

[0010] determining whether the priority of the target interrupt request is higher than the priority of the interrupt request being processed;

[0011] If it is higher, the interrupt request being processed will be suspended.

[0012] Optionally, if the priority of the target interrupt request is not higher than the priority of the interrupt request being processed, the method further includes:

[0013] The target interrupt request is suspended, and the interrupt request being processed continues to be processed.

[0014] Optionally, the target interrupt request also includes a task to be processed by an ARM processor;

[0015] Before placing the task carried by the target interrupt request into the corresponding task queue, the method further includes:

[0016] Handles tasks that require an ARM processor.

[0017] Optionally, sequentially allocating tasks in the task queue to different cores in an idle state for processing includes:

[0018] Check whether the target task queue is empty;

[0019] If it is not empty, determine whether there is an idle core executing the task in the target task queue;

[0020] If there is an idle core, the task in the target task queue is assigned to the idle core for processing;

[0021] If it is empty, another task queue is used as the target task queue, and the step of querying whether the target task queue is empty is returned to execute until other interrupt requests are received, task allocation of all task queues is completed, or there is no core to be allocated.

[0022] Optionally, after allocating the tasks in the task queue to the idle cores for processing, the method further includes:

[0023] The state of the core to which the task is assigned is set to the working state.

[0024] Optionally, when an interrupt request from the kernel is received, the method further includes:

[0025] Receive the task processing result sent by the core that sends the interrupt request;

[0026] Set the state of the core that sends the interrupt request to the idle state.

[0027] Another embodiment of the present application provides a task allocation device, which is applied to a bare metal ARM processor equipped with multiple cores, and the device includes:

[0028] A receiving module, used for receiving a target interrupt request sent by a PC and carrying at least one task to be processed by the kernel;

[0029] A processing module, used for placing the task carried by the target interrupt request into a corresponding task queue;

[0030] The allocation module is used to sequentially allocate tasks in the task queue to different idle cores for processing.

[0031] Yet another embodiment of the present application provides a computer-readable storage medium, wherein at least one computer program is stored in the computer-readable storage medium, and when the at least one computer program is executed by an ARM processor, the method described in any of the aforementioned embodiments can be implemented.

[0032] Compared with the prior art, the present application provides a task allocation method, which can first receive a target interrupt request sent by a PC and carrying at least one task that needs to be processed by the kernel; then put the task carried by the target interrupt request into a corresponding task queue; and then sequentially allocate the tasks in the task queue to different idle kernels for processing.

[0033] Compared with the prior art that uses an operating system to perform multi-threaded parallel operations, this solution does not carry an operating system, and assigns tasks to corresponding idle cores in a serial manner. There is no need to wait for feedback from the cores to which tasks have been assigned, and multiple core calls are processed using a multi-tasking method plus an interrupt mode. Multi-core calls can be solved without using an operating system, which can better improve the real-time and performance of ARM core processing, and will not cause unnecessary waste of memory resources, thereby improving the working efficiency of the ARM processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A flowchart of a task allocation method provided in an embodiment of the present application;

[0035] Figure 2 A structural diagram of a task allocation device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0037] The task allocation method provided in the embodiment of the present application is applied to a bare metal ARM processor, which is an ARM processor without an operating system. The bare metal ARM processor is an ARM processor that is directly programmed and controlled at the hardware level. Because the bare metal ARM processor does not have the additional overhead of the operating system, the ARM processor can quickly start from the power-off state and immediately start executing the program, thereby achieving fast startup, while eliminating the licensing fees and maintenance costs of the operating system. The bare metal ARM processor allows developers to customize hardware and software according to specific application requirements, thereby achieving highly optimized system performance. The bare metal ARM processor reduces potential security vulnerabilities because it does not have an operating system. From simple microcontroller applications to complex embedded systems, bare metal ARM processors can provide suitable solutions. The tasks mentioned in this application can be classical computing tasks or quantum computing tasks, and specifically can be tasks related to quantum encryption and decryption. It should be noted that the bare metal ARM processor in this application is equipped with multiple cores.

[0038] See also Figure 1 , Figure 1 A task allocation method provided in an embodiment of the present application comprises the following steps:

[0039] S201: Receive a target interrupt request sent by a PC and carrying at least one task to be processed by the kernel.

[0040] The ARM processor will receive interrupt requests sent by the PC and the kernel. The target interrupt request is an interrupt request that carries at least one task that needs to be processed by the kernel. In this application, the ARM processor handles these interrupt requests through the interrupt vector table. When an interrupt occurs, the processor jumps to the corresponding interrupt handler for execution. Each interrupt type has its specific purpose and processing method to ensure the stability and responsiveness of the system.

[0041] S202: Put the task carried by the target interrupt request into a corresponding task queue.

[0042] The ARM processor identifies the type of task carried in the target interrupt request and then places the task into a task queue of the corresponding type.

[0043] S203: Allocate the tasks in the task queue to different idle cores for processing in sequence.

[0044] Since the ARM processor is a bare metal, it cannot allocate tasks in parallel, but can only allocate tasks in series. It should be noted that in the embodiment of the present application, after the ARM processor assigns a task to a core for processing, it does not need to wait for the core to feedback information, but directly allocates the next task.

[0045] As an implementation of the embodiment of the present application, sequentially allocating tasks in the task queue to different cores in an idle state for processing may include:

[0046] Check whether the target task queue is empty;

[0047] If it is not empty, determine whether there is an idle core executing the task in the target task queue;

[0048] If there is an idle core, the task in the target task queue is assigned to the idle core for processing;

[0049] If it is empty, another task queue is used as the target task queue, and the step of querying whether the target task queue is empty is returned to execute until other interrupt requests are received, task allocation of all task queues is completed, or there is no core to be allocated.

[0050] ARM processors can assign tasks according to task queues, first assigning tasks in one task queue and then assigning tasks in another task queue. When assigning tasks, a task queue can be randomly selected as the target task queue, or the target task queue can be determined in a pre-set order, or the task queue with the most or least tasks can be selected as the target task queue. When setting task priorities, the target task queue can be determined according to the priority level. Of course, there can be other ways to determine the target task queue, which are not listed here one by one.

[0051] After determining the target task queue, first query whether the target task queue is empty, if it is empty, indicating that there is no task waiting to be processed in the target task queue, then determine a new target task queue, if it is not empty, then determine whether there is an idle kernel to execute the task in the target task queue, if there is an idle kernel, then send the task in the target task queue to the idle kernel for execution. It should be noted that if the number of idle kernels is less than the number of tasks in the target task queue, the tasks in the target task queue are sent to the idle kernels in sequence until there is no idle kernel to process the tasks in the target task queue, and then determine a new target task queue. In the embodiment of the present application, one kernel can process tasks in multiple task queues.

[0052] Exemplarily, the ARM processor is used to process encryption and decryption tasks as an example. The task queue includes a symmetric encryption and decryption task queue, an asymmetric encryption and decryption task queue, and a signature verification task queue. The asymmetric encryption and decryption task queue is now used as the target task queue. The target task queue is queried to see if it is empty. If it is empty, the symmetric encryption and decryption task queue is used as the target task queue; if it is not empty, the kernel that executes the tasks in the target task queue is queried to see if it is idle. If it exists, the tasks in the target task queue are sequentially assigned to the idle kernels until the corresponding kernels are all in working state, and then the symmetric encryption and decryption task queue is used as the target task queue; if it does not exist, the symmetric encryption and decryption task queue is directly used as the target task queue. After the signature verification task queue is assigned, if no interrupt request is received, the next round of target task queue determination and task assignment operations are performed.

[0053] As an implementation of the embodiment of the present application, in the case where there is an interrupt request being processed when the target interrupt request is received, the method may further include:

[0054] determining whether the priority of the target interrupt request is higher than the priority of the interrupt request being processed;

[0055] If it is higher, the interrupt request being processed will be suspended.

[0056] Different priorities are set for different interrupt requests. The ARM processor will first process the interrupt request with a higher priority, suspend the interrupt request being processed, and save the current execution context (including the program counter and other key registers) for later restoration. Then, the ARM processor will find the corresponding interrupt service routine (ISR) entry address according to the interrupt vector table and jump to the address to start execution. The ARM processor executes specific code to handle interrupt requests with higher priority, which usually involves reading the status register, clearing the interrupt flag, and performing necessary operations to handle the target interrupt request. Once the interrupt request is properly handled, the ISR will execute the return instruction, restore the previously saved register value from the stack, and return control to the interrupted program to continue executing the original interrupt request. In this way, the ARM processor can effectively manage multiple interrupt requests, ensuring that the system can respond to various internal and external events in a timely manner while maintaining efficient computing performance.

[0057] As an implementation of the embodiment of the present application, if the priority of the target interrupt request is not higher than the priority of the interrupt request being processed, the method further includes:

[0058] The target interrupt request is suspended, and the interrupt request being processed continues to be processed.

[0059] When the priority of the target interrupt request is the same as the priority of the interrupt request currently being processed, or lower than the priority of the interrupt request currently being processed, the target interrupt request needs to be suspended. Suspension is in the ARM processor. When an interrupt request has occurred but has not been processed, the interrupt request is in a waiting state until the interrupt request currently being processed is completed. When the interrupt request is suspended, the interrupt request will be recorded in the suspension register of the interrupt controller and wait for processing when the processor is idle. In addition to priority issues, the reason for the suspension of interrupt requests may also be resource conflicts. When resource conflicts occur: when system resources (such as interrupt controllers) are busy, new interrupt requests may also be suspended to avoid resource competition. Interrupt suspension is a management mechanism for ARM processors when processing multiple interrupt requests. Through reasonable configuration and optimization, the real-time performance and stability of the system can be effectively improved.

[0060] As an implementation method of the embodiment of the present application, the target interrupt request also includes a task that needs to be processed by the ARM processor;

[0061] Before placing the task carried by the target interrupt request into the corresponding task queue, the method further includes:

[0062] Handles tasks that require an ARM processor.

[0063] The target interrupt request can include tasks that need to be processed by the ARM processor. Such tasks are relatively simple, have a relatively fast processing speed, and occupy relatively few resources. Compared with handing them over to the kernel for processing, processing by the ARM processor saves more resources and is more efficient. When the ARM processor decomposes the tasks carried by the target interrupt request, it can identify such tasks, and the ARM processor directly processes them and feeds back the processing results to the PC. Taking the ARM processor as an example of a processor used for encryption, the target interrupt request includes symmetric encryption and decryption tasks, asymmetric encryption and decryption tasks, random number generation tasks, and signature verification tasks. The random number generation task is a task processed by the ARM processor, and the ARM processor can directly feed back the generated random number to the PC.

[0064] As an implementation manner of the embodiment of the present application, after assigning the tasks in the task queue to the idle cores for processing, the method further includes:

[0065] The state of the core to which the task is assigned is set to the working state.

[0066] As an implementation of the embodiment of the present application, when an interrupt request is received from the kernel, the method further includes:

[0067] Receive the task processing result sent by the core that sends the interrupt request;

[0068] Set the state of the core that sends the interrupt request to the idle state.

[0069] The state of the kernel indicates whether the kernel is processing a task. After assigning a task, the state of the kernel to which the task is assigned is set to the working state. In this way, no other tasks will be assigned to the kernel during the kernel's processing of the task, which can reduce the waiting time of the task and make rational use of resources. After the task processing is completed, the kernel state is set to the idle state, at which time the kernel can process tasks. By managing the state of the kernel, the ARM processor can more easily determine whether a task can be assigned.

[0070] Compared with the prior art that uses an operating system to perform multi-threaded parallel operations, this solution does not carry an operating system, and assigns tasks to corresponding idle cores in a serial manner. There is no need to wait for feedback from the cores to which tasks have been assigned, and multiple core calls are processed using a multi-tasking method plus an interrupt mode. Multi-core calls can be solved without using an operating system, which can better improve the real-time and performance of ARM core processing, and will not cause unnecessary waste of memory resources, thereby improving the working efficiency of the ARM processor.

[0071] See also Figure 2 , Figure 2 A task allocation device provided in an embodiment of the present application is applied to a bare metal ARM processor equipped with multiple cores, and the device may include:

[0072] The receiving module 201 is used to receive a target interrupt request sent by the PC and carrying at least one task to be processed by the kernel;

[0073] The processing module 202 is used to put the task carried by the target interrupt request into a corresponding task queue;

[0074] The allocation module 203 is used to allocate the tasks in the task queue to different idle cores for processing in sequence.

[0075] Regarding the specific functions and effects achieved by the above-mentioned task allocation device, reference can be made to other embodiments of the present application for comparative explanation, and no further description is given here. Each module in the task allocation device can be implemented in whole or in part by software, hardware, and a combination thereof. Each module can be embedded in or independent of an ARM processor in the form of hardware, or can be stored in a memory in the form of software, so that the ARM processor can call and execute the operations corresponding to the above modules.

[0076] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores at least one computer program, and when the at least one computer program is executed by an ARM processor, the task allocation method in any embodiment can be implemented.

[0077] The embodiments of the present application also provide a computer program product including instructions, which, when executed by a computer, enables the computer to execute the task allocation method in any of the above embodiments.

[0078] It can be understood that in the various implementations of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present application.

[0079] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0080] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0081] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0082] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0083] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0084] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0086] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0087] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A task allocation method, applied to a bare metal ARM processor equipped with multiple cores, characterized in that: The method comprises: Receive a target interrupt request from the PC carrying at least one task to be processed by the kernel; Put the task carried by the target interrupt request into the corresponding task queue; The tasks in the task queue are assigned to different idle cores for processing in turn.

2. The method according to claim 1, characterized in that In the case that there is an interrupt request being processed when the target interrupt request is received, the method further includes: determining whether the priority of the target interrupt request is higher than the priority of the interrupt request being processed; If it is higher, the interrupt request being processed will be suspended.

3. The method according to claim 2, characterized in that If the priority of the target interrupt request is not higher than the priority of the interrupt request being processed, the method further includes: The target interrupt request is suspended, and the interrupt request being processed continues to be processed.

4. The method according to claim 1, characterized in that The target interrupt request also includes tasks that need to be processed by the ARM processor; Before placing the task carried by the target interrupt request into the corresponding task queue, the method further includes: Handles tasks that require an ARM processor.

5. The method according to claim 1, characterized in that The step of sequentially allocating tasks in the task queue to different cores in an idle state for processing includes: Check whether the target task queue is empty; If it is not empty, determine whether there is an idle core executing the task in the target task queue; If there is an idle core, the task in the target task queue is assigned to the idle core for processing; If it is empty, another task queue is used as the target task queue, and the step of querying whether the target task queue is empty is returned to execute until other interrupt requests are received, task allocation of all task queues is completed, or there is no core to be allocated.

6. The method according to claim 5, characterized in that After assigning the tasks in the task queue to the idle cores for processing, the method further includes: The state of the core to which the task is assigned is set to the working state.

7. The method according to claim 1, characterized in that When an interrupt request is received from the kernel, the method further comprises: Receive the task processing result sent by the core that sends the interrupt request; Set the state of the core that sends the interrupt request to the idle state.

8. A task allocation device, applied to a bare metal ARM processor equipped with multiple cores, characterized in that: The device comprises: A receiving module, used for receiving a target interrupt request sent by a PC and carrying at least one task to be processed by the kernel; A processing module, used for placing the task carried by the target interrupt request into a corresponding task queue; The allocation module is used to allocate tasks in the task queue to different idle cores for processing in turn.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and when the at least one computer program is executed by an ARM processor, it can implement the method according to any one of claims 1 to 7.

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