A multi-task processing system for fanless industrial computers

Abstract

The present invention relates to the technical field of industrial control computers, and provides a multi-task processing system for a fanless industrial control computer. An aluminum alloy heat dissipation backplane is used to install an embedded industrial control mainboard, a memory group, and an I / O interface board, and to interconnect with the bus of the industrial control mainboard through a PCle bus; a multi-core processor and a scheduler connected to the multi-core processor are embedded on the industrial control mainboard; when the industrial control task is a multi-threaded task, the industrial control task is transmitted to multiple processing cores of the multi-core processor through the scheduler, and a unique memory is configured for each processing core in the memory group to perform multi-task parallel processing; when the industrial control task is a single-threaded task, the industrial control task is transmitted to a ready task queue through the scheduler, and the CPU authority of the multi-core processor is configured to the corresponding single-threaded task; the power supply module is respectively connected to the industrial control mainboard and the I / O interface board, and supplies power.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial computer control, and in particular to a multi-task processing system of a fanless industrial computer. Background Art

[0002] With the advancement of Industry 4.0, fanless industrial computers have gradually become core equipment in the field of intelligent manufacturing due to their low noise, high reliability and adaptability to harsh environments. However, in complex multi-tasking scenarios, traditional fanless industrial computers face the following technical bottlenecks:

[0003] Traditional industrial computers often have problems such as heat dissipation, insufficient multi-tasking capabilities, and poor real-time performance.

[0004] For example, although existing solutions improve stability through fanless design, their task scheduling still relies on fixed priority or simple polling mechanism, which makes it difficult to cope with the real-time requirements of dynamic industrial tasks (such as AGV navigation and robot arm control in parallel). Although some industrial computers (M60C series industrial computers) have introduced AI models to optimize data processing, they have not solved the delay problem caused by resource competition between tasks. For example, synchronous tasks lack hardware-level isolation mechanism, which is easy to cause bus conflicts.

[0005] Fanless industrial computers rely on passive cooling technology (such as heat pipes and heat sinks), but in high-load multi-tasking scenarios, the fixed power supply mode of the traditional static power allocation strategy will lead to the risk of local overheating, and the core temperature difference can reach ±10°C, affecting the life of the chip. Although low-power processors (such as Intel Atom) can reduce heat generation, the lack of dynamic power adjustment mechanism when tasks are interrupted makes it difficult to break through the energy efficiency ratio (TOPS / W).

[0006] Industrial tasks often require multi-protocol communication (such as EtherCAT wired control and 5G remote monitoring in parallel), but existing equipment uses a fixed interface power supply mode and cannot dynamically switch the power supply of communication components according to the task type, resulting in energy waste. Although some existing solutions support operation in a wide temperature environment, they do not realize the linkage between communication mode recognition and power supply strategy, resulting in limited endurance in mobile scenarios (such as AGV).

[0007] Traditional solutions focus on hardware heat dissipation and lack the guarantee of atomic execution of synchronous tasks. For example, emergency shutdown instructions may be delayed due to asynchronous tasks preempting resources, violating safety standards. Summary of the invention

[0008] The present invention proposes a multi-task processing system for a fanless industrial computer, which is used to solve the problems that the industrial computers in the prior art systems often have heat dissipation problems, insufficient multi-task processing capabilities, poor real-time performance and other problems.

[0009] In a first aspect, a multi-task processing system of a fanless industrial computer is provided, which is applied to the industrial computer and includes:

[0010] Aluminum alloy heat dissipation backplane, used to install embedded industrial control motherboard, memory group, I / O interface board, and interconnect with the bus of industrial control motherboard for PCle bus;

[0011] The industrial control motherboard is embedded with a multi-core processor and a scheduler connected to the multi-core processor;

[0012] Among them, the scheduler is also interconnected with the memory group and the I / O interface board;

[0013] The I / O interface board is used to receive industrial control tasks and determine whether the industrial control tasks are multi-threaded tasks or single-threaded tasks;

[0014] When the industrial control task is a multi-threaded task, the industrial control task is transmitted to multiple processing cores of the multi-core processor through the scheduler, and a unique memory is configured for each processing core in the memory group to perform multi-task parallel processing;

[0015] When the industrial control task is a single-threaded task, the industrial control task is transferred to the ready task queue through the scheduler, and the CPU authority of the multi-core processor is configured to the corresponding single-threaded task;

[0016] The power supply module is respectively connected to the industrial control main board and the I / O interface board to provide power.

[0017] In combination with the first aspect, the memory group includes a plurality of memories and a sequence buffer; wherein each physical storage element in the memory generates a plurality of storage units based on a preset unit storage amount, and each storage unit has a unique identifier;

[0018] When receiving the assigned task from the scheduler, responding to the industrial control task, and determining the storage capacity occupied by the task data to be written corresponding to the industrial control task;

[0019] By using the storage capacity, any uniquely indicated storage unit in any free memory is used as the initial storage address;

[0020] According to the initial storage address, the free storage units in the current memory are queued and sorted to generate a storage sequence corresponding to the industrial control task.

[0021] In combination with the first aspect, the industrial control mainboard further includes a plurality of hardware detection devices, wherein the hardware detection steps are as follows:

[0022] Pre-configure a monitoring period and collect first operation data within the monitoring period; wherein the first operation data includes environmental sensing data and operation status data;

[0023] According to the detection cycle, the first operation data is generated according to the cycle timing to generate a detection sequence, and the detection sequence is stored in a sequence buffer; wherein the sequence buffer is electrically connected to a preset host server through an I / O interface board, and the sequence memory includes a first cache layer and a second cache layer;

[0024] According to the sequence buffer, storing time data of the detection sequence in a first cache layer and storing detection data in a second cache layer;

[0025] Obtain the detection sequence of the next detection cycle, and compare the data with the first cache layer and the second cache layer respectively to determine whether there is data anomaly;

[0026] When there is data anomaly, extract the time data and detection data corresponding to the abnormal data, and extract the abnormal features;

[0027] Generate abnormal status prompt information based on abnormal characteristics.

[0028] In combination with the first aspect, the scheduler further includes:

[0029] The process scheduler is used to determine the task execution sequence and generate the task execution process when receiving industrial tasks;

[0030] AI model manager, which is used to receive input data and configure execution flow interfaces for different input data according to the task execution process;

[0031] The executor is used to determine whether there is a synchronous task in the industrial task according to the execution flow interface; wherein,

[0032] When there is a synchronization task, execute the stream synchronization task block;

[0033] When there is no synchronization task, a single task block is generated;

[0034] The run manager is used to return the execution result according to the synchronous task block / single task block.

[0035] In combination with the first aspect, the I / O interface board is configured with a CAN communication component; wherein the CAN communication component includes a CAN transceiver and a multi-channel digital isolator; wherein,

[0036] Multi-channel digital isolators are used to separate multiple tasks issued by the host computer.

[0037] In combination with the first aspect, the I / O interface board is also configured with a task counting clock; wherein the counting process is as follows:

[0038] Initialize the clock module on the I / O interface board;

[0039] According to the clock module, clear the interrupt flag and initialize the interrupt vector table;

[0040] After initializing the interrupt vector table, when an industrial task is received, the counting mode is started based on the signal sequence of the industrial task;

[0041] And according to the task thread of the signal sequence after being assigned by the scheduler, task counting information is generated; wherein the technical information of the synchronization task has a synchronization identifier.

[0042] In combination with the first aspect, the counting process further includes:

[0043] When the task counting information is interrupted, the conversion result is read and the power allocation coefficients of different task threads are calculated;

[0044] According to the power allocation coefficient, it is judged whether the current industrial task has reached the target allocated power, and based on the judgment result, the execution status information of the current industrial task is generated.

[0045] In combination with the first aspect, the I / O interface board is configured with a plurality of task chip select areas;

[0046] Among them, the task chip select area has a corresponding chip select signal;

[0047] When any task chip select area is accessed by the host signal, the signal of the current task chip select area is pulled low to generate a real-time signal.

[0048] In combination with the first aspect, the process of the bus of the industrial control mainboard performing PCle bus interconnection also includes:

[0049] Initialize the industrial mainboard, and upon receiving an industrial task, determine the communication mode of the current industrial task; wherein the communication mode includes a wireless communication mode and a wired communication mode; and the wireless communication mode includes a networking communication mode and a mobile communication mode;

[0050] According to the communication mode, power is supplied through the corresponding communication components in the power supply module.

[0051] In combination with the first aspect, the I / O interface board integrates a photoelectric coupling matrix interface;

[0052] Wherein, each interface in the photoelectric coupling matrix interface is configured with a shape memory alloy contact;

[0053] Each channel of each interface in the optocoupler matrix interface corresponds to a power domain, a signal domain and a thermal domain, and the power domain, the signal domain and the thermal domain respond to the optocoupler matrix interface visually through a color-changing LED matrix.

[0054] The beneficial effects of the present invention are:

[0055] The aluminum alloy heat dissipation backplane in the present invention effectively dissipates system heat, ensures stable operation of the system in a fanless environment, and extends the life of the equipment. The combination of a multi-core processor and a scheduler enables the system to efficiently handle multi-threaded tasks and improve overall processing capabilities. The scheduler flexibly schedules tasks according to the task type (single-threaded / multi-threaded) to ensure that tasks can be executed efficiently and improve system response speed. The power supply module provides stable power to the system, ensuring that each component can work normally and improving system reliability. The modular design of the system facilitates maintenance and upgrades, and users can replace or upgrade specific components as needed to improve the scalability of the system.

[0056] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0057] The technical solution of the present invention is described in detail below in combination with the first aspect through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0059] In the attached picture:

[0060] Figure 1 A system composition diagram of an industrial motherboard in an embodiment of the present invention;

[0061] Figure 2 This is a schematic diagram of the appearance of a mainboard in an embodiment of the present invention;

[0062] Figure 3 Flow chart of hardware detection steps in an embodiment of the present invention.

[0063] Illustration Description:

[0064] 1. Aluminum alloy heat dissipation back plate; 2. I / O interface board; 3. Industrial control motherboard; 4. Power supply module. DETAILED DESCRIPTION

[0065] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0066] Example 1

[0067] like Figure 1 and Figure 2As shown, the present invention proposes a multi-task processing system for a fanless industrial computer, comprising:

[0068] The aluminum alloy heat dissipation back plate 1 is used for installing and embedding the industrial control main board 3, the memory group, and the I / O interface board 2, and interconnecting the bus of the industrial control main board 3 with the PCle bus;

[0069] The industrial control mainboard 3 is embedded with a multi-core processor and a scheduler connected to the multi-core processor;

[0070] Among them, the scheduler is also interconnected with the memory group and the I / O interface board 2;

[0071] The I / O interface board 2 is used to receive the industrial control task and determine whether the industrial control task is a multi-threaded task or a single-threaded task;

[0072] When the industrial control task is a multi-threaded task, the industrial control task is transmitted to multiple processing cores of the multi-core processor through the scheduler, and a unique memory is configured for each processing core in the memory group to perform multi-task parallel processing;

[0073] When the industrial control task is a single-threaded task, the industrial control task is transferred to the ready task queue through the scheduler, and the CPU authority of the multi-core processor is configured to the corresponding single-threaded task;

[0074] The power supply module 4 is respectively connected to the industrial control mainboard 3 and the I / O interface board 2 to provide power.

[0075] The technical principle of the above scheme is:

[0076] In actual implementation, the aluminum alloy heat dissipation backplane 1 is not only used to install the industrial control motherboard 3, memory group and I / O interface board, but also realizes high-speed interconnection between these components through the PCle bus (for example, PCle, 3.0x4 channel). The function of the aluminum alloy heat dissipation backplane 1 is to dissipate heat. Aluminum alloy has good thermal conductivity and can effectively dissipate the heat generated by the industrial control motherboard 3 and the multi-core processor to ensure the stable operation of the system in a fanless environment. The present application can achieve the coordination of heat dissipation and task scheduling. The thermal conductivity characteristics of the aluminum alloy heat dissipation backplane 1 are combined with the dynamic load distribution of the multi-core processor to achieve a 30% performance improvement under fanless conditions. In terms of memory allocation, a unique memory device is configured for each processing core (physical isolation rather than logical partitioning), which avoids insufficient storage while solving the problem of task processing delay in shared memory pool solutions (which often require task sorting).

[0077] In the prior art, industrial computers usually rely on fans for heat dissipation, but fans have problems such as noise, easy damage, and dust accumulation. The present application adopts an aluminum alloy heat dissipation backplane 1 to achieve fanless heat dissipation, which solves the problems caused by fans, and optimizes the communication efficiency between components through PCle bus interconnection. The combination of fanless design and aluminum alloy heat dissipation backplane 1 improves the operating efficiency by at least 30% in the field of industrial computers, especially in high-load multi-tasking scenarios.

[0078] The multi-core processor embedded in the industrial control mainboard 3 can handle multiple tasks at the same time, improving the overall processing power of the system. The scheduler is responsible for the allocation and management of tasks to ensure that tasks can be efficiently executed on the multi-core processor. In the prior art, the task scheduling of multi-core processors usually depends on the scheduler at the operating system level, and may not be optimized for the characteristics of industrial control tasks. The present application uses a hardware-level scheduler combined with the task type judgment (single-threaded / multi-threaded) of the I / O interface board to achieve more efficient task allocation and processing. The combination of the hardware scheduler and the task type judgment makes task scheduling more accurate and efficient, which is an innovation in the field of industrial control.

[0079] Memory group, configures a unique memory device (for example: DDR4 chip) for each processing core to ensure efficient access to data during multi-task parallel processing. I / O interface board: responsible for receiving industrial control tasks and determining whether the task is single-threaded or multi-threaded so that the scheduler can perform corresponding processing. The scheduler assigns multi-threaded tasks to multiple cores of the multi-core processor, and each core uses an independent memory device for parallel processing to improve processing efficiency. The scheduler puts the single-threaded task into the ready task queue and assigns the CPU authority to the task to ensure that the single-threaded task can respond and execute quickly. The power supply module 4 provides a stable power supply for the industrial control motherboard 3 and the I / O interface board 2 to ensure that all components of the system can work normally. In the prior art, the memory allocation of multi-core processors is usually shared, which may lead to resource competition and performance bottlenecks. The present application configures a unique memory device for each processing core, avoids resource competition, and improves the efficiency of multi-task parallel processing. Due to heat dissipation limitations, traditional fanless industrial computers often require multi-core processors to run at a reduced frequency (such as 2.0GHz→1.2GHz). This solution optimizes task allocation through the hardware scheduler, allowing the multi-core processor to run continuously at full frequency (2.4GHz) and the core temperature to be stabilized within 65°C (the industrial upper limit is 85°C). The existing technology generally uses a shared memory pool. This application equips each core with a unique memory device, and the task data is stored nearby to reduce bus transmission; a single memory failure does not affect other cores, and the system reliability is improved.

[0080] The beneficial effects of the above scheme are:

[0081] The aluminum alloy heat dissipation backplane 1 in the present invention effectively dissipates system heat, ensures stable operation of the system in a fanless environment, and extends the life of the equipment. The combination of a multi-core processor and a scheduler enables the system to efficiently handle multi-threaded tasks and improve overall processing capabilities. The scheduler performs flexibly according to the task type (single-thread / multi-threaded) (for example: multi-threaded tasks: configure a unique memory for each core (physical isolation) and parallel processing; single-threaded tasks: allocate CPU permissions through the ready queue and execute exclusively), ensuring that tasks can be executed efficiently and improving system response speed. The power supply module 4 provides stable power to the system, ensuring that each component can work normally and improving system reliability. The modular design of the system facilitates maintenance and upgrades, and users can replace or upgrade specific components as needed to improve the scalability of the system.

[0082] Example 2

[0083] The memory group includes a plurality of memories and a sequence buffer; wherein each physical storage element in the memory generates a plurality of storage units based on a preset unit storage amount, and each storage unit has a unique identifier;

[0084] When receiving the assigned task from the scheduler, responding to the industrial control task, and determining the storage capacity occupied by the task data to be written corresponding to the industrial control task;

[0085] By using the storage capacity, any uniquely indicated storage unit in any free memory is used as the initial storage address;

[0086] According to the initial storage address, the free storage units in the current memory are queued and sorted to generate a storage sequence corresponding to the industrial control task.

[0087] The principle of the above technical solution is:

[0088] The storage group of the present invention is composed of multiple independent memories, each of which can work independently, thereby improving the parallel processing capability of the memory. The sequence buffer is used to temporarily store task data and sequence information to ensure the orderliness and efficiency of data storage. When the scheduler assigns tasks, the multi-core processor will determine the storage capacity occupied by the data to be written corresponding to the industrial control task.

[0089] The sequence buffer is used to temporarily store task data and sequence information to ensure the orderliness and efficiency of data storage. According to the storage capacity, a storage unit will be selected in the free memory as the initial storage address. According to the initial storage address, the free storage units in the current memory are queued and sorted to generate a storage sequence corresponding to the industrial control task. This application generates a continuous storage sequence through queue sorting, reduces data addressing delay, and combines unique identification to achieve rapid preemption of high-priority tasks.

[0090] By assigning a unique identifier to each storage unit and combining storage capacity judgment and queue sorting, multi-core processors can manage memory resources more finely and avoid memory waste. The design of multiple memories enables the system to handle the storage needs of multiple tasks at the same time, improving the efficiency of multi-tasking. By generating a storage sequence, the orderliness of task data storage is ensured, reducing conflicts and delays during data access. In multi-tasking scenarios, uniquely identified storage units isolate data access conflicts and shorten task response time. Through unique identification and dynamic allocation, rapid response to sudden large-capacity tasks (such as real-time image processing) is supported.

[0091] Example 3

[0092] like Figure 3 As shown, the industrial control mainboard 3 also includes a plurality of hardware detection devices, wherein the hardware detection steps are as follows:

[0093] Pre-configure a monitoring period and collect first operation data within the monitoring period; wherein the first operation data includes environmental sensing data and operation status data;

[0094] According to the detection cycle, the first operation data is generated according to the cycle timing to generate a detection sequence, and the detection sequence is stored in a sequence buffer; wherein the sequence buffer is electrically connected to a preset host server through an I / O interface board 2, and the sequence memory includes a first cache layer and a second cache layer;

[0095] According to the sequence buffer, storing time data of the detection sequence in a first cache layer and storing detection data in a second cache layer;

[0096] Obtain the detection sequence of the next detection cycle, and compare the data with the first cache layer and the second cache layer respectively to determine whether there is data anomaly;

[0097] When there is data anomaly, extract the time data and detection data corresponding to the abnormal data, and extract the abnormal features;

[0098] Generate abnormal status prompt information based on abnormal characteristics.

[0099] The technical principle of the above scheme is:

[0100] In the process of hardware detection, this application monitors the hardware operation data in different monitoring cycles, monitors the environmental data (such as temperature, humidity) and operation status data (such as CPU load, memory usage) in real time, and ensures that the system runs within a safe range. First, when abnormal data is detected, prompt information can be generated in time to help operation and maintenance personnel quickly locate and handle problems and avoid system failures or performance degradation. Then, by detecting the sequence and comparing historical data with current data, potential problems can be discovered in time to avoid small problems accumulating into major failures. It can extract abnormal features and generate prompt information to help operation and maintenance personnel quickly understand the cause of the problem and improve fault handling efficiency. By real-time monitoring of operation status data, the system can dynamically adjust resource allocation (such as CPU permissions, memory allocation, etc.) according to the current load to ensure that the system can still run stably under high load. By analyzing environmental data and operation status data, the system can predict potential hardware failures (such as overheating, overload, etc.) and take preventive measures in advance. The sequence buffer is connected to the host server through the I / O interface board to realize remote upload and analysis of data. Operation and maintenance personnel can remotely monitor the operation status of multiple industrial computers through the host server to achieve centralized management and reduce operation and maintenance costs.

[0101] In actual implementation, the scheduler is responsible for task allocation and scheduling, and the hardware monitoring device is responsible for monitoring the operating status of the system. The two work together to ensure that the system can still run stably under high-load tasks. For example, when the hardware detection device detects that the CPU load is too high, the scheduler can dynamically adjust the task allocation strategy to avoid system overload. The memory group is responsible for the storage and management of task data, and the hardware detection device is responsible for monitoring the memory usage rate. The two work together to ensure the efficient use of memory resources. For example, when the hardware detection device detects that the memory usage rate is too high, the system can dynamically adjust the memory allocation strategy to avoid memory overflow. The fanless design achieves efficient heat dissipation through the aluminum alloy heat dissipation backplane 1, and the hardware detection device is responsible for monitoring the ambient temperature. The two work together to ensure that the system can still run stably in a high-temperature environment. For example, when the hardware detection device detects that the ambient temperature is too high, the system can dynamically adjust the heat dissipation strategy (such as reducing the CPU frequency) to avoid overheating. The sequence buffer is connected to the host server through the I / O interface board to realize remote upload and analysis of data. Operation and maintenance personnel can remotely monitor the system status through the host server and dynamically adjust the task management strategy. For example, when the host server detects that an industrial computer is operating abnormally, it can remotely adjust the task allocation strategy to ensure the continuous execution of the task.

[0102] The above solution can solve the problem that hardware detection in the prior art mostly uses a single data stream storage. The present application solves the problem of misjudgment of mixed data in multi-task scenarios by storing and detecting data in time-sharing. For example: the need for correlation analysis between ambient temperature waveform and CPU load anomaly depends on the problem of time series alignment. And by dynamically comparing the data of the previous and subsequent cycles and combining the timestamp to lock the abnormal nodes, the efficiency of fault location is significantly improved. The present application does not rely on cloud collaboration, and environmental data and operating status data can be correlated and analyzed to improve the accuracy of anomaly detection.

[0103] Example 4

[0104] The scheduler also includes:

[0105] The process scheduler is used to determine the task execution sequence and generate the task execution process when receiving industrial tasks;

[0106] AI model manager, which is used to receive input data and configure execution flow interfaces for different input data according to the task execution process;

[0107] The executor is used to determine whether there is a synchronous task in the industrial task according to the execution flow interface; wherein,

[0108] When there is a synchronization task, execute the stream synchronization task block;

[0109] When there is no synchronization task, a single task block is generated;

[0110] The run manager is used to return the execution result according to the synchronous task block / single task block.

[0111] The technical principle of the above technical solution is:

[0112] This application sets up a process scheduler, receives industrial tasks (the scheduler and the industrial control motherboard 3 are connected to realize interactive control), and determines the execution sequence of the tasks to generate a task execution process. According to the characteristics and dependencies of the tasks, the execution order of the tasks is arranged to ensure that the tasks can be completed efficiently. According to the task execution process, the AI ​​model manager receives input data and configures the execution flow interface of different input data, and configures a dedicated execution flow interface for each task to ensure that the task data can be efficiently transmitted and processed. The executor determines whether there is a synchronous task for the industrial task based on the execution flow interface. When there is a synchronous task, the executor generates a synchronous task block to ensure that multiple tasks can be executed collaboratively. When there is no synchronous task, the executor generates a single task block to ensure that the task can be executed independently. The operation manager executes the task and returns the execution result according to the synchronous task block or the single task block. The operation manager is responsible for returning the task execution result to the scheduler to ensure the integrity of the task process. The process scheduler and the AI ​​model manager will be bound to the multi-core processor instruction set.

[0113] In the prior art, task scheduling usually relies on the scheduler at the operating system level, which may not be optimized for the characteristics of industrial tasks. The process scheduler can generate the optimal task execution sequence based on the characteristics and dependencies of the tasks, which is significantly innovative. AI Model Manager: The introduction of the AI ​​Model Manager (with NPU acceleration hardware) enables the execution flow interface to be dynamically configured according to task requirements, improving the flexibility and adaptability of the system. The executor can determine whether there are synchronous tasks for the task, and generate synchronous task blocks or single task blocks to ensure that the task can be executed efficiently. The run manager can monitor the execution process of the task and return the results to ensure the integrity and efficiency of the task process.

[0114] Example 5

[0115] The I / O interface board 2 is provided with a CAN communication component, wherein the CAN communication component includes a CAN transceiver and a multi-channel digital isolator; wherein,

[0116] Multi-channel digital isolators are used to separate multiple tasks issued by the host computer.

[0117] The technical principle of the above technical solution is:

[0118] This application uses a multi-channel digital isolator (such as the domestic ISO7330FCDWR three-channel isolator) to replace the traditional single-channel isolation solution, which can simultaneously separate multiple task signals sent by the host computer. This architecture combines the star networking capability with multi-channel isolation technology in a breakthrough way, supports independent operation of channels with different baud rates, and solves the interference coupling problem of multi-task processing in traditional CAN systems under complex electromagnetic environments. Combining digital isolation chips (such as Adum1201) with CAN transceivers (such as TAJA1050), the controller is isolated from the physical layer through an electrical isolation layer, achieving both 2500VDC high-level isolation and 1Mbps high-speed transmission. This design breaks through the bandwidth limitation of traditional optocoupler isolation while ensuring signal integrity. In terms of technical principles, multi-channel digital isolators use capacitive / magnetic coupling technology to form an isolation barrier on the signal path to block common-mode interference conduction. The CAN controller uses a non-destructive arbitration mechanism and ID filtering function to achieve task priority isolation and selective forwarding, thereby reducing bus load. Use a transceiver with a DC-DC isolated power supply (such as the SunYuan ISO CAN series) to provide independent power supply for each CAN channel. Combined with the fast response characteristics of the digital isolator (such as 0.8ns propagation delay), synchronous conditioning and isolated transmission of multiple signals can be achieved within the industrial temperature range of -40~+70℃.

[0119] Example 6

[0120] The I / O interface board 2 is also provided with a task counting clock; wherein the counting process is as follows:

[0121] Initialize the clock module on I / O interface board 2;

[0122] According to the clock module, clear the interrupt flag and initialize the interrupt vector table;

[0123] After initializing the interrupt vector table, when an industrial task is received, the counting mode is started based on the signal sequence of the industrial task;

[0124] And according to the task thread of the signal sequence after being assigned by the scheduler, task counting information is generated; wherein the technical information of the synchronization task has a synchronization identifier.

[0125] The technical principle of the above technical solution is:

[0126] This application clears the interrupt flag and initializes the vector table, so that the system can quickly respond to the burst signal of the industrial task. High-priority tasks can preempt low-priority tasks and reduce the delay of critical tasks. For example, the identification mechanism of the synchronization task can ensure the real-time synchronization of sensor data acquisition and control. Task count information helps to dynamically adjust the scheduling strategy to avoid a single task occupying the CPU for a long time. Combined with the time slice division of the timer interrupt, the system can efficiently switch between multiple tasks and improve the throughput of the I / O interface board. This feature is particularly important in resource-constrained embedded systems. Through the independent management of task threads (such as private stacks and task control blocks), the system realizes the decoupling between tasks. The counting information of each task is generated independently, which is convenient for debugging and maintenance. In addition, the introduction of synchronization identification simplifies the task coordination in complex industrial scenarios. In actual implementation, the synchronization identification uses binary flags, specific interrupt vectors, or automatically corresponding flag information in the user-defined flag library.

[0127] The combination of the interrupt mechanism of this application and the task counting clock: the existing technology (timer interrupt has been used to implement multi-task scheduling), but this solution binds the counting information with the scheduler to achieve dynamic optimization. Specific application of synchronization identification: mentions the need for synchronous acquisition of multiple sensors.

[0128] The traditional solution uses a fixed cycle to dynamically adjust the counting mode through the signal sequence, so that the task start time matches the industrial scenario requirements (such as changes in the production line rhythm) in real time, which can reduce the idle cycle. The task block triggers the hardware-level interrupt response (such as FPGA implementation) through the identification, and the task switching delay is reduced from milliseconds to microseconds to meet the high-frequency control requirements. The counting mode driven by the signal sequence shortens the task response time; the synchronous identification mechanism ensures that the execution of key personnel is not interrupted.

[0129] Example 7

[0130] The counting process also includes:

[0131] When the task counting information is interrupted, the conversion result is read and the power allocation coefficients of different task threads are calculated;

[0132] According to the power allocation coefficient, it is judged whether the current industrial task has reached the target allocated power, and based on the judgment result, the execution status information of the current industrial task is generated.

[0133] When the task count is interrupted, this application calculates the power allocation coefficient by reading the conversion result (such as task priority, execution progress and other data) and combining the current load status of the processor using a dynamic formula based on the importance coefficient (similar to the imp parameter in the MBS algorithm). By comparing the current power allocation coefficient with the preset threshold (such as the heat dissipation capacity limit or the optimal energy efficiency value), it is determined whether the task execution strategy needs to be adjusted. For example: if a high-priority task does not reach the target power, task preemption or resource reallocation is triggered; if the system as a whole exceeds the limit, frequency reduction or task migration is initiated (similar to the hot-swap processor mechanism). The power allocation coefficient is determined by multiplying the ratio of the power of the current task to the power of the total task by the priority weight.

[0134] Based on the real-time multitasking mechanism, a scheduling method combining interrupt response and cyclic scanning is adopted: task interrupt triggers power recalculation, and the main program manages the task status through the priority queue to ensure that key tasks get resources first. The dynamic window scheduling idea of ​​the chip multiprocessor can maintain high real-time performance under low power consumption conditions.

[0135] Existing industrial control systems usually adopt static power allocation strategies (such as fixed core frequency), while the above scheme triggers dynamic power adjustment through task counting interrupts to achieve real-time energy efficiency optimization. For example, in the emergency braking task of the robotic arm, the power coefficient of the motion control thread is immediately increased after the interrupt is triggered to ensure that the response time is shortened from 50ms to 15ms. In the prior art, there is energy consumption monitoring, and generally the energy consumption data and power allocation strategy are not linked. This application generates a power coefficient (such as the task progress corresponding to each watt of computing power) by quantifying the conversion results, which solves the problem of the disconnection between the energy efficiency ratio and the task requirements in the traditional solution. In addition, dynamic power allocation avoids local overheating (such as the reduction of the temperature difference between the CPU cores), which meets the stringent requirements of fanless design for uniform temperature; the power coefficient calculation introduces an ambient temperature compensation factor, which can limit high-power consumption tasks at high temperatures. The microsecond power adjustment triggered by the terminal ensures the timing determinism of high-priority tasks.

[0136] Example 8

[0137] The I / O interface board 2 is provided with a plurality of task chip selection areas;

[0138] Among them, the task chip select area has a corresponding chip select signal;

[0139] When any task chip select area is accessed by the host signal, the signal of the current task chip select area is pulled low to generate an enable signal.

[0140] The technical principle of the above technical solution is:

[0141] This application divides multiple independent "task chip select areas" on the I / O interface board, and each area corresponds to a unique chip select signal (CS) (the chip select area is divided by the hardware logic unit implemented by FPGA, and the enable signal is generated by the level conversion circuit). When the host accesses a certain area, the chip select signal of the area is pulled low, an enable signal is generated, and the processing logic of the corresponding task is activated. This mechanism is similar to the address decoding in a multi-chip system. The data paths of different tasks are isolated by hardware signals to ensure that only one task occupies the bus resources at the same time to avoid conflicts. The collaborative multi-task scheduling task switching depends on the active triggering of the chip select signal and belongs to the "collaborative multi-task" mode. Only when the current task is completed and the bus is released (the chip select signal returns to a high level) can other tasks be accessed. This design does not require a complex priority arbitration circuit, and the task execution order is directly controlled by hardware signals. The chip select area of ​​the unselected task is in a high level state, and its corresponding circuit module enters a low power or disabled state. This dynamic enabling mechanism meets the low power consumption requirements of fanless industrial computers and reduces system heat generation.

[0142] Existing industrial computer interface boards usually use fixed interface allocation or software virtualization solutions, while the above solution realizes physical-level task resource isolation through hardware-level task fragment area division combined with a signal pull-down trigger enable mechanism. For example, when processing PLC control instructions and visual inspection data at the same time, dynamic switching of fragment signals can avoid bus conflicts and reduce task response delays. Although existing dual-network dual-serial port industrial computers support multi-interface expansion, their signal control relies on software polling. This application directly generates an enable signal by pulling down the hardware signal, reducing the CPU interrupt processing overhead. At the same time, the physical isolation design of the chip select area (such as separation by PCB routing) can reduce signal crosstalk, which is suitable for industrial scenarios with high electromagnetic interference. The hardware trigger mechanism of the enable signal reduces the task switching time from microseconds to nanoseconds.

[0143] Example 9

[0144] The process of the bus of the industrial control mainboard 3 performing PCle bus interconnection also includes:

[0145] Initialize the industrial mainboard, and upon receiving an industrial task, determine the communication mode of the current industrial task; wherein the communication mode includes a wireless communication mode and a wired communication mode; and the wireless communication mode includes a networking communication mode and a mobile communication mode;

[0146] According to the communication mode, power is supplied through the corresponding communication components in the power supply module 4 .

[0147] The technical principle of the above technical solution is:

[0148] This application uses the PCIe bus to realize the interconnection of the industrial control motherboard 3, which is consistent with the development trend of modern industrial computers that emphasize scalability. Fanless industrial computers support flexible functional expansion (such as communication modules, sensor connections, etc.) through expansion slots such as PCIe, thereby meeting the needs of multi-tasking. The high bandwidth characteristics of the PCIe bus can support multi-task parallel data transmission and improve system efficiency. The core innovation lies in the dynamic selection of the power supply module 4 according to the task communication mode (wireless networking, mobile communication or wired mode). This application mentions the integration of wireless / wired communication modules in industrial control systems, but does not clarify the power supply adaptation mechanism. Instead, it describes the networking characteristics of wireless self-organizing networking technology (such as Mist Mesh), and its low-power design may be related to power supply optimization. Through communication mode recognition, targeted power supply for different modules can reduce redundant power consumption and improve energy efficiency. Fanless industrial computers rely on closed structures and industrial-grade components to achieve heat dissipation and anti-interference.

[0149] The power supply module needs to be adapted, for example, using a wide voltage input to cope with power supply fluctuations, and modular power supply to avoid system risks caused by unstable baseboard power supply in traditional industrial computers. Traditional industrial computers face the problem of redundant or insufficient power supply in complex communication scenarios (for example, the wireless module has high power consumption and requires a stable power supply, and the wired mode can simplify the power supply). Accurate power supply adaptation can be achieved through mode judgment, which not only improves system reliability (in line with the requirements for high reliability of industrial computers) but also optimizes power consumption management (in response to the demand for low-power wireless communication). The power supply module contains multiple DC-DC converters, which switch the power supply path of the communication components through FPGA-controlled relays, and the FPGA is connected to the multi-core processor.

[0150] In actual implementation, although the existing industrial computers support multiple communication interfaces (such as 4 Gigabit network ports and Wi-Fi modules), their power supply strategy is a static full-on mode, resulting in high power consumption and heat dissipation pressure. This application optimizes energy consumption under fanless heat dissipation constraints by dynamically identifying communication modes and selectively supplying power. For example, when the task only requires wired communication, turn off the power of the wireless module and reduce the power consumption of the entire machine. At the same time, by subdividing the wireless mode (networking / mobile), scene adaptation is achieved (wireless networks in the prior art are usually fixed points). For example, switch to low-power networking mode (ZigBee) in the workshop, and enable the 5G module when moving outdoors, which improves communication stability and solves the contradiction between heat dissipation and communication reliability of fanless industrial computers under multi-task high load.

[0151] Example 10

[0152] The I / O interface board 2 integrates a photoelectric coupling matrix interface;

[0153] Wherein, each interface in the photoelectric coupling matrix interface is configured with a shape memory alloy contact;

[0154] Each channel of each interface in the optocoupler matrix interface corresponds to a power domain, a signal domain and a thermal domain, and the power domain, the signal domain and the thermal domain respond to the optocoupler matrix interface visually through a color-changing LED matrix.

[0155] The technical principle of the above technical solution is:

[0156] The anti-human optocoupler matrix interface of this application realizes electrical isolation of the input / output ends through optical signal transmission, which can resist common electromagnetic interference in industrial sites (such as the optical coupling isolation characteristics) and ensure the purity of signal transmission. Combined with the adaptive deformation ability of shape memory alloy contacts (there is a phase change temperature point, and when the phase change temperature point is exceeded and the performance parameters change, an automatic alarm is issued), it can maintain stable physical contact in harsh environments such as vibration and temperature fluctuations (similar to the requirements of the Zhongguang matrix switch for connection stability), further reducing the risk of poor contact. The "thermal domain" design of each interface channel is combined with the thermal response characteristics of shape memory alloys (such as automatic adjustment of contact pressure at high temperatures to improve the heat dissipation path), which can actively optimize local heat dissipation efficiency. At the same time, the chassis heat dissipation principle mentioned by the fanless industrial computer through passive heat dissipation of the aluminum alloy body complements the independent monitoring of the thermal domain to avoid local overheating causing system frequency reduction or failure. The color-changing LED matrix uses different colors to intuitively feedback the status of the power domain (voltage stability, continuous red (more than 3 seconds) + flashing green for alarm, single green normal), signal domain (transmission status, red + green flashing in sequence to alarm, single green normal), and thermal domain (temperature red alarm + green normal) (similar to the red optical coupler displaying the logical status through a voltmeter), making it easier for operation and maintenance personnel to quickly locate abnormal channels and reduce downtime.

[0157] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A multi-task processing system for a fanless industrial computer, characterized in that: include: Aluminum alloy heat dissipation backplane, used to install embedded industrial control motherboard, memory group, I / O interface board, and interconnect with the bus of industrial control motherboard for PCle bus; The industrial control motherboard is embedded with a multi-core processor and a scheduler connected to the multi-core processor; Among them, the scheduler is also interconnected with the memory group and the I / O interface board; The I / O interface board is used to receive industrial control tasks and determine whether the industrial control tasks are multi-threaded tasks or single-threaded tasks; When the industrial control task is a multi-threaded task, the industrial control task is transmitted to multiple processing cores of the multi-core processor through the scheduler, and a unique memory is configured for each processing core in the memory group to perform multi-task parallel processing; When the industrial control task is a single-threaded task, the industrial control task is transferred to the ready task queue through the scheduler, and the CPU authority of the multi-core processor is configured to the corresponding single-threaded task; The power supply module is respectively connected to the industrial control mainboard and the I / O interface board to provide power; Wherein, the I / O interface board integrates a photoelectric coupling matrix interface; Each interface in the photoelectric coupling matrix interface is configured with a shape memory alloy contact; Each channel of each interface in the optocoupler matrix interface corresponds to a power domain, a signal domain and a thermal domain, and the power domain, the signal domain and the thermal domain respond to the optocoupler matrix interface visually through a color-changing LED matrix.

2. A multi-task processing system for a fanless industrial computer as claimed in claim 1, characterized in that: The memory group includes a plurality of memories and a sequence buffer; wherein each physical storage element in the memory generates a plurality of storage units based on a preset unit storage amount, and each storage unit has a unique identifier; When receiving the assigned task from the scheduler, responding to the industrial control task, and determining the storage capacity occupied by the task data to be written corresponding to the industrial control task; By using the storage capacity, any uniquely indicated storage unit in any free memory is used as the initial storage address; According to the initial storage address, the free storage units in the current memory are queued and sorted to generate a storage sequence corresponding to the industrial control task.

3. A multi-task processing system for a fanless industrial computer as claimed in claim 1, characterized in that: The industrial control motherboard also includes multiple hardware detection devices, wherein the hardware detection steps are as follows: Pre-configure a monitoring period and collect first operation data within the monitoring period; wherein the first operation data includes environmental sensing data and operation status data; According to the detection cycle, the first operation data is generated according to the cycle timing to generate a detection sequence, and the detection sequence is stored in a sequence buffer; wherein the sequence buffer is electrically connected to a preset host server through an I / O interface board, and the sequence memory includes a first cache layer and a second cache layer; According to the sequence buffer, storing time data of the detection sequence in a first cache layer and storing detection data in a second cache layer; Obtain the detection sequence of the next detection cycle, and compare the data with the first cache layer and the second cache layer respectively to determine whether there is data anomaly; When there is data anomaly, extract the time data and detection data corresponding to the abnormal data, and extract the abnormal features; Generate abnormal status prompt information based on abnormal characteristics.

4. A multi-task processing system for a fanless industrial computer as claimed in claim 1, characterized in that: The scheduler also includes: The process scheduler is used to determine the task execution sequence and generate the task execution process when receiving industrial tasks; AI model manager, which receives input data and configures execution flow interfaces for different input data according to the task execution process; The executor is used to determine whether there is a synchronous task in the industrial task according to the execution flow interface; wherein, When there is a synchronization task, the stream synchronization task block is executed; When there is no synchronization task, a single task block is generated; The run manager is used to return the execution result according to the synchronous task block / single task block.

5. The multi-task processing system of a fanless industrial computer as claimed in claim 1, characterized in that: The I / O interface board is equipped with a CAN communication component; wherein the CAN communication component includes a CAN transceiver and a multi-channel digital isolator; wherein, Multi-channel digital isolators are used to separate multiple tasks issued by the host computer.

6. The multi-task processing system of a fanless industrial computer according to claim 1, characterized in that: The I / O interface board is also equipped with a task counting clock; wherein the counting process is as follows: Initialize the clock module on the I / O interface board; According to the clock module, clear the interrupt flag and initialize the interrupt vector table; After initializing the interrupt vector table, when an industrial task is received, the counting mode is started based on the signal sequence of the industrial task; And according to the task thread of the signal sequence after being assigned by the scheduler, task counting information is generated; wherein the technical information of the synchronization task has a synchronization identifier.

7. A multi-task processing system for a fanless industrial computer as claimed in claim 6, characterized in that: The counting process also includes: When the task counting information is interrupted, the conversion result is read and the power allocation coefficients of different task threads are calculated; According to the power allocation coefficient, it is judged whether the current industrial task has reached the target allocated power, and based on the judgment result, the execution status information of the current industrial task is generated.

8. The multi-task processing system of a fanless industrial computer as claimed in claim 1, characterized in that: The I / O interface board is configured with a plurality of task segment areas; Among them, the task chip select area has a corresponding chip select signal; When any task chip select area is accessed by the host signal, the signal of the current task chip select area is pulled low, and an enable signal is generated.

9. The multi-task processing system of a fanless industrial computer according to claim 1, characterized in that: The process of the bus of the industrial control mainboard performing PCle bus interconnection also includes: Initialize the industrial mainboard, and upon receiving an industrial task, determine the communication mode of the current industrial task; wherein the communication mode includes a wireless communication mode and a wired communication mode; and the wireless communication mode includes a networking communication mode and a mobile communication mode; According to the communication mode, the corresponding communication components in the power supply module are powered.

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