A flash data migration method

Abstract

The present application relates to the field of flash memory storage control, and particularly relates to a flash memory data migration method. The garbage collection of the method uses a copyback command to accelerate the efficiency of data migration, and then makes a decision on whether to use copyback according to the estimation of the number of error bits based on prior data experience. During garbage collection, the number of copyback times of the page of the block to be recycled is compared with the corresponding copyback threshold THcb. If the number of copyback times CBs of the block to be recycled is less than the copyback threshold THcb, the copyback operation is performed on the block to be recycled. If the number of copyback times CBs of the block to be recycled is greater than the copyback threshold THcb, the copyback operation is not performed on the block to be recycled. The method can maintain high efficiency of copyback while maintaining high data reliability.

Description

Technical Field

[0001] This invention relates to the field of flash memory storage control, and in particular to a flash memory data migration method for improving the efficiency of garbage collection in flash memory storage devices. Background Technology

[0002] NAND flash memory, due to its erasure-then-write characteristic and the inconsistency between write and erase cells, requires garbage collection. This process involves reading valid data from the old block, writing it to the new block, and then erasing the old block. Currently, SSDs typically reserve 7% to 28% of their space, meaning that valid data occupies approximately 72% to 93% of the blocks. During garbage collection, this data is migrated. The efficiency of garbage collection affects the host's write speed and I / O command response time. Therefore, improving garbage collection efficiency can improve the write performance of storage devices and shorten I / O command response time. Due to its physical characteristics and manufacturing process, flash memory often experiences bit flips in its stored data. Therefore, SSD controllers are generally equipped with BCH or LDPC hardware encoding / decoding units. During writing, data is encoded, writing both user data and parity data to the flash memory simultaneously; during reading, data is decoded to detect and correct bit flip errors. Bit flip errors in flash memory are affected by many factors, such as data retention time, number of reads, and number of block erase / write cycles. Especially with the increasing storage density (SLC->MLC->TLC->QLC) and the development of 3D NAND, flash memory erase / write lifespan and data retention capabilities are becoming increasingly poor, making data reliability protection increasingly important.

[0003] NAND manufacturers typically provide copyback flash memory operation commands to help improve data migration efficiency. However, because the data does not enter or leave the NAND flash memory, LDPC encoding and decoding cannot be performed, leading to the accumulation of error bits. After a certain number of copyback operations, uncorrectable errors will occur during reading, resulting in data loss, which is unacceptable for solid-state storage devices. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a flash memory data migration method that can maintain high copyback efficiency while maintaining high data reliability.

[0005] To solve the aforementioned technical problem, the present invention adopts the following technical solution: a flash memory data migration method, comprising the following steps:

[0006] S01. A two-dimensional data table of the number of erase / write cycles and the data retention time was obtained through experiments;

[0007] S02. The maximum number of copyback operations that can be performed within the range of each erase / write cycle was obtained through experiments;

[0008] The data retention time and the maximum number of copybacks that can be executed are fitted to the number of erase and write cycles to obtain a threshold for the number of copybacks that varies with the number of erase and write cycles and the data retention time. This three-dimensional dataset is called CBth.

[0009] S03. Import the 3D dataset CBth and select the block S to be recycled;

[0010] S04. Read the number of erase / write cycles (PEs), data retention time during write, and global data retention time of the block to be reclaimed (S). Subtract the data retention time during write from the global data retention time to obtain the data retention time of the block. Read the number of page copybacks (CBs) of the block to be reclaimed (S).

[0011] S05. Select the free block D1 whose erase / write cycle count and PEs difference is less than the threshold T, and select the free block D2 with the smallest erase / write cycle count according to the wear leveling requirements.

[0012] S06. Based on the number of erase / write cycles and data retention time of the block S to be recycled, look up the table to determine its corresponding copyback threshold THcb;

[0013] S07. Compare the page copyback count CBs of the block to be reclaimed S with the copyback threshold THcb. If the copyback count CBs of the block to be reclaimed is less than the copyback threshold THcb, then perform a copyback operation from block S to D1 and increment the copyback count by one; if the copyback count CBs of the block to be reclaimed is greater than the copyback threshold THcb, then perform a read / write command operation via LDPC from block S to D2 and reset the copyback count to zero.

[0014] S08. Repeat step S07 until recycling is complete.

[0015] Furthermore, the process of obtaining a two-dimensional data table of the number of erase / write cycles and data retention time through experiments is as follows:

[0016] S11. Select NAND particles, confirm their activation energy, and calculate the temperature acceleration coefficient based on the Arrenius model;

[0017] S12. Place the NAND in the temperature chamber, give the number of erase / write cycles, adjust the temperature chamber to t degrees Celsius, keep the NAND at t degrees Celsius for a period of time, read the data in the NAND multiple times during this period of time, and check the number of error bits by LDPC until the number of error bits exceeds the upper limit of LDPC's error correction capability. Take the time and temperature acceleration coefficient at this time to calculate the data retention time.

[0018] S13. Repeat step S12, iterate through the number of erase / write cycles from 0 to the end of the NAND life according to the erase / write cycle interval T1, and iterate through the temperature from 25 degrees Celsius to 85 degrees Celsius according to the temperature interval T2, to obtain a two-dimensional data table of erase / write cycle count and data retention time.

[0019] S14. Fit and reduce the data in step S13, and merge similar data.

[0020] Furthermore, the process of obtaining the maximum number of copyback operations within each erase / write cycle range through experiments is as follows:

[0021] S21. Select a NAND block X with N erase / write cycles, encode the randomized data using LDPC, write it into a NAND WL, and repeat the writing until a NAND block is full.

[0022] S22. Select a NAND block Y with the same or similar number of erase / write cycles as N, read the data written in step S21, perform LDPC error detection and record the number of error bits, and write the data that has not been corrected by LDPC into NAND block Y through the copyback command.

[0023] S23. Repeat step S22 until the number of error bits exceeds the upper limit of LDPC's error correction capability;

[0024] S24. Repeat steps S21 to S23, and iterate through the number of erase / write cycles from 0 to the end of the NAND life according to the erase / write cycle interval T1 to obtain a table of error bit values ​​that varies with the number of erase / write cycles.

[0025] S25. Merge the data obtained in step S24 to determine the maximum number of copyback operations that can be performed within the range of each erase / write cycle. That is, if a copyback operation is performed again, the number of error bits will exceed the LDPC error correction limit.

[0026] Furthermore, in step S07, user data written by the host in the flash storage system is placed on a separate block, and data written by garbage collection is placed on a separate block. That is, the data newly written by the host and garbage collection do not use the same target block.

[0027] Furthermore, when each block is erased, the number of erase / write cycles is recorded in the system table, and when each block is written, the current system's global data retention time is recorded. The global data retention time is obtained by periodically acquiring the NAND temperature and integrating it according to the Arrenius model.

[0028] Furthermore, the number of copyback operations is recorded each time a copyback operation is performed.

[0029] Furthermore, the number of erase / write cycles, the data retention time during block writes, and the global data retention time are recorded in a memory table. Before the system is powered off, these are written to the pSLC. Only the data of the currently recycled block is saved in the memory table for page copyback counts, while data of non-current blocks is stored in the pSLC.

[0030] Furthermore, the erase / write cycle interval T1 is 100 times, and the temperature interval T2 is 1 degree Celsius.

[0031] Furthermore, the erase / write cycle interval T1 is 100 times.

[0032] Furthermore, the number of erase / write cycles between NAND block Y and NAND block Y does not differ by more than 50 times.

[0033] The beneficial effects of the present invention are as follows: The flash memory data migration method of the present invention mainly improves data security by using copyback operation during garbage collection and based on prior experience, thereby improving the garbage collection efficiency of solid-state storage devices, thus improving write performance and shortening IO command response time. Attached Figure Description

[0034] Figure 1 A schematic diagram of the existing waste recycling system;

[0035] Figure 2 This is a flowchart of the method described in this invention. Detailed Implementation

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0037] Example 1

[0038] Copyback is an important function in NAND Flash, allowing data to be moved within the NAND without an external controller, which is significant for improving operational efficiency. During a copyback operation, errors in the read data are inherited into the newly written NAND area. After several copybacks, an LDPC error correction is performed, clearing the accumulated errors.

[0039] Garbage collection without copyback first reads data from the NAND array into the page register, then into the buffer within the controller, followed by LDPC error correction. The corrected data is then written back to the buffer, then transmitted to the page register, and finally written back to the NAND array. The process is as follows: Figure 1: 1->3->5->6->4->2.

[0040] There are two common usage methods: 1. Use copyback garbage collection to read from the NAND array to the page register, and then write directly from the page register to the array, such as... Figure 1 1->2; 2. Use the read command to read data from the array into the page register, then transfer it to the buffer in the controller. Use LDPC for error checking. If the number of error bits is within an acceptable range, directly write the data in the page register into the NAND array. The process is as follows. Figure 1 The first method cannot guarantee data security, and the second method is less efficient than the first.

[0041] However, due to the inherent characteristics of NAND, multiple copyback operations can lead to error accumulation, affecting data security. Common factors affecting NAND data reliability include: the number of erase / write cycles, data retention capability, and read interference. This patent mainly concerns the number of erase / write cycles and data retention capability. Each erase / write operation generates a very large electric field in the tunneling oxide layer. Due to trap formation and interface damage, defects can occur in the oxide layer, causing charge trapping or release into the tunneling oxide layer, resulting in abnormal charge flowing into the storage layer. As the number of erase / write cycles increases, under the same voltage and time conditions, the charge injected into the storage layer decreases with the increase in the number of erase / write cycles. Therefore, the more erase / write cycles, the greater the probability of errors. Data retention capability refers to the ability to store information without an external power supply. The loss of charge in the storage layer causes an overall shift in the threshold voltage distribution, and the longer the time, the greater the shift. Therefore, the longer the time, the more errors are generated, and temperature accelerates this behavior. The effect of temperature stress conforms to the Arrenius model.

[0042] To address this, this embodiment discloses a data migration method applied to a flash memory storage system. This method uses the copyback command during garbage collection to accelerate data migration efficiency, and simultaneously estimates the number of error bits based on prior data experience before deciding whether to use copyback. This method can maintain both high efficiency and high data reliability while preserving the high efficiency of copyback.

[0043] The prior data collection process is as follows:

[0044] S11. Select NAND particles, confirm their activation energy, and calculate the temperature acceleration coefficient based on the Arrenius model;

[0045] S12. Place the NAND in the temperature chamber, give the number of erase / write cycles, adjust the temperature chamber to t degrees Celsius, keep the NAND at t degrees Celsius for a period of time, read the data in the NAND multiple times during this period of time, and check the number of error bits by LDPC until the number of error bits exceeds the upper limit of LDPC's error correction capability. Take the time and temperature acceleration coefficient at this time to calculate the data retention time.

[0046] S13. Repeat step S12, iterate through the number of erase / write cycles from 0 to the end of the NAND life according to the erase / write cycle number interval of 100, and iterate through the temperature from 25 degrees Celsius to 85 degrees Celsius according to the temperature interval of 1 degree Celsius, to obtain a two-dimensional data table of erase / write cycle number and data retention time.

[0047] The erase / write cycle interval and temperature interval are set according to the actual situation, and can also be other values ​​in other embodiments.

[0048] (4) Fit and reduce the data in step (3), and merge similar data.

[0049] Data collection on copyback counts and error bits:

[0050] (1) Select a NAND block X with N erase / write cycles, encode the randomized data using LDPC, and write it into a NAND WL.

[0051] (2) Repeat step (1) until a NAND block is filled;

[0052] (3) Select a NAND block Y with a write / erase cycle number of N that differs by no more than 50 times. Read the data written in step (1), check for errors using LDPC, and record the number of error bits. Write the data that has not been corrected by LDPC into block Y using the copyback command.

[0053] (4) Repeat step (3) until the number of error bits exceeds the upper limit of LDPC error correction capability;

[0054] (5) Repeat steps (1) to (4) to obtain an error bit value table that varies with the number of erase / write cycles, traversing the erase / write cycle count from 0 to the end of the declaration period at 100-cycle intervals. The erase / write cycle interval is set according to the actual situation and may be other values ​​in other embodiments.

[0055] (6) Merge the data obtained in step (5) to determine the maximum number of copyback operations that can be performed within the range of each erase / write cycle. That is, if a copyback operation is performed again, the number of error bits will exceed the upper limit of LDPC error correction.

[0056] By fitting the above two data points to the number of erase / write cycles, a copyback count threshold that varies with the number of erase / write cycles and the data retention time is obtained. This three-dimensional dataset is called CBth.

[0057] The following are some additional data recording operations and rules that the system needs to perform:

[0058] In step S07, user data written by the host in the flash storage system is placed on a separate block, and data written by garbage collection is placed on a separate block. That is, the data newly written by the host and garbage collection do not use the same target block.

[0059] When each block is erased, the number of erase / write cycles is recorded in the system table. When each block is written, the current system's global data retention time is recorded. The global data retention time is obtained by periodically acquiring the NAND temperature and integrating it according to the Arrenius model.

[0060] The number of copyback operations is recorded each time a copyback operation is performed.

[0061] The erase / write cycle counts, data retention time during block writes, and global data retention time are recorded in a memory table and written to the pSLC before system power failure. Page copyback counts only store data for the currently reclaimed block in the memory table; data for non-current blocks is stored in the pSLC.

[0062] During garbage collection, the 3D dataset CBth obtained from prior experiments is imported and then processed according to... Figure 2 The following process is used for waste recycling:

[0063] 1. Select block S to be recycled;

[0064] 2. Read the number of erase / write cycles PEs of the block S to be reclaimed;

[0065] 3. Read the data retention time when the block S to be reclaimed was written, read the global data retention time and subtract the data retention time to obtain the data retention time of the block.

[0066] 4. Read the page copyback count (CBs) of the block S to be reclaimed;

[0067] 5. Select free block D1 where the difference between the number of erase / write cycles and PEs is less than 500 times;

[0068] 6. Select the free block D2 with the fewest erase / write cycles based on the wear leveling requirements;

[0069] 7. Determine the corresponding copyback threshold THcb based on the number of erase / write cycles and data retention time of the block S to be recycled;

[0070] 8. If the number of copybacks CBs of the block to be recycled is less than the copyback threshold THcb in step (5), then a copyback operation is performed from block S to D1, and the copyback count is incremented by one; if it is greater than the threshold THcb in step (5), then a read / write command operation via LDPC is performed from block S to D2, and the copyback count is cleared to zero.

[0071] 9. Repeat step (8) until recycling is complete.

[0072] Example 2

[0073] This disclosure provides a flash memory data migration apparatus, including a processor and a memory. Optionally, the apparatus may further include a communication interface and a bus. The processor, communication interface, and memory can communicate with each other via the bus. The communication interface can be used for information transmission. The processor can invoke logical instructions in the memory to execute the flash memory data migration method of the above embodiments.

[0074] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0075] Memory, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor executes the program instructions / modules stored in the memory to perform functional applications and data processing, thereby implementing the flash memory data migration method described above.

[0076] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory.

[0077] Example 3

[0078] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the flash memory data migration method described in Embodiment 1.

[0079] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0080] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0081] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0082] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

Claims

1. A method for flash data migration, the method comprising: The method comprises the following steps: S01, obtaining a two-dimensional data table of the number of erase-write cycles and the data retention time through experiments; S02, obtaining the maximum executable copyback number in each range of the number of erase-write cycles through experiments; Fitting the data retention time, the maximum executable copyback number and the number of erase-write cycles to obtain a copyback number threshold varying with the number of erase-write cycles and the data retention time, and the three-dimensional data set is referred to as CBth; S03, importing the three-dimensional data set CBth and selecting a block S to be recycled; S04, reading the number of erase-write cycles PEs of the block S to be recycled, the data retention time at the time of writing, the global data retention time, and obtaining the data retention time of the block by subtracting the data retention time at the time of writing from the global data retention time; reading the page copyback number CBs of the block S to be recycled; S05, selecting an idle block D1 with a difference between the number of erase-write cycles and PEs less than a threshold T, and selecting an idle block D2 with the smallest number of erase-write cycles according to the wear leveling requirement; S06, looking up the corresponding copyback threshold THcb according to the number of erase-write cycles and the data retention time of the block S to be recycled; S07, comparing the page copyback number CBs of the block S to be recycled with the copyback threshold THcb, if the page copyback number CBs of the block to be recycled is less than the copyback threshold THcb, performing a copyback operation from the block S to the block D1, and adding one to the copyback count; if the page copyback number CBs of the block to be recycled is greater than the copyback threshold THcb, performing an LDPC read-write command operation from the block S to the block D2, and resetting the copyback count to zero; S08, repeating step S07 until the recycling is completed.

2. The flash data migration method of claim 1, wherein: The process of obtaining a two-dimensional data table of the number of erase-write cycles and the data retention time through experiments comprises the following steps: S11, selecting a NAND particle, confirming the activation energy thereof, and calculating a temperature acceleration coefficient according to the Arrhenius model; S12, placing the NAND in a temperature box, giving a number of erase-write cycles, adjusting the temperature of the temperature box to t degrees Celsius, keeping the NAND at t degrees Celsius for a period of time, reading the data in the NAND multiple times in the period of time, and checking the number of error bits through LDPC until the number of error bits exceeds the upper limit of the error correction capability of LDPC, and calculating the data retention time by taking the time and the temperature acceleration coefficient at this time; S13, repeatedly performing step S12, traversing the number of erase-write cycles from 0 to the end of the life of the NAND according to an interval T1 of the number of erase-write cycles, and traversing the temperature from 25 degrees Celsius to 85 degrees Celsius according to an interval T2 of the temperature, to obtain a two-dimensional data table of the number of erase-write cycles and the data retention time; S14, fitting and reducing the data in step S13, and merging similar data.

3. The flash data migration method of claim 1, wherein: The process of obtaining the maximum executable copyback number in each range of the number of erase-write cycles through experiments comprises the following steps: S21. Select a NAND block X with N erase / write cycles, encode the randomized data using LDPC, write it into a NAND WL, and repeat the writing until a NAND block is full. S22. Select a NAND block Y with the same or similar number of erase / write cycles as N, read the data written in step S21, perform LDPC error detection and record the number of error bits, and write the data that has not been corrected by LDPC into NAND block Y through the copyback command. S23. Repeat step S22 until the number of error bits exceeds the upper limit of LDPC's error correction capability; S24. Repeat steps S21 to S23, and iterate through the number of erase / write cycles from 0 to the end of the NAND life according to the erase / write cycle interval T1 to obtain a table of error bit values ​​that varies with the number of erase / write cycles. S25. Merge the data obtained in step S24 to determine the maximum number of copyback operations that can be performed within the range of each erase / write cycle. That is, if a copyback operation is performed again, the number of error bits will exceed the LDPC error correction limit.

4. The flash data migration method of claim 1, wherein: In step S07, user data written by the host in the flash storage system is placed on a separate block, and data written by garbage collection is placed on a separate block. That is, the data newly written by the host and garbage collection do not use the same target block.

5. The flash data migration method of claim 2 or 3, wherein: When each block is erased, the number of erase / write cycles is recorded in the system table. When each block is written, the current system's global data retention time is recorded. The global data retention time is obtained by periodically acquiring the NAND temperature and calculating and integrating it according to the Arrenius model.

6. The flash data migration method of claim 3, wherein: The number of copyback operations is recorded each time a copyback operation is performed.

7. The flash data migration method of claim 3, wherein: The number of erase / write cycles, the data retention time during block writes, and the global data retention time are recorded in a memory table. Before the system is powered off, these are written to pSLC. Only the page copyback count of the currently reclaimed block is stored in the memory table, while the page copyback count of non-current blocks is stored in pSLC.

8. The flash data migration method of claim 2, wherein: The erase / write cycle interval T1 is 100 times, and the temperature interval T2 is 1 degree Celsius.

9. The flash data migration method of claim 3, wherein: The interval T1 between erase / write cycles is 100 times.

10. The flash data migration method of claim 3, wherein: The number of erase / write cycles between NAND block Y and NAND block Y does not differ by more than 50.

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