High-performance Inline ECC (Error Correction Code) implementation system

Abstract

The invention relates to optimization of a storage system, in particular to a high-performance Inline ECC (Error Correction Code) implementation system, which comprises an AXI (Advanced Extensible Interface) port arbitration unit for completing multi-AXI port arbitration; the address mapping unit is used for completing mapping from an AXI system address to a DRAM address and generating and distributing a DRAM reading command, a DRAM ECC reading command, a DRAM writing command and a DRAM writing ECC command; the task scheduling unit is used for completing caching and scheduling of a DRAM reading command, a DRAM ECC reading command, a DRAM writing command and a DRAM ECC writing command; the command decoding unit is used for completing command decoding and converting a command into a standard DFI interface signal; the data verification unit is used for completing read data verification and write data verification; according to the technical scheme provided by the invention, the defect of relatively low DRAM reading and writing efficiency in the Inline ECC in the prior art can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to storage system optimization, and in particular to a high-performance Inline ECC implementation system. Background Art

[0002] Memory subsystems can experience errors due to design faults, defects, or electrical noise in any of the components. These errors are classified as hard errors (caused by design faults, defects) and soft errors (caused by system noise, or memory array bit flips caused by alpha rays, etc.). Most memory errors are caused by large memory arrays becoming increasingly dense in order to shrink process nodes, so performing end-to-end protection from the controller to the DRAM is essential to improving the overall stability of the memory subsystem.

[0003] End-to-end protection allows the system to continue running when correctable errors occur, while recording detailed information about uncorrectable errors for future debugging. Inline ECC is an end-to-end protection method. In Inline ECC, ECC data is stored on the same DRAM together with the actual data. For this feature, the read DRAM command sent by the controller needs to be decomposed into a read DRAM data command and a read DRAM ECC data command, and the write DRAM command needs to be decomposed into a write DRAM data command and a write DRAM ECC data command, which causes a sharp drop in the efficiency of reading and writing DRAM. Summary of the invention

[0004] In view of the above shortcomings of the prior art, the present invention provides a high-performance Inline ECC implementation system, which can effectively overcome the defect of low efficiency of reading and writing DRAM in Inline ECC in the prior art.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A high-performance Inline ECC implementation system includes the following units: AXI port arbitration unit, completes multi-AXI port arbitration; The address mapping unit completes the mapping of AXI system addresses to DRAM addresses, as well as the generation and allocation of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; A task scheduling unit, which completes the caching and scheduling of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; The command decoding unit completes command decoding and converts the command into a standard DFI interface signal; The data verification unit completes read data verification and write data verification.

[0006] Preferably, the address mapping unit includes the following modules: The address mapping module ADDR MAP maps the addresses of the read command RD CMD and the write command WR CMD from the AXI system address to the DRAM address, and generates a read-modify-write command RMW according to the address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit, generates a read DRAM command RD DATA CMD and a read DRAM ECC command RD ECC CMD according to the read command RD CMD, generates a write DRAM command WR DATA CMD and a write DRAM ECC command WR ECCCMD according to the write command WR CMD, and distributes the generated commands to the task scheduling unit; DRAM data correction module CORRECTOR, the internal address generator generates a read command RD CMD, and caches the read command RD CMD in the internal COR RD CMD FIFO, when the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg are all empty, the cached read command RD CMD is sent to the address mapping module ADDRMAP.

[0007] Preferably, the address mapping module ADDR MAP includes the following modules: The read-modify-write command generating module RMW GEN converts the read command RD CMD / write command WR CMD into a read-modify-write command RMW when the AXI system address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit is not aligned with the 64-bit data or the data bytes in the 64-bit data are masked. The command is decomposed by the address mapping module ADDR MAP into two read commands RD CMD and write commands WR CMD with the same and aligned addresses; The command generation module ECC CMD GEN generates a DRAM read command RD DATA CMD and a DRAM ECC read command RD ECC CMD according to the read command RD CMD generated by the AXI port arbitration unit or the read command RD CMD generated by the DRAM data correction module CORRECTOR or the read command RDCMD decomposed by the address mapping module ADDR MAP, and generates a DRAM write command WRDATA CMD and a DRAM ECC write command WR ECC CMD according to the write command WR CMD generated by the AXI port arbitration unit or the write command WR CMD decomposed by the address mapping module ADDR MAP; The command allocation module BLOCK MAP allocates the commands generated by the command generation module ECC CMD GEN to the task scheduling unit.

[0008] Preferably, when the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the command is X, if there is already a channel with the block address X, and the read command RD CMD indication flag Read and the channel valid flag valid are both 1, then the address mapping module ADDR MAP sends the read DRAM command RD DATACMD generated according to the read command RD CMD and the block tag Btoken that has been allocated to the channel to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the command is X. If there is already a channel with the block address X, and the read command RD CMD indication flag Read is 0, and the channel valid flag valid is 1, the read command RD CMD indication flag Read is set to 1, and in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the block tag Btoken that has been allocated to the channel to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, but there is a channel with a channel valid flag valid being 0, the channel is used, and a new block tag Btoken is allocated, the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECCCMD generated according to the read command RD CMD, as well as the newly allocated block tag Btoken to the first command cache module RD Page FIFO in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1. In the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the newly allocated block label Btoken to the first command cache module RDPage FIFO, and the write pointer wp is incremented by 1.

[0009] Preferably, when the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the command is X, if there is already a channel with the block address X, and the write command WR CMD indication flag Write and the channel valid flag valid are both 1, then the address mapping module ADDR MAP sends the write DRAM command WRDATA CMD generated according to the write command WR CMD and the block tag Btoken that has been allocated to the channel to the second command buffer module WR PageFIFO; When the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the command is X. If there is already a channel with the block address X, and the write command WR CMD indication flag Write is 0, and the channel valid flag valid is 1, the write command WR CMD indication flag Write is set to 1, and in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the block tag Btoken that has been allocated to the channel to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, but there is a channel with a channel valid flag valid being 0, the channel is used, and a new block tag Btoken is allocated, the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECCCMD generated according to the write command WR CMD, as well as the newly allocated block tag Btoken to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1. In the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg, and the write pointer wp is incremented by 1.

[0010] Preferably, the command allocation module BLOCK MAP includes 16 channels, and the channel structure has a write pointer wp for indicating the channel to be covered, and the structure of each channel is the same, specifically including: block address block address, block tag Btoken, read command RD CMD indication flag Read, write command WR CMD indication flag Write, channel valid flag valid; After the command allocation module BLOCK MAP is reset, the channel valid flags of all channels are invalid, that is, valid=0, and the write pointer wp points to the first channel Channel 0.

[0011] Preferably, the task scheduling unit includes the following modules: The first command buffer module RD Page FIFO buffers the DRAM read command RD DATA CMD and the DRAM ECC read command RD ECC CMD, and buffers the command in the corresponding FIFO according to the Page information of the command; The second command buffer module WR Page FIFO buffers the DRAM write command WR DATA CMD and buffers the command in the corresponding FIFO according to the Page information of the command; The third command cache module WR ECC CMD Reg caches the write DRAM ECC command WR ECC CMD. The write DRAM ECC command WR ECCCMD can be sent only after the write DRAM command WR DATA CMD with the same block tag Btoken is sent. The commands with the same block tag Btoken in the third command cache module WR ECC CMD Reg are write-merged in the order of the corresponding write DRAM command WR DATA CMD that has been sent. The task scheduling module Task SCH schedules the commands cached in the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg according to the priority, and prioritizes all commands corresponding to the block tag Btoken of the covered channels in the command allocation module BLOCK MAP, and then schedules the read DRAM command RDDATA CMD, read DRAM ECC command RD ECC CMD and write DRAM command WR DATA CMD corresponding to the block tag Btoken of the uncovered channels in the command allocation module BLOCK MAP, and finally schedules the write DRAM ECC command WR ECC CMD.

[0012] Preferably, 1 Page is a storage page of DRAM, 1 Page is divided into 8 equal parts, the first 7 equal parts of 1 Page are used to store data, each of which is 1 block, 1 block is the data size of eight burst transmissions, 1 block is divided into 8 equal parts, each equal part of 1 block is 1 access, 1 access is the data size of one burst transmission; The last part of a Page is used to store the data check code ECC. The data of one block corresponds to one data check code ECC.

[0013] Preferably, the command decoding unit includes the following modules: The main state machine Main FSM controls the controller mode switching, caches the commands scheduled by the task scheduling module Task SCH, and decodes the commands; The command selection module CMD MUX switches between the commands decoded by the main state machine Main FSM, Active commands, and Precharge commands; A data buffer module WR Buffer, which buffers the write data of the write DRAM command WR DATA CMD; A fourth command buffer module CMD Buffer, which buffers the command selected by the command selection module CMD MUX; The command decoding module CMD decode decodes the command buffered in the fourth command buffer module CMD Buffer into a standard DFI interface signal, and sends the signal to the physical interface conversion module PHY to complete the conversion of the digital interface signal to the analog interface signal.

[0014] Preferably, the data verification unit includes the following modules: The write data encoding module ENCODER calculates the corresponding data check code ECC according to the write data of the write DRAM command WR DATA CMD, and obtains the write data check code WR DATA ECC corresponding to the write DRAM ECC command WR ECC CMD; The write data cache module WECC REG caches the write data check code WR DATA ECC generated by the write data encoding module ENCODER. When sending the write DRAM ECC command WR ECC CMD, if the write data check code WR DATA ECC that is the same as the block tag Btoken of the command is ready at this time, and the read data check code RECC DATA with the same block tag Btoken exists in the read data cache module RECC REG, then the write data corresponding to the write DRAM ECC command WR ECC CMD is the concatenated data of the write data check code WR DATA ECC and the read data check code RECC DATA with the same block tag Btoken, and the write DRAM ECC command WR ECC CMD is converted into a complete burst command. The tag cache module RD token FIFO caches the tag of the DRAM read command RD DATA CMD. When the read data corresponding to the DRAM read command RD DATA CMD is returned, the corresponding tag is popped out. The tag includes AXI token and block tag Btoken. The read data decoding module DECODER calculates the corresponding data check code ECC according to the read data of the read DRAM command RD DATA CMD, obtains the read data check code RD DATA ECC, and sends it to the comparator COMP; The read data cache module RECC REG, in the case of a write-after-read command with the same block tag Btoken, the internal data may have expired, and the read data data check code RECC DATA in the read data cache module RECC REG and the write data data check code WR DATA ECC in the write data cache module WECC REG are concatenated and sent to the comparator COMP, and at the same time, the write data data check code WR DATA ECC in the write data cache module WECC REG is updated to the read data data check code RECC DATA in the read data cache module RECC REG; The comparator COMP compares the read data check code RD DATA ECC sent by the read data decoding module DECODER with the read data check code RECC DATA sent by the read data buffer module RECC REG.

[0015] Compared with the prior art, the high-performance Inline ECC implementation system provided by the present invention can merge multiple DRAM ECC data read commands and DRAM ECC data write commands, and send DRAM ECC data write commands when the system is idle. At the same time, it also solves the related problems of DRAM ECC data read commands and DRAM ECC data write commands, and when the system is idle and there is no DRAM ECC data write command, it will also send DRAM data read commands at regular intervals to verify the read-back DRAM data. If there are correctable errors in the read-back DRAM data, the corrected data will be written back to DRAM. The system greatly improves the efficiency of reading and writing DRAM, and effectively improves the overall stability of the memory subsystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a system schematic diagram of the present invention; Figure 2 It is a structural diagram of the command allocation module BLOCK MAP in the present invention; Figure 3 It is a schematic diagram of address mapping of a Page in the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] A high-performance Inline ECC implementation system, such as Figure 1 As shown, it includes the following units: AXI port arbitration unit, completes multi-AXI port arbitration; The address mapping unit completes the mapping of AXI system addresses to DRAM addresses, as well as the generation and allocation of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; A task scheduling unit, which completes the caching and scheduling of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; The command decoding unit completes command decoding and converts the command into a standard DFI interface signal; The data verification unit completes read data verification and write data verification.

[0020] ① Such as Figure 1 As shown, the address mapping unit includes the following modules: The address mapping module ADDR MAP maps the addresses of the read command RD CMD and the write command WR CMD from the AXI system address to the DRAM address, and generates a read-modify-write command RMW according to the address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit, generates a read DRAM command RD DATA CMD and a read DRAM ECC command RD ECC CMD according to the read command RD CMD, generates a write DRAM command WR DATA CMD and a write DRAM ECC command WR ECCCMD according to the write command WR CMD, and distributes the generated commands to the task scheduling unit; DRAM data correction module CORRECTOR, the internal address generator generates a read command RD CMD, and caches the read command RD CMD in the internal COR RD CMD FIFO, when the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg are all empty, the cached read command RD CMD is sent to the address mapping module ADDRMAP.

[0021] Specifically, if Figure 1 As shown, the address mapping module ADDR MAP includes the following modules: The read-modify-write command generating module RMW GEN converts the read command RD CMD / write command WR CMD into a read-modify-write command RMW when the AXI system address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit is not aligned with the 64-bit data or the data bytes in the 64-bit data are masked. The command is decomposed by the address mapping module ADDR MAP into two read commands RD CMD and write commands WR CMD with the same and aligned addresses; The command generation module ECC CMD GEN generates a DRAM read command RD DATA CMD and a DRAM ECC read command RD ECC CMD according to the read command RD CMD generated by the AXI port arbitration unit or the read command RD CMD generated by the DRAM data correction module CORRECTOR or the read command RDCMD decomposed by the address mapping module ADDR MAP, and generates a DRAM write command WRDATA CMD and a DRAM ECC write command WR ECC CMD according to the write command WR CMD generated by the AXI port arbitration unit or the write command WR CMD decomposed by the address mapping module ADDR MAP; The command allocation module BLOCK MAP allocates the commands generated by the command generation module ECC CMD GEN to the task scheduling unit.

[0022] Specifically, for the command allocation module BLOCK MAP: When the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the command is X. If there is already a channel with the block address X, and the read command RD CMD indication flag Read and the channel valid flag valid are both 1, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD generated according to the read command RD CMD and the block tag Btoken that has been allocated to the channel to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the command is X. If there is already a channel with the block address X, and the read command RD CMD indication flag Read is 0, and the channel valid flag valid is 1, the read command RD CMD indication flag Read is set to 1, and in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the block tag Btoken that has been allocated to the channel to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, but there is a channel with a channel valid flag valid being 0, the channel is used, and a new block tag Btoken is allocated, the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECCCMD generated according to the read command RD CMD, as well as the newly allocated block tag Btoken to the first command cache module RD Page FIFO in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block tag Btoken is allocated, and the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1. In the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the newly allocated block tag Btoken to the first command cache module RDPage FIFO, and the write pointer wp is increased by 1; When the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the command is X. If there is already a channel with the block address X, and the write command WR CMD indication flag Write and the channel valid flag valid are both 1, the address mapping module ADDR MAP will send the write DRAM command WR DATA CMD generated according to the write command WR CMD and the block tag Btoken that has been allocated to the channel to the second command buffer module WR Page FIFO; When the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the command is X. If there is already a channel with the block address X, and the write command WR CMD indication flag Write is 0, and the channel valid flag valid is 1, the write command WR CMD indication flag Write is set to 1, and in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the block tag Btoken that has been allocated to the channel to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, but there is a channel with a channel valid flag valid being 0, the channel is used, and a new block tag Btoken is allocated, the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECCCMD generated according to the write command WR CMD, as well as the newly allocated block tag Btoken to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1. In the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg, and the write pointer wp is incremented by 1.

[0023] like Figure 2 As shown, the command allocation module BLOCK MAP includes 16 channels. The channel structure has a write pointer wp, which is used to indicate the channel to be covered. The structure of each channel is the same, specifically including: block address block address, block tag Btoken, read command RD CMD indication flag Read, write command WR CMD indication flag Write, channel valid flag valid; After the command allocation module BLOCK MAP is reset, the channel valid flags of all channels are invalid, that is, valid=0, and the write pointer wp points to the first channel Channel 0.

[0024] ② If Figure 1 As shown, the task scheduling unit includes the following modules: The first command buffer module RD Page FIFO buffers the DRAM read command RD DATA CMD and the DRAM ECC read command RD ECC CMD, and buffers the command in the corresponding FIFO according to the Page information of the command; The second command buffer module WR Page FIFO buffers the DRAM write command WR DATA CMD and buffers the command in the corresponding FIFO according to the Page information of the command; The third command cache module WR ECC CMD Reg caches the write DRAM ECC command WR ECC CMD. The write DRAM ECC command WR ECCCMD can be sent only after the write DRAM command WR DATA CMD with the same block tag Btoken is sent. The commands with the same block tag Btoken in the third command cache module WR ECC CMD Reg are write-merged in the order of the corresponding write DRAM command WR DATA CMD that has been sent. The task scheduling module Task SCH schedules the commands cached in the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg according to the priority, and prioritizes all commands corresponding to the block tag Btoken of the covered channels in the command allocation module BLOCK MAP, and then schedules the read DRAM command RDDATA CMD, read DRAM ECC command RD ECC CMD and write DRAM command WR DATA CMD corresponding to the block tag Btoken of the uncovered channels in the command allocation module BLOCK MAP, and finally schedules the write DRAM ECC command WR ECC CMD.

[0025] like Figure 3 As shown in the figure, 1 Page is a storage page of DRAM, 1 Page is divided into 8 equal parts, the first 7 equal parts of 1 Page are used to store data, each of which is 1 block, 1 block is the data size of eight burst transmissions, 1 block is divided into 8 equal parts, each part of 1 block is 1 access, 1 access is the data size of one burst transmission; The last part of a Page is used to store the data check code ECC. The data of one block corresponds to one data check code ECC.

[0026] ③ Such as Figure 1 As shown, the command decoding unit includes the following modules: The main state machine Main FSM controls the controller mode switching, caches the commands scheduled by the task scheduling module Task SCH, and decodes the commands; The command selection module CMD MUX switches between the commands decoded by the main state machine Main FSM, Active commands, and Precharge commands; A data buffer module WR Buffer, which buffers the write data of the write DRAM command WR DATA CMD; A fourth command buffer module CMD Buffer, which buffers the command selected by the command selection module CMD MUX; The command decoding module CMD decode decodes the command buffered in the fourth command buffer module CMD Buffer into a standard DFI interface signal, and sends the signal to the physical interface conversion module PHY to complete the conversion of the digital interface signal to the analog interface signal.

[0027] ④ Such as Figure 1 As shown, the data verification unit includes the following modules: The write data encoding module ENCODER calculates the corresponding data check code ECC according to the write data of the write DRAM command WR DATA CMD, and obtains the write data check code WR DATA ECC corresponding to the write DRAM ECC command WR ECC CMD; The write data cache module WECC REG caches the write data check code WR DATA ECC generated by the write data encoding module ENCODER. When sending the write DRAM ECC command WR ECC CMD, if the write data check code WR DATA ECC that is the same as the block tag Btoken of the command is ready at this time, and the read data check code RECC DATA with the same block tag Btoken exists in the read data cache module RECC REG, then the write data corresponding to the write DRAM ECC command WR ECC CMD is the concatenated data of the write data check code WR DATA ECC and the read data check code RECC DATA with the same block tag Btoken, and the write DRAM ECC command WR ECC CMD is converted into a complete burst command. The tag cache module RD token FIFO caches the tag of the DRAM read command RD DATA CMD. When the read data corresponding to the DRAM read command RD DATA CMD is returned, the corresponding tag is popped out. The tag includes AXI token and block tag Btoken. The read data decoding module DECODER calculates the corresponding data check code ECC according to the read data of the read DRAM command RD DATA CMD, obtains the read data check code RD DATA ECC, and sends it to the comparator COMP; The read data cache module RECC REG, in the case of a write-after-read command with the same block tag Btoken, the internal data may have expired, and the read data data check code RECC DATA in the read data cache module RECC REG and the write data data check code WR DATA ECC in the write data cache module WECC REG are concatenated and sent to the comparator COMP, and at the same time, the write data data check code WR DATA ECC in the write data cache module WECC REG is updated to the read data data check code RECC DATA in the read data cache module RECC REG; The comparator COMP compares the read data check code RD DATA ECC sent by the read data decoding module DECODER with the read data check code RECC DATA sent by the read data buffer module RECC REG.

[0028] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-performance Inline ECC implementation system, characterized by: The following units are included: AXI port arbitration unit, completes multi-AXI port arbitration; The address mapping unit completes the mapping of AXI system addresses to DRAM addresses, as well as the generation and allocation of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; A task scheduling unit, which completes the caching and scheduling of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; The command decoding unit completes command decoding and converts the command into a standard DFI interface signal; The data verification unit completes read data verification and write data verification.

2. The high-performance Inline ECC implementation system according to claim 1, characterized in that: The address mapping unit includes the following modules: The address mapping module ADDR MAP maps the addresses of the read command RD CMD and the write command WR CMD from the AXI system address to the DRAM address, and generates a read-modify-write command RMW according to the address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit, generates a read DRAM command RD DATA CMD and a read DRAM ECC command RDECC CMD according to the read command RD CMD, generates a write DRAM command WR DATA CMD and a write DRAM ECC command WR ECC CMD according to the write command WR CMD, and distributes the generated commands to the task scheduling unit; DRAM data correction module CORRECTOR, the internal address generator generates a read command RD CMD, and caches the read command RDCMD in the internal COR RD CMD FIFO, when the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg are all empty, the cached read command RD CMD is sent to the address mapping module ADDR MAP.

3. The high-performance Inline ECC implementation system according to claim 2, characterized in that: The address mapping module ADDR MAP includes the following modules: The read-modify-write command generating module RMW GEN converts the read command RDCMD / write command WR CMD into a read-modify-write command RMW when the AXI system address of the read command RD CMD / write command WRCMD generated by the AXI port arbitration unit is not aligned with the 64-bit data or the data bytes in the 64-bit data are masked. The command is decomposed into two read commands RD CMD and write commands WR CMD with the same and aligned addresses by the address mapping module ADDR MAP; The command generation module ECC CMD GEN generates a DRAM read command RD DATA CMD and a DRAM ECC read command RD ECC CMD according to the read command RD CMD generated by the AXI port arbitration unit or the read command RD CMD generated by the DRAM data correction module CORRECTOR or the read command RD CMD decomposed by the address mapping module ADDR MAP, and generates a DRAM write command WR DATACMD and a DRAM ECC write command WR ECC CMD according to the write command WR CMD generated by the AXI port arbitration unit or the write command WR CMD decomposed by the address mapping module ADDR MAP; The command allocation module BLOCK MAP allocates the commands generated by the command generation module ECC CMD GEN to the task scheduling unit.

4. The high-performance Inline ECC implementation system according to claim 3, characterized in that: When the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the command is X. If a channel with block address X already exists, and the read command RD CMD indication flag Read and the channel valid flag valid are both 1, the address mapping module ADDRMAP sends the read DRAM command RD DATA CMD generated according to the read command RD CMD and the block tag Btoken that has been allocated to the channel to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the command is X. If there is already a channel with the block address X, and the read command RD CMD indication flag Read is 0, and the channel valid flag valid is 1, the read command RD CMD indication flag Read is set to 1, and in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the block tag Btoken that has been allocated to the channel to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, but there is a channel with a channel valid flag valid being 0, the channel is used, and a new block tag Btoken is allocated, the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1, and the address mapping module ADDRMAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the newly allocated block tag Btoken to the first command cache module RD Page FIFO in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1. In the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the newly allocated block label Btoken to the first command cache module RDPage FIFO, and the write pointer wp is incremented by 1.

5. The high-performance Inline ECC implementation system according to claim 4, characterized in that: When the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the command is X. If a channel with block address X already exists, and the write command WR CMD indication flag Write and the channel valid flag valid are both 1, the address mapping module ADDRMAP sends the write DRAM command WR DATA CMD generated according to the write command WR CMD and the block tag Btoken that has been allocated to the channel to the second command buffer module WR Page FIFO; When the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the command is X. If there is already a channel with the block address X, and the write command WR CMD indication flag Write is 0, and the channel valid flag valid is 1, the write command WR CMD indication flag Write is set to 1, and the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the block tag Btoken that has been allocated to the channel to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, but there is a channel with a channel valid flag valid being 0, the channel is used, and a new block tag Btoken is allocated, the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECCCMD generated according to the write command WR CMD, as well as the newly allocated block tag Btoken to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1. In the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg, and the write pointer wp is incremented by 1.

6. The high-performance Inline ECC implementation system according to any one of claims 3 to 5, characterized in that: The command allocation module BLOCK MAP includes 16 channels. The channel structure has a write pointer wp, which is used to indicate the channel to be covered. The structure of each channel is the same, specifically including: block address block address, block tag Btoken, read command RD CMD indication flag Read, write command WR CMD indication flag Write, channel valid flag valid; After the command allocation module BLOCK MAP is reset, the channel valid flags of all channels are invalid, that is, valid=0, and the write pointer wp points to the first channel Channel 0.

7. The high-performance Inline ECC implementation system according to claim 3, characterized in that: The task scheduling unit includes the following modules: The first command buffer module RD Page FIFO buffers the DRAM read command RD DATA CMD and the DRAM ECC read command RDECC CMD, and buffers the command in the corresponding FIFO according to the Page information of the command; The second command buffer module WR Page FIFO buffers the DRAM write command WR DATA CMD and buffers the command in the corresponding FIFO according to the Page information of the command; The third command cache module WR ECC CMD Reg caches the write DRAM ECC command WR ECC CMD. The write DRAM ECC command WR ECC CMD can be sent only after the write DRAM command WR DATA CMD with the same block tag Btoken is sent. The commands with the same block tag Btoken in the third command cache module WR ECC CMD Reg are write-merged in the order of the corresponding write DRAM command WR DATA CMD that has been sent. The task scheduling module Task SCH schedules the commands cached in the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg according to the priority, and prioritizes all commands corresponding to the block tag Btoken of the covered channels in the command allocation module BLOCK MAP, and then schedules the read DRAM command RD DATACMD, read DRAM ECC command RD ECC CMD and write DRAM command WR DATA CMD corresponding to the block tag Btoken of the uncovered channels in the command allocation module BLOCK MAP, and finally schedules the write DRAM ECC command WRECC CMD.

8. The high-performance Inline ECC implementation system according to claim 7, characterized in that: 1 Page is a storage page of DRAM. 1 Page is divided into 8 equal parts. The first 7 equal parts of 1 Page are used to store data, each of which is 1 block. 1 block is the data size of eight burst transmissions. 1 block is divided into 8 equal parts. Each equal part of 1 block is 1 access. 1 access is the data size of one burst transmission. The last part of a Page is used to store the data check code ECC. The data of one block corresponds to one data check code ECC.

9. The high-performance Inline ECC implementation system according to claim 7, characterized in that: The command decoding unit includes the following modules: The main state machine Main FSM controls the controller mode switching, caches the commands scheduled by the task scheduling module Task SCH, and decodes the commands; The command selection module CMD MUX switches between the commands decoded by the main state machine Main FSM, Active commands, and Precharge commands; A data buffer module WR Buffer, which buffers the write data of the write DRAM command WR DATA CMD; A fourth command buffer module CMD Buffer, which buffers the command selected by the command selection module CMD MUX; The command decoding module CMD decode decodes the command buffered in the fourth command buffer module CMD Buffer into a standard DFI interface signal, and sends the signal to the physical interface conversion module PHY to complete the conversion of the digital interface signal to the analog interface signal.

10. The high-performance Inline ECC implementation system according to claim 9, characterized in that: The data verification unit includes the following modules: The write data encoding module ENCODER calculates the corresponding data check code ECC according to the write data of the write DRAM command WR DATA CMD, and obtains the write data check code WR DATA ECC corresponding to the write DRAM ECC command WR ECC CMD; The write data cache module WECC REG caches the write data check code WRDATA ECC generated by the write data encoding module ENCODER. When sending the write DRAM ECC command WR ECC CMD, if the write data check code WR DATA ECC that is the same as the block tag Btoken of the command is ready, and the read data check code RECC DATA with the same block tag Btoken exists in the read data cache module RECC REG, then the write data corresponding to the write DRAM ECC command WR ECC CMD is the concatenated data of the write data check code WR DATA ECC and the read data check code RECC DATA with the same block tag Btoken, and the write DRAM ECC command WR ECC CMD is converted into a complete burst command. The tag cache module RD token FIFO caches the tag of the DRAM read command RD DATA CMD. When the read data corresponding to the DRAM read command RDDATA CMD is returned, the corresponding tag is popped out. The tag includes AXI token and block tag Btoken. The read data decoding module DECODER calculates the corresponding data check code ECC according to the read data of the read DRAM command RD DATA CMD, obtains the read data check code RD DATA ECC, and sends it to the comparator COMP; The read data cache module RECC REG, in the case of a write-after-read command with the same block tag Btoken, the internal data may have expired, and the read data data check code RECC DATA in the read data cache module RECC REG and the write data data check code WR DATA ECC in the write data cache module WECC REG are concatenated and sent to the comparator COMP, and at the same time, the write data data check code WR DATA ECC in the write data cache module WECC REG is updated to the read data data check code RECC DATA in the read data cache module RECC REG; The comparator COMP compares the read data check code RD DATA ECC sent by the read data decoding module DECODER with the read data check code RECC DATA sent by the read data buffer module RECC REG.

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