Data access control method of memory device, memory controller, memory device and electronic device

Abstract

The invention relates to a method for performing data access control of a memory device, a memory control cuckoo, a memory device and an electronic device. The method includes: receiving a host command from a host device to perform data access to a non-volatile memory according to the host command, the data access including data reading; and performing a read optimization procedure to maintain the correctness of data reading, for example: performing a read operation to obtain a channel value; compressing the channel values to convert the first soft bit in any channel value into a second soft bit to generate a compressed channel value; reading a plurality of compressed channel values from the volatile memory; and performing low density parity check (LDPC) decoding according to the plurality of compressed channel values by using a low density parity check (LDPC) decoding engine circuit, and performing an error recovery operation according to the channel values by using an error recovery circuit to generate error-free read data.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method for performing data access control on a memory device and related apparatus such as the memory device, a memory controller in the memory device, and an electronic device including the memory device. Background Art

[0002] A memory device may include a flash memory for storing data, and access management for the flash memory is quite complex. For example, the memory device may be a memory card, a solid state drive (SSD), or an embedded storage device (e.g., an embedded storage device that complies with the universal flash storage specification (UFS)). When manufacturers try to use downgraded flash memory dies to reduce overall costs, certain problems may occur. In particular, the associated characteristics of downgraded flash memory dies are unstable and data errors are prone to occur, which may lead to a decrease in the overall performance of the memory device. Related technologies attempt to solve this problem, however, additional problems such as certain side effects may be introduced. Therefore, a novel method and related architecture are needed to solve these problems without introducing side effects or in a manner that is less likely to introduce side effects. Summary of the invention

[0003] One of the objectives of the present invention is to provide a method for performing data access control on a memory device and related apparatus such as the memory device, a memory controller in the memory device and an electronic device including the memory device to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for controlling data access of a memory device, wherein the method can be applied to a memory controller of the memory device, the memory device can include the memory controller and a non-volatile (NV) memory, and the NV memory can include at least one NV memory element (e.g., one or more NV memory elements). The method can include: receiving a plurality of host commands from a host device for performing data access to the NV memory according to the plurality of host commands, wherein the data access includes data reading; and performing a read optimization procedure in response to at least one read command to maintain the correctness of the data reading, wherein the plurality of host commands include the at least one read command. For example, the read optimization procedure may include: performing at least one read operation on the NV memory through at least one channel of the plurality of channels to obtain a plurality of channel values, wherein any channel value of the plurality of channel values ​​comprises a sign bit and a plurality of first soft bits; performing at least one compression operation on the plurality of channel values ​​to convert the plurality of first soft bits of the any channel value into a plurality of second soft bits to generate a compressed channel value corresponding to the any channel value for buffering in a volatile memory in the memory controller, wherein a second bit number of the plurality of second soft bits is less than a first bit number of the plurality of first soft bits; reading the plurality of compressed channel values ​​respectively corresponding to the plurality of channel values ​​from the volatile memory for low-density parity-check (LDPC) code decoding; and performing the low-density parity-check code decoding according to the plurality of compressed channel values ​​by using a low-density parity-check code decoding engine circuit, and performing the low-density parity-check code decoding according to the plurality of compressed channel values ​​by using an error recovery (ERR) circuit. A read / recovery circuit performs at least one error recovery operation according to the plurality of channel values ​​to generate error-free read data for transmission back to the host device.

[0005] In addition to the above method, the present invention also provides a memory controller of a memory device, wherein the memory device includes the memory controller and an NV memory, and the NV memory may include at least one NV memory element (e.g., one or more NV memory elements). In addition, the memory controller includes a processing circuit and a transmission interface circuit, wherein the processing circuit is used to control the memory controller according to a plurality of host commands from a host device to allow the host device to access the NV memory through the memory controller, and the transmission interface circuit is used to communicate with the host device. In addition, the memory controller receives the plurality of host commands from the host device through the transmission interface circuit in the memory controller for data access to the NV memory according to the plurality of host commands, wherein the data access includes data reading. In response to at least one read command, the memory controller performs a read optimization procedure to maintain the correctness of the data reading, wherein the plurality of host commands include the at least one read command. For example, the read optimization procedure may include: performing at least one read operation on the NV memory through at least one channel of the plurality of channels to obtain a plurality of channel values, wherein any channel value of the plurality of channel values ​​comprises a sign bit and a plurality of first soft bits; performing at least one compression operation on the plurality of channel values ​​to convert the plurality of first soft bits of the any channel value into a plurality of second soft bits to generate a compressed channel value corresponding to the any channel value for buffering in a volatile memory in the memory controller, wherein a second bit number of the plurality of second soft bits is less than a first bit number of the plurality of first soft bits; reading the plurality of compressed channel values ​​respectively corresponding to the plurality of channel values ​​from the volatile memory for LDPC decoding; and performing the LDPC decoding according to the plurality of compressed channel values ​​by a LDPC decoding engine circuit and performing at least one error recovery operation according to the plurality of channel values ​​by an error recovery circuit to generate error-free read data for transmission back to the host device.

[0006] In addition to the above method, the present invention also provides a memory device including the above memory controller, wherein the memory device includes: the NV memory for storing information; and the memory controller coupled to the NV memory and used to control the operation of the memory device.

[0007] In addition to the above method, the present invention also provides an electronic device including the above memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the memory device. In addition, the memory device provides storage space for the host device.

[0008] The method and related apparatus of the present invention can ensure that the memory device can operate properly under different circumstances, in particular, can ensure the correctness of the read data. Although the relevant characteristics of the degraded flash memory die are unstable, the method and related apparatus of the present invention can perform at least one read retry operation to obtain relevant information for soft decoding, and perform the above-mentioned at least one error recovery operation to eliminate any errors caused by different memory cells and perform at least one equalization operation to combat inter-symbol interference (ISI), so as to solve the problems of the related art without introducing side effects or in a way that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0010] Figure 2 FIG. 4 is a schematic diagram of multiple LDPC code decoding control schemes according to some embodiments of the present invention.

[0011] Figure 3 The diagram is a schematic diagram of a channel value processing control scheme of a method for performing data access control of a memory device according to an embodiment of the present invention.

[0012] Figure 4A A plurality of sign bits involved in the method are illustrated according to an embodiment of the present invention.

[0013] Figure 4B A sign bit and a plurality of soft bits involved in the method are illustrated according to an embodiment of the present invention.

[0014] Figure 5A A schematic diagram of a compression processing control scheme of the method is shown according to an embodiment of the present invention.

[0015] Figure 5B According to an embodiment of the present invention, Figure 5A The lower half of FIG. 4 shows multiple candidate groups of bits and some associated probabilities.

[0016] Figure 6 According to an embodiment of the present invention, a compression mapping function involved in the compression processing control scheme of the method is illustrated.

[0017] Fig. 7A According to an embodiment of the present invention, a target memory cell and a plurality of helper memory cells involved in the method are illustrated.

[0018] Figure 7B According to another embodiment of the present invention, a target memory cell and a plurality of helper memory cells involved in the method are illustrated.

[0019] Figure 7C According to another embodiment of the present invention, a target memory cell and a plurality of helper memory cells involved in the method are illustrated.

[0020] Fig. 8A According to an embodiment of the present invention, a disturbed programming state of a target memory cell and a programming state of a helper memory cell involved in an error recovery control scheme of the method are illustrated, wherein the non-disturbed programming state of the target memory cell is also illustrated. Fig. 8A For easier understanding.

[0021] Figure 8B The error recovery involved in the error recovery control scheme of the method is illustrated according to an embodiment of the present invention, wherein the disturbed programming state and the non-disturbed programming state of the target memory cell and the programming state of the helper memory cell are illustrated in FIG. Figure 8B For easier understanding.

[0022] Figure 8C According to an embodiment of the present invention, multiple stages involved in the error recovery control scheme of the method are illustrated.

[0023] Fig. 9 A decision feedback equalization (DFE) control scheme of the method is illustrated according to an embodiment of the invention.

[0024] Fig.10 A processing result of the method is illustrated according to an embodiment of the present invention.

[0025] Fig.11 A workflow of a read optimization procedure of the method is described according to an embodiment of the present invention.

[0026]

Explanation of symbols

[0027] 10: Electronic devices

[0028] 50: Host device

[0029] 52: Processor

[0030] 54: Power supply circuit

[0031] 58: Transmission interface circuit

[0032] 100: memory device

[0033] 110: memory controller

[0034] 112: Microprocessor

[0035] 112C: Program code

[0036] 112M: Read-only memory

[0037] 114: Control logic circuit

[0038] 114D,230_i: Low-density parity check (LDPC) code decoding circuit

[0039] 114E: Equalizer Circuit

[0040] 114M, 220_i: Log-likelihood ratio (LLR) mapping circuit

[0041] 114R: Error recovery circuit

[0042] 116: Random Access Memory

[0043] 116AM: Temporary logical to physical (L2P) address mapping table

[0044] 118: Transmission interface circuit

[0045] 120: Non-volatile (NV) memory

[0046] 120C: Memory Cells

[0047] 120AM: Global logical to physical (L2P) address mapping table

[0048] 122-1~122-N E :Non-volatile (NV) memory devices

[0049] 201_i, 202_i: Low-density parity check (LDPC) code decoding engine circuit

[0050] 208_i: Quantization compression circuit

[0051] 211_i,212_i: memory

[0052] 704,708,710,720: Memory cells related to error recovery

[0053] B0~B5,B1',B2':bit

[0054] CH(i): Channel

[0055] CV: Channel value

[0056] MR: Memory Region

[0057] Phase(0)~Phase(3): Phase

[0058] P1~P8: Programming status

[0059] Sign_bit(0)~Sign_bit(2),Sign_bit(j): Sign bit

[0060] Soft_bit_org(j,k),Soft_bit_new(j,k): soft bit

[0061] Soft_Info_org,Soft_Info_new:Soft Information

[0062] t: time

[0063] Vth: threshold voltage

[0064] Avg_Latency: average latency

[0065] Cycle:

[0066] RBER: Raw Bit Error Rate

[0067] S11~S14: Steps DETAILED DESCRIPTION

[0068] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; which may be collectively referred to as a processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other through a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the host device 50, and may obtain the one or more driving voltages from the host device 50 as a power source for the memory device 100. Examples of the host device 50 may include, but are not limited to: a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include, but are not limited to, portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS or XD specifications, solid state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices conforming to the Universal Flash Storage (UFS) specification or the embedded multi-media card (eMMC) specification). According to the present embodiment, the memory device 100 may include a controller such as a memory controller 110, and may further include a non-volatile (NV) memory 120 (abbreviated as “NV memory”), wherein the memory controller 110 is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of non-volatile (NV) memory elements 122-1, 122-2, ..., and 122-N. E (abbreviated as “NV memory element”), where “NV E " may represent a positive integer greater than 1. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be E It may be a plurality of flash memory chips or a plurality of flash memory bare dies, but the present invention is not limited thereto.

[0069] like Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (which can be implemented by a static random access memory (SRAM) for example) and a transmission interface circuit 118, wherein at least a portion (for example, a portion or all) of the above components can be coupled to each other through a bus. The random access memory 116 can be used to provide internal storage space to the memory controller 110 (for example, temporarily storing information), but the present invention is not limited to this. In addition, the read-only memory 112M of this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the NV memory 120. Please note that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the NV memory 120. The transmission interface circuit 118 may comply with one or more communication specifications among different communication specifications (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, embedded multimedia card specification, or universal flash storage specification), and may enable the memory device 100 to communicate with the host device 50 (or its transmission interface circuit 58) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 may comply with the one or more communication specifications, and may enable the host device 50 to communicate with the memory device 100 (or its transmission interface circuit 118) according to the one or more communication specifications.

[0070] In the present embodiment, the host device 50 can indirectly access the NV memory 120 in the memory device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and corresponding logical addresses, and converts the plurality of host commands into a plurality of memory operation commands (which may be referred to as operation commands), and then uses the plurality of operation commands to control the NV memory 120 to read or write / program the memory cells or data pages of the corresponding physical addresses in the NV memory 120, etc., wherein the physical addresses may be associated with the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses, wherein the NV memory 120 may store a global logical-to-physical address mapping table 120AM for the memory controller 110 to control the memory device 100 to access the data in the NV memory 120, but the present invention is not limited thereto.

[0071] For better understanding, the global logical to physical address mapping table 120AM may be located in a predetermined area (e.g., a system area) within the NV memory 122-1 element, but the present invention is not limited thereto. For example, the global logical to physical address mapping table 120AM may be divided into a plurality of local logical to physical address mapping tables, and the plurality of local logical to physical address mapping tables may be stored in the NV memory elements 122-1, 122-2, and 122-N. E In the one or more NV memory elements, in particular, the NV memory elements 122-1, 122-2 and 122-N may be stored respectively. E When necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global logical-to-physical address mapping table 120AM into the random access memory 116 or other memory. For example, the memory controller 110 may load a local logical-to-physical address mapping table among the multiple local logical-to-physical address mapping tables into the random access memory 116 as a temporary logical-to-physical address mapping table 116AM, so as to access data in the NV memory 120 according to the local logical-to-physical address mapping table stored as the temporary logical-to-physical address mapping table 116AM, but the present invention is not limited thereto.

[0072] In addition, the at least one NV memory element (eg, the one or more NV memory elements, such as {122-1, 122-2, ..., 122-N E}) may include a plurality of blocks {BLK}, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the NV memory 120 is a block, and the minimum unit for the memory controller 110 to perform a data write operation on the NV memory 120 is a page, but the present invention is not limited thereto. For example, the NV memory elements 122-1, 122-2, ... and 122-N E Any NV memory element 122-n E (Symbol “n E " can represent the interval [1,N E ] may include multiple blocks, and a block within the multiple blocks may include and record a specific number of pages, wherein the memory controller 110 may access a page of a block within the multiple blocks according to a block address and a page address.

[0073] According to some embodiments, the control logic circuit 114 may include a randomization circuit and an error correction code (ECC) circuit (not shown). Figure 1 ), wherein the randomization circuit may perform a randomization operation on write data (e.g., data to be written to the NV memory 120 during a write / programming operation on the NV memory 120 in response to a write command from the host device 50) and de-randomize read data (e.g., data read from the NV memory 120 during a read operation on the NV memory 120 in response to a read command from the host device 50), and the ECC circuit may perform an ECC encoding on the write data and an ECC decoding on the read data to protect the data and / or perform error correction, but the present invention is not limited thereto. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E This may be implemented by using a degraded flash memory die. In this case, the ECC decoding may not be successful, and in particular, uncorrectable ECC (UECC) errors may easily occur. The memory controller 110 may have a more robust reading mechanism to avoid the high error rate that may be caused by using a degraded flash memory die.

[0074] The control logic circuit 114 may include a plurality of read processing sub-circuits to provide the above-mentioned more robust read mechanism, and the plurality of read processing sub-circuits may include a log-likelihood ratio (LLR) mapping circuit 114M and a low-density parity-check (LDPC) code (LDPC code) decoding circuit 114D (referred to as “LLR mapping circuit” and “LDPC code decoding circuit”, respectively), wherein the LLR mapping circuit 114M may perform a correlation mapping operation on the read data buffered in at least one memory region MR to allow the LDPC code decoding circuit 114D to perform a correlation decoding operation to obtain correct data for transmission back to the host device 50, but the present invention is not limited thereto. According to some embodiments, Figure 1 The illustrated architecture may be varied. For example, at least a portion (e.g., a portion or all) of the plurality of read processing sub-circuits, such as the LLR mapping circuit 114M and the LDPC code decoding circuit 114D, may be integrated into at least one other circuit (not the control logic circuit 114). In addition, during a read operation of the NV memory 120 in response to a read command from the host device 50, the memory controller 110 may obtain a plurality of channel values ​​{CV} from the NV memory 120 through at least one channel CH (e.g., one or more channels {CH}, such as a plurality of channels {CH(i)}) for the plurality of read processing sub-circuits to perform correlation processing to obtain correct data.

[0075] Figure 2 A schematic diagram of a plurality of LDPC code decoding control schemes according to some embodiments of the present invention, wherein the plurality of LDPC code decoding control schemes include a first LDPC code decoding control scheme and a second LDPC code decoding control scheme. Figure 2According to the first LDPC code decoding control scheme shown in the upper half of the memory controller 110, the multiple read processing sub-circuits within the memory controller 110 may include at least one LDPC code decoding engine circuit 201_i corresponding to the above-mentioned at least one channel CH, and in particular, may include multiple LDPC code decoding engine circuits {201_i} corresponding to the multiple channels {CH(i)}, such as I LDPC code decoding engine circuits {201_i|i=1,…,I} corresponding to I channels {CH(i)|i=1,…,I} (for example, "I" can represent any positive integer greater than one). For example, any one of the plurality of LDPC code decoding engine circuits {201_i} may include a volatile memory such as a memory 211_i, an LLR mapping circuit 220_i, and an LDPC code decoding circuit 230_i, and may be coupled to the NV memory 120 to obtain m bits per value (m bits per value; at Figure 2 A set of channel values ​​{CV} (denoted as "m bits / value" for simplicity) is provided for correlation processing. Any channel value CV in the set of channel values ​​{CV} may include a sign bit and a plurality of first soft bits, such as (m-1) first soft bits.

[0076] The memory controller 110 may perform at least one read operation on the NV memory 120 through the channel CH(i) to obtain the set of channel values ​​{CV} for buffering in the volatile memory such as the memory 211_i, and utilize the LLR mapping circuit 220_i to read the set of channel values ​​{CV} from the memory 211_i, and perform an LLR mapping operation on the set of channel values ​​{CV} to generate a set of p bits per value (p bits per value; Figure 2 The LDPC code decoding circuit 230_i performs at least one LDPC code decoding operation according to the set of LLR values ​​to generate correct read data for transmission back to the host device 50. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E The memory controller 110 may perform a read retry procedure to obtain soft information such as the soft bits of the channel values ​​{CV} for soft decoding such as LDPC code decoding to avoid the high error rate caused by using the degraded flash memory die.

[0077] based on Figure 2According to the second LDPC code decoding control scheme shown in the lower half of the figure, the multiple read processing sub-circuits in the memory controller 110 may include at least one LDPC code decoding engine circuit 202_i corresponding to the above-mentioned at least one channel CH, and in particular, may include multiple LDPC code decoding engine circuits {202_i} corresponding to the multiple channels {CH(i)}, such as I LDPC code decoding engine circuits {202_i|i=1,…,I} corresponding to I channels {CH(i)|i=1,…,I}, respectively. For example, any one of the plurality of LDPC code decoding engine circuits {202_i} may include a compression circuit such as a quantization compression circuit 208_i, a volatile memory such as a memory 212_i, the LLR mapping circuit 220_i, and the LDPC code decoding circuit 230_i, and may be coupled to the NV memory 120 to obtain a data value having m bits per value (at Figure 2 A set of channel values ​​{CV} (denoted as “m bits / value” for simplicity), such as the same set of channel values ​​{CV} mentioned in the first LDPC code decoding control scheme, is provided for related processing, but the present invention is not limited thereto.

[0078] The memory controller 110 may perform at least one read operation on the NV memory 120 through the channel CH(i) to obtain the set of channel values ​​{CV}, and use the quantization compression circuit 208_i to perform at least one compression operation on the set of channel values ​​{CV} to convert a plurality of first soft bits in any channel value CV in the set of channel values ​​{CV} into a plurality of second soft bits, so as to generate a compressed channel value CV corresponding to the any channel value CV. COMPRESSED , for buffering in the volatile memory such as the memory 212_i, wherein any of the channel values ​​CV may include a sign bit and the plurality of first soft bits such as (m-1) first soft bits, and the compressed channel value CV COMPRESSED The memory 212_i may include the sign bit and the plurality of second soft bits, such as (n-1) second soft bits, and the bit count of the plurality of second soft bits (e.g., the soft bit count (n-1)) is less than the bit count of the plurality of first soft bits (e.g., the soft bit count (m-1)). Thus, the memory 212_i may have buffered the n bits per value (nbits per value; at Figure 2 A set of compressed channel values ​​{CV COMPRESSEDIn addition, the memory controller 110 may use the LLR mapping circuit 220_i to read the set of compressed channel values ​​{CV} respectively corresponding to the set of channel values ​​{CV} from the memory 212_i. COMPRESSED}, and for this set of compressed channel values ​​{CV COMPRESSED} Perform LLR mapping operation to generate a value with p bits per value (in Figure 2 The LDPC code decoding circuit 230_i performs at least one LDPC code decoding operation according to the set of LLR values ​​to generate correct read data for transmission back to the host device 50. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E The memory controller 110 may perform the read retry procedure to obtain the soft information (e.g., the soft bits of the set of channel values ​​{CV}), and in particular, compress the soft information to generate compressed soft information (e.g., the set of compressed channel values ​​{CV}). COMPRESSED} respectively carry soft bits) for soft decoding such as LDPC code decoding to avoid the high error rate that may be caused by using degraded flash memory bare crystals.

[0079] Compared with the first LDPC code decoding control scheme, the second LDPC code decoding control scheme can save memory space. In particular, the ratio of the size of the total memory space of the memory {212_i|i=1,…,I} to the size of the total memory space of the memory {211_i|i=1,…,I} can be equal to (n / m), regardless of whether the memory {211_i|i=1,…,I} and the memory {212_i|i=1,…,I} are implemented by the above-mentioned at least one memory region MR (e.g., one or more memory regions {MR}, such as I memory regions {MR(i)|i=1,…,I}) or by a dedicated memory (e.g., other random access memory). For example, when m=6 and n=3, the above-mentioned ratio (n / m) can be equal to (1 / 2), but the present invention is not limited thereto. In some examples, the number of bits m, the number of bits n, and / or the ratio (n / m) can be changed. According to some embodiments, any of the above LLR values ​​may be expressed as follows:

[0080] LLR {B’} =ln(L(θ0|x) / L(θ1|x));…………………………………………Eq(1)

[0081] Where “L()” may represent the probability function, “L(θ0|x)” may represent the probability that the sign bit is equal to 0, “L(θ1|x)” may represent the probability that the sign bit is equal to 1, and “LLR {B’} " may represent any of the above LLR values ​​(eg, an LLR value when the soft bit is equal to a set of soft bits {B'} such as bits {B1', ..., B(n-1)'}), but the present invention is not limited thereto.

[0082] According to some embodiments, the memory controller 110 may receive the plurality of host commands from the host device 50 through the transmission interface circuit 118 in the memory controller 110, so as to perform data access to the NV memory 120 according to the plurality of host commands, wherein the data access may include data reading. In addition, in response to at least one read command among the plurality of host commands, the memory controller 110 may perform a read optimization procedure to maintain the correctness of the data reading. For example, the read optimization procedure may include the above operations of the LDPC code decoding engine circuit 201_i, and in particular, may include similar operations of the I LDPC code decoding engine circuits {201_i|i=1,…,I}. For another example, the read optimization procedure may include the above operations of the LDPC code decoding engine circuit 202_i, and in particular, may include similar operations of the I LDPC code decoding engine circuits {202_i|i=1,…,I}.

[0083] Figure 3 According to an embodiment of the present invention, a memory device (eg Figure 1 Schematic diagram of a channel numerical processing control scheme of a method for data access control of a memory device 100 shown in FIG. 1 . The multiple read processing sub-circuits within the memory controller 110 may include the at least one LDPC code decoding engine circuit 202_i corresponding to the at least one channel CH, such as the I LDPC code decoding engine circuits {202_i|i=1,…,I} corresponding to the I channels {CH(i)|i=1,…,I}, respectively, and further include an error recovery circuit 114R and an equalizer circuit 114E. For example, the error recovery circuit 114R and the equalizer circuit 114E may be located at Figure 1 In the control logic circuit 114 shown in FIG. 1 , the I LLR mapping circuits {220_i|i=1,…,I} corresponding to the I channels {CH(i)|i=1,…,I} can be regarded as Figure 1 The multiple sub-circuits of the LLR mapping circuit 114M shown in the figure and the I LDPC code decoding circuits {230_i|i=1,…,I} corresponding to the I channels {CH(i)|i=1,…,I} respectively can be regarded as Figure 1The LDPC code decoding circuit 114D is shown as a plurality of sub-circuits, but the present invention is not limited thereto. According to some embodiments, at least a portion (e.g., a portion or all) of the plurality of read processing sub-circuits, such as the I LDPC code decoding engine circuits {202_i|i=1, ..., I}, the error recovery circuit 114R and the equalizer circuit 114E, can be integrated into the at least one other circuit (not the control logic circuit 114) mentioned above.

[0084] For better understanding, it is assumed that any one of the multiple blocks {BLK} in the NV memory 120 can be configured as a J-level cell block, and "J" can represent a positive integer. For example, when J=1, the block BLK can be a single-level cell (SLC) block; and, when J>1, the block BLK can be a multiple / multi-level cell (MLC) block, wherein if J=2, the block BLK can be a double-level cell (DLC) block, if J=3, the block BLK can be a triple-level cell (TLC) block, if J=4, the block BLK can be a quadruple-level cell (QLC) block, and the rest can be deduced accordingly; but the present invention is not limited thereto. Based on the channel numerical processing control scheme, the read optimization program may include the multiple read processing sub-circuits (for example Figure 3 The related operations of the architecture shown in the figure may include, in particular, the following operations:

[0085] (1) The memory controller 110 may perform at least one read operation on the NV memory 120 through at least one channel CH(i) among the plurality of channels {CH(i)} to obtain a plurality of channel values ​​{CV}, wherein any channel value CV among the plurality of channel values ​​{CV} may include a sign bit Sign_bit(j) and (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)}, for example, “j” may represent an integer falling within the interval [0,(J-1)], and “k” may represent an integer falling within the interval [1,(m-1)];

[0086] (2) The memory controller 110 may utilize the quantization compression circuit 208_i to perform at least one compression operation on the plurality of channel values ​​{CV} to convert the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} in any of the channel values ​​CV into (n-1) soft bits {Soft_bit_new(j,k)|k=1,…,(n-1)} to generate a compressed channel value CV corresponding to the channel value CV. COMPRESSED , for buffering in the volatile memory such as the memory 212_i, wherein the number of bits of the (n-1) soft bits {Soft_bit_new(j,k)|k=1, . . . , (n-1)} (e.g., the number of soft bits (n-1)) is less than the number of bits of the (m-1) soft bits {Soft_bit_org(j,k)|k=1, . . . , (m-1)} (e.g., the number of soft bits (m-1));

[0087] (3) The memory controller 110 may utilize the LLR mapping circuit 220_i to read a plurality of compressed channel values ​​{CV} respectively corresponding to the plurality of channel values ​​{CV} from the volatile memory, such as the memory 212_i. COMPRESSED}, and for the multiple compressed channel values ​​{CV COMPRESSED} performing an LLR mapping operation to generate a plurality of LLR values; and

[0088] (4) The memory controller 110 may utilize the LDPC code decoding circuit 230_i to perform at least one LDPC code decoding operation according to the plurality of LLR values, utilize the error recovery circuit 114R to perform at least one error recovery operation according to the plurality of channel values ​​{CV}, and utilize the equalizer circuit 114E to perform at least one equalization operation according to the plurality of channel values ​​{CV} to generate correct read data for transmission back to the host device 50. For example, the equalizer circuit 114E may represent a decision feedback equalizer circuit, and the at least one equalization operation may represent at least one decision feedback equalization operation.

[0089] However, the present invention is not limited thereto. According to some embodiments, the operation of the read optimization procedure may be varied. In addition, the at least one read operation may include a first read operation and a plurality of read retry operations for the first read operation, wherein the sign bit Sign_bit(j) in any of the channel values ​​CV may be obtained from the first read operation, and the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} in any of the channel values ​​may be obtained from the plurality of read retry operations.

[0090] The related devices (e.g., memory controller 110, memory device 100, and electronic device 10) operated according to the method can ensure the correctness of the read data, and based on the read optimization procedure including the at least one LDPC code decoding operation, the at least one error recovery operation, and the at least one equalization operation, the correct read data can have no errors. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E This can be implemented by means of a degraded flash memory die. In this case, although the relevant characteristics of the degraded flash memory die are unstable, the relevant device operated according to this method can obtain soft information for soft decoding through read retries, and perform error recovery to eliminate any errors caused by different memory cells and perform equalization to combat inter-symbol interference, so as to solve the problems of the relevant technology without introducing side effects or in a manner that is unlikely to introduce side effects. In addition, the relevant device operated according to this method can achieve the best configuration without being limited by the trade-offs between various considerations. For example, the above-mentioned various considerations may include:

[0091] (1) A first consideration: whether to use degraded flash memory die;

[0092] (2) A second consideration: whether the accuracy of the read data can be maintained;

[0093] (3) A third consideration: whether to adopt a soft decoding mechanism; and

[0094] (4) A fourth consideration: whether to allocate more memory space for soft decoding;

[0095] The related equipment operated by this method can directly reduce the overall cost by using degraded flash memory bare crystals without being limited by the trade-off between the first consideration and the second consideration. In particular, soft information can be obtained through the read retry program for soft decoding, and error recovery can be performed to eliminate adverse effects between memory cells in various directions, and equalization such as decision feedback equalization can be performed to combat inter-symbol interference. In this way, the chance of successful reading during daily use by users can be increased while using degraded flash memory bare crystals to reduce the overall cost. Quantization compression can also be performed to significantly reduce the memory space required for soft decoding and perform soft decoding efficiently without being limited by the trade-off between the third consideration and the fourth consideration.

[0096] Figure 4AAccording to an embodiment of the present invention, a plurality of sign bits Sign_bit(0), Sign_bit(1) and Sign_bit(2) involved in the method are illustrated. A group of memory cells 120C in the NV memory 120 can be configured as J-stage cells, and any memory cell in the group of memory cells 120C can be in a plurality of candidate programming states {P} such as 2 J programming states {P1,…,P2 J}. For example, when J=3, the group of memory cells 120C can be configured as three-level cells, and any memory cell in the group of memory cells 120C can be in a programming state P selected from the plurality of candidate programming states {P}, such as 8 programming states {P1, ..., P8}, where Figure 4A The horizontal axis shown in the lower half of may represent a threshold voltage Vth, and according to some viewpoints, the threshold voltage Vth may be referred to as a read voltage, but the present invention is not limited thereto. According to some embodiments, Figure 4A The plurality of candidate programming states {P1, ..., P8} and / or the level count J of the group of memory cells 120C shown may be varied. For example, the level count J may be equal to any value in a series of values ​​{1, 2, 3, 4, ...}.

[0097] like Figure 4A As shown in the upper half of FIG. 1 , the memory controller 110 may refer to a predetermined encoding rule to encode the 2 J programming states {P1,…,P2 J} Such as the 8 programming states {P1, ..., P8} associated with 2 J The predetermined codes are such as the 8 predetermined codes {111,011,001,101,100,000,010,110}, where the 2 J Any of the predetermined codes may include J sign bits {Sign_bit(j)|j=0, ..., (J-1)} such as 3 sign bits Sign_bit(0), Sign_bit(1) and Sign_bit(2), but the present invention is not limited thereto. According to some embodiments, the predetermined encoding rule, the 2 J A reservation code such as Figure 4A The 8 predetermined codes {111, 011, 001, 101, 100, 000, 010, 110} shown and / or the order J may be varied.

[0098] Figure 4BAccording to an embodiment of the present invention, the method involves the sign bit Sign_bit(j) and the (m-1) soft bits Soft_bit_org(j,k)|k=1,…,(m-1)}. During the read optimization process, the memory controller 110 may perform the first read operation to obtain the sign bit Sign_bit(j), and further perform the read retry process to perform the multiple read retry operations to obtain the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)}, wherein the soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} may indicate how strong or weak the sign bit Sign_bit(j) is. Bit 1 (if Sign_bit(j)=1), or bit 0 (if Sign_bit(j)=0) indicating how strong or weak the sign bit Sign_bit(j) is, and according to some viewpoints, these soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} can be used to accurately indicate the position of the programming state P associated with the sign bit Sign_bit(j) on the Vth axis to improve the accuracy of detecting the position of this programming state P on the Vth axis, but the present invention is not limited to this. For example, when k=1, the memory controller 110 may perform the first read retry operation to obtain the first soft bit Soft_bit_org(j,1); when k=2, the memory controller 110 may perform the first read retry operation to obtain the first soft bit Soft_bit_org(j,2); when k=3, the memory controller 110 may perform the third read retry operation to obtain the third soft bit Soft_bit_org(j,3); when k=4, the memory controller 110 may perform the fourth read retry operation to obtain the fourth soft bit Soft_bit_org(j,4); and the rest may be deduced accordingly.

[0099] For better understanding, arrows corresponding to k=1, k=2, k=3, k=4, etc. can be drawn on Figure 4B The operations for detecting the position of the programming state P on the Vth axis are indicated, but the present invention is not limited thereto. According to some embodiments, these operations, the related detection directions on the Vth axis (e.g., positive direction or negative direction), and / or the related detection positions on the Vth axis may be changed.

[0100] Figure 5AA schematic diagram of a compression processing control scheme of the method is depicted according to an embodiment of the present invention. For example, assuming m=6, in any of the above-mentioned channel values ​​CV input to the quantization compression circuit 208_i, the sign bit Sign_bit(j) may include a bit B0, and the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} may include 5 bits B1, B2, B3, B4 and B5 (for example: any binary value in the binary value {00000, 00001,…,11111}); and assuming n=3, in the above-mentioned compressed channel value CV output from the quantization compression circuit 208_i COMPRESSED , the sign bit Sign_bit(j) may include the same bit B0, and the (n-1) soft bits {Soft_bit_new(j,k)|k=1,…,(n-1)} may include 2 bits B1' and B2' (e.g., any binary value among the binary values ​​{00,01,10,11}), but the present invention is not limited thereto. According to some embodiments, the number of soft bits (m-1), the number of soft bits (n-1), and / or the related bit arrangement may be changed.

[0101] When n=3, the set of soft bits {B'}, such as bits {B1', ..., B(n-1)'}, can represent bits {B1', B2'} (e.g., any binary value among binary values ​​{00, 01, 10, 11}), and equation Eq(1) can be rewritten as follows:

[0102] LLR {B1’,B2’} =ln(L(θ0|x) / L(θ1|x));…………………………………………Eq(2)

[0103] Among them, “LLR {B1’,B2’} ” may represent the LLR value when the soft bit is equal to the bit {B1', B2'}.

[0104] Figure 5B According to an embodiment of the present invention, Figure 5A The lower half of the figure shows multiple candidate bits {B0, B1', B2'} and some related probabilities. For example, the bits {B0, B1', B2'} can be equal to any one of the eight candidate bits {011, 010, 001, 000, 100, 101, 110, 111}, where the probability that {B0, B1', B2'} = 011 can be 97%, and the probability that {B0, B1', B2'} = 111 can be 0.01%, but the present invention is not limited to this. According to some embodiments, the number of bits (n-1) of the bits {B1', ..., B(n-1)'}, the corresponding 2 nThe candidate bits and / or the associated probabilities may be varied. In addition, for {B1', B2'} = 11, the equation Eq (2) may be rewritten as follows:

[0105] LLR 11 = ln(97% / 0.01%);

[0106] However, the present invention is not limited thereto. In some examples, the LLR value LLR 11 It can change accordingly when the relevant probability changes.

[0107] Figure 6 According to one embodiment of the present invention, a compression mapping function involved in the compression processing control scheme of the method is illustrated, wherein the horizontal axis can represent the original soft information Soft_Info_org (e.g., the decimal value of the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)}), and the vertical axis can represent the new soft information Soft_Info_new (e.g., the decimal value of the (n-1) soft bits {Soft_bit_new(j,k)|k=1,…,(n-1)}). The memory controller 110 can use the quantization compression circuit 208_i to compress the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} in any of the above-mentioned channel values ​​CV according to the compression mapping function to generate a compressed channel value CV COMPRESSED For example, assuming m=6 and n=3, the memory controller 110 may use the quantization compression circuit 208_i to compress the (m-1) soft bits {Soft_bit_org(j,k)|k=1,...,(m-1)} according to the compression mapping function such as Figure 5A The 5 bits B1, B2, B3, B4 and B5 shown in the upper half of the figure are used to generate the (n-1) soft bits {Soft_bit_new(j,k)|k=1,…,(n-1)} such as Figure 5AThe two bits B1' and B2' shown in the lower half of , in particular, the decimal values ​​of the five bits B1, B2, B3, B4 and B5 can be mapped from any sub-mapping range of a mapping range (e.g., a range of the interval [0,31]) in a plurality of sub-mapping ranges (e.g., the ranges of the intervals [0,3], [4,7], [8,11] and [12,31]) to a corresponding mapping value in a plurality of mapping values ​​(e.g., values ​​0, 1, 2 and 3) to become the two bits B1' and B2', but the present invention is not limited thereto. According to some embodiments, the compression mapping function, the mapping range and its plurality of sub-mapping ranges, the number of soft bits (m-1), and / or the number of soft bits (n-1) can be varied.

[0108] Fig. 7A According to one embodiment of the present invention, a target memory cell and a plurality of helper memory cells involved in the method are illustrated. For better understanding, taking a two-dimensional (2D) flash memory as an example of the NV memory 120, a set of error-recovery-related memory cells 704 may include the target memory cell and four memory cells adjacent to the target memory cell, and the memory controller 110 may utilize the error recovery circuit 114R to perform at least one of the above-mentioned error recovery operations based on the multiple channel values ​​{CV} to eliminate any errors caused by the multiple helper memory cells (e.g., the four memory cells adjacent to the target memory cell), but the present invention is not limited thereto. According to certain embodiments, the type of the NV memory 120, the number of the multiple helper memory cells for the target memory cell, and / or the arrangement of the multiple helper memory cells may be varied.

[0109] Figure 7B According to another embodiment of the present invention, a target memory cell and a plurality of helper memory cells involved in the method are illustrated. For better understanding, taking a 2D flash memory as an example of the NV memory 120, a group of error recovery-related memory cells 708 may include the target memory cell and eight memory cells surrounding the target memory cell, and the memory controller 110 may utilize an error recovery circuit 114R to perform at least one of the above-mentioned error recovery operations based on the multiple channel values ​​{CV} to eliminate any errors caused by the multiple helper memory cells (e.g., the eight memory cells surrounding the target memory cell), but the present invention is not limited thereto. According to certain embodiments, the type of the NV memory 120, the number of the multiple helper memory cells for the target memory cell, and / or the arrangement of the multiple helper memory cells may be varied.

[0110] Figure 7CAccording to another embodiment of the present invention, a target memory cell and a plurality of helper memory cells involved in the method are illustrated. For better understanding, taking a three-dimensional (3D) flash memory as an example of the NV memory 120, a first group of error recovery-related memory cells 708 may include the target memory cell and eight memory cells surrounding the target memory cell in the same layer, a second group of error recovery-related memory cells 710 may include nine memory cells corresponding to the first group of error recovery-related memory cells 708 in another layer (e.g., an upper layer), and a third group of error recovery-related memory cells 720 may include nine memory cells corresponding to the first group of error recovery-related memory cells 708 in another layer (e.g., a lower layer). In addition, the memory controller 110 may utilize the error recovery circuit 114R to perform the at least one error recovery operation according to the plurality of channel values ​​{CV} to eliminate any errors caused by the plurality of helper memory cells (e.g., 8 memory cells surrounding the target memory cell, 9 memory cells in the other layer, such as the upper layer, and 9 memory cells in the above-mentioned further layer, such as the lower layer), but the present invention is not limited thereto. According to some embodiments, the type of the NV memory 120, the number of the plurality of helper memory cells for the target memory cell, and / or the arrangement of the plurality of helper memory cells may be varied.

[0111] Fig. 8A According to an embodiment of the present invention, a disturbed programming state of a target memory cell and a programming state of a helper memory cell #q involved in an error recovery control scheme of the method are illustrated, wherein the non-disturbed programming state of the target memory cell is also illustrated. Fig. 8A For ease of understanding, it is assumed that all error recovery-related memory cells for this target memory cell may include Q helper memory cells #1, #2, ... and #Q (for example, "Q" may represent a positive integer), and helper memory cell #q may be one of the Q helper memory cells #1, #2, ... and #Q (for example, "q" may be an integer falling within the interval [1, Q]). Fig. 7A , Figure 7B and Figure 7CThe target memory cell and the plurality of helper memory cells described in any of the illustrated embodiments may be used as examples of the target memory cell and the Q helper memory cells #1, #2, ... and #Q in this embodiment. Due to the interference of the helper memory cell #q, the programming state of the target memory cell may change from the non-interfering programming state to the disturbed programming state, but the present invention is not limited thereto. According to some embodiments, the disturbed programming state and the non-interfering programming state of the target memory cell, and / or the programming state of the helper memory cell #q may be changed.

[0112] Figure 8B The error recovery involved in the error recovery control scheme of the method is illustrated according to an embodiment of the present invention, wherein the disturbed programming state and the non-disturbed programming state of the target memory cell and the programming state of the helper memory cell #q are illustrated in FIG. Figure 8B For ease of understanding. The memory controller 110 may utilize the error recovery circuit 114R to perform the above-mentioned at least one error recovery operation according to the plurality of channel values ​​{CV} to eliminate any error caused by the helper memory cell #q, and in particular, to restore the programming state of the target memory cell from the disturbed programming state to the non-disturbed programming state, but the present invention is not limited thereto. According to some embodiments, the disturbed programming state and the non-disturbed programming state of the target memory cell, and / or the programming state of the helper memory cell #q may be changed.

[0113] Figure 8C According to an embodiment of the present invention, the error recovery control scheme of the method involves multiple phases Phase (0), Phase (1), Phase (2) and Phase (3). For example, in Phase (0), the error recovery circuit 114R may determine the target memory cell (e.g. Figure 4Aany one of the memory cells 120C of the group described in the illustrated embodiment) and a plurality of helper memory cells corresponding to the target memory cell, such as the Q helper memory cells #1, #2, ... and #Q; in phase Phase (1), the error recovery circuit 114R can read the target memory cell to generate a target memory cell read result of the target memory cell, wherein the target memory cell read result can include J channel values ​​{CV} for the target memory cell obtained from performing multiple reads (for example, by performing a normal read and performing the read retry procedure); in phase Phase (2), the error recovery circuit 114R can read the plurality of helper memory cells such as the Q helper memory cells and #Q to generate multiple helper memory cell read results #1, #2, ... and #Q for the multiple helper memory cells, wherein the helper memory cell read result #q of the helper memory cell #q may include J channel values ​​{CV} for the helper memory cell #q obtained from performing multiple reads (for example, by performing normal reads and performing the read retry procedure); and in phase (3), the error recovery circuit 114R may perform error recovery on the target memory cell read result based on the multiple helper memory cell read results #1, #2, ... and #Q to eliminate any errors caused by the multiple helper memory cells such as the Q helper memory cells #1, #2, ... and #Q.

[0114] Fig. 9 According to an embodiment of the present invention, a decision feedback equalization control scheme of the method is illustrated, wherein the horizontal axis may represent time t. The memory controller 110 may utilize the equalizer circuit 114E to equalize any memory cell (e.g., Figure 4A The read data of any one of the memory cells in the group of memory cells 120C described in the embodiment shown, such as a plurality of bits read from the memory cell, is subjected to the above-mentioned equalization, such as the decision feedback equalization (at Fig. 9The memory controller 110 may include J channel values ​​{CV} for the memory cell obtained from performing multiple reads (e.g., by performing a normal read and performing the read retry procedure), and the plurality of bits may represent respective bits {B0, B1, ..., B(m-1)} of the J channel values ​​{CV}. The memory controller 110 may utilize an equalizer circuit 114E to perform the decision feedback equalization on the read data (e.g., respective bits {B0, B1, ..., B(m-1)} of the J channel values ​​{CV}), and in particular, detect respective channel responses of the plurality of channels {CH(i)} according to at least one predetermined channel model to determine relevant parameters of the equalizer circuit 114E, so as to perform the decision feedback equalization on the subsequent bits for the channel CH(i) according to the previous bits, so as to change the subsequent bits from a state with inter-symbol interference (at Fig. 9 The symbol is marked as “with ISI” for simplicity) and adjusted to a state without ISI (at Fig. 9 For better understanding, the soft information in the J channel values ​​{CV} (e.g., their respective soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)}, such as their respective bits {B1,…,B(m-1)}) may indicate how strong or weak a bit in the corresponding hard information (e.g., their respective sign bits Sign_bit(j), such as their respective bits B0) is bit 1 (if Sign_bit(j)=1), or how strong or weak a bit in the corresponding hard information is bit 0 (if Sign_bit(j)=0), but the present invention is not limited thereto. According to some embodiments, the above-mentioned equalization, such as the decision feedback equalization, the hard information and soft information in the J channel values ​​{CV}, and / or the strength of the hard information indicated by the soft information in the J channel values ​​{CV} may be varied.

[0115] Fig.10 According to an embodiment of the present invention, a processing result of the method is illustrated, wherein the horizontal axis may represent the raw bit error rate RBER, which may be expressed in units of percentage (denoted as "%" for simplicity), and the vertical axis may represent the average latency Avg_Latency, which may be expressed in units of cycle (denoted as "Cycle" for simplicity), but the present invention is not limited thereto. In addition, the relevant configuration for obtaining the processing result may include: using additive white Gaussian noise (AWGN) for analysis, and using LDPC code decoding as the above-mentioned soft decoding mechanism to generate the average latency Avg_Latency (in Fig.10for simplicity). Figure 2 The first LDPC code decoding control scheme shown in the upper half of FIG. 1 configures m=6 so that the number of soft bits (m-1) is equal to 5; and for Figure 2 The second LDPC code decoding control scheme shown in the lower half of FIG. 1 configures m=6 and n=3 so that the number of soft bits (m-1) is equal to 5 and the number of soft bits (n-1) is equal to 2. Fig.10 As shown, the relationship between the average delay Avg_Latency of the second LDPC code decoding control scheme and the original bit error rate RBER (labeled as "3-bit compression" for simplicity) can be quite close to the relationship between the average delay Avg_Latency of the first LDPC code decoding control scheme and the original bit error rate RBER (labeled as "6-bit original" for simplicity), which indicates that the above-mentioned quantization compression can indeed significantly reduce the memory space required for soft decoding and efficiently perform soft decoding without significantly affecting the overall performance.

[0116] Fig.11 According to one embodiment of the present invention, a workflow of the read optimization procedure of the method is described. In response to the at least one read command among the plurality of host commands, the memory controller 110 may Fig.11 The workflow shown is used to perform the read optimization process.

[0117] In step S11, the memory controller 110 may perform the at least one read operation on the NV memory 120 through the at least one channel CH(i) among the plurality of channels {CH(i)} to obtain the plurality of channel values ​​{CV}. For example, any of the plurality of channel values ​​{CV} may include the sign bit Sign_bit(j) and the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)}.

[0118] In step S12, the memory controller 110 may utilize the quantization compression circuit 208_i to process the plurality of channel values.

[0119] {CV} performs the above-mentioned at least one compression operation to convert the (m-1) soft bits {Soft_bit_org(j,k)|k=1,…,(m-1)} (in any of the above-mentioned channel values ​​CV) into the (n-1) soft bits {Soft_bit_new(j,k)|k=1,…,(n-1)} to generate the compressed channel value CV (corresponding to this channel value CV) COMPRESSED, for buffering in the volatile memory such as memory 212_i. For example, since n < m, the number of bits of the (n - 1) soft bits {Soft_bit_new(j,k)|k = 1,…,(n - 1)} (e.g., the number of soft bits (n - 1)) is less than the number of bits of the (m - 1) soft bits {Soft_bit_org(j,k)|k = 1,…,(m - 1)} (e.g., the number of soft bits (m - 1)).

[0120] In step S13, the memory controller 110 can use the LDPC code decoding engine circuit 202_i to read from the volatile memory such as memory 212_i the multiple compressed channel values {CV COMPRESSED}, respectively corresponding to the multiple channel values {CV}, for LDPC code decoding. For example, the memory controller 110 can use the LLR mapping circuit 220_i to read from the volatile memory such as memory 212_i the multiple compressed channel values {CV COMPRESSED}, and perform the LLR mapping operations on the multiple compressed channel values {CV COMPRESSED} to generate the multiple LLR values for subsequent operations by the LDPC code decoding circuit 230_i.

[0121] In step S14, the memory controller 110 can use the LDPC code decoding engine circuit 202_i to perform LDPC code decoding based on the multiple compressed channel values {CV COMPRESSED} (e.g., the multiple compressed channel values {CV COMPRESSED} just read from the volatile memory such as memory 212_i in step S13), and use the error recovery circuit 114R to perform at least one of the above error recovery operations based on the multiple channel values {CV}, and further use the equalizer circuit 114E to perform at least one of the above equalization operations based on the multiple channel values {CV}, to generate the error-free read data for returning to the host device 50. For example, the memory controller 110 can use the LLR mapping circuit 220_i in the LDPC code decoding engine circuit 202_i to read from the volatile memory such as memory 212_i the multiple compressed channel values {CV COMPRESSED} respectively corresponding to the multiple channel values {CV}. When performing LDPC code decoding based on the multiple compressed channel values {CV COMPRESSED} using the LDPC code decoding engine circuit 202_i, the memory controller 110 can use the LLR mapping circuit 220_i in the LDPC code decoding engine circuit 202_i to perform operations on the multiple compressed channel values {CV COMPRESSED}Perform the LLR mapping operations to generate the multiple LLR values, and use the LDPC code decoding circuit 230_i in the LDPC code decoding engine circuit 202_i to perform the above-mentioned at least one LDPC code decoding operation according to the multiple LLR values.

[0122] Based on the read optimization procedure including the LDPC code decoding, the at least one error recovery operation and the at least one equalization operation, the correct read data does not have any errors. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0123] For a better understanding, the method can be used Fig.11 According to some embodiments, one or more steps may be performed in Fig.11 For example, the LDPC code decoding circuit 230_i may include at least one variable node unit (VNU), at least one barrel shifter (BS) and at least one check node unit (CNU). When the LDPC code decoding engine circuit 202_i is used according to the plurality of compressed channel values ​​{CV COMPRESSED When performing the LDPC code decoding, the memory controller 110 may utilize multiple sub-circuits of the LDPC code decoding circuit 230_i, such as the at least one VNU, the at least one BS, and the at least one CNU, to perform the at least one LDPC code decoding operation. For the sake of simplicity, similar contents in these embodiments are not repeated here.

[0124] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for controlling data access of a memory device, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the method comprising: receiving a plurality of host commands from a host device for performing data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes data reading; as well as In response to at least one read command, a read optimization procedure is performed to maintain the correctness of the data read, wherein the plurality of host commands include the at least one read command, and the read optimization procedure includes: Performing at least one read operation on the non-volatile memory through at least one channel among the plurality of channels to obtain a plurality of channel values, wherein any channel value among the plurality of channel values ​​comprises a sign bit and a plurality of first soft bits; Performing at least one compression operation on the plurality of channel values ​​to convert the plurality of first soft bits in any one of the channel values ​​into a plurality of second soft bits to generate a compressed channel value corresponding to the any one of the channel values ​​for buffering in a volatile memory in the memory controller, wherein a second bit number of the plurality of second soft bits is less than a first bit number of the plurality of first soft bits; reading a plurality of compressed channel values ​​respectively corresponding to the plurality of channel values ​​from the volatile memory for low-density parity-check (LDPC) code decoding; as well as An LDPC decoding engine circuit is used to perform the LDPC decoding according to the compressed channel values, and an error recovery circuit is used to perform at least one error recovery operation according to the channel values ​​to generate error-free read data for transmission back to the host device.

2. The method according to claim 1, characterized in that The at least one read operation includes a first read operation and a plurality of read retry operations, wherein the sign bit in any one channel value is obtained from the first read operation, and the plurality of first soft bits in any one channel value are obtained from the plurality of read retry operations.

3. The method according to claim 1, characterized in that Any error recovery operation of the at least one error recovery operation includes: Determining a target memory cell and a plurality of helper memory cells corresponding to the target memory cell; Reading the target memory cell to generate a target memory cell reading result of the target memory cell; reading the plurality of helper memory cells to generate a plurality of helper memory cell reading results of the plurality of helper memory cells; as well as The target memory cell reading result is error-recovered according to the helper memory cell reading results to eliminate any errors caused by the helper memory cells.

4. The method according to claim 1, characterized in that Utilizing the LDPC decoding engine circuit to perform the LDPC decoding according to the plurality of compressed channel values, and utilizing the error recovery circuit to perform the at least one error recovery operation according to the plurality of channel values ​​to generate the error-free read data further comprises: The LDPC decoding engine circuit is used to perform the LDPC decoding according to the plurality of compressed channel values, the error recovery circuit is used to perform the at least one error recovery operation according to the plurality of channel values, and an equalizer circuit is used to perform at least one equalization operation according to the plurality of channel values ​​to generate the error-free read data.

5. The method according to claim 4, characterized in that The equalizer circuit represents a decision feedback equalizer circuit, and the at least one equalization operation represents at least one decision feedback equalization (DFE) operation.

6. The method according to claim 4, characterized in that Based on the read optimization procedure including the LDPC code decoding, the at least one error recovery operation and the at least one equalization operation, the correct read data does not have any error.

7. The method according to claim 1, characterized in that Utilizing the LDPC decoding engine circuit to perform the LDPC decoding according to the plurality of compressed channel values ​​further comprises: Utilizing a log-likelihood ratio (LLR) mapping circuit in the LDPC decoding engine circuit to perform a log-likelihood ratio mapping operation on the plurality of compressed channel values ​​to generate a plurality of log-likelihood ratio values; and A LDPC decoding circuit in the LDPC decoding engine circuit is used to perform at least one LDPC decoding operation according to the plurality of log likelihood ratio values.

8. The method according to claim 1, characterized in that Based on the read optimization procedure including the at least one LDPC decoding operation and the at least one error recovery operation, the correct read data does not have any error.

9. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller; as well as a transmission interface circuit for communicating with the host device; in: The memory controller receives the plurality of host commands from the host device through the transmission interface circuit in the memory controller, so as to perform data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes data reading; and In response to at least one read command, the memory controller performs a read optimization procedure to maintain the correctness of the data read, wherein the plurality of host commands include the at least one read command, and the read optimization procedure includes: Performing at least one read operation on the non-volatile memory through at least one channel among the plurality of channels to obtain a plurality of channel values, wherein any channel value among the plurality of channel values ​​comprises a sign bit and a plurality of first soft bits; Performing at least one compression operation on the plurality of channel values ​​to convert the plurality of first soft bits in any one of the channel values ​​into a plurality of second soft bits to generate a compressed channel value corresponding to the any one of the channel values ​​for buffering in a volatile memory in the memory controller, wherein a second bit number of the plurality of second soft bits is less than a first bit number of the plurality of first soft bits; reading a plurality of compressed channel values ​​respectively corresponding to the plurality of channel values ​​from the volatile memory for low-density parity-check (LDPC) code decoding; and An LDPC decoding engine circuit is used to perform the LDPC decoding according to the compressed channel values, and an error recovery circuit is used to perform at least one error recovery operation according to the channel values ​​to generate error-free read data for transmission back to the host device.

10. A memory device comprising the memory controller according to claim 9, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

11. An electronic device comprising the memory device according to claim 10, and further comprising: The host device is coupled to the memory device, wherein the host device includes: at least one processor for controlling the operation of the host device; as well as a power supply circuit coupled to the at least one processor and configured to provide power to the at least one processor and the memory device; The memory device provides storage space for the host device.

Images