Embedded Large Model Acceleration System Platform
By directly connecting the CPU and FPGA processor in an embedded system and replacing the PCIe card with 10 Gigabit Ethernet, the problems of high cost and poor stability of embedded AI are solved, and efficient and stable AI accelerated data transmission is achieved.
Patent Information
- Application Number
- CN202411807423.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-04-04
AI Technical Summary
In the embedded field, using SoCs to achieve AI acceleration is costly and lacks stability, and PCIe cards are not suitable for embedded applications.
Design an embedded large-model acceleration system platform, by setting up the CPU and FPGA processor on the same motherboard, and directly connecting the CPU and FPGA using the 10 Gigabit XGMII interface, using a fixed MAC address and a custom Ethernet frame type for data communication, and directly constructing Ethernet frames through original sockets in the user state.
Reduces hardware costs, improves system integration, reduces development cycles, and achieves stable data communication without the need for additional development of dedicated drivers.
Smart Images
Figure CN119759842A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of model acceleration, and in particular to an embedded large model acceleration system platform. Background Art
[0002] Large models usually refer to artificial intelligence models with large parameters and high complexity. They are widely used in many fields such as natural language processing, computer vision, and autonomous driving. At present, most AI acceleration devices are used in the form of PCIe cards, but PCIe cards are large and not suitable for embedded fields. At present, most embedded fields use system-on-chip (SoC) to achieve AI acceleration, but SoC is generally expensive and the driver is complex. Once there is a bug in the driver, it will cause the system to crash in serious cases. It usually takes a long time to develop stable driver software. Summary of the invention
[0003] An embodiment of the present application provides an embedded large model acceleration system platform to solve the problems of high cost and lack of stability in the execution of AI acceleration by integrated SoC of embedded systems in related technologies.
[0004] The platform includes a CPU processor and at least one FPGA processor arranged on the same motherboard; the FPGA processor has an AI acceleration engine built in, and the CPU processor is used to start and control model acceleration;
[0005] The CPU processor and at least one FPGA processor are directly connected via a 10 Gigabit XGMII interface, wherein the CPU processor sends Ethernet data frames and receives model acceleration results to the FPGA processor based on a fixed source MAC address, the FPGA processor receives Ethernet data frames based on a fixed target MAC address, and constructs Ethernet frames based on the model acceleration results for sending.
[0006] Specifically, the CPU processor uses a fixed source MAC address with the target FPGA processor through system software settings; the FPGA processor side enables the Ethernet MAC IP core to determine the fixed target MAC address.
[0007] Specifically, the FPGA processor is connected to a high-bandwidth memory HBM, in which AI model parameters are stored;
[0008] After receiving the data frame from the CPU processor, the FPGA processor parses and obtains the control instruction according to the set target communication protocol, and starts the AI acceleration operation calculation according to the control instruction.
[0009] Specifically, Ethernet frame data is constructed between the CPU processor and the FPGA processor through a raw socket.
[0010] Specifically, when the CPU processor communicates with the FPGA processor, a raw socket is created and a preset Ethernet frame type is selected;
[0011] Construct an Ethernet frame header, encapsulate the function code instructions for controlling AI acceleration according to a preset protocol, and obtain Ethernet frame data; the function code instructions are used to control the AI acceleration engine to perform corresponding operations.
[0012] Specifically, the CPU processor sends Ethernet frame data according to the target MAC address of the FPGA processor;
[0013] When the FPGA processor receives the Ethernet frame data, it parses and extracts the function code instruction according to the preset protocol;
[0014] Calling the AI acceleration engine based on the function code instruction and performing corresponding operation calculations to obtain result data;
[0015] Constructs the Ethernet frame header, encapsulates the result data according to the preset protocol, and returns it to the CPU processor.
[0016] Specifically, the CPU processor is provided with a first protocol processing unit and a service processing unit, the first protocol processing unit is used to determine the Ethernet frame type and encapsulation protocol type set with the FPGA processor, encapsulate and construct the Ethernet frame and parse the received Ethernet frame data;
[0017] The business processing unit is used to determine and generate function code instructions for operating the AI acceleration engine, and execute the encapsulation construction step after determining the function code instructions and the encapsulation protocol type.
[0018] Specifically, the FPGA processor is provided with a second protocol processing unit and an AI acceleration engine;
[0019] The second protocol processing unit is used to parse the Ethernet frame data received by the MAC end, extract the function code instruction, and perform protocol encapsulation;
[0020] The AI acceleration engine stores AI operators for model acceleration and performs corresponding operation calculations according to function code instructions.
[0021] Specifically, the format of the Ethernet frame data includes 6-Byte target MAC address bits, 6-Byte source MAC address bits, 2-Byte data type bits, and 46-1500-Byte preset protocol bits; the preset protocol is matched according to the CPU processor and the FPGA processor, and parsed when the match is consistent.
[0022] Specifically, the preset protocol bits include a 2-byte length field bit, a 2-byte function code field, a 4-byte address field, a 2-byte check field, and the rest are data fields.
[0023] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:
[0024] 1. Placing the CPU and FPGA processor on the same motherboard and connecting them directly through Ethernet MAC, without the need for phy chips and isolation transformers, can greatly reduce the motherboard area and effectively reduce hardware costs.
[0025] 2. Use raw sockets directly in user mode to build Ethernet frames to achieve data communication between the CPU processor side and the FPGA processor side. There is no need to develop additional dedicated drivers. This is stable and reliable and effectively shortens the development cycle.
[0026] 3. Use 10G network instead of PCIe card to realize embedded AI accelerated data transmission, improve integration and reduce cost investment.
[0027] 4. Directly connect the 10 Gigabit Ethernet MAC of the CPU and FPGA processor, use fixed MAC addresses and custom Ethernet frame types, and construct Ethernet frames in user mode to achieve data communication between the two. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is a structural diagram of an embedded large model acceleration system platform provided in an embodiment of the present application;
[0029] Figure 2 It is a schematic diagram of the interaction between the CPU processor and the FPGA processor provided in the embodiment of the present application;
[0030] Figure 3 It is a flowchart of the CPU processor executing data communication;
[0031] Figure 4 It is a schematic diagram of the flow of data communication performed by the FPGA processor;
[0032] Figure 5 is an Ethernet data structure provided by an embodiment of the present application;
[0033] Figure 6 It is a custom protocol structure provided in the embodiment of the present application;
[0034] Figure 7 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION
[0035] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0036] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.
[0037] Figure 1 This is a schematic diagram of the structure of the embedded large model acceleration system platform provided by the embodiment of the present application. The system is targeted at embedded systems, that is, systems where the CPU processor and the FPGA processor operate in coordination. The CPU processor is mainly used for global control, and the FPGA processor is controlled by the CPU processor and is mainly used for AI acceleration. Traditional AI acceleration systems use PCIe to communicate data between the CPU and the AI acceleration card. However, the present application provides the premise that the embedded system needs to achieve efficient data communication as much as possible to improve system integration and reduce costs. Therefore, Figure 1 The system architecture adopts the CPU+FPGA solution. The platform includes a CPU processor and at least one FPGA processor set on the same motherboard; the FPGA processor has a built-in AI acceleration engine. The CPU processor and at least one FPGA processor are directly connected through the set 10G XGMII interface. The CPU processor sends Ethernet data frames to the FPGA processor based on a fixed source MAC address and receives the model acceleration results fed back by the FPGA processor. The FPGA processor receives the Ethernet data frames sent by the CPU processor based on a fixed target MAC address, and constructs Ethernet frames based on the model acceleration results for transmission.
[0038] In the embodiment of the present application, in addition to the commonly used RJ45 interface, USB interface, serial port, SD card, etc., the most important thing in the hardware motherboard design is to place the CPU and FPGA on the same motherboard, and directly connect the Ethernet MAC of the two through the XGMII interface. The CPU processor is set by the system software, and a fixed source MAC address is used between the CPU and the target FPGA processor. After the system is started, the network card device can be seen through the ifconfig command. The Ethernet MAC IP core is enabled on the FPGA processor side to determine its fixed target MAC address.
[0039] In some embodiments, for AI acceleration scenarios, especially to implement large language model (LLM) acceleration functions, the FPGA processor also needs to be connected to a high-bandwidth memory HBM, which stores LLM weight data and KV cache. Figure 2 The diagram of the interaction between the CPU processor and the FPGA processor is shown in Figure 1. The CPU can select an ARM processor, such as the LS1046A of the NXP Layerscape series or the Marvell Armada8040 of the Marvell ARMADA series. The FPGA selects the XCV80 of the AMD Versal HBM series with a built-in AI engine, which supports large-capacity HBM video memory. After receiving the data frame from the CPU processor, the FPGA processor parses and obtains the control instruction according to the set target communication protocol, and calls the LLM acceleration engine according to the control instruction to achieve LLM acceleration.
[0040] For the function of replacing the PCIe card to achieve efficient data interaction and transmission, this application builds Ethernet frame data between the CPU processor and the FPGA processor through raw sockets based on MAC to MAC between the CPU and FPGA. The CPU processor sends Ethernet frame data according to the target MAC address of the FPGA processor, and the FPGA processor also feeds back Ethernet frame data based on the source MAC address of the CPU processor.
[0041] Figure 3 This is a flow chart of the CPU processor executing data communication. When the CPU processor needs to communicate with the FPGA processor, it will first create a raw socket and select a preset Ethernet frame type. The Ethernet frame type here can be customized according to the actual situation. Especially in the multi-FPGA scenario, different Ethernet frame types can be bound to different FPGA devices. In this way, in the case of wrong transmission and mistransmission, the FPGA side will not start incorrectly, ensuring safe and stable execution. The creation function is:
[0042] socket(AF_PACKET,SOCK_RAW,htons(0xA0B0));
[0043] 0xA0B0 is the custom Ethernet frame type above, indicating that the application receives data with Ethernet frame type 0xA0B0. This method is used to send and receive only the data of the target FPGA.
[0044] Furthermore, the Ethernet frame header is constructed, and the function code instructions for controlling LLM acceleration are encapsulated according to the preset protocol to obtain Ethernet frame data. Since the source / destination MAC address and Ethernet frame type are fixed values, the Ethernet frame header is easy to construct. Then the service data is encapsulated according to the custom protocol, where the function code instructions are used to control the LLM acceleration engine to perform corresponding operations, that is, the operation category of the LLM acceleration engine, such as loading LLM weights, performing LLM reasoning, etc., and other fields are set accordingly according to the function code. Finally, the encapsulated data is sent out, and the processing result data returned by the FPGA side is waited for and received.
[0045] Correspondingly, Figure 2 The CPU processor is provided with a first protocol processing unit and a service processing unit. The first protocol processing unit is used to determine the Ethernet frame type and encapsulation protocol type set with the FPGA processor, encapsulate and construct the Ethernet frame, and parse the received Ethernet frame data. The service processing unit is used to determine and generate function code instructions for the LLM acceleration engine operation, and execute the encapsulation construction step after determining the function code instructions and the encapsulation protocol type. Based on this, when multiple FPGA processors are included, the CPU processor can set the corresponding encapsulation protocol in advance according to different target MAC addresses (i.e., FPGA processors), so as to ensure accurate transmission and parsing of data between MAC to MAC ends.
[0046] Figure 4 It is a flowchart of the FPGA processor executing data communication. The CPU processor sends Ethernet frame data according to the target MAC address of the FPGA processor. Correspondingly, after receiving the Ethernet frame data from the CPU processor side, the target FPGA processor parses and extracts the function code instructions according to the preset protocol. The preset protocol here is set in advance, and the data frame can be parsed when they match each other. That is to say, when the protocol encapsulated on the CPU side is inconsistent with the protocol on the target FPGA side, the function code instructions cannot be correctly parsed and extracted. Furthermore, after the protocol matches and is successfully parsed, the FPGA processor calls the LLM acceleration engine based on the function code instructions and performs corresponding operation calculations to obtain the result data. Next, the Ethernet frame header is constructed, and the result data is encapsulated according to the preset protocol and returned to the CPU processor.
[0047] In order to achieve the normal execution of the processes such as protocol matching, parsing and encapsulation, a second protocol processing unit and an LLM acceleration engine can be set in the FPGA processor; the second protocol processing unit is used to parse the Ethernet frame data received by the MAC end, extract the function code instructions, and perform protocol encapsulation. The LLM acceleration engine stores the LLM operator for model acceleration, and performs the corresponding calculation operation according to the function code instructions.
[0048] Regarding the design of Ethernet frames, this application uses standard Ethernet data structures, such as Figure 5 As shown in FIG. 1 , the format of the Ethernet frame data includes 6-byte target MAC address bits, 6-byte source MAC address bits, 2-byte data type bits, and 46-1500-byte preset protocol bits. The preset protocol is matched according to the CPU processor and the FPGA processor, and parsing can be performed when the match is consistent.
[0049] The target MAC and source MAC are the MAC addresses of the FPGA side and the CPU side respectively. They are fixed values and can be set at will, such as D8:5E:D3:AA:BB:CC. The type field is a custom type such as 0xA0B0, as long as it is different from the existing Ethernet frame type defined by the IEEE 802.3 standard. The CPU side application mainly judges and receives the data sent by the FPGA side based on this type.
[0050] In one possible implementation, a custom protocol such as Figure 6 As shown in the figure, the preset protocol bits include a 2-byte length field, a 2-byte function code field, a 4-byte address field, a 2-byte check field, and the rest are data fields. The length field indicates the length of all data including the length field; the function code indicates the type of operation performed, such as loading LLM weights, loading Embedding data, performing LLM reasoning, performing hardware reset, etc.; the address field indicates the LLM acceleration engine register address on the FPGA side or the HBM memory address, that is, the write location of the CPU side data; the data field is the actual data to be sent; the check field is to ensure the integrity of data transmission, and the CRC16 check algorithm is used here.
[0051] In summary, the beneficial effects brought about by this application include the following:
[0052] 1. Placing the CPU and FPGA processor on the same motherboard and connecting them directly through Ethernet MAC, without the need for phy chips and isolation transformers, can greatly reduce the motherboard area and effectively reduce hardware costs.
[0053] 2. Use raw sockets directly in user mode to build Ethernet frames to achieve data communication between the CPU processor side and the FPGA processor side. There is no need to develop additional dedicated drivers. This is stable and reliable and effectively shortens the development cycle.
[0054] 3. Use 10 Gigabit network instead of PCIe to realize embedded AI accelerated data transmission, improve integration and reduce cost investment.
[0055] 4. Directly connect the 10 Gigabit Ethernet MAC of the CPU and FPGA processor, use fixed MAC addresses and custom Ethernet frame types, and construct Ethernet frames in user mode to achieve data communication between the two.
[0056] It should be noted that the embedded large model acceleration system platform provided in the embodiment of the present application is only illustrated by the division of the above-mentioned functional modules / functional units. In actual applications, the above-mentioned function allocation can be completed by different functional modules / functional units as needed, that is, the internal structure of the embedded large model acceleration system platform is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the embedded large model acceleration system platform method provided in the above method embodiment and the implementation method of the embedded large model acceleration system platform provided in this embodiment belong to the same concept. The specific implementation process of the embedded large model acceleration system platform provided in this embodiment is detailed in the above method embodiment, which will not be repeated here.
[0057] Figure 7 The structural block diagram of an embedded computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or in other ways. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various types of chips.
[0058] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.
[0059] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.
[0060] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.
[0061] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.
[0062] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, arranged on the front panel of the computer device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the computer device or in a folding design; in other embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device. Even, the display screen can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.
[0063] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.
[0064] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.
[0065] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.
[0066] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.
Claims
1. An embedded large model acceleration system platform, characterized in that: The platform includes a CPU processor and at least one FPGA processor arranged on the same motherboard; the FPGA processor has an AI acceleration engine built in, and the CPU processor is used to start and control model acceleration; The CPU processor and at least one FPGA processor are directly connected via a 10 Gigabit XGMII interface, wherein the CPU processor sends Ethernet data frames and receives model acceleration results to the FPGA processor based on a fixed source MAC address, the FPGA processor receives Ethernet data frames based on a fixed target MAC address, and constructs Ethernet frames based on the model acceleration results for sending.
2. The embedded large model acceleration system platform according to claim 1, characterized in that: The CPU processor is set by system software to use a fixed source MAC address with the target FPGA processor; The FPGA processor side enables the Ethernet MAC IP core and determines a fixed target MAC address.
3. The embedded large model acceleration system platform according to claim 2, characterized in that: The FPGA processor is connected to a high-bandwidth memory HBM, in which AI model parameters are stored; After receiving the data frame from the CPU processor, the FPGA processor parses and obtains the control instruction according to the set target communication protocol, and starts the corresponding AI operation calculation according to the control instruction.
4. The embedded large model acceleration system platform according to any one of claims 1 to 3, characterized in that: The CPU processor and the FPGA processor construct Ethernet frame data through the original socket.
5. The embedded large model acceleration system platform according to claim 4, characterized in that: When the CPU processor communicates with the FPGA processor, a raw socket is created and a preset Ethernet frame type is selected; Construct an Ethernet frame header, encapsulate the function code instructions for controlling AI acceleration according to a preset protocol, and obtain Ethernet frame data; the function code instructions are used to control the AI acceleration engine to perform corresponding operations.
6. The embedded large model acceleration system platform according to claim 5, characterized in that: The CPU processor sends Ethernet frame data according to the target MAC address of the FPGA processor; When the FPGA processor receives the Ethernet frame data, it parses and extracts the function code instruction according to the preset protocol; Calling the AI acceleration engine based on the function code instruction and performing corresponding operation calculations to obtain result data; Constructs the Ethernet frame header, encapsulates the result data according to the preset protocol, and returns it to the CPU processor.
7. The embedded large model acceleration system platform according to claim 5, characterized in that: The CPU processor is provided with a first protocol processing unit and a service processing unit, the first protocol processing unit is used to determine the Ethernet frame type and encapsulation protocol type set with the FPGA processor, encapsulate and construct the Ethernet frame and parse the received Ethernet frame data; The business processing unit is used to determine and generate function code instructions for AI model operations, and execute the encapsulation construction step after determining the function code instructions and the encapsulation protocol type.
8. The embedded large model acceleration system platform according to claim 6, characterized in that: The FPGA processor is provided with a second protocol processing unit and an AI acceleration engine; The second protocol processing unit is used to parse the Ethernet frame data received by the MAC end, extract the function code instruction, and perform protocol encapsulation; The AI acceleration engine stores AI operators for model acceleration and performs corresponding operation calculations according to function code instructions.
9. The embedded large model acceleration system platform according to any one of claims 5 to 8, characterized in that: The format of the Ethernet frame data includes 6-Byte target MAC address bits, 6-Byte source MAC address bits, 2-Byte data type bits, and 46-1500-Byte preset protocol bits; the preset protocol is matched according to the CPU processor and the FPGA processor, and parsed when the match is consistent.
10. The embedded large model acceleration system platform according to claim 9, characterized in that: The preset protocol bits include a 2-byte length field bit, a 2-byte function code field, a 4-byte address field, a 2-byte check field, and the rest are data fields.