Method and apparatus for preventing voltage short pulse wave interference attacks in microcontroller

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for preventing voltage short pulse wave interference attacks in microcontrollers. An example apparatus (110) includes logic circuitry (200) operable to suspend processing circuitry (114) in response to voltage short-time pulse wave disturbances; digital generator circuitry (202) operable to generate a number; a counter (204) operable to adjust a count corresponding to the number after the end of the voltage short pulse wave interference; and the logic circuitry (200) is operable to cancel pausing of the processing circuitry (114) after the count reaches a value.

Description

[0001] Related Applications

[0002] This application is related to commonly assigned U.S. patent application serial number 18 / 309,340, entitled “VOLTAGE GLITCH DETECTOR,” filed on April 28, 2023. U.S. patent application serial number 18 / 309,340 is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description relates generally to circuits and, more particularly, to methods and apparatus for preventing voltage glitch attacks in microcontrollers. Background Art

[0004] Microcontrollers and / or other computing devices include processing circuitry (e.g., a central processing unit, a graphics processing unit, and / or any other type of processing unit) that relies on a clock signal to execute instructions and / or synchronize with other components connected to the processing circuitry. In some examples, the clock signal may be generated by an oscillator. When the processing circuitry is started, booted, and / or initialized, the processing circuitry uses the clock signal for basic timing and control to execute instructions required for startup, booting, and / or initialization. Summary of the invention

[0005] Examples of the present specification include an apparatus comprising: logic circuitry operable to suspend processing circuitry in response to a voltage short-term pulse wave interference; a number generator circuitry operable to generate a number; a counter operable to adjust a count corresponding to the number after the voltage short-term pulse wave interference ends; and the logic circuitry is operable to un-suspend the processing circuitry after the count reaches a certain value. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is an example microcontroller described in conjunction with the examples described herein.

[0007] Figure 2 yes Figure 1 A block diagram of an example of a single short-time pulse wave interference protection circuit system.

[0008] Figure 3 yes Figure 1 A block diagram of an example of a multi-glitch protection circuit system.

[0009] Figure 4 It means that it can be implemented through execution Figure 1 A flow chart of a method and / or operation of a glitch protection circuit system.

[0010] Figure 5 It means that it can be implemented through execution Figure 1 A flow chart of a method and / or operation of a multi-glitch protection circuit system.

[0011] Figures 6 to 7 Description and Figure 1 The timing diagram corresponding to the output signal of the component in the single short-time pulse wave interference protection circuit system.

[0012] Figures 8 to 9 Description and Figure 1 A timing diagram corresponding to the output signals of components in a multi-short-time pulse wave interference protection circuit system.

[0013] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0014] The drawings are not necessarily to scale. In general, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0015] Microcontrollers and / or other controllers are implemented in various electronic devices to perform operations and / or tasks. Such controllers include processing circuit systems (e.g., CPUs, GPUs, etc.) to facilitate the execution of instructions, thereby performing operations and / or tasks in conjunction with other peripheral devices (e.g., sensors, motors, keyboards, user interfaces, etc.). The processing circuit system utilizes a clock signal to execute instructions. Therefore, the microcontroller includes and / or is connected to one or more clock oscillators that generate a clock signal for the processing circuit system to execute instructions. A power source (e.g., a battery, a plug, etc.) is connected to a terminal of the microcontroller (e.g., a VDD terminal, a digital logic VDD (VDDD) terminal, etc.) to provide power to components of the microcontroller.

[0016] During startup, start-up, restart, initialization, etc., the processing circuitry of the microcontroller executes various instructions to prepare for operation. Such instructions may cause one or more of the registers of the microcontroller to be set to configure a different configuration. Such instructions may correspond to the initialization of security protocols to protect the microcontroller from attacks such as unintended debug settings or denial of service attacks.

[0017] Some attackers may attempt to corrupt information in a microcontroller by applying voltage glitches, clock glitches, electromagnetic injection, etc. For example, during startup, an attacker may apply voltage glitches to the power supply voltage terminals to reduce the power supply voltage. When the power supply voltage drops, the processing circuit system may unintentionally skip one or more operations. Therefore, an attacker may apply voltage glitches during startup to try to cause the processing circuit system to skip security protocols and / or debug configuration during startup, and then exploit / exploit the security vulnerability created by the voltage glitches during startup.

[0018] Voltage glitch detection circuitry may be implemented in a microcontroller to identify voltage glitches. Voltage glitch detection circuitry may be implemented to identify voltage glitches at a supply voltage terminal, an internal voltage rail, and / or any other terminal or rail of the microcontroller. When the voltage glitch detection circuitry detects a voltage glitches, the voltage glitch detection circuitry outputs a signal (e.g., a high voltage) to indicate that a voltage glitches is occurring. Additional example details of voltage glitch detection may be found in commonly assigned U.S. patent application Ser. No. 18 / 309,340, referenced in paragraph

[0001] of this specification.

[0019] Some microcontrollers use a voltage glitch indication signal to reset the processing circuitry. The reset processing circuitry clears the information that the processing circuitry was configured with when the voltage glitch occurred and restarts the startup, start-up, and initialization process from the beginning. Although the reset processing circuitry prevents glitch-based attacks, the reset process takes time and / or resources to re-execute instructions that were executed before the voltage glitch. Therefore, resetting the processing circuitry in response to a glitch may result in delays and / or power consumption overhead.

[0020] The examples disclosed herein utilize logic circuitry to protect a microcontroller from attacks based on voltage short-time pulse wave interference without the delay and / or power overhead associated with the reset processing circuitry. The examples disclosed herein utilize logic circuitry to suspend the operation of the processing circuitry in response to a detected voltage short-time pulse wave interference. The examples disclosed herein may include logic circuitry that can be configured to suspend the operation of the processing circuitry by gating the clock signal (preventing the processing circuitry from receiving the clock signal from the clock oscillator). However, the logic circuitry can be configured to suspend the processing circuitry using any function and / or operation that stops or interrupts the normal execution of the code of the processing circuitry. If the processing circuitry does not receive the clock signal, the processing circuitry will interrupt the execution of the instruction, thereby suspending the operation until the clock signal is received. After the short-time pulse wave interference detection circuitry determines that the voltage short-time pulse wave interference has ended, the examples disclosed herein may include a circuitry that can be configured to generate a random number and wait for a duration corresponding to the random number until the suspension of the processing circuitry is canceled (for example, the clock signal is canceled to gate so that the processing circuitry will receive the clock signal and continue to operate). Randomizing the time to unpause after a glitch provides additional security from an attacker. For example, if an attacker attempts to apply multiple glitches, the attacker will not be able to predict the timing of the glitch protection protocol if the timing of each detected glitch is different. Examples disclosed herein also utilize logic circuitry to protect other components of the microcontroller (e.g., accelerators, subsystems, registers, etc.) by locking such components based on detected voltage glitches.

[0021] In addition, the examples disclosed herein utilize logic circuit systems to track and / or mitigate multiple short-time pulse wave interference. The examples disclosed herein may utilize logic circuit systems to use one or more counters to track the number of identified short-time pulse wave interference (for example, the total number of short-time pulse wave interference and / or the number of short-time pulse wave interference that has occurred within a threshold amount of time). When one or more counters reach a custom threshold, the examples disclosed herein utilize logic circuit systems to interrupt the operation of the processing circuit system (for example, by causing the processing circuit system to enter a standby mode). As used herein, the standby mode may include a sleep mode, a low power mode, and / or any mode different from a normal operating mode. The examples disclosed herein may include circuit systems that can be configured to block and / or delay any instructions to exit the interrupt and / or standby mode until after a random duration to provide additional security from attackers. Examples The examples disclosed herein, such as electronic devices of microcontrollers, can prevent voltage short-time pulse wave interference in a fast and effective manner.

[0022] Figure 1 An example microcontroller 100 is illustrated. However, the microcontroller 100 may be another controller device, including any semiconductor device or integrated circuit, such as a power management integrated circuit. The example microcontroller 100 includes one or more clock oscillators 102, an example clock controller 104, an example voltage glitch detection circuitry 106, an example voltage glitch protection circuitry 108, an example single glitch protection circuitry 110, an example multi-glitch protection circuitry 112, an example processing circuitry 114, an example accelerator 116, an example debug subsystem 118, an example general purpose input output (GPIO) 120, and an example power management controller 122.

[0023] Figure 1 The clock oscillator 102 is a device for generating a clock signal. The clock oscillator 102 may include one or more oscillators to generate a periodic signal, which the processing circuit system 114 can use to execute instructions. For example, the clock oscillator 102 may include a first oscillator for generating a first clock signal having a first frequency and a second oscillator for generating a second clock signal having a second frequency. The clock oscillator 102 outputs the generated clock signal to the clock controller 104. In some examples, the clock oscillator 102 may be implemented outside the microcontroller 100, and the clock signal may be provided by the external clock oscillator via a terminal of the microcontroller 100. Figure 1 The clock controller 104 obtains the system clock from the series clock oscillator 102 and distributes the clock signal to other components of the microcontroller 100 via the voltage glitch protection circuitry 108 .

[0024] Figure 1The voltage glitch detection circuitry 106 is a circuitry that detects voltage glitches on internal and / or external rails. For example, the voltage glitch detection circuitry 106 may detect voltage glitches at a VDDD terminal, an internal bus, and / or any other terminal or bus of the microcontroller 100. As described above, a voltage glitch (e.g., also referred to as a voltage undershoot) corresponds to a voltage drop at a terminal or node below an expected value. Thus, the voltage glitch detection circuitry 106 determines when the voltage at a terminal or node is below a threshold. In some examples, the voltage glitch detection circuitry 106 additionally or alternatively identifies a voltage glitch based on a slope and / or width of the voltage glitch. During a voltage glitch, the voltage glitch detection circuitry 106 outputs a signal indicative of the voltage glitch. For example, when there is no voltage glitch, the voltage glitch detection circuitry 106 may output a first voltage (e.g., 0 volts (V) or a logic low). When there is a voltage glitch, the voltage glitch detection circuitry 106 may output a second voltage (e.g., 1.3V or a logic high). The output of the voltage glitch detection circuitry 106 is output to the voltage glitch protection circuitry 108.

[0025] Figure 1The voltage glitch protection circuitry 108 prevents voltage glitches identified by the voltage glitch detection circuitry 106. The voltage glitch protection circuitry 108 includes a single glitch protection circuitry 110 and a multi-glitch protection circuitry 112. In some examples, the single glitch protection circuitry 110 and the multi-glitch protection circuitry 112 are comprised of hardware components and do not rely on instructions from the processing circuitry 114 to operate. In other examples, the voltage glitch protection circuitry 108 may include a combination of hardware and software (e.g., hardware-assisted or software) to implement the techniques described herein. In this way, the voltage glitch protection circuitry 108 may continue to operate when the processing circuitry 114 is suspended. The single glitch protection circuitry 110 determines how to handle a detected glitch. For example, single glitch protection circuitry 110 determines whether to suspend processing circuitry 114, lock accelerator 116, lock debug subsystem 118, and / or reset processing circuitry 114 in response to the voltage glitch. For example, if the voltage glitch drops below a first threshold voltage (e.g., below 1.08V), single glitch protection circuitry 110 may suspend processing circuitry 114 and / or lock accelerator 116 and / or debug subsystem 118. Additionally, if the voltage glitch drops below a second threshold voltage (e.g., 0.6V), single glitch protection circuitry 110 may restart, reboot, etc. processing circuitry 114. After the voltage glitch ends, single glitch protection circuitry 110 may be configured to wait a random amount of time (e.g., a pseudo-random or quasi-random amount of time) before unpausing processing circuitry 114 and / or unlocking accelerator 116 and / or debug subsystem 118. Figure 2 , but the single short-time pulse wave interference protection circuit system 110 can be responsive to the detected voltage short-time pulse wave interference to suspend and / or lock any component and / or device of the microcontroller 100. Figure 2 The example glitch protection circuitry 110 is further described.

[0026] Figure 1The multi-glitch protection circuitry 112 handles multiple glitches that may occur during a startup, start-up, and / or initialization process. The multi-glitch protection circuitry 112 may include a first counter that tracks back-to-back glitches and / or a threshold number of glitches that occur within a threshold amount of time. Additionally, the multi-glitch protection circuitry 112 may include a second counter that tracks the threshold number of glitches throughout the startup, start-up, and / or initialization process. If back-to-back glitches (e.g., two glitches within a short amount of time) and / or a threshold total number of glitches occur, the multi-glitch protection circuitry 112 interrupts the operation of the processing circuitry 114 by causing the processing circuitry 114 to enter a standby mode. For example, the multi-glitch protection circuitry 112 may instruct the power management controller 122 to enter the standby mode. Additionally, the multiple glitch protection circuitry 112 may transmit an indication of the multiple glitches to the GPIO 210 to provide an indication of the multiple glitches to a user (eg, via a user interface). Figure 3 The multi-glitch protection circuitry 112 is further described.

[0027] Figure 1 The processing circuit system 114 executes the instructions. As described above, the processing circuit system 114 executes the instructions using the clock signal generated by the clock oscillator 102. Therefore, when the voltage short pulse wave interference protection circuit system 108 gates the clock signal, the processing circuit system 114 suspends or interrupts operation until the clock signal is not gated. Figure 1 The accelerator 116 is a subsystem and / or one or more processing devices that can perform computationally intensive operations (e.g., instead of being performed by the processing circuit system 114). In some examples, the accelerator 116 can be a cryptographic accelerator (e.g., an Advanced Encryption Standard (AES) accelerator, a public key accelerator (PKA), etc.) that installs and / or stores security keys and / or other security data. Therefore, in response to the voltage glitch, the voltage glitch protection circuit system 108 locks the security keys and / or security data in the accelerator 116 to prevent tampering that may be caused by the glitch. In some examples, the voltage glitch protection circuit system 108 locks the accelerator 116 by changing the settings of the firewall to prevent access to the accelerator 116. Figure 1The debug subsystem 118 of the debug subsystem 118 defines and manages debug sessions, and defines and / or stores information related to when debug modes are enabled and / or disabled, permissions, etc. Thus, in response to a voltage glitch, the voltage glitch protection circuitry 108 locks information in the debug subsystem 118 to prevent tampering that may be caused by the glitch.

[0028] Figure 2 Include Figure 1 A block diagram of an example single glitch protection circuit system 110 is shown. Figure 2 Include Figure 1 The single glitch protection circuitry 110 includes an example clock gating logic circuitry 200, an example random number generator circuitry 202, and an example counter 204.

[0029] Figure 1The clock gating logic circuit system 200 manages the operation and / or access of the processing circuit system 114, the accelerator 116, and / or the debugging subsystem 118 based on the output of the voltage glitch detection circuit system 106. The clock gating logic circuit system 200 obtains the clock signal from the clock controller. If the voltage glitch detection circuit system 106 is outputting a signal indicating the absence of a voltage glitch, the clock gating logic circuit system 200 forwards the clock signal to the example processing circuit system 114 and does not lock any data in the accelerator 116 and / or the debugging subsystem 118. When the voltage glitch detection circuit system 106 outputs a signal indicating a voltage glitch, the clock gating logic circuit system 200 causes the processing circuit system 114 to suspend the execution of instructions. For example, the clock gating logic circuit system 200 may gate the clock signal to prevent the clock signal from reaching the processing circuit system 114. In the absence of the clock signal, the processing circuit system 114 interrupts or suspends the execution of instructions. In addition, when the voltage glitch detection circuitry 106 outputs a signal indicating a voltage glitch, the clock gating logic circuitry 200 locks information contained in the accelerator 116 and / or the debug subsystem 118 so that the information cannot be changed or accessed. For example, the clock gating logic circuitry 200 may change the settings in the firewall to prevent access to the accelerator 116 and / or the debug subsystem 118. The clock gating logic circuitry 200 maintains the gated clock signal and / or the locked accelerator 116 and / or the debug subsystem 118 until the clock gating logic circuitry 200 obtains a signal from the counter 204, as further described below. After the counter 204 outputs a signal indicating the end of the pause, the clock gating logic circuitry 200 unpauses the processing circuitry 114, unlocks the accelerator 116, and / or unlocks the debug subsystem 118. For example, the clock gating logic circuitry 200 may un-gate the clock signal to allow the clock signal to pass to the processing circuitry 114, thereby allowing the processing circuitry 114 to continue operating in the stopped state. Additionally, clock gating logic circuitry 200 may unlock accelerator 116 and / or debug subsystem 118. For example, clock gating logic circuitry 200 may change the settings of a firewall to access accelerator 116 and / or debug subsystem 118.

[0030] After the signal from the voltage glitch detection circuitry 106 indicates that the voltage glitch has ceased, Figure 2 The random number generator circuit system 202 generates a random number. The random number can be selected from a set of pre-selected numbers, or can be any number within a certain range of numbers. As further described below, the random number is used to generate a random delay amount before continuing operation after the voltage short pulse wave interference stops. The random number generator circuit system 202 outputs the generated number to the counter 204.

[0031] Figure 2 The counter 204 of the random number generator circuit system 202 operates as a timer to generate a delay amount based on the number generated by the random number generator circuit system 202. For example, the counter 204 obtains the number generated by the random number generator circuit system 202 and counts down from the number to a predefined value (e.g., 0) or counts up from a predefined number (e.g., 0) to the number. The counter 204 can use a clock signal from one of the clock oscillators 102 to count up or down. After completing the count corresponding to the random number, the counter 204 outputs a signal to the clock gate logic circuit system 200 to trigger the unpause of the processing circuit system 114 and / or the unlocking of the accelerator 116 and / or the debug subsystem 118. In this way, the clock gate logic circuit system 200 will unpause the operation at different times after different voltage short pulse wave interferences, thereby generating randomization to confuse and / or avoid additional attacks from attackers.

[0032] Figure 3 Include Figure 1 A block diagram of an example multi-glitch protection circuit system 112 is shown. Figure 3 Include Figure 1 The voltage glitch detection circuitry 106, the processing circuitry 114, the GPIO 120, and the power management controller 122. The multi-glitch protection circuitry 112 includes an example clock counting circuitry 300, an example counter logic 302, an example counter 304, an example comparator 306, an example glitch counting circuitry 308, example logic gates 310, 316, and an example logic circuitry 312. Figure 3 An example forced standby state register 314 is further included.

[0033] Figure 3 The example clock counting circuit system 300 obtains a user selected and / or configured / configurable value. The value corresponds to a user defined and / or desired amount of time for setting within the counter logic 302. In some examples, the clock counting circuit system 300 is one or more registers storing the user defined value. After a threshold amount of time, the glitch count tracked by the counter logic 302 is reset. Thus, the counter logic 302 tracks more than one glitch occurring within a threshold duration (e.g., consecutive glitches). The clock counting circuit system 300 provides the user defined value to the counter logic 302.

[0034] Figure 3The counter logic 302 may be configured to identify consecutive glitches (e.g., two or more glitches occurring within a threshold amount of time). For example, the counter logic 302 may include a counter that increments based on each pulse of a clock signal after a voltage glitch occurs and resets the count after a threshold number of clock signal pulses. In such an example, the counter logic 302 outputs a first voltage (e.g., a low voltage or 0V) unless a threshold number of glitches occur after the first glitches occur. If a subsequent threshold number of glitches occur within a threshold amount of time before resetting the count, the counter logic 302 outputs a second voltage (e.g., a high voltage or 1.3V). In combination with Figure 5 Examples of adjusting the count based on the number of short-term pulse wave interference are further described. In some examples, counter logic 302 can be implemented in, as part of, or the same as logic circuit system 312 and / or logic. Figure 8 Examples of adjusting the count based on a clock signal are further described.

[0035] Figure 3 The counter 304 tracks the total number of voltage glitches. Thus, when the output of the voltage glitches detection circuitry 106 reflects the detection of a new glitches, the counter 304 adjusts (e.g., increments) to track the total number of voltage glitches identified. The comparator circuitry 306 accesses the count of voltage glitches in the counter 304, as further described below.

[0036] Figure 3 The comparator circuit system 306 of the GPIO 120 accesses the total glitch count from the counter 304 and compares the total glitch count to a threshold value to generate a total glitch count signal. The threshold value may be a user-defined threshold value obtained via the GPIO 120 (e.g., via a user interface) and / or stored in the glitch count threshold circuit system 308. The glitch count threshold circuit system 308 may be one or more registers that store the user-defined glitch count threshold value provided by the user via the GPIO 120 using the user interface. If the total glitch count is less than the threshold value, the comparator circuit system 306 outputs a first voltage (e.g., 0V or a logic low) to indicate that the total glitch count is below the threshold value. If the total glitch count is greater than the threshold value, the comparator circuit system 306 outputs a second voltage (e.g., 1.3V or a logic high) to indicate that the total glitch count is above the threshold value.

[0037] Figure 3An example logic gate 310 is a logic OR gate. Logic gate 310 obtains a first signal from counter logic 302 and a second signal from comparator circuit system 306. When the output of counter logic 302 and / or the output of comparator 306 corresponds to a first voltage (e.g., logic high or 1.3V), logic gate 310 outputs a first voltage (e.g., logic high voltage or 1.3V). When the output of counter logic 302 and the output of comparator 305 both correspond to a second voltage (e.g., logic low or 0V), the logic circuit system outputs a second voltage (e.g., logic low or 0V). The output of logic gate 310 is output to logic circuit system 312.

[0038] Figure 3 The logic circuit system 312 of the logic gate 310 performs one or more actions based on the output of the logic gate 310. For example, after the logic gate 310 switches from the second voltage (e.g., 0V) to the first voltage (e.g., 1.3V) indicating a number of short-time pulse wave interferences greater than a threshold, the logic circuit system 312 performs the task of interrupting the operation of the processing circuit system 114 and causes the processing circuit system 114 to enter the standby mode for at least the threshold amount of time. In some examples, after the output of the logic gate 310 switches from the second voltage to the first voltage, the logic circuit system 312 causes the processing circuit system 114 to interrupt operation. The logic circuit system 312 can gate the clock signal (as described above in conjunction with Figure 2 Logic circuitry 312 waits for processing circuitry 114 to assert the interrupt instruction, and outputs a processing circuitry interrupt signal back to logic circuitry 312. After obtaining the interrupt signal from processing circuitry 114, logic circuitry 312 deasserts the processing circuitry interrupt input, and determines that processing circuitry 114 enters a low power mode and / or a standby mode by transmitting a standby mode request to power management controller 122 (e.g., via logic gate 316).

[0039] In some instances, Figure 3 The logic circuit system 312 drives the pin of GPIO 120 (e.g., outputs a logic high voltage) to provide information to the user related to short-term pulse wave interference, short-term pulse wave interference count, standby mode, etc. The information may include the number of short-term pulse wave interference, the type of short-term pulse wave interference (e.g., total number and continuous), the time when the short-term pulse wave interference occurred, the time to enter the standby mode, etc. In addition, the logic circuit system 312 may store a value in the forced standby state register 314 to indicate that forced standby has occurred. The logic circuit system 312 may include and / or may be connected to a counter or timer to track the duration and / or a random number generator. In some examples, the random number generator may be composed of Figure 2 The random number generator circuit system 202 is implemented, and / or the counter or timer may be implemented by Figure 2 The generated random number may be generated after the logic circuit system 312 and / or the processing circuit system 114 outputs the standby request, and the counter may be clocked using a clock signal (e.g., from Figure 1 102) to and / or from the randomly generated number. In this way, logic circuitry 312 can prevent exiting the standby mode (e.g., preventing wakeup) until after the count is completed. In this way, an attacker cannot override the standby mode until after the randomized duration. In some examples, logic circuitry 312 can be configured to detect the presence of a randomized duration in counter logic 302 and / or Figure 2 embodied in the clock gating logic circuit system 200, as counter logic 302 and / or Figure 2 part of the clock gating logic circuitry 200, or may be coupled with the counter logic 302 and / or Figure 2 The clock gate logic circuit system 200 is the same.

[0040] Figure 3 An example logic gate 316 is a logic OR gate. Logic gate 316 obtains a first signal from logic circuit system 312 and a second signal from processing circuit system 114. When the output of logic circuit system 312 and / or the output of processing circuit system 114 corresponds to a first voltage (e.g., logic high or 1.3V), logic gate 316 outputs the first voltage (e.g., logic high voltage or 1.3V). When the output of logic circuit system 312 and the output of processing circuit system 114 both correspond to a second voltage (e.g., logic low or 0V), the logic circuit system outputs the second voltage (e.g., logic low or 0V). The output of logic gate 316 is output to power management controller 122. In this way, power management controller 122 can enter standby mode in response to a trigger from logic circuit system 312 and / or processing circuit system 114.

[0041] Figure 4 It means that Figure 1 The processing circuitry of the microcontroller 100 or any other circuitry of the microcontroller 100 may perform and / or instantiate a method and / or a flowchart of example operations 400 for preventing single voltage short-time pulse wave interference. Figure 1 Description of the microcontroller 100 Figure 4 The present invention relates to instructions and / or operations of the present invention, but the instructions and / or operations may be described in conjunction with any type of circuitry that implements the processing circuitry. Figure 4 Some of the processes shown in the can be performed in an order other than the order described, and many processes can be performed simultaneously in parallel. In addition, in some examples of the present disclosure, the Figure 4 The process shown in .

[0042] Figure 4 The machine readable instructions and / or operations 400 of the embodiment of the present invention begin at block 402, where the clock gating logic circuit system 200 determines whether a glitch has been detected based on the output of the voltage glitch detection circuit system 106. For example, if the output of the voltage glitch detection circuit system 106 is a first voltage, the clock gating logic circuit system 200 determines that a glitch has not been detected. After the voltage glitch detection circuit system 106 changes the first voltage to a second voltage, the clock gating logic circuit system 200 determines that a glitch has been detected. In some examples, the clock gating logic circuit system 200 determines that a glitch is occurring based on a rising edge of the output of the voltage glitch detection circuit system 106. If the clock gating logic circuit system 200 determines that a glitch has not been detected (block 402: No), control returns to block 402. If the clock gating logic circuit system 200 determines that a glitch has been detected (block 402: yes), the clock gating logic circuit system 200 determines whether the glitch is a large glitch or a small glitch (block 404). A small glitch is a glitch that causes the power supply voltage to drop below a first threshold (e.g., 1V), and a large glitch is a glitch that causes the power supply voltage to drop below a second threshold (e.g., 0.5V). The second threshold is based on the amount of voltage drop that may cause a register to unintentionally change value (e.g., roll over). In some examples, the voltage glitch detection circuit system 106 may transmit a first signal when the monitored voltage drops below a first threshold corresponding to a small glitch, and transmit a second signal when the monitored voltage drops below a second threshold corresponding to a large glitch. In some examples, two voltage glitch detection circuit systems may be implemented in the microcontroller 100. For example, a first voltage glitch detection circuitry may detect a small glitch, and a second voltage glitch detection circuitry may detect a large glitch. In this manner, clock gating logic circuitry 200 may determine whether a glitch is a large glitch or a small glitch based on the output of one or more voltage glitch detection circuitry.

[0043] If the clock gating logic circuitry 200 determines that the glitch is a large glitch (block 404: large), the clock gating logic circuitry 200 triggers a chip reset by sending a reset instruction to the processing circuitry 114 (block 406). In this way, any stored values ​​that may have flipped due to the large glitch can be reset when the chip is reset and the startup, start-up, and / or initialization process can be restarted. If the clock gating logic circuitry 200 determines that the glitch is a small glitch (block 404: small), the clock gating logic circuitry 200 halts the processing circuitry 114 by gating the clock signal to prevent the processing circuitry 114 from obtaining the clock signal (block 408). As described above, in the absence of the clock signal, the processing circuitry 114 will not execute instructions. Therefore, gating the clock signal halts the processing circuitry 114 from executing instructions. Additionally or alternatively, the clock gate logic circuit system 200 may be configured to pause the processing circuit system 114 by asserting a stall or interrupt signal or using any other method. At block 410, the clock gate logic circuit system 200 locks the key and / or security data in the accelerator 116. For example, the clock gate logic circuit system 200 may be configured to apply read / write protection to the accelerator 116 so that no data can be read from or written to the accelerator 116 during the lock period. As another example, the clock gate logic circuit system 200 may adjust the firewall settings to prevent access to the key and / or security data of the accelerator 116. At block 412, the clock gate logic circuit system 200 locks the data in the debug subsystem 118. For example, the clock gate logic circuit system 200 may adjust the firewall settings to prevent data access or modification by the debug subsystem 118. Additionally or alternatively, the clock gate logic circuit system 200 may be configured to apply read / write protection to one or more of the accelerators 116.

[0044] At block 414, the clock gating logic circuit system 200 determines whether the glitch has ended (e.g., based on a falling edge of the output of the voltage glitch detection circuit system 106). If the clock gating logic circuit system 200 determines that the glitch has not ended (block 414: No), control returns to block 414 until the end of the glitch is detected. If the clock gating logic circuit system 200 determines that the glitch has ended (block 414: Yes), the random number generator circuit system 202 generates a random number (block 416). In other examples, the clock gating logic circuit system 200 may be configured to generate a non-random number having a value that is difficult for an attacker to predict. Therefore, the attacker may not be able to determine the timing loop information about the device. At block 418, the counter 204 waits for a duration corresponding to the random number (block 418). For example, the counter 204 may increment or decrement the counter from a preset value (e.g., zero) to / from a random value to a preset value to wait for a random duration corresponding to the random number. At block 420, after the random duration, the example clock-gating logic circuitry 200 un-pauses the processing circuitry 114 by de-gating the clock signal to allow the processing circuitry 114 to receive the clock signal and continue to execute instructions. Additionally or alternatively, the clock-gating logic circuitry 200 may be configured to de-assert a stall or interrupt signal to un-pause the processing circuitry 114. At block 422, the clock-gating logic circuitry 200 unlocks the keys and / or secure data in the accelerator 116. For example, the clock-gating logic circuitry 200 may adjust the firewall settings to allow access to the keys and / or secure data of the accelerator 116. At block 424, the clock-gating logic circuitry 200 unlocks the data in the debug subsystem 118. For example, the clock-gating logic circuitry 200 may adjust the firewall settings to allow data access or modification by the debug subsystem 118. At block 424, control returns to block 402.

[0045] Figure 5 It means that Figure 1 The processing circuitry of the microcontroller 100 or any other circuitry of the microcontroller 100 may perform and / or instantiate a method and / or a flowchart of example operations 500 for preventing multi-voltage short-time pulse wave interference. Figure 1 Description of the microcontroller 100 Figure 5 The present invention relates to instructions and / or operations of the present invention, but the instructions and / or operations may be described in conjunction with any type of circuitry that implements the processing circuitry.

[0046] Figure 5The machine readable instructions and / or operations 500 of the embodiment of the present invention begin at block 502, where the counter logic 302 and / or the counter 304 determine whether a voltage glitch is detected. For example, the counter logic 302 and / or the counter 304 may determine that a voltage glitch is detected when the output of the voltage glitch detection circuit system 106 rises from a low voltage to a high voltage. If the counter logic 302 and / or the counter 304 determine that a glitch is not detected (block 502: No), control returns to block 502 until a glitch is detected. If the counter logic 302 and / or the counter 304 determine that a glitch is detected (block 502: Yes), the counter logic 302 initiates clock tracking by adjusting a first count based on a clock signal (block 503). At block 504, the counter 304 adjusts a second count. For example, if the counter 304 is counting up to the threshold number, the second count will be incremented, and if the counter 304 is counting down from the threshold number, the second count will be decremented.

[0047] At block 506, the counter logic 302 determines whether a threshold number of glitches have occurred while the clock is being tracked (e.g., whether there are a threshold number of glitches (continuous (B2B) glitches) within a threshold duration). If the counter logic 302 determines that a threshold number of glitches have occurred while the clock is being tracked (block 506: yes), control continues to block 514. If the counter logic 302 determines that the first count has not reached the first threshold (block 506: no), the second counter 304 determines whether the second count has reached the second threshold (block 508). In other words, the counter logic 302 may be configured to determine whether the number of glitches has reached the second threshold while the clock is being tracked. If the second counter 304 determines that the second count has reached the second threshold (block 508: yes), control continues to block 514. If the second counter 304 determines that the second count has not reached the second threshold (block 508: no), the counter logic 302 determines whether the first count has reached a threshold corresponding to a user-defined threshold amount of time (block 510). If the counter logic 302 determines that the first count has reached the threshold (block 510: No), the counter logic 302 and / or the counter 304 determines whether a subsequent short pulse wave interference is detected (block 511). If the first counter logic 302 determines that the first count has reached the threshold (block 510: Yes), the counter logic 302 resets the first count (block 512) and control returns to block 502.

[0048] If the counter logic 302 and / or counter 304 determine that a subsequent glitch has not been detected (block 511: No), control returns to block 510. If the counter logic 302 and / or counter 304 determine that a subsequent glitch has been detected (block 511: Yes), control returns to block 504. At block 514, the example logic circuitry 312 determines that a glitch threshold has been reached (e.g., via the output of logic gate 310), and the logic circuitry 312 outputs a multiple glitch indication signal to the forced standby state register 314 and / or GPIO 120. In this manner, information related to multiple glitches may be provided to a user (via an interface) and / or another device via GPIO 120, and an indication of forced standby may be stored in the forced standby state register 314. In some examples, the forced standby state register 314 may indicate to the power management controller 122 and / or any other device whether forced standby is in place.

[0049] At block 516, the example logic circuitry 312 interrupts the processing circuitry operation. The logic circuitry 312 may interrupt the processing circuitry operation by gating the clock signal and / or transmitting an instruction to the processing circuitry 114. At block 518, the logic circuitry 312 and / or the processing circuitry 114 triggers the standby state by sending an instruction to the power management controller 122 (e.g., via the logic gate 316). At block 520, the logic circuitry 312 and / or the counter 204 start a timer and / or a counter. At block 522, the example logic circuitry 312 and / or the random number generator circuitry 202 generates a random number. At block 524, the example logic circuitry 312 and / or the example power management controller 122 determines whether a wake-up signal has been obtained (e.g., via the GPIO 120). If the example logic circuitry 312 and / or the example power management controller 122 determines that a wake-up signal has not been obtained (block 524: No), control returns to block 524 until a wake-up signal is obtained. If the example logic circuitry 312 and / or the example power management controller 122 determines that a wake-up signal has been obtained (block 524, yes), the example logic circuitry 312 determines whether a timer and / or counter has reached a threshold based on the random number (block 526). For example, the timer and / or counter may be designed to count up to the random number or count down from the random number.

[0050] If the logic circuit system 312 determines based on the random number that the timer and / or counter has reached the threshold value (block 526: yes), the logic circuit system 312 triggers the exit of the standby mode by instructing the power management controller 122 to exit the standby mode and / or by resetting the forced standby state register 314 (block 528). In some examples, the power management controller 122 monitors the forced standby state register 314 to determine when the standby mode can be exited. Therefore, the logic circuit system 312 can reset the register 314 so that the power management controller 122 can exit the standby mode after resetting the register 314 and obtaining the request to exit the standby mode. If the logic circuit system 312 determines based on the random number that the timer and / or counter has not reached the threshold value (block 528), the logic circuit system 312 and / or the power management controller 122 waits for the threshold time to be reached to exit the standby mode (block 530). As described above, the logic circuit system 312 can indicate that the threshold amount of time has been reached by sending an instruction to the power management controller 122 and / or by resetting the value in the register 314.

[0051] Figure 6 is with Figure 2 The example timing diagram 600 corresponds to an example timing of the operation of the single short pulse wave interference protection circuit system 110. The example timing diagram 600 includes an example input voltage 601, an example internal voltage 602, an example short pulse wave interference based reset timing diagram 604 and an example short pulse wave interference based pause timing diagram 606. The input voltage 601 corresponds to Figure 1 The internal voltage 602 corresponds to an input terminal of the microcontroller 100 that obtains a voltage from a power supply (eg, VDDD). The internal voltage 602 corresponds to a voltage rail that connects the input terminal of the microcontroller 100 to other components within the microcontroller 100. Although Figure 6 The timing diagrams correspond to specific voltage levels, but the voltage levels, slopes, thresholds, etc. can correspond to any voltage levels, slopes, thresholds, etc.

[0052] Figure 6 The input voltage 601 of the microcontroller 100 is set to a specific voltage (e.g., 1.32V). However, as shown in the input voltage 601, the short-term pulse wave interference causes the input voltage 601 to drop or undershoot the expected voltage for a duration. Due to the internal capacitance and / or inductance of the components within the microcontroller 100, the short-term pulse wave interference applied to the input voltage 601 at the input terminal of the microcontroller 100 causes a smoother and longer voltage dip on the internal voltage rail, as shown in the internal voltage 602. The short-term pulse wave interference causes the internal voltage to drop below the short-term pulse wave interference threshold of 1.08V for a duration. When Figure 2When the voltage glitch detection circuitry 106 detects that the input voltage 601 and / or the internal voltage 602 drops below a threshold, some techniques reset the chip (e.g., corresponding to diagram 604), while other techniques suspend the processing circuitry (e.g., corresponding to diagram 606). In diagram 604, after the glitch ends, the chip is restarted, and the processing circuitry must reinitialize the application and re-execute any instructions executed before the glitch. In diagram 606, after the glitch ends, the logic circuitry can be configured to cause the processing circuitry to resume operation after a random delay, thereby resulting in latency and power savings improvements.

[0053] Figure 7 is with Figure 2 1. Example timing diagram 700 corresponding to example timing of operation of single glitch protection circuitry 110 of the embodiment of the present invention. Example timing diagram 700 includes example processing circuitry clock signal 701, example glitch detection output 702, example accelerator lock signal 704, example debug lock signal 706, example random number generator trigger 708, and example random delay counter signal 710. Example processing circuitry clock signal 701 corresponds to a clock signal obtained at processing circuitry 114. Glitch detection output signal 702 corresponds to the output of voltage glitch detection circuitry 106. Accelerator lock signal 704 and debug lock signal 706 correspond to signals output by clock gating logic circuitry 200 to accelerator 116 and debug subsystem 117. Random delay counter 710 corresponds to the count tracked by counter 204.

[0054] Before the glitch detection output signal 702 changes from a low voltage to a high voltage, the clock signal 701 is oscillating. Therefore, the processing circuit system 114 executes instructions based on the clock signal 701. After the glitch, the output 702 changes to a high voltage (e.g., indicating that a voltage glitch is occurring), and the single glitch protection circuit system 110 gates the clock signal 701 to prevent the processing circuit system from obtaining the clock signal. Therefore, the clock signal 701 remains low until the single glitch detection circuit system de-gates the clock signal. In addition, the single glitch protection circuit system 110 locks the accelerator 116 and the debug subsystem 118, as shown in signals 704, 706. After the glitch ends and the glitch detection output signal 702 drops to a low voltage, the random number generator circuit system 202 is triggered to generate a random number. As indicated by the random number trigger signal 708. Counter 204 uses the random number to generate a random delay amount (e.g., by incrementing a count to the random number, by incrementing a count from the random number, etc.), as shown at random delay counter 710. After the random delay ends, clock gating logic circuitry 200 de-gates the clock signal and unlocks accelerator 116 and debug subsystem 118, as indicated by processing circuitry clock signal 701, accelerator lock signal 704, and debug lock signal 706.

[0055] Figure 8 is with Figure 3 1. An example timing diagram 800 is shown corresponding to an example timing of operation of the multi-glitch protection circuitry 112 of FIG. 1. The example timing diagram 800 includes an example clock signal 802, an example glitch detection output signal 804, an example first count signal 806, an example count threshold signal 808, an example continuous glitch indication signal 810, an example total glitch count threshold signal 812, an example second count signal 814, and an example multi-glitch detection signal 816. The clock signal 802 corresponds to the output of the one or more oscillators 102. The glitch detection output 804 corresponds to the output of the voltage glitch detection circuitry 106. The counter signal 806 corresponds to the count tracked by the counter logic 302. The first count signal 808 corresponds to the value stored in the counting circuitry 300. The continuous (B2B) glitch indication signal 810 corresponds to the output of the counter logic 302. Glitch count threshold 812 corresponds to the value stored in glitch count threshold circuitry 308. Second counter signal 814 corresponds to the count tracked by counter 304. Multi-glitch detection signal 816 corresponds to the signal output by comparator circuitry 306.

[0056] When the voltage glitch detection circuitry 106 detects a first glitch, as shown in glitch detection output 804, the counter logic 302 begins counting rising edges of the clock signal 802. However, the counter logic 302 may count up or down based on any portion of the clock signal 802. Figure 8 In the example of , the threshold number of clock pulses is based on the count signal 808 corresponding to 16 clock pulses (e.g., hexadecimal 10). Therefore, if the threshold number of short-time pulse wave interference occurs within the duration corresponding to 16 clock pulses (e.g., Figure 8 2), then a B2B glitch detection signal is triggered, as shown in the B2B glitch indication signal 810. In addition, the counter 304 tracks the total number of glitches that occurred. Thus, for each clock pulse of the glitch detection output signal 804, the counter 304 increments the total glitch count, as shown in the second count signal 814. Because Figure 8 The glitch count threshold in is set to 3, as shown in glitch count threshold 812, so when the counter signal 814 reaches a count of 3, the multi-glitch detect signal triggers.

[0057] Fig. 9 is with Figure 3 14. Example timing diagram 900 corresponds to example timing of operation of multi-glitch protection circuitry 112 of FIG. Example timing diagram 900 includes example B2B or multi-glitch detection signal 902, example processing circuitry interrupt input signal 904, example processing circuitry interrupt output signal 906, example standby request override signal 908, example standby entry signal 910, and example IO pin output signal 912. B2B or multi-glitch detection signal 902 corresponds to the output of logic gate 310. Processing circuitry interrupt input signal 904 corresponds to the output from logic circuitry 312 to processing circuitry 114. Processing circuitry interrupt output signal 906 corresponds to the output signal from processing circuitry 114 to logic circuitry 312. Standby request override signal 908 corresponds to the output of logic circuitry 312, processing circuitry 114, and / or logic gate 316 to power management controller 122. IO pin output signal 912 corresponds to the output of GPIO 120.

[0058] After triggering the B2B or multi-short pulse wave interference detection signal 902 by the logic gate 310, the logic gate circuit system 312 triggers the processing circuit system interrupt input signal 904 to cause the processing circuit system 114 to interrupt and / or suspend operation. After the interrupt instruction, the processing circuit system 114 responds by triggering the processing circuit system interrupt output signal 908. After triggering the processing interrupt output signal 906, the logic circuit system 312 and / or the processing circuit system 114 triggers the standby request override signal 908. As described above, the power management controller 122 initiates the standby mode based on the triggering of the standby request override signal 908. In addition, after triggering the processing interrupt output signal 906, the logic circuit system 312 triggers the IO pin output 912 via the GPIO 120 to indicate to the user or device that a forced standby is occurring due to multiple short-time pulse wave interference. After triggering the standby override signal 908, the power management controller 122 triggers the standby entry, as shown in the standby entry signal 910.

[0059] exist Figures 1 to 3 Implementation Figure 1 However, Figures 1 to 3 One or more of the elements, processes, and / or means described in the drawings may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0060] In addition, the clock oscillator 102, the clock controller 104, the voltage glitch detection circuit system 106, the voltage glitch protection circuit system 108, the single glitch protection circuit system 110, the multiple glitch protection circuit system 112, the processing circuit system 114, the accelerator 116, the debug subsystem 118, the GPIO 120, the power management controller 122, the clock gating logic circuit system 200, the random number generator circuit system 202, the counter 204, the clock counting circuit system 300, the counter logic 302, the counter 304, the comparator circuit system 306, the glitch count threshold circuit system 308, the logic gates 310, 316, the logic circuit system 312 and / or the forced standby state register 314 may be implemented by hardware, software, firmware and / or any combination of hardware, software and / or firmware. Thus, for example, clock oscillator 102, clock controller 104, voltage glitch detection circuitry 106, voltage glitch protection circuitry 108, single glitch protection circuitry 110, multi-glitch protection circuitry 112, processing circuitry 114, accelerator 116, debug subsystem 118, GPIO Any of 120, power management controller 122, clock gate logic circuit system 200, random number generator circuit system 202, counter 204, clock counting circuit system 300, counter logic 302, counter 304, comparator circuit system 306, short-term pulse wave interference count threshold circuit system 308, logic gates 310, 316, logic circuit system 312 and / or forced standby state register 314 can be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and / or field programmable logic devices (FPLDs).

[0061] When any apparatus or system solution of this patent is read to cover pure software and / or firmware implementations, the clock oscillator 102, the clock controller 104, the voltage short-time pulse wave interference detection circuit system 106, the voltage short-time pulse wave interference protection circuit system 108, the single short-time pulse wave interference protection circuit system 110, the multi-short-time pulse wave interference protection circuit system 112, the processing circuit system 114, the accelerator 116, the debugging subsystem 118, the GPIO 120, power management controller 122, clock gate logic circuit system 200, random number generator circuit system 202, counter 204, clock counting circuit system 300, counter logic 302, counter 304, comparator circuit system 306, short-time pulse wave interference count threshold circuit system 308, logic gates 310, 316, logic circuit system 312 and / or at least one of the forced standby state register 314 are hereby explicitly defined as including a non-temporary computer-readable storage device or storage disk, such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including software and / or firmware. Still further, clock oscillator 102, clock controller 104, voltage glitch detection circuitry 106, voltage glitch protection circuitry 108, single glitch protection circuitry 110, multiple glitch protection circuitry 112, processing circuitry 114, accelerator 116, debug subsystem 118, GPIO 120, power management controller 122, clock gating logic circuitry 200, random number generator circuitry 202, counter 204, clock counting circuitry 300, counter logic 302, counter 304, comparator circuitry 306, glitch count threshold circuitry 308, logic gates 310, 316, logic circuitry 312, and / or forced standby state register 314 may include other than Figures 1 to 3 The present invention may include one or more elements, processes and / or devices in addition to or in place of the elements, processes and / or devices shown in the present invention, and / or may include more than one of any or all of the elements, processes and devices described. As used herein, the phrase "communication" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals and / or one-time events.

[0062] Figures 4 to 5 The display is used for implementation Figures 1 to 3The microcontroller 100 of the present invention is a flowchart of an example hardware logic, machine readable instructions, hardware implemented state machine, and / or any combination thereof. The machine readable instructions may be one or more executable programs or portions of an executable program for execution by a computer processor. The program may be implemented in software stored on a non-transitory computer readable storage medium such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disk, or memory associated with a processor, but the entire program and / or portions thereof may alternatively be executed by a device other than a processor, and / or implemented in firmware or dedicated hardware.

[0063] In addition, although the reference Figures 4 to 5 The flowcharts illustrated in describe example procedures, but many other methods of implementing the microcontroller 100 may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Also or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuitry, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform corresponding operations without executing software or firmware.

[0064] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like. The machine-readable instructions as described herein may be stored as data (e.g., portions of instructions, code, representations of code, and the like) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). The machine-readable instructions may require one or more of installation, modification, adaptation, update, combination, supplementation, configuration, decryption, decompression, decapsulation, distribution, redistribution, compilation, and the like in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, where the portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as the program described herein.

[0065] In another example, the machine-readable instructions may be stored in a state where a computer can read them, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding programs may be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Thus, the described machine-readable instructions and / or corresponding programs encompass these machine-readable instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs when stored or otherwise at rest or in transit.

[0066] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0067] As mentioned above, Figure 8 The example processes of may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on a non-transitory computer and / or machine readable medium, such as a hard drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for a short period of time, temporary buffering and / or caching of information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media.

[0068] Example methods, apparatus, and articles of manufacture have been described to improve the accuracy and / or efficiency of current limiting circuitry. The described methods, apparatus, and articles of manufacture improve the accuracy and / or efficiency of current limiting circuitry using a diode-connected device, a current source, and a gain stage.

[0069] Although certain example methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture falling within the scope of the claims of this patent.

[0070] When identifying multiple elements or components that can be mentioned separately, the descriptors "first", "second", "third", etc. are used in this article. Unless otherwise specified or known based on the context of use of such descriptors, such descriptors do not give any priority, physical order, or arrangement in a list or time ordering, but are only used as labels to refer to multiple elements or components respectively, so as to facilitate understanding of the described examples. In some instances, the descriptor "first" can be used to refer to an element in a specific embodiment, while the same element can be referred to in the claims by different descriptors such as "second" or "third". In these cases, these descriptors are used only for the convenience of referring to multiple elements or components.

[0071] In this specification and claims, unless otherwise stated, the terms "including" and "having" and variations thereof are included in a manner similar to the term "comprising". Unless otherwise stated, "about", "approximately" or "substantially" preceding a value means + / -10% of the stated value. In another example, "about", "approximately" or "substantially" preceding a value means + / -5% of the stated value. In another example, "about", "approximately" or "substantially" preceding a value means + / -1% of the stated value.

[0072] As used herein, the terms "couple", "coupled", "couples", and variations thereof may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal for controlling device B to perform an action, then: in a first instance, device A is coupled to device B; or in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A. In addition, the terms "couple", "coupled", "couples", or variations thereof include indirect or direct electrical or mechanical connections.

[0073] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0074] Although not in Figures 1 to 3Although all are individually labeled in the , the components or elements of the systems and circuits described therein have one or more conductors or terminals that allow signals to enter and / or exit the components or elements. The conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0075] As used herein, a "terminal" of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component generally refers to a conductor, such as a wire, trace, pin, pad, or other connector or interconnect, which enables a component, device, system, etc. to be electrically and / or mechanically connected to another component, device, system, etc. For example, a terminal can be used to receive or provide an analog or digital electrical signal (or only a signal), or electrically connected to a common or ground reference. Thus, an input terminal or input is used to receive a signal from another component, device, system, etc. An output terminal or output is used to provide a signal to another component, device, system, etc. Other terminals can be used to connect to a common, ground, or voltage reference, such as a reference terminal or a ground terminal. The terminal of an IC or PCB may also be referred to as a pin (vertical conductor) or a pad (planar conductor). A node refers to a connection point or interconnection point of two or more terminals. An example number of terminals and nodes may be shown. However, depending on a specific circuit or system topology, there may be more or fewer terminals and nodes. However, in some cases, "terminals," "nodes," "interconnects," "pads," and "pins" may be used interchangeably.

[0076] Example methods, devices, systems, and articles of manufacture for preventing voltage short-time pulse wave interference attacks in microcontrollers are disclosed herein. Additional examples and combinations thereof include the following: Example 1 includes a device, the device comprising: a logic circuit system, which is operable to suspend a processing circuit system in response to a voltage short-time pulse wave interference; a digital generator circuit system, which is operable to generate a number; a counter, which is operable to adjust a count corresponding to the number after the voltage short-time pulse wave interference ends; and the logic circuit system is operable to unsuspend the processing circuit system after the count reaches a certain value.

[0077] Example 2 includes the apparatus of example 1, wherein the logic circuitry is operable to halt the processing circuitry by preventing the processing circuitry from receiving a clock signal.

[0078] Example 3 includes the apparatus of example 1, wherein the logic circuitry is operable to un-pause the processing circuitry by allowing the processing circuitry to receive a clock signal.

[0079] Example 4 includes the apparatus of example 1, wherein the logic circuitry is to lock data in the subsystem.

[0080] Example 5 includes an apparatus according to Example 1, wherein the number is a first number, the count is a first count, the value is a first value, and the voltage glitch is a first voltage glitch, wherein the logic circuitry is operable to suspend the processing circuitry in response to a second voltage glitch, the digital generator circuitry is operable to generate a second number different from the first number, the counter is operable to adjust a second count corresponding to the second number after the second voltage glitch ends, and the logic circuitry is operable to un-suspend the processing circuitry after the second count reaches a second value.

[0081] Example 6 includes an apparatus according to Example 1, wherein the counter is a first counter, the count is a first count, and the logic circuit system is a first logic circuit system, further comprising: a second counter, which is operable to adjust a second count in response to the voltage short-time pulse wave interference and output a multi-short-time pulse wave interference indication signal when the second count meets a threshold; and a second logic circuit system, which is operable to cause the processing circuit system to enter a standby mode based on the multi-short-time pulse wave interference indication signal.

[0082] Example 7 includes the apparatus of example 6, wherein the threshold is user defined.

[0083] Example 8 includes an apparatus according to Example 1, wherein the counter is a first counter, the count is a first count, and the logic circuit system is a first logic circuit system, further comprising: a second counter, which is operable to output a continuous short-time pulse wave interference indication signal when a subsequent voltage short-time pulse wave interference is detected within a threshold duration; and a second logic circuit system, which is operable to cause the processing circuit system to enter a standby mode based on the continuous short-time pulse wave interference indication signal.

[0084] Example 9 includes the apparatus of example 8, wherein the threshold duration is user defined.

[0085] Example 10 includes the apparatus of Example 8, wherein the second logic circuitry is to generate a number and prevent the processing circuitry from exiting the standby mode until a threshold amount of time corresponding to the number.

[0086] Example 11 includes a method comprising: suspending execution of instructions by processing circuitry in response to a voltage glitch; generating a number; and unsuspending the processing circuitry based on the number.

[0087] Example 12 includes the method of example 11, wherein the suspending the execution of instructions by the processing circuitry includes preventing the processing circuitry from receiving a clock signal.

[0088] Example 13 includes the method of example 12, wherein the un-pausing the execution of instructions by the processing circuitry includes allowing the processing circuitry to receive the clock signal.

[0089] Example 14 includes the method of Example 11, further comprising adjusting a count in response to the voltage glitch, and causing the processing circuitry to enter a standby mode based on the count.

[0090] Example 15 includes the method of Example 11, further including determining that a subsequent voltage glitches is detected within a threshold duration after the voltage glitches are detected, and causing the processing circuit system to enter a standby mode in response to determining that the subsequent voltage glitches are detected within the threshold duration.

[0091] Example 16 includes an apparatus comprising: counter logic circuitry operable to adjust a count based on a voltage glitch; and logic circuitry operable to cause processing circuitry to enter a standby mode based on the count.

[0092] Example 17 includes the apparatus of Example 16, wherein the logic circuitry is operable to prevent the standby mode from terminating until a timer reaches a threshold duration.

[0093] Example 18 includes an apparatus according to Example 16, wherein the count is a count of clock pulses occurring after the voltage short pulse wave interference, and wherein the logic circuit system is operable to cause the processing circuit system to enter the standby mode if a subsequent voltage short pulse wave interference is detected within a user-defined threshold time amount.

[0094] Example 19 includes the apparatus of Example 18, wherein the counter logic circuitry is operable to reset the count after the user-defined threshold amount of time.

[0095] Example 20 includes the apparatus of Example 16, wherein the logic circuitry is operable to cause the processing circuitry to enter the standby mode by adjusting a value stored in a status register corresponding to the standby mode.

[0096] Example 21 includes the apparatus of Example 16, wherein the count corresponds to a count of voltage glitches, wherein the logic circuitry is operable to cause the processing circuitry to enter a standby mode when the count reaches a user-defined threshold.

[0097] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. A device comprising: logic circuitry operable to suspend execution of instructions by the processing circuitry in response to a voltage glitch; as well as a digital generator circuit system operable to generate a digital number, Wherein the logic circuitry is operable to un-pause the processing circuitry based on the number.

2. The apparatus of claim 1, wherein the logic circuitry is operable to halt execution of instructions by the processing circuitry by preventing the processing circuitry from receiving a clock signal.

3. The apparatus of claim 2, wherein the logic circuitry is operable to un-pause the execution of instructions by the processing circuitry by allowing the processing circuitry to receive the clock signal.

4. The apparatus of claim 1, further comprising a subsystem, wherein the logic circuitry is operable to lock the subsystem in response to the voltage glitch.

5. The apparatus of claim 4, wherein the logic circuitry is operable to lock data stored in the subsystem in response to the voltage glitch.

6. The apparatus of claim 1 , wherein the digital number is a first digital number and the voltage glitch is a first voltage glitch, wherein: The logic circuitry is operable to suspend the processing circuitry in response to a second voltage glitch; The number generator circuitry is operable to generate a second number different from the first number; and The logic circuitry is operable to un-pause the processing circuitry based on the second number after pausing the processing circuitry in response to the second voltage glitch.

7. The apparatus of claim 1, wherein the logic circuitry is a first logic circuitry, the apparatus further comprising: a counter operable to adjust a count in response to the voltage glitch; and Second logic circuitry is operable to cause the processing circuitry to enter a standby mode based on the count.

8. The apparatus of claim 7, wherein the second logic circuitry is operable to cause the processing circuitry to enter the standby mode in response to determining that the count satisfies a user-defined threshold.

9. The apparatus of claim 1, wherein the logic circuitry is a first logic circuitry, the apparatus further comprising: The second logic circuitry is operable to: determining that a subsequent voltage glitch is detected within a threshold duration after the voltage glitch is detected; and The processing circuitry is caused to enter a standby mode in response to determining that the subsequent voltage glitch is detected within the threshold duration.

10. The apparatus of claim 9, wherein the threshold duration is user defined.

11. The apparatus of claim 9, wherein the number is a first number, and wherein the second logic circuitry is operable to: generating a second number; and The processing circuitry is prevented from exiting the standby mode based on the second number.

12. A method comprising: suspending execution of instructions by the processing circuit system in response to a voltage short pulse wave interference; Generate numbers; as well as The processing circuitry is unpaused based on the number.

13. The method of claim 12, wherein the halting the processing circuitry to halt the execution of instructions comprises preventing the processing circuitry from receiving a clock signal.

14. The method of claim 13, wherein the un-pausing the execution of instructions by the processing circuitry comprises allowing the processing circuitry to receive the clock signal.

15. The method of claim 12, further comprising: adjusting a count in response to the voltage glitch; and The processing circuitry is caused to enter a standby mode based on the count.

16. The method of claim 12, further comprising: determining that a subsequent voltage glitch is detected within a threshold duration after the voltage glitch is detected; and The processing circuitry is caused to enter a standby mode in response to determining that the subsequent voltage glitch is detected within the threshold duration.

17. An apparatus comprising: counter logic circuitry operable to adjust a count based on a voltage glitch; as well as Logic circuitry is operable to cause processing circuitry to enter a standby mode based on the count.

18. The apparatus of claim 17, wherein the logic circuitry is operable to prevent the standby mode from terminating until a timer reaches a threshold duration.

19. The apparatus of claim 17, wherein the count is a count of clock pulses occurring after the voltage glitch, wherein the logic circuitry is operable to cause the processing circuitry to enter the standby mode if a subsequent voltage glitch is detected within a user defined threshold amount of time.

20. The apparatus of claim 19, wherein the counter logic circuitry is operable to reset the count after the user defined threshold amount of time.

21. The apparatus of claim 17, wherein the logic circuitry is operable to cause the processing circuitry to enter the standby mode by adjusting a value stored in a status register corresponding to the standby mode.

22. The apparatus of claim 17, wherein the count corresponds to a count of voltage glitches, wherein the logic circuitry is operable to cause the processing circuitry to enter a standby mode when the count reaches a user-defined threshold.

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