Design method, design device and computer readable storage medium of semiconductor structure

Abstract

The present disclosure provides a design method of a semiconductor structure, a design device and a computer readable storage medium, wherein the design method of the semiconductor structure comprises: adjusting a wiring mode of a metal line in a representative volume element to obtain a plurality of representative volume elements with different metal line wiring modes; establishing a plurality of first finite element simulation models for the plurality of representative volume elements, and obtaining equivalent material properties of the plurality of first finite element simulation models respectively; and based on the equivalent material properties of the plurality of first finite element simulation models and a material property of a substrate, establishing a plurality of second finite element simulation models for a semiconductor structure to be designed, and simulating warping deformation of the plurality of second finite element simulation models during a heat treatment process and after the heat treatment process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor structure design, and more particularly to a semiconductor structure design method, design equipment, and computer-readable storage medium. Background Technology

[0002] Semiconductor structures (such as memory) typically consist of a wafer and interconnect structures formed on the wafer, which are composed of multiple metal lines. During the manufacturing process of the interconnect structures, wafer warping can occur due to factors such as thermal expansion coefficient mismatch, thereby reducing the performance of the semiconductor structure. Summary of the Invention

[0003] This disclosure provides a method for designing a semiconductor structure. The semiconductor structure to be designed includes a substrate and an interconnect layer located on the substrate. The interconnect layer includes a plurality of periodically arranged minimum repeatable volume units. The minimum repeatable volume units are used as representative volume elements of the interconnect layer. The representative volume element includes an interlayer dielectric layer and a plurality of metal lines located within the interlayer dielectric layer. The design method includes:

[0004] Adjust the wiring pattern of the metal lines within the representative volume element to obtain multiple representative volume elements with different metal line wiring patterns;

[0005] Multiple first finite element simulation models are established for multiple representative volume elements, and the equivalent material properties of the multiple first finite element simulation models are obtained respectively.

[0006] Based on the equivalent material properties of multiple first finite element simulation models and the material properties of the substrate, multiple second finite element simulation models are established for the semiconductor structure to be designed, and the warping deformation of the multiple second finite element simulation models during and after the heat treatment process is simulated.

[0007] In some embodiments, the representative volume element includes multiple metal layers located within the interlayer dielectric layer, each of the metal layers including at least one metal line extending parallel to the substrate plane; adjusting the wiring method of the metal lines within the representative volume element includes:

[0008] Adjust the wiring method of the metal lines in at least one of the metal layers.

[0009] In some embodiments, any of the metal layers includes one or more regions, each region having multiple metal lines extending in the same direction and uniformly arranged in a direction intersecting the extending direction.

[0010] In some embodiments, the equivalent material properties of multiple first finite element simulation models are obtained, including:

[0011] Stress is applied to each of the first finite element simulation models along multiple directions, and finite element simulation calculations are performed to obtain the first strain of each of the first finite element simulation models in the stress direction.

[0012] Based on the applied stress and the first strain of the first finite element simulation model, the equivalent elastic modulus and Poisson's ratio of each of the first finite element simulation models in the plurality of directions are obtained.

[0013] In some embodiments, the equivalent elastic modulus of the first finite element simulation model in any direction is calculated according to the following relationship (1).

[0014]

[0015] Among them, V m Let dV be the volume of the first finite element simulation model. m σ is the integral variable, referring to the infinitesimal volume element during integration. S When stress is applied to the first finite element simulation model in any direction, the small volume element dV in the first finite element simulation model m The stress ε S1 For the tiny volume element dV m Under stress σ S The strain generated along the stress direction under the action of The equivalent stress applied to the first finite element simulation model, The equivalent strain of the first finite element simulation model along the stress direction is given.

[0016] In some embodiments, obtaining the equivalent material properties of multiple first finite element simulation models respectively further includes:

[0017] Thermal loads are applied to each of the first finite element simulation models along multiple directions, and finite element simulation calculations are performed to obtain the temperature change and the second strain along the thermal load direction of each first finite element simulation model.

[0018] Based on the applied thermal load, the temperature change, and the second strain, the equivalent thermal expansion coefficient of each of the first finite element simulation models in the plurality of directions is obtained.

[0019] In some embodiments, the equivalent thermal expansion coefficient of the first finite element simulation model is obtained according to the following relationship (2):

[0020]

[0021] Among them, Vm Let dV be the volume of the first finite element simulation model. m ε is the integral variable, referring to the infinitesimal volume element during integration. S2 For a small volume unit dV m Deformation produced along the direction of the thermal load when the temperature changes by ΔT.

[0022] In some embodiments, the shape of the first finite element simulation model includes a cuboid, and a surface of the cuboid parallel to the substrate plane includes vertices A, B, C, and D, wherein vertices A and B are linearly adjacent, vertices A and C are diagonally adjacent, and vertices B and D are diagonally adjacent. The direction from vertex A to vertex B is defined as the x-axis direction, the direction from vertex A to vertex D is defined as the y-axis direction, and the direction perpendicular to the x-axis and y-axis directions is defined as the z-axis direction. Stress and thermal loads are applied to the first finite element simulation model along multiple directions, including:

[0023] Stress and thermal loads are applied to the first finite element simulation model along the x-axis, y-axis, z-axis, a first direction, a second direction, and a third direction, respectively; wherein the first direction forms a 45° angle with the x-axis and y-axis; the second direction forms a 45° angle with the x-axis and z-axis; and the third direction forms a 45° angle with the y-axis and z-axis.

[0024] This disclosure also provides a design apparatus for semiconductor structures, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the design method as described in any of the above embodiments.

[0025] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the design method as described in any of the above embodiments.

[0026] This disclosure provides a semiconductor structure design method, design apparatus, and computer-readable storage medium. The semiconductor structure to be designed includes a substrate and an interconnect layer on the substrate. The interconnect layer includes a plurality of periodically arranged minimum repeatable volume units, which are used as representative volume elements of the interconnect layer. Each representative volume element includes an interlayer dielectric layer and a plurality of metal lines located within the interlayer dielectric layer. The semiconductor structure design method includes: adjusting the wiring pattern of the metal lines within the representative volume elements to obtain multiple representative volume elements with different metal line wiring patterns; establishing multiple first finite element simulation models for the multiple representative volume elements and obtaining the equivalent material properties of each of the multiple first finite element simulation models; establishing multiple second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate, and simulating the warping deformation of the multiple second finite element simulation models during and after heat treatment. This disclosure, through adjusting the wiring pattern of metal lines within a representative volume element (RVE) and establishing a first simulation model for the representative volume element, can obtain the equivalent material properties of representative volume elements with different metal wiring patterns. Then, based on the equivalent material properties of these representative volume elements and the material properties of the substrate, multiple second simulation models are established, and the warpage deformation of these multiple second simulation models is obtained. In this way, the warpage deformation of the semiconductor structure under different metal wiring patterns can be obtained, thereby allowing the selection of the metal wiring pattern with the lowest warpage value from a limited set of metal wiring patterns. This effectively adjusts and controls the warpage deformation of the semiconductor structure, improving the success rate of subsequent bonding and packaging processes. Furthermore, this disclosure uses the smallest repeatable volume unit in the interconnect layer of the semiconductor structure to be designed as the representative volume element for modeling, rather than modeling all metal patterns in the interconnect layer, saving simulation computational complexity and cost.

[0027] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A flowchart illustrating a semiconductor structure design method provided in this disclosure embodiment;

[0030] Figure 2 This is a schematic diagram of the semiconductor structure to be designed provided in an embodiment of this disclosure;

[0031] Figure 3 A three-dimensional structural schematic diagram of a representative volume element provided in an embodiment of this disclosure;

[0032] Figure 4 Figures (1) to (4) in this disclosure are different examples of the arrangement of metal lines in any metal layer of a representative volume element provided in the embodiments of this disclosure;

[0033] Figure 5 This is a schematic diagram of the first finite element simulation model established in the embodiments of this disclosure;

[0034] Figure 6 The warpage distribution of the semiconductor structure calculated using the second finite element simulation model established for embodiments of this disclosure;

[0035] Figure 7 A schematic diagram of the structure of the design device provided in the embodiments of this disclosure;

[0036] Figure 8 This is a schematic diagram of a computer-readable storage medium structure provided in an embodiment of this disclosure. Detailed Implementation

[0037] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid obscuring the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0039] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] Semiconductor structures (such as memory) typically consist of a wafer and interconnect structures formed on the wafer, which are composed of multiple metal lines. During the manufacturing process of the interconnect structures, wafer warping can occur due to factors such as thermal expansion coefficient mismatch, thereby reducing the performance of the semiconductor structure.

[0044] Based on this, the present disclosure provides a method for designing a semiconductor structure. The semiconductor structure to be designed includes a substrate and an interconnect layer on the substrate. The interconnect layer includes a plurality of periodically arranged minimum repeatable volume units. The minimum repeatable volume units are used as representative volume elements of the interconnect layer. The representative volume element includes an interlayer dielectric layer and a plurality of metal lines located within the interlayer dielectric layer. For details, please refer to [link to relevant documentation]. Figure 1 As shown in the figure, the method includes the following steps:

[0045] Step S101: Adjust the wiring method of the metal lines in the representative volume element to obtain multiple representative volume elements with different metal line wiring methods;

[0046] Step S102: Establish multiple first finite element simulation models for multiple representative volume elements, and obtain the equivalent material properties of the multiple first finite element simulation models respectively;

[0047] Step S103: Based on the equivalent material properties of multiple first finite element simulation models and the material properties of the substrate, establish multiple second finite element simulation models for the semiconductor structure to be designed, and simulate the warping deformation of multiple second finite element simulation models during and after heat treatment.

[0048] This disclosure, through adjusting the wiring pattern of metal lines within a representative volume element (RVE) and establishing a first simulation model for the representative volume element, can obtain the equivalent material properties of representative volume elements with different metal wiring patterns. Then, based on the equivalent material properties of these representative volume elements and the material properties of the substrate, multiple second simulation models are established, and the warpage deformation of these multiple second simulation models is obtained. In this way, the warpage deformation of the semiconductor structure under different metal wiring patterns can be obtained, thereby allowing the selection of the metal wiring pattern with the lowest warpage value from a limited set of metal wiring patterns. This effectively adjusts and controls the warpage deformation of the semiconductor structure, improving the success rate of subsequent bonding and packaging processes. Furthermore, this disclosure uses the smallest repeatable volume unit in the interconnect layer of the semiconductor structure to be designed as the representative volume element for modeling, rather than modeling all metal patterns in the interconnect layer, saving simulation computational complexity and cost.

[0049] The design method of the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0050] like Figure 2 and Figure 3 As shown, in some embodiments, the semiconductor structure to be designed includes a substrate 10 and an interconnect layer 11 located on the substrate 10. The interconnect layer 11 includes a plurality of periodically arranged minimum repeatable volume units 12. The minimum repeatable volume units 12 are used as representative volume elements 13 of the interconnect layer 11. The representative volume element 13 includes an interlayer dielectric layer 14 and a plurality of metal lines 151 located within the interlayer dielectric layer 14.

[0051] Here, the semiconductor structure to be designed refers to the semiconductor structure that has not yet undergone layout design. Subsequently, from a limited number of metal wiring methods, the metal wiring method with the lowest warpage value is selected, and the layout design of the semiconductor structure is performed based on this metal wiring method with the lowest warpage value. The semiconductor structure to be designed includes 3D semiconductor structures.

[0052] Here, substrate 10 can be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 10 is a silicon (Si) wafer.

[0053] In some embodiments, the substrate 10 may further include device structures (not shown) formed on and / or inside the substrate 10, such as transistors, word lines, bit lines and other device structures.

[0054] like Figure 3 As shown, in some embodiments, the representative volume element 13 includes multiple metal layers 15 located within the interlayer dielectric layer 14, and each metal layer 15 includes at least one metal line 151 extending parallel to the plane of the substrate 10. In practice, the metal line 151 may be a metal line constituting a metal pad within the interconnect layer 11. In some embodiments, the metal line 151 may also include a dummy metal line, which is not used to transmit electrical signals. By adding dummy metal lines to the interconnect layer 11, the distribution of the metal lines 151 in the interconnect layer 11 is made more uniform, thereby allowing the interconnect layer 11 to be arranged periodically from a plurality of minimum repeatable volume elements 12.

[0055] In practice, the interlayer dielectric layer 14 can be a multilayer structure formed in different processes. For example... Figure 3As shown, in some embodiments, the dielectric layer 14 includes multiple first sublayers 141 and at least one second sublayer 142, with the first sublayers 141 and the second sublayers 142 stacked alternately in a vertical direction, and multiple metal layers 15 distributed in the multiple first sublayers 141. In some embodiments, the representative volume element 13 may also include a plug (not shown) formed in the second sublayer 142, which can be used to electrically connect two adjacent metal layers 15.

[0056] In the actual process, the materials of the first sub-layer 141 and the second sub-layer 142 can be the same or different. The materials of the first sub-layer 141 and the second sub-layer 142 include one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.; the materials of the metal wire 151 and the plug (not shown) can include one or more of W (tungsten), Cu (copper), Co (cobalt), TiN (titanium nitride), Ti (titanium), Ta (tanium), TaN (tanium nitride) and Al (aluminum).

[0057] First, step S101 is executed to adjust the wiring method of the metal lines 151 within the representative volume element 13 to obtain multiple representative volume elements 13 with different wiring methods of the metal lines 151.

[0058] In some embodiments, adjusting the wiring pattern of the metal lines 151 within the representative volume element 13 includes adjusting the wiring pattern of the metal lines 151 in at least one metal layer 15. The wiring pattern here can refer to at least one of the following: the number of metal lines 151, their extension direction, their arrangement direction, and their placement position. Thus, by adjusting the wiring pattern of the metal lines 151 in one or more metal layers 15 within the representative volume element 13, the warpage of the semiconductor structure under design can be adjusted in multiple directions parallel to the substrate 10 (e.g., the x-axis and y-axis directions), rather than being limited to adjusting the warpage of the semiconductor structure under design in only one direction.

[0059] In some embodiments, the number of metal lines 151 in each metal layer 15 can be adjusted to one or more. When there are multiple metal lines 151 in a metal layer 15, the multiple metal lines 151 can be arranged in the same or different directions. The number, extension direction, arrangement direction and other parameters of metal lines 151 in any two metal layers 15 in the representative volume element 13 can be adjusted to be the same or different.

[0060] It should be noted that representative volume elements 13 with different metal line 151 wiring methods need to meet layout design rules to avoid adversely affecting the performance of the final manufactured semiconductor structure. In some embodiments, adjusting the wiring method of the metal lines 151 in the representative volume element 13 also includes adjusting parameters such as the distribution position and number of plugs (not shown) between adjacent metal layers 15.

[0061] like Figure 4 As shown, in some embodiments, any metal layer 15 includes one or more regions Q, each region Q having multiple metal lines 151 extending in the same direction and uniformly arranged in directions intersecting (including perpendicular or oblique) the extending direction. Some embodiments of this disclosure design the metal layer 15 of the representative volume element 13 to include one or more regions Q, with each region Q having multiple metal lines 151 extending in the same direction and uniformly arranged in directions intersecting the extending direction. Thus, the metal lines 151 in the representative volume element 13 are arranged in a certain regularity, which can reduce the complexity and cost of simulation calculations, and the more uniform distribution of the metal lines 151 in the representative volume element 13 is beneficial for reducing the warpage of the semiconductor structure.

[0062] In some embodiments, adjusting the wiring method of the metal lines 151 in at least one metal layer 15 includes adjusting the extension direction and / or arrangement direction of multiple metal lines 151 in at least one region Q in at least one metal layer 15, the number of regions Q, and the arrangement of multiple regions Q.

[0063] like Figure 4 As shown in Figure (1), the metal layer 15 may include a region Q, in which multiple metal lines 151 extend in the same direction and are arranged in a direction intersecting with their extension direction. The extension direction and arrangement direction of the multiple metal lines 151 can be adjusted, and the angle between the extension direction and arrangement direction of the multiple metal lines 151 can vary between greater than 0° and less than or equal to 90°.

[0064] In some embodiments, when the metal layer 15 includes multiple regions Q, in any two regions Q of the metal layer 15, the extension direction of multiple metal lines 151 in one region Q can be the same as or intersect (including perpendicular or oblique) with the extension direction of multiple metal lines 151 in the other region Q, and the arrangement direction of multiple metal lines 151 in one region Q can be the same as or intersect (including perpendicular or oblique) with the arrangement direction of multiple metal lines 151 in the other region Q. The extension direction and arrangement direction of multiple metal lines 151 in any one or more regions Q of one or more metal layers 15 can be adjusted, and the included angle between the extension direction and arrangement direction of multiple metal lines 151 can vary between greater than 0° and less than or equal to 90°.

[0065] Figure 4Figures (2) to (4) show examples of different arrangements of the metal lines 151 when the metal layer 15 includes four regions Q arranged in a 2×2 array. In fact, the multiple metal lines 151 in the four regions Q can also have other arrangements. In addition, the number and arrangement of regions Q in any metal layer 15 can be adjusted. Any metal layer 15 can also include more or fewer regions Q, such as two regions Q arranged in a 1×2 array, three regions Q arranged in a 1×3 array, six regions Q arranged in a 2×3 array, nine regions Q arranged in a 3×3 array, etc.

[0066] Next, step S102 is executed to establish multiple first finite element simulation models for multiple representative volume elements 13, and to obtain the equivalent material properties of the multiple first finite element simulation models respectively.

[0067] The multiple representative volume elements 13 here refer to multiple representative volume elements 13 with different wiring methods for the metal wires 151. In some embodiments, a first finite element simulation model can be established for the representative volume elements 13 using finite element simulation software. Specifically, the first finite element simulation model can be established based on the geometric shape, material characteristic parameters, and other properties of the representative volume elements 13. Here, the material characteristic parameters include the elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, heat capacity, and other parameters of the materials such as the metal wires 151, dielectric layer 12, and plugs in the representative volume elements 13.

[0068] In some embodiments, obtaining the equivalent material properties of the first finite element simulation model includes performing simulation calculations using finite element simulation software to obtain parameters such as the equivalent modulus, equivalent Poisson's ratio, and equivalent coefficient of thermal expansion of the first finite element simulation model.

[0069] In some embodiments, the equivalent material properties of multiple first finite element simulation models are obtained, including:

[0070] Stress is applied to each first finite element simulation model along multiple directions, and finite element simulation calculation is performed to obtain the first strain of each first finite element simulation model in the stress direction.

[0071] Based on the applied stress and the first strain of the first finite element simulation model, the equivalent elastic modulus and Poisson's ratio of each first finite element simulation model in multiple directions are obtained.

[0072] like Figure 5As shown, in some embodiments, the shape of the first finite element simulation model is the same as the shape of the representative volume element 13. The shape of the first finite element simulation model includes a cuboid (including a cube with equal side lengths). The first finite element simulation model includes a cuboid. A surface of the cuboid parallel to the substrate plane includes vertices A, B, C, and D. Vertices A and B are linearly adjacent, vertices A and C are diagonally adjacent, and vertices B and D are diagonally adjacent. The direction from vertex A to vertex B is defined as the x-axis direction, the direction from vertex A to vertex D is defined as the y-axis direction, and the direction perpendicular to the x-axis and y-axis directions is defined as the z-axis direction. Stress is applied to the first finite element simulation model along multiple directions, including: applying stress to the first finite element simulation model along the x-axis direction, y-axis direction, z-axis direction, a first direction, a second direction, and a third direction. The first direction forms a 45° angle with the x-axis and y-axis directions; the second direction forms a 45° angle with the x-axis and z-axis directions; and the third direction forms a 45° angle with the y-axis and z-axis directions. Thus, by applying stress to the first finite element simulation model along the x-axis, y-axis, z-axis, first direction, second direction, and third direction respectively, the first strain of the first finite element simulation model in these multiple directions can be obtained, and then the elastic modulus of the first finite element simulation model in these multiple directions can be obtained. Based on the elastic modulus in these multiple directions, the Poisson's ratio of the first finite element simulation model can be obtained, thereby making the material properties of the subsequently established second finite element simulation model closer to the material properties of the actual semiconductor structure and improving the accuracy of the second finite element simulation model.

[0073] In some embodiments, performing finite element simulation calculations to obtain the first strain in the stress direction for each first finite element simulation model includes: obtaining the strain in the stress direction of a plurality of small volume elements in the first finite element simulation model; then, by integrating the ratio of the stress borne by the plurality of small volume elements to the strain in the stress direction, the equivalent elastic modulus of the first finite element simulation model can be obtained.

[0074] In some embodiments, the equivalent elastic modulus of the first finite element simulation model in any direction can be calculated according to the following relationship (1).

[0075]

[0076] Among them, V m Let dV be the volume of the first finite element simulation model. m σ is the integral variable, referring to the infinitesimal volume element during integration. S When stress is applied to the first finite element simulation model in any direction, the small volume element dV in the first finite element simulation model m The stress εS1 For small volume elements dV m Under stress σ S The strain generated along the stress direction under the action of , The equivalent stress applied to the first finite element simulation model, The equivalent strain along the stress direction of the first finite element simulation model is given.

[0077] Any direction here includes, but is not limited to, any direction along the x-axis, y-axis, z-axis, first direction, second direction, and third direction. In some embodiments, stress is applied to the first finite element simulation model along the x-axis, y-axis, z-axis, first direction, second direction, and third direction, and finite element simulation calculations are performed to obtain the strain generated by the first finite element simulation model along the above-mentioned multiple directions. Then, the equivalent elastic modulus of the first finite element simulation model in the above-mentioned multiple directions is obtained according to the above-mentioned relationship (1). Then, the equivalent Poisson's ratio of the first finite element simulation model in the above-mentioned multiple directions is calculated based on the equivalent elastic modulus of the first finite element simulation model in different directions.

[0078] In some embodiments, when simulating applying stress to a first finite element simulation model to calculate its first strain along the stress direction, the first finite element simulation model can be set to have strain only along the stress direction, and its strain in other directions besides the stress direction can be set to 0. By adding this constraint, the complexity and cost of simulation calculation can be reduced.

[0079] In some embodiments, obtaining the equivalent material properties of multiple first finite element simulation models respectively further includes:

[0080] Thermal loads are applied to each first finite element simulation model along multiple directions, and finite element simulation calculations are performed to obtain the temperature change and the second strain along the thermal load direction of each first finite element simulation model.

[0081] Based on the applied thermal load, temperature change, and second strain, the equivalent thermal expansion coefficients of each first finite element simulation model in multiple directions are obtained.

[0082] In some embodiments, performing finite element simulation calculations to obtain the temperature change and the second strain along the thermal load direction for each first finite element simulation model includes: obtaining the temperature change and strain along the thermal load direction for multiple small volume elements in the first finite element simulation model; then, by integrating the ratio of the strain to the temperature change of the multiple small volume elements along the thermal load direction, the equivalent thermal expansion coefficient of the first finite element simulation model can be obtained.

[0083] In some embodiments, when calculating the equivalent thermal expansion coefficient of the first finite element simulation model, the representative volume element 13 can be defined as a free expansion period type. Specifically, the equivalent thermal expansion coefficient of the first finite element simulation model in any direction can be obtained according to the following relationship (2):

[0084]

[0085] Among them, V m Let dV be the volume of the first finite element simulation model. m ε is the integral variable, referring to the infinitesimal volume element during integration. S2 For a small volume unit dV m Deformation produced along the direction of thermal load when the temperature changes by ΔT.

[0086] Any direction here includes, but is not limited to, any direction along the x-axis, y-axis, z-axis, first direction, second direction, and third direction. In some embodiments, thermal loads are applied to the first finite element simulation model along the x-axis, y-axis, z-axis, first direction, second direction, and third direction, respectively, and then the equivalent thermal expansion coefficients of the first finite element simulation model in the above-mentioned multiple directions are obtained according to the above-mentioned relationship (2).

[0087] In some embodiments, when simulating the application of a thermal load to a first finite element simulation model to calculate its second strain along the thermal load direction, the first finite element simulation model can be set to have strain only along the thermal load direction, and its strain in other directions besides the thermal load direction can be set to 0. By adding this constraint, the complexity and cost of simulation calculation can be reduced.

[0088] However, this is not the only one. In some embodiments, obtaining the equivalent material properties of multiple first finite element simulation models also includes obtaining the equivalent thermal conductivity, equivalent heat capacity, and other material properties of multiple first finite element simulation models.

[0089] Next, step S103 is executed, based on the equivalent material properties of multiple first finite element simulation models and the material properties of substrate 10, to establish multiple second finite element simulation models of the semiconductor structure to be designed, and to simulate the warping deformation of multiple second finite element simulation models during and after the heat treatment process.

[0090] Multiple minimum repeatable volume units 12 are periodically arranged to form the interconnect layer 11 of the semiconductor structure. Therefore, by taking the minimum repeatable volume unit 12 as a representative volume element 13 and modeling it, the equivalent material properties of the representative volume element 13 can be obtained, and thus the equivalent material properties of the interconnect layer 11 can be obtained. Then, based on the equivalent material properties of the representative volume element 13, the material properties of the substrate 10, and the geometric parameters of the interconnect layer 11 and the substrate 10, a second simulation model of the semiconductor structure can be established using finite element simulation software. Compared with modeling all the metal patterns in the entire interconnect layer 11, this saves on the complexity and cost of simulation calculation.

[0091] Here, the material properties of substrate 10 include parameters such as elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, and heat capacity. In some embodiments, substrate 10 also includes device structures (not shown) formed on and / or inside substrate 10, and the material properties of substrate 10 and the device structures formed on and / or inside substrate 10 can be equivalent to the material properties of substrate 10 itself. For example, if the material of substrate 10 is silicon, the material properties of substrate 10 and the device structures formed on and / or inside substrate 10 can be equivalent to the material properties of silicon.

[0092] In some embodiments, matching heat treatment parameters, such as annealing temperature, heating rate, and holding time, can be set in the second finite element simulation model according to the actual heat treatment process parameters and boundary conditions of the semiconductor structure. The finite element simulation software is then used to perform simulation calculations to simulate the warping deformation of the second finite element simulation model during and after the heat treatment process.

[0093] In some embodiments, simulating the warping deformation of the second finite element simulation model during and after heat treatment further includes: post-processing and analyzing the warping deformation obtained from the simulation, and extracting key characteristic parameters of the warping of the second finite element simulation model, such as maximum warping amount, warping direction, and warping region distribution. Figure 6 As shown, this is a simulation of a semiconductor structure obtained in one embodiment of the present disclosure, showing the warping distribution along the z-axis after undergoing a heat treatment process.

[0094] In some embodiments, the wiring pattern of the metal lines 151 in the representative volume element 13 can be adjusted according to the warping deformation obtained from the simulation. Then, steps S102 and S103 are executed again. In this way, the wiring pattern of the metal lines 151 in the representative volume element 13 can be adjusted in a targeted manner to reduce the warping of the semiconductor structure after heat treatment.

[0095] Thus, by analyzing and comparing the warpage deformation of semiconductor structures with different metal wiring methods, the metal wiring method with the lowest warpage value can be selected.

[0096] As can be seen, by adjusting the wiring method of the metal lines 151 within the representative volume element 13 and establishing a first simulation model for the representative volume element 13, the equivalent material properties of the representative volume element 13 with different metal line 151 wiring methods can be obtained. Then, based on the equivalent material properties of the multiple representative volume elements 13 and the material properties of the substrate, multiple second simulation models are established, and the warpage deformation of the multiple second simulation models is obtained. In this way, the warpage deformation of the semiconductor structure under different metal wiring methods can be obtained, thereby allowing the selection of the metal wiring method with the lowest warpage value from a limited number of metal wiring methods, effectively adjusting and controlling the warpage deformation of the semiconductor structure, and improving the success rate of subsequent bonding and packaging processes.

[0097] Here, the lowest warp value can be the lowest overall warp value of the second simulation model in all directions, or the lowest average warp value in all directions.

[0098] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure.

[0099] This disclosure also provides a design device 21 for semiconductor structures, such as... Figure 7 As shown, it includes: a memory 22, a processor 24, and a computer program 23 stored in the memory 22 and executable on the processor 24. When the processor 24 executes the computer program 23, it implements a design method provided in the above embodiments, such as: adjusting the wiring pattern of the metal lines in the representative volume element to obtain multiple representative volume elements with different metal line wiring patterns; establishing multiple first finite element simulation models for the multiple representative volume elements and obtaining the equivalent material properties of the multiple first finite element simulation models respectively; establishing multiple second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate respectively, and simulating the warping deformation of the multiple second finite element simulation models during and after the heat treatment process.

[0100] This disclosure also provides a computer-readable storage medium 25, such as... Figure 8As shown, a computer-readable storage medium 25 stores a computer program 26. When the computer program 26 is executed by a processor, it implements a semiconductor structure design method provided in the above embodiments, such as: adjusting the wiring pattern of metal lines in a representative volume element to obtain multiple representative volume elements with different metal line wiring patterns; establishing multiple first finite element simulation models for multiple representative volume elements and obtaining the equivalent material properties of the multiple first finite element simulation models respectively; establishing multiple second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate respectively, and simulating the warping deformation of the multiple second finite element simulation models during and after the heat treatment process.

[0101] It should be noted that the above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of designing a semiconductor structure, characterized by, The semiconductor structure to be designed comprises a substrate and an interconnection layer on the substrate, the interconnection layer comprises a plurality of minimum repeatable volume units arranged periodically, the minimum repeatable volume unit is taken as a representative volume element of the interconnection layer, the representative volume element comprises an interlayer dielectric layer and a plurality of metal lines in the interlayer dielectric layer; the design method comprises: adjusting the wiring mode of the metal lines in the representative volume element to obtain a plurality of representative volume elements with different metal line wiring modes; establishing a plurality of first finite element simulation models for the plurality of representative volume elements respectively, and obtaining equivalent material properties of the plurality of first finite element simulation models respectively; based on the equivalent material properties of the plurality of first finite element simulation models and the material properties of the substrate, establishing a plurality of second finite element simulation models for the semiconductor structure to be designed, and simulating the warping deformation of the plurality of second finite element simulation models during and after the heat treatment process.

2. The design method according to claim 1, characterized by The representative volume element comprises a plurality of metal layers in the interlayer dielectric layer, any of the metal layers comprises at least one metal line extending in a direction parallel to the substrate plane; adjusting the wiring mode of the metal lines in the representative volume element comprises: adjusting the wiring mode of the metal lines in at least one of the metal layers.

3. The method of designing according to claim 2, wherein, Any of the metal layers comprises one region or a plurality of regions, each region has a plurality of metal lines extending in the same direction and uniformly arranged in a direction intersecting with the extending direction.

4. The method of claim 1, wherein The equivalent material properties of the plurality of first finite element simulation models are obtained respectively, comprising: applying stress to each of the first finite element simulation models in a plurality of directions respectively, and performing finite element simulation calculation to obtain a first strain of each of the first finite element simulation models in the stress direction; based on the applied stress and the first strain of the first finite element simulation model, obtaining the equivalent elastic modulus and Poisson's ratio of each of the first finite element simulation models in the plurality of directions.

5. The method of designing according to claim 4, wherein, The equivalent elastic modulus of the first finite element simulation model in any direction is calculated according to the following relationship (1) wherein V m is the volume of the first finite element simulation model, dV m is an integral variable, referring to a small volume element when performing integration, σ S is the stress that the small volume element dV m suffers when a stress is applied to the first finite element simulation model in any direction, ε S1 is the strain that the small volume element dV m suffers in the stress direction under the action of the stress σ S , is the equivalent stress applied to the first finite element simulation model, is the equivalent strain of the first finite element simulation model in the stress direction.

6. The method of claim 4, wherein, The equivalent material properties of the plurality of first finite element simulation models are obtained respectively, further comprising: applying thermal load to each of the first finite element simulation models in a plurality of directions respectively, and performing finite element simulation calculation to obtain the temperature change and a second strain of each of the first finite element simulation models in the thermal load direction; based on the applied thermal load, the temperature change and the second strain, obtaining the equivalent thermal expansion coefficient of each of the first finite element simulation models in the plurality of directions.

7. The method of designing according to claim 6, wherein, The equivalent thermal expansion coefficient of the first finite element simulation model in any direction is obtained according to the following relationship (2): where V m is the volume of the first finite element simulation model, dV m is an integral variable, referring to a small volume element when performing integration, ε S2 is the small volume unit dV m the strain generated in the direction of the thermal load when the temperature change is ΔT.

8. The method of claim 6, wherein, The shape of the first finite element simulation model includes a cuboid, one surface of the cuboid parallel to the substrate plane includes vertex A, vertex B, vertex C, vertex D, wherein vertex A and vertex B are linearly adjacent, vertex A and vertex C are diagonally adjacent, vertex B and vertex D are diagonally adjacent, the direction from vertex A to vertex B is defined as the x-axis direction, the direction from vertex A to vertex D is defined as the y-axis direction, and the direction perpendicular to the x-axis direction and the y-axis direction is defined as the z-axis direction; stress and thermal load are applied to the first finite element simulation model in multiple directions respectively, including: Stress and thermal load are applied to the first finite element simulation model in the x-axis direction, the y-axis direction, the z-axis direction, a first direction, a second direction, and a third direction respectively; wherein the first direction forms a 45° angle with the x-axis direction and the y-axis direction; the second direction forms a 45° angle with the x-axis direction and the z-axis direction; and the third direction forms a 45° angle with the y-axis direction and the z-axis direction.

9. A design apparatus for a semiconductor structure, characterized by comprising: including: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the design method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and the computer program is executed by the processor to implement the design method according to any one of claims 1 to 8.

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