A chip and electronic device

Abstract

This application discloses a chip and electronic device, relating to the field of integrated circuits, to solve the problem that existing technologies cannot repair registers on a chip. The chip includes: a main controller, a repair controller, a first register group, and a data interface. The main controller is connected between the data interface, the repair controller, and the first register group. The data interface receives a signal to be stored and sends it to the main controller when the first register group is functioning normally. The repair controller sends a signal to be repaired to the main controller when the first register group is malfunctioning. The main controller sends the signal to be stored from the data interface to the first register group, or sends the signal to be repaired from the repair controller to the first register group. This solution allows for the repair of malfunctioning registers during chip use.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a chip and an electronic device. Background Technology

[0002] As the size of system-on-chip (SoC) chips continues to increase and process nodes continue to evolve towards deeper nanometer dimensions, the probability of defects occurring during chip manufacturing also increases. When engineers discover defects in a chip during use, they hope to repair them to extend the chip's lifespan. However, currently, it is impossible to repair defective registers.

[0003] Therefore, how to design chips so that engineers can repair malfunctioning registers is a problem that urgently needs to be solved. Summary of the Invention

[0004] This invention provides a chip and an electronic device for repairing abnormal registers on the chip during its use.

[0005] In a first aspect, the present invention provides a chip comprising: a main controller, a repair controller, a first register group, and a data interface, wherein the main controller is connected between the data interface, the repair controller, and the first register group; the data interface is configured to receive a signal to be stored and send it to the main controller when the first register group is functioning normally; the repair controller is configured to send a signal to be repaired to the main controller when the first register group is malfunctioning; and the main controller is configured to send the signal to be stored from the data interface to the first register group, or to send the signal to be repaired from the repair controller to the first register group.

[0006] This application achieves partial register repair capability by adding only a small amount of circuitry to the traditional design for test (DFT) scan chain and controller-by-controller approach. That is, by adding a small amount of logic circuitry and a repair controller. Since the added logic circuitry is minimal, it does not affect the overall chip area and power consumption, allowing the chip to operate normally by default. When an anomaly occurs in the first register group, the first register group can be repaired.

[0007] Optionally, the chip also includes a first multiplexer, and the repair controller includes a signal control interface and a data transmission interface; the first multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal, the first input terminal is connected to the data interface, the second input terminal is connected to the data transmission interface, the output terminal is connected to the first input terminal of the main controller, and the control terminal is connected to the signal control interface; the repair controller is used to output a first level through the signal control interface when the first register group is normal, and to output a second level through the signal control interface when the first register group is abnormal; the first multiplexer is used to connect the first input terminal and the output terminal when the control terminal receives the first level, and to connect the second input terminal and the output terminal when the control terminal receives the second level.

[0008] The above scheme controls the data writing direction of the main controller through the signal control interface of the repair controller. That is, by default, the signal control interface outputs the first level, and the main controller writes data from the first line. When the register needs to be repaired, the signal control interface outputs the second level, and the main controller writes data from the repair controller.

[0009] Optionally, the chip also includes a second multiplexer and a second register group. The second register group is the register group located before the first register group on the chip's register link. The repair controller also includes a repair enable interface. Both the main controller and the first register group include scan input interfaces. The second multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal is connected to the output interface of the second register group, the second input terminal is connected to the scan input interface of the main controller, the output terminal is connected to the scan input interface of the first register group, and the control terminal is connected to the repair enable interface. The repair controller is used to output a first level through the repair enable interface when the first register group is normal, and to output a second level through the repair enable interface when the first register group is abnormal. The second multiplexer is used to connect the first input terminal and the output terminal when the control terminal receives the first level, and to connect the second input terminal and the output terminal when the control terminal receives the second level.

[0010] The above scheme controls the connection direction of the scan input interface si of the first register group by using the repair enable interface of the repair controller. That is, by default, the repair enable interface outputs the first level, and the first register group is connected to the preceding second register group to form a long scan chain. When the register needs to be repaired, the repair enable interface outputs the second level, and the first register group is directly connected to the main controller. In other words, the main controller can directly control the scanning of the first register group, turning the original long scan chain into a short scan chain. This increases the scanning efficiency of the main controller for the first register group.

[0011] Optionally, there are N first register groups, N repair enable interfaces, and N second multiplexers. The N second register groups are connected in parallel and correspond one-to-one with the N second multiplexers and N repair enable interfaces, where N is an integer greater than or equal to 2.

[0012] Optionally, the chip also includes a third multiplexer and a clock switching unit. The repair controller further includes a repair enable interface, a clock interface, and a clock enable interface. The first input of the clock switching unit is connected to the clock signal output, the second input of the clock switching unit is connected to the clock enable interface, the output of the clock switching unit is connected to the first input of the third multiplexer, the second input of the third multiplexer is connected to the clock interface, the output of the third multiplexer is connected to the clock signal input in the first register group, and the control terminal of the third multiplexer is connected to the repair enable interface. The repair controller is used to enable repair when the first register group is normal. The interface outputs a first level and a third level through the clock enable interface. In the event of an anomaly in the first register group, it outputs a second level through the repair enable interface and a fourth level through the clock enable interface. A third multiplexer is used to connect its first input and output when the control terminal receives the first level, and to connect its second input and output when the control terminal receives the second level. A clock switching unit is used to turn off the clock signal when the second input receives the fourth level, and to turn on the clock signal when the second input receives the third level.

[0013] The above scheme controls whether to repair the first register group through the repair enable interface of the repair controller, and controls the opening and closing of the clock switching unit through the clock enable interface. In this way, the functional clock of the first register group can be turned off during repair, and after the first register group is repaired, since the functional clock is turned off, there is no clock edge trigger to update the data, and the registers in the first register group will remain unchanged in their current state. Thus, it can be ensured that the repaired value is "locked" in the register.

[0014] Optionally, there are N first register groups, N third multiplexers, and N clock switching units. The N first register groups are connected in series and correspond one-to-one with the N third multiplexers and N clock switching units, where N is an integer greater than or equal to 2.

[0015] Optionally, there are N sets of the first register group, the third multiplexer, the repair enable interface, the clock interface, the clock enable interface, and the clock switching unit. The N sets of the first register group are connected in parallel and correspond one-to-one with the N sets of the third multiplexer, the N sets of the repair enable interface, the N sets of the clock interface, the N sets of the clock enable interface, and the N sets of the clock switching unit, where N is an integer greater than or equal to 2.

[0016] Optionally, the chip also includes a fourth multiplexer and a third register group. The third register group is the register group located after the first register group on the chip's register chain. The repair controller also includes a repair enable interface. Both the main controller and the first register group include output interfaces. The fourth multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal is connected to the output interface of the first register group. The second input terminal is connected to the output interface of the third register group. The output terminal is connected to the output interface of the main controller. The control terminal is connected to the repair enable interface. The repair controller is used to output a first level through the repair enable interface when the first register group is normal, and to output a second level through the repair enable interface when the first register group is abnormal. The fourth multiplexer is used to connect the second input terminal and the output terminal when the control terminal receives the first level, and to connect the first input terminal and the output terminal when the control terminal receives the second level.

[0017] The above scheme controls the connection direction of the output interface of the first register group by the repair enable interface of the repair controller. That is, by default, the repair enable interface outputs the first level, and the first register group is connected to the third register group to form a long scan chain. When the register needs to be repaired, the repair enable interface outputs the second level, and the first register group is directly connected to the main controller. In other words, the output of the first register group is directly transmitted to the main controller, turning the original long scan chain into a short scan chain. In this way, the scanning efficiency of the main controller on the first register group can be increased.

[0018] Optionally, there are N first register groups, repair enable interfaces, and fourth multiplexers. The N first register groups are connected in parallel and correspond one-to-one with the N fourth multiplexers and N repair enable interfaces, where N is an integer greater than or equal to 2.

[0019] Optionally, the chip also includes an OR unit, the repair controller also includes a repair enable interface, and both the main controller and the first register group also include a scan enable interface; the OR unit includes a first input terminal, a second input terminal, and an output terminal; the first input terminal is connected to the repair enable interface, the second input terminal is connected to the scan enable interface of the main controller, and the output terminal is connected to the scan enable interface of the first register group; the repair controller is used to output a first level through the repair enable interface when the first register group is normal, and to output a second level through the repair enable interface when the first register group is abnormal.

[0020] The above scheme uses the repair enable interface of the repair controller to control the scan enable interface of the first register group. That is, by default, the repair enable interface outputs the first level, and the main controller controls the scan enable interface of the long chain registers on the entire chip. When the registers need to be repaired, the repair enable interface of the repair controller controls the scan enable interface of the first register group. In this way, the original long scan chain is turned into a short scan chain, which can increase the scanning efficiency of the main controller on the first register group.

[0021] Optionally, there are N first register groups and N OR units. The N first register groups are connected in series and correspond one-to-one with the N OR units, where N is an integer greater than or equal to 2.

[0022] Optionally, there are N first register groups, repair enable interfaces, and / or units. The N first register groups are connected in parallel and correspond one-to-one with the N OR units and N repair enable interfaces, where N is an integer greater than or equal to 2.

[0023] Optionally, the first register group includes multiple registers connected in series. The scan input interface of the first register group is the scan input interface of the head register, and the output interface is the output interface of the tail register. In this way, multiple registers in the first register group can be repaired.

[0024] Optionally, the system also includes a processor connected to the repair controller. The processor is configured to send a repair signal to the repair controller in the event of an anomaly in the first register set. The repair signal includes the location of the first register set and repair data. Thus, a repair signal can be written to the repair controller via the processor.

[0025] In a second aspect, the present invention provides an electronic device comprising the chip described in the first aspect.

[0026] The technical effects that can be achieved by the first and second aspects mentioned above can be referred to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here.

[0027] These or other implementations of this application will become clearer and easier to understand in the following description of the embodiments. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1A schematic diagram of a traditional cell pattern structure for diagnosing chip structure via a scan chain is provided for an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of a conventional scanning chain structure provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of another chip structure provided in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of another chip structure provided in an embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of another chip structure provided in an embodiment of the present invention;

[0035] Figure 7 This is a schematic diagram of another chip structure provided in an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of another chip structure provided in an embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of another chip structure provided in an embodiment of the present invention;

[0038] Figure 10 A schematic diagram of a chip structure in which multiple first register groups are connected in series, provided for an embodiment of the present invention;

[0039] Figure 11 A schematic diagram of a chip structure in which multiple first register groups are connected in parallel, provided for an embodiment of the present invention;

[0040] Figure 12 A schematic diagram illustrating the process of adding a first register group in series during the design phase, as provided in an embodiment of the present invention;

[0041] Figure 13 This is a schematic diagram illustrating a process for adding a parallel first register group during the design phase, as provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and beneficial effects of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] The following provides explanations for some of the terms used in this application. It should be noted that these explanations are for the convenience of those skilled in the art and do not constitute a limitation on the scope of protection claimed in this application.

[0044] I. Direct Memory Access (DMA).

[0045] DMA is a hardware mechanism that allows peripheral devices or hardware subsystems to directly access system memory without continuous intervention from the central processing unit (CPU).

[0046] II. SOC.

[0047] A System-on-a-Chip (SoC) is an integrated circuit that integrates multiple functional modules onto a single chip. An SoC typically includes multiple functional units such as a processor core, memory, and peripheral interfaces.

[0048] III. DFT.

[0049] DFT is an important methodology used in integrated circuit design. Its main purpose is to improve chip testability, that is, to take chip testing needs into account during the chip design stage and integrate testing functions into the chip design.

[0050] IV. DFT scan chain.

[0051] DFT scan chains refer to connecting one or more flip-flops (or registers) inside a chip in series to form a structure similar to a shift register. In test mode, test data can be input into the chip through these chains, or the internal state can be read out. This design greatly improves the controllability and observability of the internal nodes of the chip, making it easier to detect and diagnose faults.

[0052] 5. Shift enable state.

[0053] The shift-enabled state refers to a state in which a register can perform data shift operations. In DFT scan chain design, this state allows data to be moved bit by bit through the scan chain, thereby enabling access and configuration of the register. When a register is in the shift-enabled state, it can act as part of the scan chain, receiving data input from the previous stage and passing data to the next stage register in the scan chain.

[0054] As mentioned in the background, chip design allows engineers to repair defective chips, thereby extending their lifespan. However, in existing technologies, traditional chip repair methods involve inserting Design-Fold Logic (DFT) during the chip design phase to perform a memory-built-in-self-test (MBIST). This test detects and repairs damaged areas in the memory. However, for registers, existing DFT tools and design methods can only detect the location of defective registers, not repair them. Damage to critical registers (such as parameter control registers in analog devices, chip module enable registers, and power management control registers) can severely impact the entire chip. Therefore, designing chips that allow engineers to repair defective or damaged registers at minimal cost, thus extending chip lifespan, is a pressing issue that needs to be addressed.

[0055] In DFT technology, scan testing is a crucial component; it involves inserting a DFT scan chain during the DFT design phase to diagnose functional issues in the chip. For example, please refer to... Figure 1 This diagram illustrates a traditional cell-mode structure for diagnosing chip structures via a scan chain. In this cell structure, the multiplexer (also called a data selector, MUX) has two inputs, si and di, a control input se, and an output connected to a register (or flip-flop). The register (or flip-flop) has a clock interface clk. When the cell structure is in normal operation, the signal level at se is 0. The MUX obtains data D from di and transmits it to the register (or flip-flop). After being clocked, data D becomes data Q. When the cell structure is in scan mode, the signal level at se is 1. The MUX obtains data D from si and transmits it to the register (or flip-flop). After being clocked, data D becomes data Q. In this case, the data transmitted from di is ignored.

[0056] Based on the above-described schematic diagram of the traditional scan chain unit structure, please refer to... Figure 2 The schematic diagram of a traditional scan chain structure shown is understandable. Figure 2 It is a scan chain obtained by connecting multiple unit structures in series. Each unit structure can be referred to the above. Figure 1 .Depend on Figure 2It can be seen that the si interface of the next unit structure is connected to the so interface of the previous unit structure, and all unit structures share a single se signal. That is, when the signal level output by the se terminal is 1, the entire scan chain can be scanned. The data is first input from the si of the first unit structure, and the output so is used as the input of the si of the next unit structure. This process can be repeated to achieve scanning of all unit structures, and the data at the di data input terminal of all unit structures is ignored.

[0057] However, this diagnostic method relies on the configuration of DFT diagnostic mode; once exiting diagnostic mode, all registers will revert to their original functional state. Therefore, how to design chips so that engineers can repair defective registers is a pressing issue that needs to be addressed.

[0058] Based on this, the present invention provides a chip that, by adding a repair controller, can repair abnormal registers during the use of the chip.

[0059] Please see Figure 3 The diagram illustrates the structure of a chip 300, which includes a main controller 320, a repair controller 310, a first register group 330, and a data interface. The main controller 320 is connected between the data interface, the repair controller 310, and the first register group 330. The data interface is used to receive a signal to be stored and send it to the main controller 320 when the first register group 330 is functioning normally. The repair controller 310 is used to send a signal to be repaired to the main controller 320 when the first register group 330 is malfunctioning. The main controller 320 is used to send the signal to be stored from the data interface to the first register group 330, or to send the signal to be repaired from the repair controller 310 to the first register group 330.

[0060] In one possible implementation, please participate. Figure 4 The diagram shows the structure of another chip. Chip 300 also includes a first multiplexer 340, and the repair controller 310 includes a signal control interface 311 and a data transmission interface 312; the first multiplexer 340 includes a first input terminal 341, a second input terminal 342, an output terminal 343, and a control terminal 344. The first input terminal 341 is connected to the data interface, the second input terminal 342 is connected to the data transmission interface 312, the output terminal 343 is connected to the first input terminal 321 of the main controller 320, and the control terminal 344 is connected to the signal control interface 311.

[0061] The repair controller 310 is used to output a first level through the signal control interface 311 when the first register group 330 is normal, and to output a second level through the signal control interface 311 when the first register group 330 is abnormal. The first multiplexer 340 is used to turn on the first input terminal 3411 and the output terminal 343 when the control terminal 344 receives the first level, and to turn on the second input terminal 342 and the output terminal 343 when the control terminal 344 receives the second level.

[0062] Optionally, the first level can be a low level, and the second level can be a high level.

[0063] The above scheme controls the data writing direction of the main controller through the signal control interface of the repair controller. That is, by default, the signal control interface outputs the first level, and the main controller writes data from the first line. When the register needs to be repaired, the signal control interface outputs the second level, and the main controller writes data from the repair controller.

[0064] In one possible implementation, please participate. Figure 5 The diagram illustrates the structure of another chip. Chip 300 also includes a second multiplexer 350 and a second register group 390. The second register group 390 is the register group located before the first register group 300 on the chip's register link. The repair controller 310 also includes a repair enable interface 313. The main controller 320 includes a scan input interface 322, and the first register group 330 includes a scan input interface 331. The second multiplexer 350 includes a first input terminal 351, a second input terminal 352, an output terminal 353, and a control terminal 354. The first input terminal 351 is connected to the output interface 391 of the second register group 390, the second input terminal 352 is connected to the scan input interface 322 of the main controller 320, the output terminal 353 is connected to the scan input interface 331 of the first register group 330, and the control terminal 354 is connected to the repair enable interface 313.

[0065] The repair controller 310 is used to output a first level through the repair enable interface 313 when the first register group 330 is normal, and to output a second level through the repair enable interface 313 when the first register group 330 is abnormal; the second multiplexer 350 is used to turn on the first input terminal 351 and the output terminal 353 when the control terminal 354 receives the first level, and to turn on the second input terminal 352 and the output terminal 353 when the control terminal 354 receives the second level.

[0066] The above scheme controls the connection direction of the scan input interface si of the first register group by the repair enable interface of the repair controller. That is, by default, the repair enable interface outputs the first level, and the first register group is connected to the preceding second register group to form a long scan chain. When the register needs to be repaired, the repair enable interface outputs the second level, and the first register group is directly connected to the main controller. In other words, the main controller can directly control the scanning of the first register group, turning the original long scan chain into a short scan chain. In this way, the scanning efficiency of the first register group by the main controller can be increased.

[0067] In one possible implementation, there are N first register groups 330, repair enable interface 313, and second multiplexer 350. The N second register groups are connected in parallel and correspond one-to-one with the N second multiplexers 350 and the N repair enable interfaces 313, where N is an integer greater than or equal to 2.

[0068] In one possible implementation, please participate. Figure 6 The diagram shows the structure of another chip. Chip 300 also includes a third multiplexer 360 and a clock switching unit 410. The repair controller 310 also includes a repair enable interface 313, a clock interface 314, and a clock enable interface 315. The first input terminal 411 of the clock switching unit 410 is connected to the clock signal output terminal, the second input terminal 412 of the clock switching unit 410 is connected to the clock enable interface 315, the output terminal 413 of the clock switching unit 410 is connected to the first input terminal 361 of the third multiplexer 360, the second input terminal 362 of the third multiplexer 360 is connected to the clock interface 314, the output terminal 363 of the third multiplexer 360 is connected to the clock signal input terminal 332 in the first register group 330, and the control terminal 364 of the third multiplexer 360 is connected to the repair enable interface 313.

[0069] The repair controller 310 is configured to output a first level through the repair enable interface 313 and a third level through the clock enable interface 314 when the first register group 330 is normal; and to output a second level through the repair enable interface 313 and a fourth level through the clock enable interface 314 when the first register group 330 is abnormal. The third multiplexer 360 is configured to connect its first input terminal 361 and output terminal 363 when its control terminal 364 receives the first level, and to connect its second input terminal 362 and output terminal 363 when its control terminal 364 receives the second level. The clock switching unit 410 is configured to turn off the clock signal when its second input terminal 412 receives the fourth level, and to turn on the clock signal when its second input terminal 412 receives the third level.

[0070] Optionally, the first level is low, the second level is high, the third level is high, and the fourth level is low.

[0071] The above scheme controls whether to repair the first register group through the repair enable interface of the repair controller, and controls the opening and closing of the clock switching unit through the clock enable interface. In this way, the functional clock of the first register group can be turned off during repair, and after the first register group is repaired, since the functional clock is turned off, there is no clock edge trigger to update the data, and the registers in the first register group will remain unchanged in their current state. Thus, it can be ensured that the repaired value is "locked" in the register.

[0072] Optionally, there are N first register groups 330, N third multiplexers 360, and N clock switching units 410. The N first register groups are connected in series and correspond one-to-one with the N third multiplexers and the N clock switching units, where N is an integer greater than or equal to 2.

[0073] Optionally, there are N units of the first register group 330, the third multiplexer 360, the repair enable interface 315, the clock interface 314, the clock enable interface 313, and the clock switching unit 410. The N first register groups 330 are connected in parallel and correspond one-to-one with the N third multiplexers 360, the N repair enable interfaces 315, the N clock interfaces 314, the N clock enable interfaces 313, and the N clock switching units 410, where N is an integer greater than or equal to 2.

[0074] In one possible implementation, please participate. Figure 7 The diagram illustrates the structure of another chip. Chip 300 also includes a fourth multiplexer 370 and a third register group 400. The third register group 400 is the register group located after the first register group on the chip's register link. Repair controller 310 also includes a repair enable interface 313. Main controller 320 includes an output interface 323. First register group 330 includes an output interface 333. The fourth multiplexer 370 includes a first input terminal 371, a second input terminal 372, an output terminal 373, and a control terminal 374. The first input terminal 371 is connected to the output interface 333 of the first register group 330. The second input terminal 372 is connected to the output interface 401 of the third register group 400. The output terminal 373 is connected to the output interface 323 of the main controller 320. The control terminal 374 is connected to the repair enable interface 313.

[0075] The repair controller 310 is used to output a first level through the repair enable interface 313 when the first register group 330 is normal, and to output a second level through the repair enable interface 313 when the first register group 330 is abnormal; the fourth multiplexer 370 is used to turn on the second input terminal 372 and the output terminal 373 when the control terminal 374 receives the first level, and to turn on the first input terminal 371 and the output terminal 373 when the control terminal 374 receives the second level.

[0076] The above scheme controls the connection direction of the output interface of the first register group by the repair enable interface of the repair controller. That is, by default, the repair enable interface outputs the first level, and the first register group is connected to the third register group to form a long scan chain. When the register needs to be repaired, the repair enable interface outputs the second level, and the first register group is directly connected to the main controller. In other words, the output of the first register group is directly transmitted to the main controller, turning the original long scan chain into a short scan chain. In this way, the scanning efficiency of the main controller on the first register group can be increased.

[0077] Optionally, there are N first register groups 330, repair enable interface 313 and fourth multiplexer 370. The N first register groups 330 are connected in parallel and correspond one-to-one with the N fourth multiplexers 370 and the N repair enable interfaces 313, where N is an integer greater than or equal to 2.

[0078] In one possible implementation, please participate. Figure 8 The diagram illustrates the structure of another chip. Chip 300 also includes an OR unit 380, repair controller 310 includes a repair enable interface 313, main controller 320 includes a scan enable interface 324, and first register group 330 includes a scan enable interface 334; OR unit 380 includes a first input terminal 381, a second input terminal 382, ​​and an output terminal 383; the first input terminal 381 is connected to the repair enable interface 313, the second input terminal 382 is connected to the scan enable interface 324 of the main controller 320, and the output terminal 383 is connected to the scan enable interface 334 of the first register group 330.

[0079] The repair controller 310 is used to output a first level through the repair enable interface 313 when the first register group 330 is normal, and to output a second level through the repair enable interface 313 when the first register group 330 is abnormal.

[0080] The above scheme uses the repair enable interface of the repair controller to control the scan enable interface of the first register group. That is, by default, the repair enable interface outputs the first level, and the main controller controls the scan enable interface of the long chain registers on the entire chip. When the registers need to be repaired, the repair enable interface of the repair controller controls the scan enable interface of the first register group. In this way, the original long scan chain is turned into a short scan chain, which can increase the scanning efficiency of the main controller on the first register group.

[0081] Optionally, there are N first register groups 330 and N OR units 380. The N first register groups 330 are connected in series and correspond one-to-one with the N OR units 380, where N is an integer greater than or equal to 2.

[0082] Optionally, there are N first register groups 330, repair enable interfaces 313 and / or units 380. The N first register groups 330 are connected together and correspond one-to-one with the N or units 380 and the N repair enable interfaces 313, where N is an integer greater than or equal to 2.

[0083] Optionally, the first register group includes multiple registers connected in series. The scan input interface of the first register group is the scan input interface of the head register, and the output interface is the output interface of the tail register. In this way, multiple registers in the first register group can be repaired.

[0084] Optionally, chip 300 also includes a processor connected to the repair controller; the processor is used to send a repair signal to the repair controller in the event of an anomaly in the first register set, the repair signal including the location of the first register set and repair data. Thus, a repair signal can be written to the repair controller via the processor.

[0085] This application achieves partial register repair capability by adding only a small amount of circuitry to the traditional DFT scan chain and per-controller architecture, namely, adding a small amount of logic circuitry and a repair controller. Since the added logic circuitry is minimal, it does not affect the overall chip area and power consumption, allowing the chip to operate normally by default. When an anomaly occurs in the first register group, the first register group can be repaired.

[0086] The above describes a chip that can repair register sets. The following example will be used to explain and illustrate the above content.

[0087] Please see Figure 9The diagram shows the structure of another chip. This chip includes a rerepair controller 310, a first register group 330, and a main controller 320. The input terminals i1 and i2 of the main controller 320 are connected to data interfaces TDI and TMS via a first line, and to the rerepair controller via a second line. The main controller is also connected to the first register group.

[0088] By default, the main controller 320 is used to send the signal to be stored input from the data interface through the first line to the first register group 330; if there is an abnormality in the first register group (such as when the normal function configuration path of the register fails or is damaged), the repair controller sends the signal to be repaired to the main controller through the second line, and the main controller obtains the signal to be repaired and sends it to the first register group.

[0089] Optionally, the main controller can be a JTAG controller (tap controller).

[0090] Optionally, the chip also includes a first multiplexer 340. The repair controller 310 includes a signal control interface TEN, a data transmission interface TMS, and a data transmission interface TDI. The first multiplexer 340 includes first input terminals a1 and a2, second input terminals b1 and b2, output terminals c1 and c2, and control terminals d1 and d2. The first input terminals a1 and a2 are respectively connected to the data interfaces TMS and TDI. The second input terminals b1 and b2 are respectively connected to the data transmission interfaces TMS and TDI of the repair controller. The output terminals c1 and c2 are respectively connected to the input terminals i1 and i2 of the main controller 320. The control terminals d1 and d2 are both connected to the signal control interface TEN.

[0091] Based on the above connection relationship, the signal control interface ten of the repair controller 310 outputs a first level by default (for example, if the first level is low, the signal level output by the ten terminal is 0). At this time, the first input terminals a1 and a2 and the output terminals c1 and c2 of the first multiplexer 340 are turned on, that is, the main controller 320 writes data from the tdi and tms of the first line. When the first register group is abnormal, that is, when the first register group needs to be repaired, the signal control interface ten of the repair controller 310 outputs a second level (for example, if the second level is high, the signal level output by the ten terminal is 1). At this time, the second input terminals b1 and b2 and the output terminals c1 and c2 of the first multiplexer 340 are turned on, that is, the main controller 320 writes data from the tdi and tms of the second line. In other words, the main controller 320 writes data from the repair controller and at the same time shuts down the data transmission of the first line.

[0092] The above scheme controls the data writing direction of the main controller through the signal control interface ten of the repair controller. That is, by default, the signal control interface ten outputs the first level, and the main controller writes data from the first line. When the register needs to be repaired, the signal control interface ten outputs the second level, and the main controller writes data from the repair controller.

[0093] Optionally, a second multiplexer 350 is also included. The repair controller 310 also includes a repair enable interface (repairenable). Both the main controller 320 and the first controller group 330 include a scan input interface (si). The second multiplexer 350 includes a first input terminal (a3), a second input terminal (b3), an output terminal (c3), and a control terminal (d3). The first input terminal (a3) ​​is connected to the output interface (so) of the second register group 390. The second register group 390 is a register group located before the first register group 330 on the chip register link. It is understood that the second register group 390 may include one or more registers, without specific limitations. When the second register group 390 has multiple registers, the first input terminal (a3) ​​of the second multiplexer 350 is connected to the output interface (so) of the last register in the second register group 390. The second input terminal (b3) of the second multiplexer 350 is connected to the scan input interface (si) of the main controller, the output terminal is connected to the scan input interface (si) of the first register group 330, and the control terminal is connected to the repair enable interface (repair enable) of the repair controller 310.

[0094] Based on the above connection relationships, the repair enable interface of the repair controller 310 outputs a first level by default (for example, if the first level is low, the signal level output by the repair enable terminal is 0). At this time, the first input terminal a3 and the output terminal c3 of the second multiplexer 350 are connected, that is, the scan input interface si of the first register group 330 is connected to the output interface so of the second register group 390. When the first register group 330 is abnormal, that is, when the first register group needs to be repaired, the repair enable interface of the repair controller 310 outputs a second level (for example, if the second level is high, the signal level output by the repair enable terminal is 1). At this time, the second input terminal b3 and the output terminal c3 of the second multiplexer 350 are connected, that is, the scan input interface si of the first register group 330 is directly connected to the scan input interface si of the main controller 320.

[0095] The above scheme controls the connection direction of the scan input interface si of the first register group by using the repair enable interface of the repair controller. That is, by default, the repair enable interface outputs the first level, and the first register group is connected to the preceding second register group to form a long scan chain. When the register needs to be repaired, the repair enable interface outputs the second level, and the first register group is directly connected to the main controller. In other words, the main controller can directly control the scanning of the first register group, turning the original long scan chain into a short scan chain. This increases the scanning efficiency of the first register group by the main controller.

[0096] Optionally, it also includes a third multiplexer 360 and a clock switching unit icg, and the repair controller 310 also includes a repair enable interface, a clock interface tck and a clock enable interface clken.

[0097] The clock switching unit icg is connected to both the clock enable interface clken and the clock signal function. It is used to disable the function clock signal when the clock enable interface clken outputs a first level (e.g., a low level, in which case the signal level output by clken is 0), and to enable the function clock signal when the clock enable interface clken outputs a second level (e.g., a low level, in which case the signal level output by clken is 1). In other words, the clock enable interface clken controls the opening and closing of the clock switching unit icg.

[0098] The third multiplexer 360 includes a first input terminal a4, a second input terminal b4, an output terminal c4, and a control terminal d4. The first input terminal a4 is connected to the clock switching unit icg, the second input terminal b4 is connected to the clock interface tck of the repair controller 310, the output terminal c4 is connected to the clock signal clk of the registers in the first register group 330, and the control terminal d4 is connected to the repair enable interface repair enable of the repair controller 310. It is understood that if there are multiple registers in the first register group, the output terminal c4 is connected to the clock signal clk of each register.

[0099] Based on the above connection relationships, the repair enable interface of the repair controller 310 outputs a first level by default (for example, if the first level is low, the signal level output by the repair enable terminal is 0), and the clock enable interface clken defaults to a second level (for example, if the second level is high, the signal level output by the clken terminal is 1). At this time, the first input terminal a4 and the output terminal c4 of the third multiplexer 360 are turned on, that is, the clock signal of the first register group 330 is controlled by the main controller 320. When the first register group 330 is abnormal, that is, when the first register group needs to be repaired, the repair enable interface of the repair controller 310 outputs a second level (for example, if the second level is high, the signal level output by the repair enable terminal is 1), and the clock enable interface clken outputs a first level (for example, if the first level is high, the signal level output by the clken terminal is 0). At this time, the second input terminal b4 and the output terminal c4 of the third multiplexer 360 are turned on, that is, the clock signal of the first register group 330 is controlled by the repair controller 310, and the function clock signal is turned off.

[0100] The above solution uses the repair enable interface of the repair controller to control whether to repair the first register group, and the clock enable interface clken to control the opening and closing of the clock on / off unit icg. In this way, the functional clock of the first register group can be turned off during repair, and after repair, since the functional clock is turned off and there is no clock edge trigger to update the data, the registers in the first register group will maintain their current state. This ensures that the repaired values ​​are "locked" in the registers.

[0101] Optionally, a fourth multiplexer 370 is also included. The repair controller 310 also includes a repair enable interface (repairenable). The main controller 320 and the first register group both include an output interface (so). The fourth multiplexer 370 includes a first input terminal (a5), a second input terminal (b5), an output terminal (c5), and a control terminal (d5). The first input terminal (a5) is connected to the output interface (so) of the first register group 330. The second input terminal (b5) is connected to the output interface (so) of the third register group 400. The third register group 400 is a register group located after the first register group in the chip's register chain. It is understood that the third register group 400 can have one or more registers. When the third register group 400 has multiple registers, the second input terminal (b5) of the fourth multiplexer 370 is connected to the output interface (so) of the last register in the third register group 400. The output terminal (c5) is connected to the output interface (so) of the main controller 320. The control terminal (d5) is connected to the repair enable interface (repair enable) of the repair controller 310.

[0102] Based on the above connection relationships, the repair enable interface of the repair controller 310 outputs a first level by default (for example, if the first level is low, the signal level output by the repair enable terminal is 0). At this time, the second input terminal b5 and the output terminal c5 of the fourth multiplexer 370 are connected, that is, the output interface so of the first register group 330 is connected to the scan input interface si of the subsequent third register group 400. When the first register group 330 is abnormal, that is, when the first register group needs to be repaired, the repair enable interface of the repair controller 310 outputs a second level (for example, if the second level is high, the signal level output by the repair enable terminal is 1). At this time, the first input terminal a5 and the output terminal c5 of the fourth multiplexer 370 are connected, that is, the output interface so of the first register group 330 is directly connected to the output interface so of the main controller 320.

[0103] The above scheme controls the connection direction of the output interface SO of the first register group by using the repair enable interface of the repair controller. That is, by default, the repair enable interface outputs the first level, and the first register group is connected to the third register group to form a long scan chain. When the register needs to be repaired, the repair enable interface outputs the second level, and the first register group is directly connected to the main controller. In other words, the output of the first register group is directly transmitted to the main controller, turning the original long scan chain into a short scan chain. This increases the scanning efficiency of the main controller for the first register group.

[0104] Optionally, it also includes an OR unit 380, and the repair controller 310 further includes a repair enable interface. The main controller 320 and the first register group both include a scan enable interface se. The OR unit includes a first input e, a second input f, and an output g. The first input e is connected to the repair enable interface se of the repair controller 310, the second input f is connected to the scan enable interface se of the main controller 320, and the output g is connected to the scan enable interface se of the first register group 330.

[0105] The above scheme uses the repair enable interface of the repair controller to control the scan enable interface se of the first register group. That is, by default, the repair enable interface outputs the first level, and the main controller controls the scan enable interface se of the long chain registers on the entire chip. When a register needs to be repaired, the repair enable interface of the repair controller controls the scan enable interface se of the first register group. In this way, the original long scan chain is turned into a short scan chain, which can increase the scanning efficiency of the main controller for the first register group.

[0106] Optionally, the first register group includes M registers, where M is a positive integer. When M is 1, the scan input interface si and output interface so of the first register group are unique. When M is greater than or equal to 2, the M registers in the first register group are cascaded, the scan input interface si of the first register group is the scan input interface si of the head register, and the output interface so is the output interface so of the tail register. Figure 3 For example, if M=2, please continue reading. Figure 3 The output terminal C3 of the second multiplexer 350 is connected to the scan input interface Si of the first register in the first register group 330, and the first input terminal A5 of the fourth multiplexer 370 is connected to the output interface So of the second (and last) register in the first register group 330. In this way, multiple registers in the first register group can be repaired.

[0107] Optionally, a processor is also included, connected to the repair controller 310, for sending a repair signal to the repair controller 310 in the event of an anomaly in the first register group 330. The repair signal includes the location of the first register group and repair data. Thus, the processor can write the repair signal to the repair controller.

[0108] Furthermore, optionally, the processor can be DMA or CPU.

[0109] The above solution, by adding a repair controller, can quickly repair the first register group when it is abnormal (such as when the normal function configuration path of the register fails or is damaged). After the repair, the chip enters the normal working mode, and the value of the configured register remains valid, thus achieving the goal of repairing the register.

[0110] The above describes the connection relationships between the repair register, the first register group, the main controller, and different control logic units. The first register group can be one or multiple, and these register groups can be connected in parallel or in series. The following sections describe the connection relationships between the repair register, the first register group, the main controller, and different control logic units in the cases of multiple first register groups connected in series and in parallel.

[0111] 1. Multiple register groups are connected in series.

[0112] Please see Figure 10 The diagram illustrates a chip structure with multiple first register groups connected in series, using two register groups as an example. As shown, the connections between the main controller, repair controller, first multiplexer, second multiplexer, and fourth multiplexer are the same as described above, and therefore will not be repeated here. It is worth noting that the output of the second multiplexer is connected to the first register group among the multiple first register groups, and the first input of the fourth multiplexer is connected to the last register group among the multiple first register groups. In this way, multiple first register groups can be connected in series to form a short scan chain.

[0113] Continue reading Figure 10 If N first register groups are connected in series, then there are N third multiplexers and N clock switching units (icg). Each of the N third multiplexers corresponds one-to-one with one of the N clock switching units (icg), and each of the N third multiplexers corresponds one-to-one with one of the N first register groups, where N is a positive integer. For example, in the diagram, there are two first register groups, 3301 and 3302. First register group 3301 corresponds to third multiplexer 3601, and first register group 3302 corresponds to third multiplexer 3602. The connection relationship and function of the clock switching units (icg) are the same as described above and will not be repeated here.

[0114] Each third multiplexer includes a first input, a second input, an output, and a control terminal. The first input is connected to the clock switching unit icg, the second input is connected to the clock interface tck of the repair controller 310, and the control terminal is connected to the repair enable interface repair enable of the repair controller 310. The output is connected to the clock signal clk of the corresponding register in the first register group. For example, the output of the third multiplexer 3601 is connected to the clock signal clk of the first register group 3301, and the output of the third multiplexer 3602 is connected to the clock signal clk of the first register group 3302.

[0115] Optionally, it also includes N OR units. The repair controller 310 also includes a repair enable interface, and the main controller 320 and each first register group include a scan enable interface se. The OR unit includes a first input e, a second input f, and an output g. The first input e is connected to the repair enable interface of the repair controller 310, the second input f is connected to the scan enable interface se of the main controller 320, and the output g is connected to the scan enable interface se of the first register group 330.

[0116] 2. Multiple register groups are connected in parallel.

[0117] Please see Figure 11 The diagram shows a chip structure with multiple first register groups connected in parallel, with two register groups as an example. As can be seen from the diagram, the connection relationships of the main controller, repair controller, and first multiplexer are the same as described above; therefore, they will not be repeated here.

[0118] Continue reading Figure 11 If there are N first register groups connected in parallel, there are N second multiplexers. The N second multiplexers correspond one-to-one with the N first register groups. The repair controller 310 also includes N repair enable interfaces, which correspond one-to-one with the N second multiplexers. The main controller 320 and the first controller group 330 both include a scan input interface si, where N is a positive integer.

[0119] Each second multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal is connected to the output interface so of the second register group, wherein the second register group is the register group located before the first register group on the chip register link. When the second register group has multiple registers, the first input terminal of the second multiplexer is connected to the output interface so of the last register in the second register group. The second input terminal of the second multiplexer is connected to the scan input interface si of the main controller, the output terminal is connected to the scan input interface si of the corresponding first register group, and the control terminal is connected to the repair enable interface corresponding to the repair controller 310.

[0120] for example, Figure 11 The first register group 3301 corresponds to the second multiplexer 3501. The first input of the second multiplexer 3501 is connected to the output interface so of the preceding register group, the output is connected to the scan input interface si of the first register group 3301, and the control is connected to the repair enable interface repair enable0 of the repair controller 310. The first register group 3302 corresponds to the second multiplexer 3502. The first input of the second multiplexer 3502 is connected to the output interface so of the preceding register group, the output is connected to the scan input interface si of the first register group 3302, and the control is connected to the repair enable interface repair enable1 of the repair controller 310.

[0121] Optionally, it also includes N third multiplexers and N clock switching units (icg). The N third multiplexers correspond one-to-one with the N clock switching units, and the N third multiplexers also correspond one-to-one with the N first register groups. The repair controller 310 also includes N repair enable interfaces, N clock interfaces, and N clock enable interfaces, each corresponding one-to-one with the N third multiplexers, where N is a positive integer. The function of the clock switching unit (icg) is the same as described above and will not be repeated here.

[0122] Each third multiplexer includes a first input, a second input, an output, and a control terminal. The first input is connected to the corresponding clock switching unit (icg), the second input is connected to the clock interface (tck) of the repair controller 310, the output is connected to the clock signal (clk) of the register in the corresponding first register group, and the control terminal is connected to the repair enable interface of the repair controller 310. It is understood that if there are multiple registers in the first register group, the output is connected to the clock signal (clk) of each register.

[0123] for example, Figure 11 The first register group 3301 corresponds to the third multiplexer 3601. The second input terminal of the third multiplexer 3601 is connected to the clock interface tck0 of the repair controller 310, the output terminal is connected to the clock signal clk of the first register group 3301, and the control terminal is connected to the repair enable interface repair enable0 of the repair controller 310. Figure 5 The first register group 3302 corresponds to the third multiplexer 3602. The second input of the third multiplexer 3602 is connected to the clock interface tck1 of the repair controller 310, the output is connected to the clock signal clk of the first register group 3302, and the control is connected to the repair enable interface repair enable1 of the repair controller 310.

[0124] Optionally, it also includes N fourth multiplexers, each corresponding to one of the N first register groups. The repair controller also includes N repair enable interfaces. The main controller and each first register group include output interfaces, where N is a positive integer.

[0125] Each fourth multiplexer includes a first input, a second input, an output, and a control terminal. The first input is connected to the output interface SO of the first register group, and the second input is connected to the output interface SO of the third register group. The third register group is the register group located after the first register group on the chip's register link. When the third register group has multiple registers, the second input of the fourth multiplexer is connected to the output interface SO of the last register in the third register group, the output is connected to the output interface SO of the main controller 320, and the control terminal is connected to the repair enable interface of the repair controller 310.

[0126] for example, Figure 11 The first register group 3301 corresponds to the fourth multiplexer 3701. The first input terminal of the fourth multiplexer 3701 is connected to the output interface so of the first register group 3301, and the control terminal is connected to the repair enable interface repair enable0 of the repair controller 310. The first register group 3302 corresponds to the fourth multiplexer 3702. The first input terminal of the fourth multiplexer 3702 is connected to the output interface so of the first register group 3302, and the control terminal is connected to the repair enable interface repair enable1 of the repair controller 310.

[0127] Optionally, it also includes N OR units, each corresponding to one of the N first register groups. The repair controller also includes N repair enable interfaces, and the main controller and each first controller group also include a scan enable interface, where N is a positive integer.

[0128] Each unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the repair enable interface of the repair controller 310, the second input terminal is connected to the scan enable interface se of the main controller 320, and the output terminal is connected to the scan enable interface of the first register group.

[0129] for example, Figure 11The first register group 3301 corresponds to the OR unit 3801. The first input terminal of the OR unit 3801 is connected to the repair enable interface 310 of the repair controller (repair enable0), and the output terminal is connected to the scan enable interface of the first register group 3301. The first register group 3302 corresponds to the OR unit 3802. The first input terminal of the OR unit 3802 is connected to the repair enable interface 310 of the repair controller (repair enable1), and the output terminal is connected to the scan enable interface of the first register group 3302.

[0130] By adding a repair controller and a small amount of logic circuitry to the existing chip, the above method can be used to repair some registers. The following is a complete example illustrating the chip's operation after power-on:

[0131] First, after the chip powers on, the repair controller enters a WAIT state after the chip resets, waiting for data write operations from the processor (such as CPU or DMA). If an engineer discovers an anomaly in a register during chip use, a repair signal (including the register group number to be repaired and the correction data) is written to the processor. For example, the repair signal can be stored in memory or a specific location accessible to the CPU. The repair signal is retrieved by executing a DMA operation or by the CPU executing a software program. Then, the processor writes the repair signal to the repair controller (for example, DMA directly writes data from memory to the repair controller's registers, or the CPU writes the repair signal to the repair controller's registers via the bus). The repair controller checks if the repair signal is valid; if valid, it performs the following repair operations:

[0132] Step 1: The signal control interface ten of the repair controller changes from 0 to 1, controlling the data writing direction of the main controller. That is, the main controller changes from writing data from the first line to writing data from the second line. In other words, the main controller reads the repair signal from the repair controller. At the same time, the scan enable interface se of the main controller changes from 0 to 1, entering the scan state.

[0133] Step 2: Change the signal of the controller clock enable interface clken from 1 to 0 to turn off the clock on / off unit icg, that is, turn off the function clock of the first register group.

[0134] Step 3: The repair enable interface of the repair controller generates enough clock pulses to repair the register group according to the length of the register group to be repaired. At the same time, it controls the main repairer to shift the correction data. The number of clock pulses required for the shift is equal to the length of the scan chain of the repair register group. In this way, each register can obtain the corresponding correction value.

[0135] Step 4: When the clock pulse counter of the repair enable interface of the repair controller decrements to 0, the repair operation is complete. Afterwards, the signal of the repair enable interface becomes 0, the clock signal of the clock enable interface remains 0, and the repaired register group enters normal operating mode. Thus, after repair is complete, the signal of the clock enable interface remains low, the function clock remains off, and the corrected value is latched into the registers. That is, after repair, the repaired register group will be in a fixed value state.

[0136] Step 5: When all register groups to be repaired have completed the correction operation, the signal of the signal control interface ten of the repair controller changes from 1 to 0, releasing control over the main controller. At the same time, the repair controller enters the control (CONTROL) working state, and the chip continues to perform subsequent normal working states. That is, the scan enable interface se of the main controller changes from 1 to 0, exiting the scan state, and the main controller writes data from the first line.

[0137] Through the above steps, a system design method can be implemented to quickly repair registers by scanning chain shifting when the chip is powered on, and then save register data by cutting off the clock. That is, in synchronous sequential circuits, register state updates are controlled by the clock signal. When the clock is turned off, there is no clock edge to trigger data updates, and the register will maintain its current state. In this scheme, the corrected value is first written to the register through a shift operation, and then these corrected values ​​are maintained by turning off the function clock. Thus, even if the system continues to run subsequently, these repaired registers will retain their corrected values. Furthermore, the repair controller in this application is implemented using a state machine. It is in a WAIT state before repair, an operating state during repair, and a CONTROL state after repair. Implementing the repair function through a state machine with three states simplifies the repair circuit, reduces its area, and minimizes the impact on the original logic function.

[0138] The above describes the structure and corresponding functions of a chip. The following describes how to design the chip, that is, how to insert a repair controller and repair control interface (including clock control logic and MUX unit) during the chip design stage.

[0139] Optionally, script tools can be used to insert repair controllers and repair control interfaces.

[0140] First, we will introduce the design flow of the chip structure when multiple first register groups are used serially. Please refer to [link / reference]. Figure 12 The flowchart illustrates the process of adding the first cascaded register group during the design phase, including the following steps:

[0141] Step 610: Traverse the entire scan chain on the chip to determine if there is a first register group that needs to be repaired. If there is, proceed to step 630. If not, proceed to step 620.

[0142] Step 620: End the process.

[0143] Step 630: Obtain the first register group that needs to be repaired from the K registers on the chip.

[0144] Here, K and N are positive integers. It's understandable that a chip may have hundreds of thousands or even millions of registers, a very large number. Repairing all registers would be too complex. Therefore, this application selects a subset of registers on the chip as repairable registers, groups them, and connects them together to form a short chain—for example, 20 registers, 10 registers, or even fewer registers per group. This way, when a repairable register malfunctions, the malfunctioning register can be quickly repaired.

[0145] Step 640: Obtain the position of the first register group in the K registers and the number of registers in the first register group, insert the repair control interface and create a short chain for the first register group.

[0146] For example, please refer to the basics. Figure 9 Assuming that Figure 9 The first register group 330 is designated as a repairable register group. The location of the first register group 330 (i.e., its position on the chip scan chain, for example, 4) and the number of registers (the first register group 330 has two registers, therefore the number of registers is 2) are obtained, and a repair control interface is inserted. Here, the repair control interface includes adding a clock enable interface (clken), a clock interface (tck), etc., to the repair controller, as well as the aforementioned first multiplexer, second multiplexer, third multiplexer, fourth multiplexer, and OR unit. This allows the repair controller to repair the first register group according to the repair control interface. Simultaneously, one or more registers in the first register group are connected together to form a short chain of registers.

[0147] Step 650: Determine whether the first register group is the first group. If yes, proceed to step 660; otherwise, proceed to step 670.

[0148] Step 660: Add the repair enable interface and the corresponding connection logic circuit to the repair controller, and then execute step 680.

[0149] Here, if it is the first register group, then a repair enable interface needs to be created.

[0150] Step 670: Add the first register set after the created repairable register set, and recalculate the number of registers in the repairable register set, then proceed to step 680.

[0151] If it is not the first register group, it is added after the already created repairable register group, and the number of registers in the repairable register group after the addition is recalculated.

[0152] Step 680: Add connection circuitry according to the repair enable interface, then return to step 610.

[0153] Here, the connection circuit between the first multiplexer, second multiplexer, third multiplexer, fourth multiplexer, or unit, repair controller, first register, and main controller is created. In this way, a repairable first register group short chain can be created, and each first register group can be accessed by the main controller and the repair controller. Then, during use, the abnormal first register group can be repaired according to the repair controller.

[0154] The above scheme can achieve serial connection of the register group to be repaired. The serial connection method has a simpler structure and only has one repair interface, but the repair time will increase with the increase of the number of serial registers.

[0155] Next, the design flow of the chip architecture when multiple first register groups are used in parallel is described. Please refer to [link / reference]. Figure 13 The flowchart illustrates the process of adding a parallel first register group during the design phase, including the following steps:

[0156] Step 710: Traverse the entire scan chain on the chip to determine if there is a first register group that needs to be repaired. If there is, proceed to step 730. If not, proceed to step 720.

[0157] Step 720: End the process.

[0158] Step 730: Obtain the first register group that needs to be repaired from the K registers on the chip.

[0159] Here, K and N are positive integers. It's understandable that a chip may have hundreds of thousands or even millions of registers, a very large number. Repairing all registers would be too complex. Therefore, this application selects a subset of registers on the chip as repairable registers, groups them, and connects them together to form a short chain—for example, 20 registers, 10 registers, or even fewer registers per group. This way, when a repairable register malfunctions, the malfunctioning register can be quickly repaired.

[0160] Step 740: Obtain the position of the first register group in the K registers and the number of registers in the first register group, insert the repair control interface and create a short chain for the first register group.

[0161] For example, please refer to the basics. Figure 9 Assuming that Figure 9 The first register group 330 is designated as a repairable register group. The location of the first register group 330 (i.e., its position on the chip scan chain, for example, 4) and the number of registers (the first register group 330 has two registers, therefore the number of registers is 2) are obtained, and a repair control interface is inserted. Here, the repair control interface includes adding a clock enable interface (clken), a clock interface (tck), etc., to the repair controller, as well as the aforementioned first multiplexer, second multiplexer, third multiplexer, fourth multiplexer, and OR unit. This allows the repair controller to repair the first register group according to the repair control interface. Simultaneously, one or more registers in the first register group are connected together to form a short chain of registers.

[0162] Step 750: Add the repair enable interface and the corresponding connection logic circuit to the repair controller.

[0163] Understandably, each first register group corresponds to a repair enable interface and a corresponding connection logic circuit, meaning that each first register group can be accessed by the main controller and the repair controller.

[0164] Step 760: Add connection circuitry based on the repair enable interface, then return to step 710.

[0165] Here, the connection circuit between the first multiplexer, second multiplexer, third multiplexer, fourth multiplexer, or unit, repair controller, first register, and main controller is created. In this way, a repairable register group short chain can be created, and each first register group can be accessed by the main controller and the repair controller. Then, during use, the abnormal first register group can be repaired according to the repair controller.

[0166] The above scheme enables parallel connection of register groups to be repaired. Since each first register group corresponds to a repair enable interface, each first register group can be individually disabled, meaning it does not participate in the repair operation. This saves repair time. Therefore, while the parallel connection method increases the number of repair interfaces in the register repair controller, the time overhead for repairing registers when the chip powers on is well controlled.

[0167] The above scheme can be used to repair multiple register groups. By setting the current register access mode to short scan chain mode, that is, configuring the bypass register of the short scan chain according to the location information of the register to be repaired, the original long scan chain is transformed into a very short scan chain, achieving the effect of rapid configuration. It also enables the register group to be repaired on the chip to be in the shift enable state. In this way, the repair controller can access each register that needs to be repaired through the constructed short scan chain.

[0168] This application achieves partial register repair capability by adding only a small amount of circuitry to the traditional DFT scan chain and per-controller architecture, namely, adding a small amount of logic circuitry and a repair controller. Since the added logic circuitry is minimal, it does not affect the overall chip area and power consumption, allowing the chip to operate normally by default. When an anomaly occurs in the first register group, the first register group can be repaired.

[0169] Based on the chips described above, this application can also provide an electronic device that includes the chip provided in any of the above embodiments. Optionally, the chip may be a processing chip, a memory chip, or a combination of both.

[0170] Optionally, in addition to the chip, the electronic device may also include other components, such as a housing, in which the chip is encapsulated and protected. Some electronic devices with display functions may also have a display, such as one or more screens. In this case, the chip is connected to the display and also has a driving function to drive the display to show images.

[0171] Of course, in other scenarios, electronic devices may have other components, which will not be listed here.

[0172] Based on the exemplary embodiments described in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the appended claims. Furthermore, although the disclosures in this application are presented by way of one or more exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation on its own.

[0173] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0174] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise indicated. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation is possible in orders other than those given in the embodiments illustrated or described in this application.

[0175] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

Claims

1. A chip, characterized in that, include: The system includes a main controller, a repair controller, a first register group, a data interface, and a first multiplexer. The repair controller includes a signal control interface and a data transmission interface. The first multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal is connected to the data interface, the second input terminal is connected to the data transmission interface, the output terminal is connected to the first input terminal of the main controller, and the control terminal is connected to the signal control interface. The data interface is used to receive the signal to be stored and send it to the main controller when the first register group is normal. The repair controller is used to output a first level through the signal control interface when the first register group is normal, and to output a second level through the signal control interface when the first register group is abnormal, so as to send the signal to be repaired to the main controller. The first multiplexer is configured to connect the first input terminal and the output terminal when the control terminal receives a first level, and to connect the second input terminal and the output terminal when the control terminal receives a second level. The main controller is configured to send the signal to be stored from the data interface to the first register group, or to send the signal to be repaired from the repair controller to the first register group.

2. The chip as described in claim 1, characterized in that, The chip also includes a second multiplexer and a second register group, wherein the second register group is the register group located before the first register group on the register link of the chip, the repair controller also includes a repair enable interface, and both the main controller and the first register group include a scan input interface; The second multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal is connected to the output interface of the second register group, the second input terminal is connected to the scan input interface of the main controller, the output terminal is connected to the scan input interface of the first register group, and the control terminal is connected to the repair enable interface. The repair controller is configured to output a first level through the repair enable interface when the first register group is normal, and to output a second level through the repair enable interface when the first register group is abnormal. The second multiplexer is configured to connect the first input terminal and the output terminal when the control terminal receives a first level, and to connect the second input terminal and the output terminal when the control terminal receives a second level.

3. The chip as described in claim 2, characterized in that, There are N first register groups, N repair enable interfaces, and N repair enable interfaces. The N first register groups are connected in parallel and correspond one-to-one with the N second multiplexers and N repair enable interfaces. N is an integer greater than or equal to 2.

4. The chip as described in any one of claims 2-3, characterized in that, The first register group includes multiple registers connected in series. The scan input interface of the first register group is the scan input interface of the head register, and the output interface of the first register group is the output interface of the tail register.

5. The chip as described in claim 1, characterized in that, The chip also includes a third multiplexer and a clock switching unit, and the repair controller also includes a repair enable interface, a clock interface, and a clock enable interface. The first input terminal of the clock switching unit is connected to the clock signal output terminal, the second input terminal of the clock switching unit is connected to the clock enable interface, the output terminal of the clock switching unit is connected to the first input terminal of the third multiplexer, the second input terminal of the third multiplexer is connected to the clock interface, the output terminal of the third multiplexer is connected to the clock signal input terminal in the first register group, and the control terminal of the third multiplexer is connected to the repair enable interface. The repair controller is configured to output a first level through the repair enable interface and a third level through the clock enable interface when the first register group is normal; and to output a second level through the repair enable interface and a fourth level through the clock enable interface when the first register group is abnormal. The third multiplexer is configured to turn on its first input and output terminals when the control terminal of the third multiplexer receives the first level, and to turn on its second input and output terminals when the control terminal of the third multiplexer receives the second level. The clock switching unit is used to turn off the clock signal when the second input terminal receives a fourth level, and to turn on the clock signal when the second input terminal receives a third level.

6. The chip as described in claim 5, characterized in that, There are N first register groups, N third multiplexers, and N clock switching units. The N first register groups are connected in series and correspond one-to-one with the N third multiplexers and N clock switching units, where N is an integer greater than or equal to 2.

7. The chip as described in claim 5, characterized in that, There are N of each of the first register group, the third multiplexer, the repair enable interface, the clock interface, the clock enable interface, and the clock switching unit. The N first register groups are connected in parallel and correspond one-to-one with the N third multiplexers, the N repair enable interfaces, the N clock interfaces, the N clock enable interfaces, and the N clock switching units, where N is an integer greater than or equal to 2.

8. The chip as described in claim 1, characterized in that, The chip also includes a fourth multiplexer and a third register group, wherein the third register group is the register group located after the first register group on the register link of the chip, the repair controller also includes a repair enable interface, and both the main controller and the first register group include output interfaces; The fourth multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal is connected to the output interface of the first register group; the second input terminal is connected to the output interface of the third register group; the output terminal is connected to the output interface of the main controller; and the control terminal is connected to the repair enable interface. The repair controller is configured to output a first level through the repair enable interface when the first register group is normal, and to output a second level through the repair enable interface when the first register group is abnormal. The fourth multiplexer is used to turn on the second input terminal and the output terminal when the control terminal receives the first level, and to turn on the first input terminal and the output terminal when the control terminal receives the second level.

9. The chip as described in claim 8, characterized in that, There are N first register groups, N repair enable interfaces, and N fourth multiplexers. The N first register groups are connected in parallel and correspond one-to-one with the N fourth multiplexers and N repair enable interfaces. N is an integer greater than or equal to 2.

10. The chip as described in claim 1, characterized in that, The chip also includes an OR unit, the repair controller also includes a repair enable interface, and both the main controller and the first register group also include a scan enable interface; The unit includes a first input terminal, a second input terminal, and an output terminal; the first input terminal is connected to the repair enable interface, the second input terminal is connected to the scan enable interface of the main controller, and the output terminal is connected to the scan enable interface of the first register group. The repair controller is configured to output a first level through the repair enable interface when the first register group is normal, and to output a second level through the repair enable interface when the first register group is abnormal.

11. The chip as described in claim 10, characterized in that, There are N first register groups and N OR units. The N first register groups are connected in series and correspond one-to-one with the N OR units, where N is an integer greater than or equal to 2.

12. The chip as described in claim 10, characterized in that, There are N first register groups, N repair enable interfaces, and N OR units. The N first register groups are connected together and correspond one-to-one with the N OR units and N repair enable interfaces. N is an integer greater than or equal to 2.

13. The chip as described in claim 12, characterized in that, The chip also includes a processor, which is connected to the repair controller; The processor is configured to send a repair signal to the repair controller in the event of an anomaly in the first register group, the repair signal including the location of the first register group and repair data.

14. An electronic device, characterized in that, Includes the chip as described in any one of claims 1-13.

Images