Delay calculation method, electronic equipment and storage medium

Abstract

The invention discloses a delay calculation method, electronic equipment and a storage medium, and the method comprises the steps: constructing a reduced-order model of an interconnection line corresponding to a driver model and a receiver model, and enabling the reduced-order model to be provided with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; determining an output voltage waveform of the driver by using a preset step length and an impedance function; taking the output voltage waveform of the driver as input, and determining an input voltage waveform of a receiver by using a preset delay voltage threshold and a transfer function; determining the input conversion time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and further determining a delay calculation result; according to the method, transient analysis is combined with the composite current source model, the corresponding driver output voltage waveform and the corresponding receiver input voltage waveform are determined, then analysis and accurate delay calculation are carried out, and the accuracy of a delay calculation result can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a delay calculation method, an electronic device and a storage medium. Background Art

[0002] In the static timing analysis of integrated circuits, accurate and fast delay calculation is crucial. When performing delay calculation, the timing path is usually divided into multiple stages, each of which includes the driver unit, the RC network at the unit output, and the pin capacitance at the network load end. By establishing the corresponding driver model, RC model, and receiver model, the unit delay and line delay calculation are performed.

[0003] In practice, the researchers of this application found that the current technology only performs simple segmentation on the driver output voltage interval when calculating the effective capacitance, and divides the three intervals into three sections using the common delay voltage threshold, the minimum conversion voltage threshold, and the maximum conversion voltage threshold. However, when using a composite current source model, it is necessary to calculate the receiver input waveform through the driver output waveform, and after obtaining the receiver conversion time, update the pin capacitance through a lookup table. The driver output waveform obtained by simple segmentation is still different from the real waveform, which leads to the distortion of the calculated receiver input waveform, the pin capacitance obtained by the lookup table is inaccurate, and the delay result obtained after the final iterative convergence is inaccurate. When the supply voltage is reduced, the driver output waveform is more nonlinear, and the error generated is more obvious, that is, the waveform obtained by simple segmentation cannot accurately represent the distortion of the driver output waveform, resulting in inaccurate analysis results of the delay calculation. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a delay calculation method, an electronic device and a storage medium, which can accurately represent the driver output voltage waveform and the receiver input voltage waveform, and improve the accuracy of the analysis results of the delay calculation.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a delay calculation method, including: constructing a reduced-order model of the interconnection line corresponding to the driver model and the receiver model, wherein the reduced-order model is set with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; using a preset step size and the impedance function, determining the driver output voltage waveform corresponding to the driver model; using the driver output voltage waveform as input, using a preset delay voltage threshold and the transfer function, determining the receiver input voltage waveform corresponding to the receiver model; using the driver output voltage waveform and the receiver input voltage waveform, determining the input conversion time corresponding to the receiver model, and then determining the delay calculation result.

[0006] In some embodiments, constructing a reduced-order model of an interconnect corresponding to a driver model and a receiver model includes: determining the driver model and the receiver model based on timing information provided by a preset first file; and establishing the reduced-order model of the interconnect based on parasitic parameter information, the driver model, and the receiver model provided by a preset second file.

[0007] In some embodiments, the reduced-order model of the interconnect is established according to the parasitic parameter information, the driver model and the receiver model provided by a preset second file, including: establishing a first circuit equation and a second circuit equation corresponding to a driver output current and a driver output voltage according to the interconnect information provided by the preset second file; and establishing a third circuit equation and a fourth circuit equation corresponding to the driver output voltage and the receiver input voltage; performing Laplace transform using the first circuit equation and the second circuit equation to determine the impedance function; and performing Laplace transform using the third circuit equation and the fourth circuit equation to determine the transfer function; and forming the reduced-order model with the transfer function and the impedance function.

[0008] In some embodiments, the impedance function includes a first impedance function and a second impedance function; the use of a preset step size and the impedance function to determine the driver output voltage waveform corresponding to the driver model includes: using a preset output load range to determine the current curve and the corresponding voltage curve corresponding to each load, and then establishing a current curve set and a voltage curve set output by the driver; determining an interpolation coefficient and a corresponding start time based on a preset starting capacitance, and saving the corresponding output current waveform starting point of the current curve set and the output voltage waveform starting point of the voltage curve set; determining the current voltage using a preset voltage change value and a starting voltage, and determining the current time and the corresponding voltage change rate using the current voltage and the interpolation coefficient, and determining the current current based on the current time; adding a preset step size to the current time, and determining the output voltage using a recursive convolution method through the output current waveform and the first impedance function or the second impedance function, and then determining the driver output voltage waveform corresponding to the driver model.

[0009] In some embodiments, determining the current current based on the current time includes: using the first voltage curve and the second voltage curve corresponding to the two endpoints of the output load interval to determine the first time and the second time corresponding to the current voltage, and using the first current curve and the second current curve corresponding to the two endpoints of the output load interval to determine the first current corresponding to the first time and the second current corresponding to the second time; then determining the time difference ratio of the first time difference between the current time and the first time and the second time difference between the second time and the first time, and determining the current difference between the second current and the first current, and determining the current current based on the product of the time difference ratio and the current difference, and the first current, and saving the current voltage and the current current to the corresponding output voltage waveform and output current waveform.

[0010] In some embodiments, the method of determining the output voltage using a recursive convolution method includes: obtaining a first zero pole and a second zero pole of a first impedance function or a second impedance function, and obtaining the output voltage of a previous time step; determining the output voltage using a recursive convolution method based on the preset step size, the first zero pole, the second zero pole, the current current corresponding to the output current waveform, and the order of the reduced-order model.

[0011] In some embodiments, it also includes: determining the relationship between the current time and the first time and the second time corresponding to the current voltage; if the current time is between the first time and the second time, determining the current current using the current time; if the current time is outside the first time and the second time, adjusting the two endpoints of the output load interval so that the adjusted current time is between the first time and the second time, and then determining the current current using the adjusted current time.

[0012] In some embodiments, it also includes: performing numerical detection on the current voltage, current current and voltage change rate; when the numerical value is normal, calculating the difference between the voltage change rate corresponding to the current step size and the voltage change rate corresponding to the previous step size; using the change rate difference to calculate the local truncation error, and then adjusting the preset step size through the first relationship between the local truncation error and the preset error tolerance, and the size of the voltage change rate; if a numerical abnormality occurs, marking the solution of the current step size invalid, and performing a rollback process.

[0013] In some embodiments, it also includes: using a delayed voltage threshold to judge the current voltage; when the current voltage of the previous step is less than the delayed voltage threshold and the current voltage of the current step is greater than the delayed voltage threshold, switching the first impedance function or the second impedance function in the reduced-order model to the second impedance function or the first impedance function; if the delayed voltage threshold is outside the current voltage of the previous step and the current voltage of the current step, using the end voltage threshold to judge the current voltage, wherein the delay voltage threshold and the end voltage threshold are in a multiple relationship; when the current voltage is less than the end voltage threshold point, resolving the output voltage.

[0014] In some embodiments, the transfer function includes a first transfer function and a second transfer function; the use of a preset delay voltage threshold and the transfer function to determine the receiver input voltage waveform corresponding to the receiver model includes: using the driver output voltage waveform as input to obtain the third zero pole and the fourth zero pole of the first transfer function or the second transfer function; based on the preset step size, the third zero pole, the fourth zero pole, the point information corresponding to the driver output voltage waveform and the order of the reduced-order model, determining the receiver input voltage waveform through recursive convolution.

[0015] In some embodiments, the use of the driver output voltage waveform and the receiver input voltage waveform to determine the input conversion time corresponding to the receiver model, and then determine the delay calculation result, includes: obtaining a delay threshold voltage, a first conversion threshold voltage and a second conversion threshold voltage, and obtaining a reference time corresponding to a current curve in a current curve concentration; using the driver output voltage waveform and a first time corresponding to the delay threshold voltage, and then determining a unit delay with the first time and the reference time; using the driver output voltage waveform and the first conversion threshold voltage to determine a second time, and using the driver output voltage waveform and the second conversion threshold voltage to determine a third time, and then using the second time and the third time to determine a unit output conversion time; using the driver output voltage waveform and the fourth time corresponding to the delay threshold voltage and the fifth time corresponding to the receiver input voltage waveform and the delay threshold voltage to determine the interconnection line delay; using the receiver input voltage waveform and the sixth time corresponding to the second conversion threshold voltage and the seventh time corresponding to the receiver input voltage waveform and the first conversion threshold voltage to determine the lower-level unit input conversion time.

[0016] In some embodiments, it also includes: comparing the absolute change and relative change of the input conversion time corresponding to the current iteration and the previous iteration; if there is no convergence, using the current input conversion time to update the preset output load range, and then recalculating the driver output waveform.

[0017] To solve the above technical problems, the present application also provides an electronic device, comprising a memory and a processor coupled to the memory, wherein the memory stores at least one computer program, and when the at least one computer program is loaded and executed by the processor, it is used to implement the above method.

[0018] In order to solve the above technical problems, the present application also provides a storage medium, which has at least one program. When the at least one program is loaded and executed by a processor, it is used to implement the above method.

[0019] Different from the current technology, the delay calculation method provided by the present application includes: constructing a reduced-order model of the interconnection line corresponding to the driver model and the receiver model, wherein the reduced-order model is set with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; using a preset step size and impedance function, determining the driver output voltage waveform corresponding to the driver model; using a preset delay voltage threshold and transfer function, determining the receiver input voltage waveform corresponding to the receiver model; using the driver output voltage waveform and the receiver input voltage waveform, determining the input conversion time corresponding to the receiver model, and then determining the delay calculation result. That is, the present application uses transient analysis combined with a composite current source model (driver model and receiver model) to determine the corresponding driver output voltage waveform, that is, the corresponding receiver input voltage waveform, and then performs analysis and accurate calculation of delay, which can effectively improve the accuracy of the delay calculation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0021] Figure 1 It is a flowchart of an embodiment of a delay calculation method in this application;

[0022] Figure 2 It is a schematic diagram of the structure of the model in this application;

[0023] Figure 3 This is a flow chart of an embodiment of step S20 in this application;

[0024] Figure 4 is a schematic diagram of the driver output voltage waveform in this application;

[0025] Figure 5 It is a structural schematic diagram of an embodiment of an electronic device in the present application;

[0026] Figure 6 It is a structural diagram of an embodiment of a storage medium in the present application. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present invention, but are not intended to limit the scope of the present invention. Similarly, the following examples are only partial embodiments of the present invention rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0028] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] In the static timing analysis of integrated circuits, accurate and fast delay calculation is crucial. When performing delay calculation, the timing path is usually divided into multiple stages, each of which includes the driver unit, the RC network at the unit output, and the pin capacitance at the network load end. By establishing the corresponding driver model, RC model, and receiver model, the unit delay and line delay calculation are performed. For designs using advanced processes, the RC model is modeled using appropriate model reduction techniques. The driver and receiver models use the composite current source (CCS) model.

[0030] When the load at the output includes interconnect resistance, an equivalent load capacitance is generally found so that the timing of the original design at the output matches the design with this equivalent load capacitance. This equivalent load capacitance is called the "effective capacitance" and depends on the input impedance of the driving cell and its load. Using the effective capacitance and the input transition time, the delay and transition time of the cell are looked up in a lookup table and calculated.

[0031] In the existing delay calculation technology based on the composite current source model, a more accurate method is to segment the driver output voltage interval and calculate the delay by interpolating at the segment voltage threshold. The effective capacitance corresponding to each interval is updated according to the delay calculation result, and the driver output voltage waveform and the receiver input voltage waveform are obtained after multiple iterations and convergence.

[0032] When calculating the effective capacitance, the prior art only performs a simple segmentation on the driver output voltage interval, and divides the intervals into three sections using the commonly used delay voltage threshold, conversion minimum voltage threshold, and conversion maximum voltage threshold. However, when using a composite current source model, it is necessary to calculate the receiver input waveform through the driver output waveform, and after obtaining the receiver conversion time, update the pin capacitance through a lookup table. The driver output waveform obtained using simple segmentation is still different from the actual waveform, which leads to distortion of the calculated receiver input waveform, inaccurate pin capacitance obtained from the lookup table, and inaccurate delay results obtained after the final iterative convergence. When the supply voltage is reduced, the driver output waveform becomes more nonlinear, and the resulting error becomes more obvious.

[0033] In addition, when it comes to signal integrity analysis, a more complete and real waveform is needed to show the influence of coupling capacitance. The waveform obtained by simple segmentation cannot accurately represent the distortion of the driver output waveform, resulting in inaccurate analysis results.

[0034] Therefore, the present application proposes a delay calculation method, which uses transient analysis combined with a composite current source model (driver model and receiver model) to determine the corresponding driver output voltage waveform, that is, the corresponding receiver input voltage waveform, and then performs analysis and accurate calculation of the delay, which can effectively improve the accuracy of the delay calculation results.

[0035] See also Figure 1 , Figure 1 is a flow chart of an embodiment of the delay calculation method in the present application; it should be noted that if there is a substantial result, the method of the present application is not based on Figure 1 The process sequence shown is limited.

[0036] like Figure 1 As shown, the delay calculation method in this application includes the following steps:

[0037] S10, constructing a reduced-order model of the interconnection line corresponding to the driver model and the receiver model, wherein the reduced-order model is set with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model.

[0038] Among them, the transfer function is the frequency domain matrix transfer function obtained after Laplace transform of the circuit equation with the driver output voltage and the receiver input voltage as input and output; the impedance function is the transfer function obtained after Laplace transform of the circuit equation with the driver output current and the driver output voltage as input and output, also known as the impedance function; the reduced-order model is the correlation model of the interconnection line established based on the parasitic parameter information corresponding to the driver model and the receiver model; the driver model provides a current curve that changes with time, and the receiver model provides an input capacitance with a delay threshold as the boundary.

[0039] Specifically, a driver model and a receiver model of the composite current source model are determined, and a reduced-order model of the interconnection line is established according to parasitic parameter information corresponding to the preset driver model and receiver model.

[0040] S20 , using a preset step size and impedance function, determining a driver output voltage waveform corresponding to the driver model.

[0041] The preset step size is the step size added to the current time during the transient analysis process.

[0042] Specifically, the starting time is determined using the starting capacitor to obtain the starting point of the driver output voltage waveform, as well as the point position of the driver output voltage waveform corresponding to the current voltage and the current current corresponding to the current time; then a preset step size is added for analysis, and combined with the impedance function, the point position of the driver output voltage waveform corresponding to the increase of the preset step size is determined, and then the driver output voltage waveform corresponding to the driver model is determined.

[0043] S30, taking the driver output voltage waveform as input, using a preset delay voltage threshold and a transfer function, determining a receiver input voltage waveform corresponding to the receiver model.

[0044] The preset delay voltage threshold is provided by the receiver model.

[0045] Specifically, the driver output voltage waveform determined in the previous step is used as input, and the receiver input voltage waveform is solved by the transfer function through the recursive convolution method, wherein the switching point of the transfer function is used as the preset delay voltage threshold. Then the time value of each point of the receiver input voltage waveform corresponds to the point of the driver output waveform one by one, and then the complete receiver input voltage waveform can be determined.

[0046] S40, using the driver output voltage waveform and the receiver input voltage waveform to determine the input conversion time corresponding to the receiver model, and then determine the delay calculation result.

[0047] The input conversion time corresponding to the receiver model is determined according to the delay voltage threshold and the conversion voltage threshold.

[0048] Specifically, after determining the driver output voltage waveform and the receiver input voltage waveform, the delay thresholds provided by the receiver model, such as the delay voltage threshold and the conversion voltage threshold, can be used to determine the input conversion time corresponding to the receiver model. The delay calculation result can then be determined based on the changes in the input conversion time between the previous iteration and the current iteration.

[0049] In this embodiment, transient analysis is combined with a composite current source model (driver model and receiver model) to determine the corresponding driver output voltage waveform, that is, the corresponding receiver input voltage waveform, and then perform analysis and accurate calculation of delay, which can effectively improve the accuracy of the delay calculation results.

[0050] In some embodiments, before building the reduced-order model, the process further includes reading the timing information provided by the first file and the parasitic parameter information provided by the second file, that is, the interconnection line information.

[0051] Then step S10 may further include the following steps:

[0052] Read the preset first file and second file.

[0053] Among them, the preset first file is a cell library file, which provides a driver model and a receiver model of a composite current source model. The driver model provides a current curve that changes with time, and the receiver model provides multiple input capacitors separated by a delay voltage threshold, such as a first input capacitor 1 and a second input capacitor 2; the preset second file is a parasitic parameter file.

[0054] Specifically, various files required for static timing analysis are read in, including a cell library file containing cell timing information created using a timing library format, and a parasitic parameter file containing interconnect parasitic parameter information described using a standard parasitic exchange format.

[0055] Furthermore, a third file and a fourth file may also be read in, the third file being a netlist file describing circuit functions written in a hardware description language, and the fourth file being a design constraint file providing timing constraint information.

[0056] The driver model and the receiver model are determined according to the timing information provided by the preset first file.

[0057] Among them, because the cell library file as the first file includes timing information, such as cell timing information, the driver model and the receiver model of the composite current source model can be determined according to the cell timing information included in the cell library file.

[0058] See also Figure 2 , Figure 2 It is a schematic diagram of the structure of the model in this application.

[0059] like Figure 2 As shown, the driver model and the receiver model of the composite current source model are connected to the reduced-order model respectively.

[0060] A reduced-order model of the interconnection line is established according to the parasitic parameter information, the driver model and the receiver model provided by the preset second file.

[0061] The parasitic parameter information provided by the second file is information such as resistance and capacitance corresponding to the interconnection line provided by the parasitic parameter file.

[0062] Then, an interconnect line reduction model is established based on the driver model and the receiver model, as well as the parasitic parameter information provided by the parasitic parameter file.

[0063] In some embodiments, establishing a reduced-order model of an interconnect line may further include the following steps.

[0064] According to the interconnection line information provided by the preset second file, that is, the parasitic parameter information, including the resistance and capacitance of the interconnection line, etc., a first circuit equation and a second circuit equation corresponding to the driver output current and the driver output voltage are established;

[0065] The first circuit equation and the second circuit equation may be established using a modified nodal analysis (MNA).

[0066] Specifically, using the resistance and capacitance information of the interconnection lines provided in the parasitic parameter file, such as the driver output current and the driver output voltage, the corresponding first circuit equation and the second circuit equation are established through the improved node method.

[0067] The first circuit equation is:

[0068]

[0069] The second circuit equation is:

[0070] u drv (t) = L T x.

[0071] Among them, i drv is the driver output current; u drv is the driver output voltage; G and C are n×n conductance and energy storage element matrices, x is the n-dimensional MNA variable vector, i drv (t) is the input excitation vector, B is n×N i Connection matrix, L is n×N o The detection matrix, u drv (t) is N o dimensional output vector.

[0072] And establish the third circuit equation and the fourth circuit equation corresponding to the driver output voltage and the receiver input voltage.

[0073] Specifically, using the resistance and capacitance information of the interconnection lines provided in the parasitic parameter file, such as the driver output voltage and the receiver input voltage, the corresponding third circuit equation and fourth circuit equation are established through the improved node method.

[0074] The third circuit equation is:

[0075]

[0076] The fourth circuit equation is:

[0077] u rec (t) = L T x.

[0078] Among them, u rec is the receiver input voltage, u drv (t) is the input excitation vector, u rec (t) is N o dimensional output vector.

[0079] An impedance function is determined by performing Laplace transformation using the first circuit equation and the second circuit equation; and a transfer function is determined by performing Laplace transformation using the third circuit equation and the fourth circuit equation.

[0080] Among them, the third circuit equation and the fourth circuit equation, which take the driver output voltage and the receiver input voltage as input and output, are Laplace transformed to obtain the transfer function corresponding to the frequency domain matrix.

[0081] The transfer function is:

[0082] H(s)=L T (G+sC) -1 B.

[0083] Among them, s is the independent variable.

[0084] By performing Laplace transform on the first circuit equation and the second circuit equation with the driver output current and the driver output voltage as input and output, the corresponding transfer function can also be obtained. Here, the transfer function corresponding to the first circuit equation and the second circuit equation is used as the impedance function.

[0085] That is, the impedance function is:

[0086] Z(s)=L T (G+sC) -1 B.

[0087] Among them, s is the independent variable.

[0088] Then, the transfer function and impedance function are used to form a reduced-order model of the interconnect.

[0089] In some embodiments, it is also necessary to find the zero-pole form of each term in the transfer function.

[0090] Specifically, the block moment of the transfer matrix can be obtained through iterative algorithms and projection methods, specifically Arnoldi method, projection method combined with Krylov subspace, and then the zero-pole form of each term of the matrix transfer function can be determined through moment matching.

[0091] The calculation formula for the zero-pole form is as follows:

[0092]

[0093] Among them, q is the order of the reduced-order model, k m and p m are the zeros and poles of the impedance function respectively.

[0094] The time domain output response corresponding to a given input can be obtained through transfer function and inverse Laplace transform.

[0095] Then, when using the composite current source receiver model, the impedance function corresponding to the circuit equation with the driver output current and the driver output voltage as input and output can be obtained. In some embodiments, the impedance function may include a first impedance function z1(t) and a second impedance function z2(t) for subsequent switching; the transfer function corresponding to the circuit equation with the driver output voltage and the receiver input voltage as input and output can also be obtained. In some embodiments, the transfer function may include a first transfer function h1(t) and a second transfer function h2(t) for subsequent switching; wherein the first impedance function z1(t) and the first transfer function h1(t) correspond to the first input capacitor 1, and the second impedance function z2(t) and the second transfer function h2(t) correspond to the second input capacitor 2.

[0096] Next, step 20 is performed to determine the driver output voltage waveform corresponding to the driver model using the preset step size and impedance function.

[0097] Specifically, an embodiment of step S20 may include the following steps:

[0098] The current curve and the corresponding voltage curve corresponding to each load are determined by using the preset output load interval, and then the current curve set and the voltage curve set of the driver output are established.

[0099] Among them, the output load area corresponding to the preset output load interval driver model, because each load has a corresponding current curve, and the voltage curve corresponding to the current curve of each load can be calculated, therefore, the current curve set and voltage curve set of the driver output can be established.

[0100] Specifically, a preset output load interval is obtained, and then the current curve corresponding to each load segmentation point is determined based on the preset output load interval, and then the corresponding voltage curve is calculated, and then the current curves corresponding to all load segmentation points are used to establish a driver output current curve set, and the voltage curves corresponding to all load segmentation points are used to establish a driver output voltage curve set.

[0101] In some embodiments, the preset output load range can be provided by the unit library file as the first file; in addition, the fourth file, i.e., the design constraint file, can be used to give the driver input conversion time, combined with the driver input conversion time and the output load range, to find out the current curve corresponding to each load segment point and calculate the corresponding voltage curve.

[0102] Next, the interpolation coefficient and the corresponding start time are determined according to the preset start capacitance, and the start point of the output current waveform of the corresponding current curve set and the start point of the output voltage waveform of the voltage curve set are saved.

[0103] Among them, the starting capacitance can be the minimum capacitance value in the output load interval; the endpoints of the output load interval include the first endpoint C1 and the second endpoint C2, and the initial time of the current curve corresponding to the first endpoint C1 and the second endpoint C2 can include the first initial time 1 and the second initial time 2.

[0104] Specifically, the minimum capacitance within the output load interval is obtained as the starting capacitance, and the first endpoint C1 and the second endpoint C2 of the output load interval are obtained, corresponding to the first initial time 1 and the second initial time 2 respectively, and then the interpolation coefficient is determined based on the starting capacitance, the first endpoint C1 and the second endpoint C2, for example, the interpolation coefficient is determined by the ratio of a first ratio of the starting capacitance to the first endpoint to a second ratio of the second endpoint to the first endpoint.

[0105] The interpolation coefficients are calculated as follows:

[0106] k=(C init -C1) / (C2-C1).

[0107] Among them, C init is the starting capacitance and k is the interpolation coefficient.

[0108] In some embodiments, the starting voltage may be updated by calculating the effective capacitance.

[0109] Then, the time is interpolated and the starting time corresponding to the starting capacitance is determined by the first initial time, the second initial time and the interpolation coefficient; for example, the first product is determined by the difference between the second initial time and the first initial time and the product of the interpolation coefficient, and then the starting time is determined by the sum of the first product and the first initial time.

[0110] The start time is calculated as follows:

[0111] t init =t c1 +k(t c2 -t c1 ).

[0112] Among them, t init is the start time.

[0113] In some embodiments, the starting voltage is 0 or vdd, and the starting current is 0, thereby preserving the starting point of the output voltage waveform and the starting point of the output current waveform.

[0114] Furthermore, the current voltage is determined using the preset voltage change value and the starting voltage, and the current time and the corresponding voltage change rate are determined using the current voltage and the interpolation coefficient, and the current current is determined based on the current time.

[0115] The preset voltage change value is a selected smaller voltage change value.

[0116] Specifically, a smaller voltage change value is selected, and then the current voltage can be obtained according to the starting voltage and the voltage change value; then the first voltage curve and the second voltage curve corresponding to the first end point and the second end point of the output load interval are used to find out the first time corresponding to the current voltage in the first voltage curve, and find out the second time corresponding to the current voltage in the second voltage curve, and then the current time after the voltage change is obtained by interpolation calculation; and then the starting step length is determined by the difference between the starting time and the current time, and the voltage change rate is determined. In addition, the first current current and the second current current in the first current curve and the second current curve corresponding to the first end point and the second end point of the output load interval are respectively found at the first time and the second time, and then the first time difference between the current time and the first time and the time difference ratio between the second time and the second time difference of the first time are determined, and the current difference between the second current and the first current is determined, and the current current is determined according to the product of the time difference ratio and the current difference, and the first current, and the current voltage and the current current are saved in the corresponding output voltage waveform and output current waveform.

[0117] For example, a smaller voltage change value is selected, and then the current voltage v can be obtained based on the starting voltage and the voltage change value. out , and then find the current voltage v through the first terminal C1 of the output load interval out The first time 1 corresponding to the output load interval and the second terminal C2 to find the current voltage v out The corresponding second time 2 is then used to calculate the difference to obtain the current time after the voltage change.

[0118] The current time is calculated as follows:

[0119] t now =t1+k(t2-t1).

[0120] Among them, t now is the current time.

[0121] The starting step length is calculated as follows:

[0122] t step =t now -t init .

[0123] Among them, t step is the starting step length, t init is the start time.

[0124] In addition, the voltage change rate is / , where is the time change value.

[0125] And the first current 1 and the second current 2 corresponding to the first time and the second time are respectively found through the first current curve corresponding to the first terminal of the output load and the second current curve corresponding to the second terminal.

[0126] The current is calculated as follows:

[0127]

[0128] Among them, i out is the current.

[0129] Then save the current voltage point (t now ,v out ) and the current point (t now ,i out ) into the output voltage waveform and output current waveform.

[0130] Next, a preset step is added to the current time, and the output voltage is determined by using the output current waveform and the first impedance function or the second impedance function in a recursive convolution manner, thereby determining the driver output voltage waveform corresponding to the driver model.

[0131] The impedance function includes a first impedance function and a second impedance function, one of which may be used first and then switched according to a change in the output voltage.

[0132] Specifically, at the current time t now On the basis of, add a preset step length, that is, add a starting step length t step, and then through the output current waveform and the first impedance function z1(t) or the second impedance function z1(t) obtained above, the first impedance function can be used initially to solve the output voltage using a recursive convolution method.

[0133] In some embodiments, the first zero pole and the second zero pole of the impedance function can also be calculated by a calculation formula in the form of zero poles, and the output voltage of the previous time step can be obtained; then based on the preset step size, the first zero pole, the second zero pole, the current current corresponding to the output current waveform and the order of the reduced-order model, the output voltage is determined by recursive convolution.

[0134] The output voltage calculation process is as follows:

[0135]

[0136] Among them, v out is the output voltage, k m is the first zero pole of the impedance function, p m is the second zero pole of the impedance function; t step is the preset step length, which can also be the starting step length; i out is the current; q is the order of the reduced-order model; v prev is the output voltage at the previous time step.

[0137] Furthermore, the magnitude relationship between the current time and the first time and the second time corresponding to the current voltage can be determined, and then based on the magnitude relationship, the first endpoint and the second endpoint of the output load interval are adjusted so that the current time is between the first time and the second time, and then the corresponding current current value is determined using the adjusted current time.

[0138] For example, the current voltage v is found by respectively searching the first voltage curve corresponding to the first terminal C1 of the output load and the second voltage curve corresponding to the second terminal C2. out The corresponding first time 1 and second time 2, and then determine the current time t now The relationship between the first time 1 and the second time 2; if the current time t now If the current time is between the first time 1 and the second time 2, the current current can be determined using the current time; if the current time t now If the current time t is outside the first time 1 and the second time 2, it is necessary to adjust the two endpoints of the output load interval, that is, adjust the first endpoint C1 and the second endpoint C2, so that the adjusted current time t now is between the first time 1 and the second time 2, and then uses the adjusted current time t now Determine the current flow.

[0139] Furthermore, the preset step size of the transient analysis can also be adjusted.

[0140] Specifically, numerical detection is performed on the current voltage, current current and voltage change rate to determine whether each value is normal; when the value is normal, the difference between the voltage change rate corresponding to the current step size and the voltage change rate corresponding to the previous step size is calculated; the local truncation error is calculated using the change rate difference, and then the preset step size is adjusted through the first relationship between the local truncation error and the preset error tolerance, and the size of the voltage change rate; if a numerical abnormality occurs, the solution of the current step size is marked invalid, and a rollback process is performed.

[0141] For example, check the current voltage v out , whether the current current and voltage change rate / values ​​are normal, that is, whether they are within a reasonable range. The reasonable range can be set according to actual conditions.

[0142] When an abnormal value is detected, the preset step size is reduced, that is, the initial step size t is reduced. step The value of the step length is marked as invalid, and the current voltage v is retracted. out and the current current value; if the value is detected to be normal, the voltage change rate / corresponding to the current step length and the voltage change rate / corresponding to the previous step length are calculated, and then the change rate difference Δ / is used to calculate the local truncation error, and then the preset step length is adjusted through the first relationship between the local truncation error and the preset error tolerance, and the size of the voltage change rate / , that is, the initial step length t is adjusted. step , so that the current voltage v calculated after adjusting the initial step size out , the current current value is within a reasonable range.

[0143] Furthermore, the delayed voltage threshold can be used to judge the current voltage. If the current voltage passes the delayed voltage threshold, the first impedance function or the second impedance function is switched to the second impedance function or the first impedance function; otherwise, it is further judged whether the current voltage reaches the end voltage threshold, and when the current voltage reaches the end voltage threshold, the calculation process is ended.

[0144] Specifically, when the current voltage of the previous step is less than the delay voltage threshold and the current voltage of the current step is greater than the delay voltage threshold, the first impedance function or the second impedance function is switched to the second impedance function or the first impedance function; that is, the corresponding reduced-order model is switched to the corresponding reduced-order model; if the delay voltage threshold is outside the current voltage of the previous step and the current voltage of the current step, the current voltage is judged using the end voltage threshold, wherein the delay voltage threshold and the end voltage threshold are in a multiple relationship; when the current voltage is less than the end voltage threshold point, the output voltage is solved again.

[0145] For example, if the delay voltage threshold is 0.5vdd, then the current voltage v of the previous step is determined. out When the current voltage of the current step is less than 0.5vdd and is greater than or equal to 0.5vdd, the first impedance function z1(t) is switched to the second impedance function z2(t). If the current voltage change does not pass the delay voltage threshold, it is determined whether the current voltage reaches the end voltage threshold vdd. If it reaches the end voltage threshold vdd, the calculation process is terminated. If the current voltage does not reach the end voltage threshold vdd, the current voltage v is recalculated. out calculate.

[0146] In order to more clearly illustrate the operation process of step S20, an explanation is given below with reference to the accompanying drawings.

[0147] See also Figure 3 , Figure 3 This is a flowchart of an embodiment of step S20 in the present application.

[0148] like Figure 3 As shown, step S20 may include:

[0149] S31. Establish an output current curve set and a voltage curve set.

[0150] That is, according to the output load range, the current curve corresponding to each load segment point is found, and the corresponding voltage curve is calculated, so as to establish a driver output current curve set and a driver output voltage curve set.

[0151] S32, transient analysis initialization.

[0152] That is, the interpolation coefficient is calculated through the starting capacitance, and the starting time is determined, and the starting point corresponding to the output voltage waveform and the output current waveform is saved with the corresponding starting voltage and starting current.

[0153] S33, transient analysis starts.

[0154] That is, a voltage change value is selected, and the current voltage is obtained according to the starting voltage and the voltage change value. Then, the first time and the second time corresponding to the current voltage are determined through the two endpoints of the load interval, and then interpolation calculation is performed to obtain the current time, as well as the corresponding starting step size and voltage change rate; and then, the first current and the second current corresponding to the first time and the second time are determined respectively through the two endpoints of the output load interval, thereby determining the current current.

[0155] S34, single-step solution of transient analysis.

[0156] That is, the current time is increased by a preset step length, that is, the starting step length is increased, and the output voltage is solved through the output current waveform and impedance function.

[0157] S35. Adjust the transient analysis step size.

[0158] That is, check whether the current voltage, current current, and voltage change rate are within a reasonable range. If there is no abnormality in the values, adjust the preset step size.

[0159] S36: Determine whether rollback is required.

[0160] If the value in step S35 is abnormal, a rollback process is performed and the process returns to step S34 for single-step solution.

[0161] S37. Save the single-step solution result.

[0162] That is, save the current voltage point and the current current point to the output voltage waveform and the output current waveform.

[0163] S38: Determine whether the critical threshold point has been reached.

[0164] That is, determine whether the current voltage change reaches the delayed voltage threshold, that is, determine whether the current voltage passes the delayed voltage threshold. If it passes, execute step S39; otherwise, determine whether it reaches the end voltage threshold. If it reaches, end; otherwise, return to step S34 for single-step solution.

[0165] S39, switch the reduced-order model.

[0166] That is, when the current voltage changes through the delayed voltage threshold, the reduced-order model is switched from the reduced-order model corresponding to the first impedance function to the reduced-order model corresponding to the second impedance function.

[0167] Next, the operation of step S40 is performed to determine the input conversion time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and then determine the delay calculation result.

[0168] See also Figure 4 , Figure 4 Schematic diagram of the driver output voltage waveform in this application.

[0169] like Figure 4 As shown, each time the driver output voltage waveform is solved, a corresponding waveform graph is obtained. Taking four solutions as an example, the time range is 0ns-1ns, the voltage range is 0vdd-1vdd, the waveform corresponding to the first solution is iter1, the waveform corresponding to the second solution is iter2, the waveform corresponding to the third solution is iter3, and the waveform corresponding to the fourth solution is iter4.

[0170] Next, the operation process of step S30 is executed, taking the driver output voltage waveform as input, and using the preset delay voltage threshold and transfer function to determine the receiver input voltage waveform corresponding to the receiver model.

[0171] Step S30 may include the following operations:

[0172] The driver output voltage waveform is used as input to obtain the third zero pole and the fourth zero pole of the first transfer function or the second transfer function.

[0173] Among them, because the driver output voltage waveform is used as input, the first transfer function and the second transfer function are used to solve the receiver input voltage waveform through recursive convolution, and the switching point of the first transfer function and the second transfer function is the delay voltage threshold 0.5vdd. At this time, the time value of each point of the receiver input voltage waveform corresponds one-to-one to the point of the driver output voltage waveform. Therefore, the third zero pole corresponds to the first zero pole, and the fourth zero pole corresponds to the second zero pole.

[0174] Based on the preset step size, the third zero pole, the fourth zero pole, the point information corresponding to the driver output voltage waveform and the order of the reduced-order model, the receiver input voltage waveform is determined by recursive convolution.

[0175] Specifically, an iterative method is used to solve the potential information corresponding to the delay voltage threshold and the conversion voltage threshold to obtain a complete receiver input voltage waveform.

[0176] The calculation process can adopt the calculation process of output voltage, as follows:

[0177]

[0178] Among them, v out is the output voltage, k m is the first zero pole of the impedance function, that is, the third zero pole of the transfer function; p m is the second zero pole of the impedance function, that is, the fourth zero pole of the transfer function; t step is the preset step length, which can also be the starting step length; i out is the current; q is the order of the reduced-order model; v prev is the output voltage at the previous time step.

[0179] Step S40 may include the following operations:

[0180] A delay voltage threshold, a first conversion voltage threshold and a second conversion voltage threshold are obtained, and a reference time corresponding to a current curve in a current curve set is obtained.

[0181] Among them, when solving the driver output voltage waveform and the receiver input voltage waveform, the delay voltage threshold and the conversion voltage threshold can be obtained at the same time, and the conversion voltage threshold includes a first conversion voltage threshold and a second conversion voltage threshold; the reference time is the reference time corresponding to the current curve of the current curve concentration of the composite current source model.

[0182] In some embodiments, the delay voltage threshold may be 0.5 vdd, the first conversion voltage threshold may be 0.3 vdd, and the second conversion voltage threshold may be 0.7 vdd.

[0183] The driver output voltage waveform and the third time corresponding to the delay voltage threshold are used to determine the unit delay based on the third time and the reference time.

[0184] The third time is the time when the delay voltage threshold corresponds to the driver output voltage waveform.

[0185] Specifically, the delay voltage threshold is used to search for a corresponding time in the driver output voltage waveform to serve as the third time, and then the difference between the third time and the reference time is used as the unit delay.

[0186] The delay is calculated as follows:

[0187] =05-.

[0188] Among them, 05 is the third time, is the reference time, and is the unit delay.

[0189] Next, the fourth time is determined using the driver output voltage waveform and the first conversion voltage threshold, and the fifth time is determined using the driver output voltage waveform and the second conversion voltage threshold, and then the unit output conversion time is determined using the fourth time and the fifth time.

[0190] The fourth time is the time when the first conversion voltage threshold corresponds to the driver output voltage waveform, and the fifth time is the time when the second conversion voltage threshold corresponds to the driver output voltage waveform.

[0191] Specifically, the first conversion voltage threshold is used to find the corresponding time in the driver output voltage waveform as the fourth time, and the second conversion voltage threshold is used to find the corresponding time in the driver output voltage waveform as the fifth time, and then the difference between the fourth time and the fifth time is used as the unit output conversion time.

[0192] The unit output transition time is calculated as follows:

[0193] -=07-03.

[0194] Among them, 07 is the fourth time, 03 is the fifth time, and - is the unit output conversion time.

[0195] Next, the interconnection delay is determined using the third time, a sixth time corresponding to the receiver input voltage waveform and the delay voltage threshold.

[0196] The sixth time is the time when the delay voltage threshold corresponds to the receiver input voltage waveform.

[0197] Specifically, the delay voltage threshold is used to find the corresponding time in the receiver input voltage waveform to serve as the sixth time, and then the difference between the third time and the sixth time is used as the interconnection line delay.

[0198] The interconnect delay is calculated as follows:

[0199] =05-05.

[0200] Among them, 05 is the sixth time, which is the interconnection delay.

[0201] Next, the lower unit input conversion time is determined using the seventh time corresponding to the receiver input voltage waveform and the second conversion voltage threshold and the eighth time corresponding to the receiver input voltage waveform and the first conversion voltage threshold.

[0202] The seventh time is the time corresponding to the second conversion voltage threshold in the receiver input voltage waveform, and the eighth time is the time corresponding to the first conversion voltage threshold in the receiver input voltage waveform.

[0203] Specifically, the time corresponding to the second conversion voltage threshold in the receiver input voltage waveform is used as the seventh time, and the time corresponding to the first conversion voltage threshold in the receiver input voltage waveform is used as the eighth time, and the difference between the seventh time and the eighth time is used as the input conversion time of the lower-level unit.

[0204] The lower level unit input conversion time is calculated as follows:

[0205] -=07-03.

[0206] Among them, 07 is the seventh time, 03 is the eighth time, and - is the input conversion time of the lower-level unit.

[0207] Furthermore, the absolute change and relative change of the input conversion time corresponding to the current iteration and the previous iteration can be compared; and then, based on the absolute change and relative change, it is determined whether the output conversion time of the lower-level unit converges; if it converges, the delay calculation is terminated; if it does not converge, the current input conversion time is used to update the preset output load range, and then the driver output waveform is recalculated.

[0208] Specifically, when the absolute change is less than the first change threshold and / or the relative change is less than the second change threshold, it is considered to be converged and the delay calculation is terminated.

[0209] When the absolute change is greater than the first change threshold and / or the relative change is greater than the second change threshold, it is considered that there is no convergence, and the preset output load interval is updated, and then the driver output waveform is recalculated; that is, according to the updated use of the current input conversion time, the receiver load value is searched in the receiver model in the composite current source model, such as the first receiver load value 1 and the second receiver load value 2, and then the reduced-order model of the interconnection line is updated; and the effective capacitance corresponding to the voltage change value of the driver output voltage is calculated in combination with the Pi model as the starting capacitance of the next iteration.

[0210] In this embodiment, transient analysis is combined with a composite current source model (driver model and receiver model) to determine the corresponding driver output voltage waveform, that is, the corresponding receiver input voltage waveform, and then perform analysis and accurate calculation of delay, which can effectively improve the accuracy of the delay calculation results.

[0211] Furthermore, the present application also provides an electronic device.

[0212] See also Figure 5 , Figure 5 It is a structural diagram of an embodiment of an electronic device in the present application.

[0213] like Figure 5 As shown, the electronic device 500 includes a memory 510 and a processor 520 coupled to the memory. The memory stores at least one computer program. When the at least one computer program is loaded and executed by the processor, it is used to implement the aforementioned delay calculation method.

[0214] Furthermore, the present application also provides a storage medium.

[0215] See also Figure 6 , Figure 6 It is a structural diagram of an embodiment of a storage medium in the present application.

[0216] like Figure 6 As shown, the storage medium 600 has at least one program 610, which, when loaded and executed, is used to implement the aforementioned delay calculation method; wherein the storage medium is a computer-readable storage medium.

[0217] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0218] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0219] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0220] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0221] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A delay calculation method, characterized in that: include: Constructing a reduced-order model of the interconnect corresponding to the driver model and the receiver model, wherein the reduced-order model is set with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; Determine the driver output voltage waveform corresponding to the driver model by using the preset step size and the impedance function; Taking the driver output voltage waveform as input, using a preset delay voltage threshold and the transfer function, determining a receiver input voltage waveform corresponding to the receiver model; The input conversion time corresponding to the receiver model is determined by using the driver output voltage waveform and the receiver input voltage waveform, thereby determining the delay calculation result.

2. The method according to claim 1, characterized in that The step of constructing a reduced-order model of an interconnect corresponding to a driver model and a receiver model includes: Determine the driver model and the receiver model according to the timing information provided by the preset first file; The reduced-order model of the interconnection line is established according to the parasitic parameter information provided by the preset second file, the driver model and the receiver model.

3. The method according to claim 2, characterized in that The step of establishing the reduced-order model of the interconnect line according to the parasitic parameter information provided by the preset second file, the driver model and the receiver model comprises: According to the interconnection line information provided by the preset second file, a first circuit equation and a second circuit equation corresponding to the driver output current and the driver output voltage are established; and a third circuit equation and a fourth circuit equation corresponding to the driver output voltage and the receiver input voltage are established; Performing Laplace transformation using the first circuit equation and the second circuit equation to determine the impedance function; and performing Laplace transformation using the third circuit equation and the fourth circuit equation to determine the transfer function; The reduced-order model is composed of the transfer function and the impedance function.

4. The method according to claim 1, characterized in that: The impedance function includes a first impedance function and a second impedance function; The method of determining a driver output voltage waveform corresponding to the driver model by using the preset step size and the impedance function includes: Using the preset output load interval, determine the current curve and the corresponding voltage curve corresponding to each load, and then establish the current curve set and the voltage curve set of the driver output; Determine an interpolation coefficient and a corresponding start time according to a preset start capacitance, and save a corresponding start point of an output current waveform of the current curve set and a start point of an output voltage waveform of the voltage curve set; Determine the current voltage using the preset voltage change value and the starting voltage, and determine the current time and the corresponding voltage change rate using the current voltage and the interpolation coefficient, and determine the current current according to the current time; A preset step size is added to the current time, and the output voltage is determined by using the output current waveform and the first impedance function or the second impedance function in a recursive convolution manner, thereby determining the driver output voltage waveform corresponding to the driver model.

5. The method according to claim 4, characterized in that The determining the current current according to the current time includes: Determine a first time and a second time corresponding to the current voltage by using a first voltage curve and a second voltage curve corresponding to two endpoints of the output load interval, and determine a first current corresponding to the first time and a second current corresponding to the second time by using a first current curve and a second current curve corresponding to two endpoints of the output load interval; Then, determine the first time difference between the current time and the first time, the time difference ratio between the second time and the second time difference between the first time, and determine the current difference between the second current and the first current, and determine the current current based on the product of the time difference ratio and the current difference and the first current, and save the current voltage and the current current to the corresponding output voltage waveform and output current waveform.

6. The method according to claim 4, characterized in that The method of determining the output voltage by using a recursive convolution method includes: Obtaining a first zero pole and a second zero pole of the first impedance function or the second impedance function, and obtaining an output voltage of the previous time step; The output voltage is determined by recursive convolution based on the preset step size, the first zero pole, the second zero pole, the current current corresponding to the output current waveform and the order of the reduced-order model.

7. The method according to claim 5, characterized in that Also includes: Determine the magnitude relationship between the current time and the first time and the second time corresponding to the current voltage; If the current time is between the first time and the second time, the current current is determined using the current time; If the current time is outside the first time and the second time, the two end points of the output load interval are adjusted so that the adjusted current time is between the first time and the second time, and the current current is determined using the adjusted current time.

8. The method according to claim 5, characterized in that Also includes: Performing numerical detection on the current voltage, current current and voltage change rate; When the value is normal, calculate the difference between the voltage change rate corresponding to the current step length and the voltage change rate corresponding to the previous step length; Calculating a local truncation error using the change rate difference, and then adjusting a preset step size according to a first relationship between the local truncation error and a preset error tolerance and the magnitude of the voltage change rate; If a numerical anomaly occurs, the current step size solution is marked as invalid and a rollback is performed.

9. The method according to claim 5, characterized in that Also includes: Use the delayed voltage threshold to judge the current voltage; When the current voltage of the previous step length is less than the delay voltage threshold, and the current voltage of the current step length is greater than the delay voltage threshold, switching the first impedance function or the second impedance function to the second impedance function or the first impedance function; If the delay voltage threshold is outside the current voltage of the previous step and the current voltage of the current step, the end voltage threshold is used to judge the current voltage, wherein the delay voltage threshold and the end voltage threshold are in a multiple relationship; When the current voltage is less than the end voltage threshold point, the output voltage is solved again.

10. The method according to claim 1, characterized in that The transfer function includes a first transfer function and a second transfer function; The method of taking the driver output voltage waveform as input and using a preset delay voltage threshold and the transfer function to determine a receiver input voltage waveform corresponding to the receiver model includes: Using the driver output voltage waveform as input, obtaining the third zero pole and the fourth zero pole of the first transfer function or the second transfer function; Based on the preset step size, the third zero pole, the fourth zero pole, the point information corresponding to the driver output voltage waveform and the order of the reduced-order model, the receiver input voltage waveform is determined by recursive convolution.

11. The method according to claim 1, characterized in that: The step of determining the input conversion time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and then determining the delay calculation result, comprises: Acquire a delay voltage threshold, a first conversion voltage threshold, and a second conversion voltage threshold, and acquire a reference time corresponding to a current curve in a current curve set; Using the driver output voltage waveform and a third time corresponding to the delay voltage threshold, and then determining the unit delay with the third time and the reference time; Determine a fourth time using the driver output voltage waveform and the first switching voltage threshold, and determine a fifth time using the driver output voltage waveform and the second switching voltage threshold, and then determine a unit output switching time using the fourth time and the fifth time; determining an interconnection delay using the third time, a sixth time corresponding to the receiver input voltage waveform and the delay threshold voltage; The input conversion time of the lower unit corresponding to the receiver model is determined using the seventh time corresponding to the receiver input voltage waveform and the second conversion voltage threshold and the eighth time corresponding to the receiver input voltage waveform and the first conversion voltage threshold.

12. The method according to claim 11, characterized in that Also includes: Compare the absolute and relative changes in input conversion time corresponding to the current iteration and the previous iteration; Then, whether the output conversion time converges is determined based on the absolute change and relative change; If it does not converge, the preset output load interval is updated using the current input conversion time, and the driver output waveform is then recalculated.

13. An electronic device, characterized in that: The electronic device includes a memory and a processor coupled to the memory, the memory stores at least one computer program, and when the at least one computer program is loaded and executed by the processor, it is used to implement the method according to any one of claims 1 to 12.

14. A storage medium, characterized in that: The storage medium has at least one program, and when the at least one program is loaded and executed by the processor, it is used to implement the method according to any one of claims 1 to 12.

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