Integrated circuit and forming method thereof

Abstract

The embodiment of the invention discloses an integrated circuit and a forming method thereof. An integrated circuit includes a first cell region including a first set of transistors having a first size, a second cell region including a second set of transistors having a second size, and first and second sets of conductors. The first and second cell regions have a first height. The first and second sets of transistors include respective first or second active regions on a first level. The first set of conductors is on the first metal layer over the front side of the substrate and is coupled with the first or second set of transistors. A second set of conductors is on the second metal layer below the backside of the substrate and is coupled with the first set of transistors. The first and second sets of conductors are configured to provide a supply voltage or a reference supply voltage.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuits and methods of forming the same. Background Art

[0002] Recent trends in integrated circuit (IC) miniaturization have resulted in smaller devices that consume less power but provide more functionality at higher speeds. The miniaturization process has also led to tighter design and manufacturing specifications as well as reliability challenges. For example, as ICs become smaller and more complex, the operating voltages of these digital devices continue to decrease, impacting IC performance. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits while ensuring that the design and manufacturing specifications for the standard cell layout are met. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a first unit region, comprising at least a first group of transistors, the first unit region extending in a first direction and having a first height in a second direction different from the first direction, the first group of transistors comprising: a first active region extending along the first direction and located on a first level; a second unit region, comprising at least a second group of transistors, the second unit region extending in the first direction and having a first height in the second direction, the second group of transistors comprising: a second active region extending in the first direction, located on the first level, and separated from the first active region in the second direction; a first group of conductors extending in the first direction, located on a first metal layer above a front side of a substrate, overlapping with the first active region or the second active region, and coupled to at least the first group of transistors or the second group of transistors, the first group of conductors being configured to provide at least a power supply voltage or a reference power supply voltage; and a second group of conductors extending in the first direction, located on a second metal layer below a back side of the substrate, coupled to at least the first group of transistors, the second group of conductors being configured to provide at least a power supply voltage or a reference power supply voltage; wherein the first group of transistors has a first size, and the second group of transistors has a second size different from the first size.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a first group of transistors, located in a first region, the first region extending in a first direction and having a first height in a second direction different from the first direction, the first group of transistors comprising: a first active region extending in the first direction and located on a first level; a second group of transistors, located in a second region, the second region extending in the first direction and having a second height in the second direction, the second height being different from the first height, the second group of transistors comprising: a second active region extending in the first direction, located on the first level, and separated from the first active region in the second direction; a first group of conductors extending in the first direction and located On a first metal layer above the front side of the substrate, overlapping with the first active area and coupled to at least a first group of transistors, a first group of conductors is configured to provide at least a power supply voltage or a reference power supply voltage, each conductor in the first group of conductors is separated from each other by a first pitch in a second direction; and a second group of conductors extends in the first direction, is located on the first metal layer, and is coupled to at least a second group of transistors, the second group of conductors is configured to provide at least a power supply voltage or a reference power supply voltage, each conductor in the second group of conductors is separated from each other by a second pitch in the second direction, and the second pitch is different from the first pitch, wherein the first group of transistors has a first size, and the second group of transistors has a second size different from the first size.

[0005] According to another aspect of an embodiment of the present application, a method for forming an integrated circuit is provided, the method comprising: manufacturing a first group of transistors in a first row on a front side of a substrate, the first row extending in a first direction, the first group of transistors including at least a first transistor, and the first group of transistors having a first size; manufacturing a second group of transistors in a second row on the front side of the substrate, the second row extending in the first direction and being separated from the first row in a second direction different from the first direction, the second group of transistors including a second transistor, and the second group of transistors having a second size different from the first size; electrically coupling a first group of conductors on the front side of the substrate to at least the first group of transistors or the second group of transistors, wherein electrically coupling the first group of conductors on the front side of the substrate to at least the first group of transistors or the second group of transistors comprises:

[0006] Depositing a first conductive material on a first metal layer on the front side of a substrate to form a first group of conductors, the first group of conductors being electrically coupled to at least the first group of transistors or the second group of transistors; and electrically coupling a second group of conductors on the back side of the substrate to at least the first group of transistors, wherein electrically coupling the second group of conductors on the back side of the substrate to at least the first group of transistors includes: depositing a second conductive material on a second metal layer on the back side of the substrate to form a second group of conductors, the second group of conductors being electrically coupled to at least the first group of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A is a schematic diagram of a layout design according to some embodiments.

[0009] Figure 1B is a schematic diagram of a layout design according to some embodiments.

[0010] Figure 2A-2C are corresponding diagrams of corresponding portions of layout designs for corresponding integrated circuits according to some embodiments.

[0011] Figure 3A-3G is a diagram of an integrated circuit according to some embodiments.

[0012] Figure 4A-4B is a corresponding diagram of an integrated circuit according to some embodiments.

[0013] Figure 5A-Figure 5B is a corresponding diagram of an integrated circuit according to some embodiments.

[0014] Figure 6A-6B is a corresponding diagram of an integrated circuit according to some embodiments.

[0015] Figure 7A-7B is a corresponding diagram of an integrated circuit according to some embodiments.

[0016] Figure 8A-B is a corresponding diagram of an integrated circuit according to some embodiments.

[0017] Figure 9A-9B is a corresponding diagram of an integrated circuit according to some embodiments.

[0018] Figure 10A-10B is a corresponding diagram of an integrated circuit according to some embodiments.

[0019] Figure 11A-11B is a functional flow diagram of a corresponding method of manufacturing an IC device according to some embodiments.

[0020] Fig.12 is a flow chart of a method of manufacturing an integrated circuit according to some embodiments.

[0021] Fig.13 is a flow chart of a method of generating a layout design for an integrated circuit according to some embodiments.

[0022] Fig.14is a schematic diagram of a system for designing an IC layout and fabricating IC circuits according to some embodiments.

[0023] Fig.15 is a block diagram of an IC manufacturing system and its associated IC manufacturing flow according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0026] According to some embodiments, the integrated circuit includes a first unit region. In some embodiments, the first unit region extends in a first direction. In some embodiments, the first unit region has a first height in a second direction. In some embodiments, the second direction is different from the first direction.

[0027] In some embodiments, the first cell region includes at least a first group of transistors. In some embodiments, the first group of transistors includes a first active region extending along a first direction and located on a first level.

[0028] In some embodiments, the integrated circuit further comprises a second unit region. In some embodiments, the second unit region extends in the first direction. In some embodiments, the second unit region has a first height in the second direction.

[0029] In some embodiments, the second unit region includes at least a second group of transistors. In some embodiments, the second group of transistors includes a second active region extending in the first direction, located on the first level, and separated from the first active region in the second direction.

[0030] In some embodiments, the integrated circuit further comprises a first set of conductors. In some embodiments, the first set of conductors extends in a first direction, is located on a first metal layer, and overlaps the first active area or the second active area. In some embodiments, the first metal layer is located above the front side of the substrate. This is referred to as a "front side power rail or technology".

[0031] In some embodiments, the first set of conductors is coupled to the first set of transistors or the second set of transistors. In some embodiments, the first set of conductors is configured to provide at least a supply voltage or a reference supply voltage.

[0032] In some embodiments, the integrated circuit further comprises a second set of conductors. In some embodiments, the second set of conductors extend in the first direction and are located on a second metal layer. In some embodiments, the second metal layer is located below the back side of the substrate, referred to as a "back side power rail or technology".

[0033] In some embodiments, the second set of conductors is configured to provide at least a supply voltage or a reference supply voltage. In some embodiments, the second set of conductors is coupled to at least the first set of transistors.

[0034] In some embodiments, the first group of transistors has a first size. In some embodiments, the second group of transistors has a second size. In some embodiments, the second size is different from the first size.

[0035] In some embodiments, by including an integrated circuit having a front-side power rail and a back-side power rail, the first group of transistors and the second group of transistors have different sizes, thereby resulting in a more flexible integrated circuit and corresponding design.

[0036] Figure 1A is a schematic diagram of a layout design 100A according to some embodiments.

[0037] Figure 1B is a schematic diagram of a layout design 100B according to some embodiments.

[0038] Layout design 100A is a layout diagram of an integrated circuit, such as Figure 3A-3G Integrated circuit 300A, Figure 4A-4B Integrated circuit 400, Figure 5A-Figure 5B Integrated circuit 500, Figure 6A-6B IC 600 or Figure 7A-7B The layout design 100A may be used to manufacture an integrated circuit such as Figures 3A to 3GIntegrated circuit 300A, FIG. 4A to FIG. 4B Integrated circuit 400, FIG. 5A to FIG. 5B Integrated circuit 500, FIG. 6A to FIG. 6B IC 600 or FIG. 7A to FIG. 7B Integrated circuit 700.

[0039] The layout design 100B is a layout diagram of an integrated circuit, such as Figure 8A-B Integrated circuit 800, Figure 9A-9B IC 900 or Figure 10A-10B The layout design 100B may be used to manufacture an integrated circuit, such as Figure 8A-B Integrated circuit 800, Figure 9A-9B IC 900 or FIG. 10A to FIG. 10B 1000 of integrated circuits.

[0040] Layout design 100A or 100B includes standard cell layout designs 102a, 102b, 102c, 104a, and 104b. In some embodiments, layout design 100A or 100B includes Figure 1A Additional elements not shown.

[0041] Each standard cell layout design 102a, 102b, 102c, 104a, and 104b extends in at least a first direction X. Each standard cell layout design 102a, 102b, 102c, 104a, and 104b is separated from another standard cell layout design 102a, 102b, 102c, 104a, and 104b in a second direction Y. In some embodiments, the second direction Y is different from the first direction X.

[0042] The standard cell layout design 102a has a cell boundary 101a extending in a first direction X. In some embodiments, the standard cell layout structure 102a is adjacent to other standard cell layouts (not shown for ease of illustration) along the cell boundary 101a in the first direction.

[0043] The standard cell layout design 102a is adjacent to the standard cell layout structure 102b along the cell boundary 101b in the first direction X. The standard cell layout design 102b is adjacent to the standard cell layout structure 102c along the cell boundary 101c in the first direction X. The standard cell layout design 102c is adjacent to the standard cell layout structure 104a along the cell boundary 101d in the first direction X. The standard cell layout design 104a is adjacent to the standard cell layout structure 104b along the cell boundary 101e in the first direction X.

[0044] The standard cell layout design 104 b has a cell boundary 101 e extending in the first direction X. In some embodiments, the standard cell layout structure 104 b is adjacent to other standard cell layouts (not shown for ease of illustration) along the cell boundary 101 e in the first direction.

[0045] Other configurations or numbers of standard cell layout designs 102a, 102b, 102c, 104a, and 104b are within the scope of the present disclosure. For example, Figure 1A Layout design 100A includes one column (column 1) and five rows (rows 1-5) of cells (e.g., standard cell layout designs 102a, 102b, 102c, 104a, and 104b). Other numbers of rows and / or columns in layout design 100A are also within the scope of the present disclosure. For example, in some embodiments, layout design 100A includes at least one additional column of cells, similar to column 1, and adjacent to column 1. For example, in some embodiments, layout design 100A includes at least one additional row of cells, similar to row 2, adjacent to row 1 along cell boundary 101a. For example, in some embodiments, layout design 100A includes at least one additional row of cells, similar to row 4, adjacent to row 1 along cell boundary 101a. For example, in some embodiments, layout design 100A includes at least one additional row of cells, similar to row 4, adjacent to row 5 along corresponding cell boundary 101f. For example, in some embodiments, layout design 100A includes at least one additional row of cells, similar to row 1, adjacent to row 5 along corresponding cell boundary 101f. In some embodiments, the standard cell layout designs 102 a , 102 b , and 102 c alternate in the second direction Y with the standard cell layout structures 104 a and 104 b .

[0046] exist Figure 1A In the layout design 100A, each of the standard cell layout designs 102a, 102b, 102c, 104a, or 104b has a height H1 in the second direction Y.

[0047] At least one of the standard cell layout designs 102a, 102b, or 102c is the same as another. In some embodiments, at least one of the standard cell layout designs 102a, 102b, or 102c is a different layout design than another.

[0048] At least one of the standard cell layout designs 104a or 104b is the same as the other. In some embodiments, at least one of the standard cell layout designs 104a or 104b is a different layout design than the other.

[0049] In some embodiments, at least one of standard cell layout designs 102a, 102b, or 102c is the same layout structure as one of standard cell layout structures 104a or 104b. In some embodiments, at least one of standard cell layout designs 102a, 102b, or 102c is a different layout design than one of standard cell layout designs 104a or 104b.

[0050] In some embodiments, standard cell layout designs 102a, 102b, and 102c may be used to fabricate integrated circuit 300 ( Figure 3A-3G ) part 390, integrated circuit 400 ( Figure 4A-4B ) portion 490, integrated circuit 500 ( Figure 5A-Figure 5B ) part 590, integrated circuit 600 ( Figure 6A-6B ) portion 690 or integrated circuit 700 ( Figure 7A-7B ) of at least one of the portions 790.

[0051] In some embodiments, standard cell layout designs 104a and 104b may be used to fabricate integrated circuit 300 ( Figure 3A-3G ) part 392, integrated circuit 400 ( Figure 4A-4B ) portion 492, integrated circuit 500 ( Figure 5A-Figure 5B ) part 592, integrated circuit 600 ( Figure 6A-6B ) portion 692 or integrated circuit 700 ( Figure 7A-7B ) of at least one of the portions 792.

[0052] In some embodiments, one or more of the standard cell layout designs 102a, 102b, 102c, 104a, or 104b is a layout design of a logic gate unit. In some embodiments, the logic gate unit includes AND, OR, NAND, NOR, XOR, INV, AND-OR-invert (AOI), OR-AND-invert (OAI), MUX, flip-flop, BUFF, latch, delay, or clock unit. In some embodiments, one or more of the standard cell layout designs 102a, 102b, 102c, 104a, or 104b is a layout design of a memory cell. In some embodiments, the memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM), or a read-only memory (ROM). In some embodiments, one or more of the standard cell layout designs 102a, 102b, 102c, 104a, or 104b includes a layout design of one or more active or passive elements. Examples of active components include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFET / NFET), etc.), FinFETs (fin field effect transistors), nanosheet transistors, nanowire transistors, complementary FET (CFET) transistors, and planar MOS transistors with convex source / drain. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0053] Other configurations or numbers of layout designs 100A are also within the scope of the present disclosure.

[0054] Figure 1B is a schematic diagram of a layout design 100B according to some embodiments.

[0055] Layout Design 100B is Figure 1A The layout design 100A is a variation of the layout design 100A, so similar detailed description is omitted. Figure 1A Compared with the layout design 100A of the present invention, the layout design 100B has a mixed row design including at least two rows having different heights, and thus similar detailed descriptions are omitted. For example, the standard cell layout designs 104a and 104b of the layout design 100B have different heights from the standard cell layout designs 102a, 102b, or 102c in the layout design 100B, and thus similar detailed descriptions are omitted.

[0056] The layout design 100B is a layout diagram of an integrated circuit, such as Figure 8A-B Integrated circuit 800, Figure 9A-9B IC 900 or Figure 10A-10B The layout design 100B may be used to manufacture an integrated circuit, such as Figure 8A-B Integrated circuit 800, Figure 9A-9B IC 900 or FIG. 10A to FIG. 10B 1000 of integrated circuits.

[0057] Layout design 100B includes standard cell layout designs 102a, 102b, 102c, 104a, and 104b. In some embodiments, layout design 100B includes Figure 1B Additional elements not shown.

[0058] exist Figure 1B In the layout design 100B, each of the standard cell layout designs 102a, 102b, or 102c has a height H1 in the second direction Y, and each of the standard cell layout designs 104a or 104b has a height H2 in the second direction Y. The height H2 is different from the height H1.

[0059] In some embodiments, standard cell layout designs 102a, 102b, and 102c may be used to fabricate portion 890 of integrated circuit 800. Figure 8A-B ), portion 990 of integrated circuit 900 ( Figure 9A-9B ) or portion 1090 of integrated circuit 1000 ( Figure 10A-10B ) at least one of ).

[0060] In some embodiments, standard cell layout designs 104a and 104b may be used to fabricate portion 892 of integrated circuit 800 ( Figure 8A-B ), portion 992 of integrated circuit 900 ( Figure 9A-9B ) or portion 1092 of integrated circuit 1000 ( Figure 10A-10B ) at least one of ).

[0061] Other configurations or numbers of layout designs 100B are also within the scope of the present disclosure.

[0062] Figure 2A-2C is a diagram of a layout design according to some embodiments.

[0063] Figure 2A-2C are respective diagrams of respective portions 200A- 200C of layout design 200 of respective integrated circuit 300 , according to some embodiments.

[0064] Layout Design 200 is Figure 1A Layout design 100A is similar to the layout design 100A, so similar detailed description is omitted. Layout design 200 is Figure 3A-3GA layout of the integrated circuit 300 is provided.

[0065] Portion 200A includes one or more components of layout design 200, namely, an active level or oxide diffusion (OD) level, a metal on diffusion (MD) level, a metal 0 (M0) level, a metal 1 (M1) level, a metal 2 (M2) level, a metal 3 (M3) level, a via on metal 0 (V0) level, a via on metal 1 (V1) level, a via on metal 2 (V2) level, and a feed-through via (FTV) level. In some embodiments, the FTV level connects the front side and the back side of layout design 200. In some embodiments, the FTV level connects one or more components on the front side 303a of integrated circuit 300 with one or more components on the back side 303b of integrated circuit 300.

[0066] Portion 200B includes one or more components of layout design 200 at the OD level, backside metal diffusion (BMD) level, backside metal 0 (BMO), and FTV level.

[0067] Portion 200C includes one or more components of layout design 200 at the OD level, the MD level, the M0 level, and the FTV level.

[0068] Figure 2A-2C 2 is a corresponding diagram of corresponding portions 200A- 200C of layout design 200 , which are simplified for ease of explanation.

[0069] For ease of explanation, Figure 1A-Figure 10B One or more of the marker elements in Figure 1A-Figure 10B In some embodiments, the layout design 200 includes Figure 2A-2C Additional elements not shown.

[0070] Layout design 200 includes one or more components of an OD level, an MD level, an M0 level, an M1 level, an M2 level, an M3 level, a V0 level, a V1 level, a V2 level, a FTV level, a BMD level, and a BMO level. In some embodiments, at least layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000 includes Figure 2A-2C , Figure 3A-3G , Figure 4A-4B , Figure 5A-Figure 5B , Figure 6A-6B , Figure 7A-7B , Figure 8A-B , Figure 9A-9B or Figure 10A-10B Additional elements not shown.

[0071] Layout design 200 can be used to manufacture Figure 3A-3G Integrated circuit 300.

[0072] Part 200A is Figure 3A The layout of the portion 300A of the integrated circuit 300, the portion 200B is Figure 3B The layout of the portion 300B of the integrated circuit 300, the portion 200C is Figure 3C For the sake of brevity, similar detailed description is omitted. In some embodiments, at least one of the portions 200A or 200C is referred to as a front view of the layout design 200. In some embodiments, the portion 200B is referred to as a back view of the layout design 200.

[0073] In some embodiments, the layout design 200 is a cell 201. The cell 201 has cell boundaries 201a and 201b extending along a first direction X, and cell boundaries 201c and 201d extending along a second direction Y.

[0074] In some embodiments, unit 201 corresponds to Figure 1A For the sake of brevity, similar detailed description is omitted. In some embodiments, the cell boundary 201a or 201b is Figure 1A For the sake of brevity, similar detailed descriptions of the corresponding cell boundaries 101a or 101f of the layout design 100A are omitted.

[0075] In some embodiments, at least one of the first direction X, the second direction Y, or the third direction Z is different from another of the first direction X, the second direction Y, or the third direction Z. In some embodiments, the layout design 200 abuts other cell layout designs (not shown) along cell boundaries 201 c and 201 d. In some embodiments, the layout design 200 abuts other cell layout designs (not shown) along cell boundaries 201 a and 201 b extending in the first direction X. In some embodiments, the cell 201 can be used to manufacture the cell 301.

[0076] In some embodiments, cell 201 is a standard cell and layout design 200 corresponds to a layout of a standard cell defined by cell boundaries 201a, 201b, 201c, and 201d. In some embodiments, cell 201 is a predefined portion of layout design 200 that includes one or more transistors and electrical connections configured to perform one or more circuit functions. In some embodiments, cell 201 is bounded by cell boundaries 201a, 201b, 201c, and 201d and therefore corresponds to an area of ​​a functional circuit component or device that is part of a standard cell.

[0077] Layout design 200 includes portion 290 and portion 292 .

[0078] In some embodiments, portion 290 is Figure 1A For the sake of brevity, similar detailed descriptions are omitted for the standard cell layout designs 102a, 102b, and 102c of the layout design 100A. In some embodiments, portion 292 is Figure 1A Similar detailed descriptions of the standard cell layout designs 104a and 104b of the layout design 100A are omitted for the sake of brevity.

[0079] The layout design 200 includes at least one of the cell layout patterns 210 a , 210 b , or 210 c (collectively referred to as “cell layout group 210 ”) extending along the first direction X. The embodiments of the present disclosure use the term “layout pattern”, which is also referred to as “pattern” hereinafter in the rest of the present disclosure for brevity.

[0080] The cell layout group 210 may be used to manufacture a corresponding cell group 310 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the cell layout pattern 210a, 210b, or 210c may be used to manufacture a corresponding cell 310a, 310b, or 310c in the cell group 310 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0081] Each cell layout 210a, 210b, or 210c is located in a corresponding row 1, 2, or 3 of layout design 200. Each of rows 1, 2, 3, 4, and 5 is a corresponding row 1, 2, 3, 4, and 5 of layout design 100A or 100B, and similar detailed descriptions are omitted for brevity.

[0082] For ease of illustration, layout design 200 shows a single cell layout 210a, 210b, or 210c within corresponding row 1, 2, or 3 of layout design 200. In some embodiments, one or more rows of cell layout group 210 include one or more additional cell layouts in corresponding row 1, 2, or 3 of layout design 200.

[0083] The layout design 200 further includes at least one of the cell layouts 211 a or 211 b extending along the first direction X (collectively referred to as “cell layout group 211 ”).

[0084] The cell layout group 211 may be used to manufacture a corresponding cell group 311 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the cell layout pattern 211a or 211b may be used to manufacture a corresponding cell 311a or 311b in the cell group 311 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0085] Each cell layout 211 a or 211 b is located within a corresponding row 4 or 5 of layout design 200 .

[0086] For ease of illustration, layout design 200 shows a single cell layout 211a or 211b within respective row 4 or 5 of layout design 200. In some embodiments, one or more rows of cell layout group 211 include one or more additional cell layouts in respective row 4 or 5 of layout design 200.

[0087] Each cell layout of the cell layout group 210 includes at least one of active area patterns 202a or 202b (collectively referred to as "active area pattern group 202") extending in the first direction X. Each active area pattern of the active area pattern group 202 is separated from each other in the second direction Y.

[0088] Each cell layout in the cell layout group 211 includes at least one of active area patterns 204a or 204b (collectively referred to as “active area pattern group 204”) extending along the first direction X. Each active area pattern in the active area pattern group 204 is separated from each other in the second direction Y.

[0089] Active area pattern set 202 may be used to fabricate a corresponding active area set 302 of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. Active area pattern set 204 may be used to fabricate a corresponding active area set 304 of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0090] In some embodiments, at least one of the active area groups 302 or 304 is located on the front side 303a of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, at least one of the active area groups 302 or 304 corresponds to source and drain regions of one or more complementary FET (CFET) transistors. In some embodiments, at least one of the active area groups 302 or 304 corresponds to source and drain regions of one or more nanosheet transistors or nanowire transistors. In some embodiments, at least one of the active area groups 302 or 304 corresponds to source and drain regions of one or more finFET transistors. In some embodiments, at least one of the active area groups 302 or 304 corresponds to source and drain regions of one or more planar transistors. Other transistor types are also within the scope of the present disclosure.

[0091] In some embodiments, the active area pattern 202a or 202b may be used to fabricate the corresponding active area 302a or 302b in the active area group 302 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the active area pattern 204a or 204b may be used to fabricate the corresponding active area 304a or 304b in the active area group 304 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0092] In some embodiments, active area pattern groups 202 and 204 are referred to as oxide diffusion (OD) regions that define at least source or drain diffusion regions of integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 or layout design 200 .

[0093] In some embodiments, at least one of the active area patterns 202a or 204a may be used to manufacture source and drain regions of a P-type transistor of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000, and at least one of the active area patterns 202b or 204b may be used to manufacture drain and source regions of an N-type transistor in the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0094] In some embodiments, at least one of the active area patterns 202a or 204a may be used to manufacture source and drain regions of an N-type transistor of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000, and at least one of the active area patterns 202b or 204b may be used to manufacture drain and source regions of a P-type transistor in the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0095] In some embodiments, active area pattern group 202 or 204 is located at a first layout level. In some embodiments, the first layout level corresponds to an active level or OD level of one or more of layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the OD level is higher than the BMO level.

[0096] The active area layout patterns 202 a and 202 b each have a width W1 a in the second direction Y. In some embodiments, the width W1 a is referred to as a first size.

[0097] The active area layout patterns 204 a and 204 b each have a width W2 a in the second direction Y. In some embodiments, the width W2 a is referred to as a second size.

[0098] In some embodiments, an increase in width W1a results in an increase in the corresponding speed and driving strength of a corresponding transistor fabricated by the corresponding active area pattern 202a or 202b. In some embodiments, a decrease in width W1a results in a decrease in the corresponding speed and driving strength of a corresponding transistor fabricated by the corresponding active area pattern 202a or 202b.

[0099] In some embodiments, the increase in width W2a results in an increase in the corresponding speed and driving strength of the corresponding transistor manufactured by the corresponding active area pattern 204a or 204b. In some embodiments, the decrease in width W2a results in a decrease in the corresponding speed and driving strength of the corresponding transistor manufactured by the corresponding active area pattern 204a or 204b.

[0100] In some embodiments, the width W1a is greater than the width W2a. In these embodiments, the corresponding speed and driving strength of the corresponding transistor manufactured by the corresponding active area pattern 202a or 202b are greater than the corresponding speed and driving strength of the corresponding transistor manufactured by the corresponding inactive area pattern 204a or 204b, and the active area pattern group 202 is referred to as a "large device" and the active area pattern group 204 is referred to as a "small device".

[0101] Other configurations, arrangements on other layout levels, or numbers of patterns in the active area pattern groups 202 or 204 are within the scope of the present disclosure.

[0102] Each cell layout of the cell layout group 210 further includes one or more contact patterns 206 a or 206 b (collectively referred to as “contact pattern group 206 ”) extending along the second direction Y.

[0103] Each contact pattern of the contact pattern group 206 is separated from adjacent contact patterns of the contact pattern group 206 at least in the first direction X or the second direction Y.

[0104] The contact pattern set 206 may be used to manufacture a corresponding contact set 306 of an integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0105] In some embodiments, the contact pattern 206a or 206b of the contact pattern group 206 may be used to fabricate the corresponding contact 306a or 306b of the contact group 306. In some embodiments, the contact pattern group 206 is also referred to as a metal overdiffusion (MD) pattern group.

[0106] In some embodiments, at least one of the contact patterns 206a or 206b of the contact pattern set 206 may be used to fabricate a source terminal or a drain terminal of one of the N-type or P-type transistors of the integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0107] In some embodiments, the contact pattern 206a may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 206a may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0108] In some embodiments, the contact pattern 206b may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 206b may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0109] In some embodiments, contact pattern group 206 overlaps active area pattern group 202. Contact pattern group 206 is located at a second layout level. In some embodiments, the second layout level corresponds to a contact level or an MD level of one or more of layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the second layout level is different from the first layout level.

[0110] Other configurations in the contact pattern group 206 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0111] Each cell layout of the cell layout group 210 further includes one or more contact patterns 207 a or 207 b extending along the second direction Y (collectively referred to as “contact pattern group 207 ”).

[0112] Each contact pattern of the contact pattern group 207 is separated from adjacent contact patterns of the contact pattern group 207 at least in the first direction X or the second direction Y.

[0113] The contact pattern set 207 may be used to manufacture a corresponding contact set 307 of an integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0114] In some embodiments, the contact pattern 207a or 207b of the contact pattern group 207 may be used to fabricate the corresponding contact 307a or 307b of the contact group 307. In some embodiments, the contact pattern group 207 is also referred to as a backside metal diffusion (BMD) pattern group.

[0115] In some embodiments, at least one of the contact patterns 207a or 207b of the contact pattern set 207 may be used to fabricate a source terminal or a drain terminal of one of the N-type or P-type transistors of the integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0116] In some embodiments, the contact pattern 207a may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 207a may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0117] In some embodiments, the contact pattern 207b may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 207b may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0118] In some embodiments, the contact pattern group 207 overlaps the active area pattern group 202. The contact pattern group 207 is located at a third layout level. In some embodiments, the third layout level corresponds to a backside contact level or a backside MD (BMD) level of one or more of the layout design 200 or the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the third layout level is different from the first layout level and the second layout level.

[0119] In some embodiments, the BMD level is higher than the BMO level. In some embodiments, the BMD level is above the back side 303b of the integrated circuit 300. In some embodiments, the BMD level is lower than the OD level, the POLY level, the MD level, the M0 level, the M1 level, the M2 level, and the M3 level.

[0120] Other configurations, arrangements on other layout levels, or numbers of patterns in the contact pattern group 207 are within the scope of the present disclosure.

[0121] Each cell layout in the cell layout group 211 further includes one or more contact patterns 208 a , 208 b , 208 c or 208 d (collectively referred to as “contact pattern group 208 ”) extending along the second direction Y.

[0122] Each contact pattern of the contact pattern group 208 is separated from adjacent contact patterns of the contact pattern group 208 at least in the first direction X or the second direction Y.

[0123] The contact pattern set 208 may be used to manufacture a corresponding contact set 308 of an integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0124] In some embodiments, the contact pattern 208a, 208b, 208c, or 208d of the contact pattern group 208 may be used to manufacture corresponding contacts 308a, 308b, 308c, or 308d of the contact group 308. In some embodiments, the contact pattern group 208 is also referred to as an MD pattern group.

[0125] In some embodiments, at least one of the contact patterns 208a, 208b, 208c or 208d of the contact pattern set 208 may be used to fabricate a source terminal or a drain terminal of one of the N-type or P-type transistors of the integrated circuit 300, 400, 500, 600, 700, 800, 900 or 1000.

[0126] In some embodiments, the contact pattern 208a may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 208a may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0127] In some embodiments, the contact pattern 208b may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 208b may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0128] In some embodiments, the contact pattern 208c may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 208c may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0129] In some embodiments, the contact pattern 208d may be used to fabricate a source terminal of a P-type or N-type transistor. In some embodiments, the contact pattern 208d may be used to fabricate a drain terminal of a P-type or N-type transistor.

[0130] In some embodiments, the contact pattern group 208 overlaps the active area pattern group 204. The contact pattern group 208 is located on the second layout level.

[0131] Other configurations, arrangements on other layout levels, or numbers of patterns in the contact pattern group 208 are within the scope of the present disclosure.

[0132] The layout design 200 also includes one or more conductive feature patterns 230 a , 230 b , 230 c , 230 d , 230 e , or 230 f (collectively referred to as “conductive feature pattern group 230 ”) extending along the first direction X.

[0133] Each conductive component pattern in the conductive component pattern group 230 is separated from another conductive component pattern in the conductive component pattern group 230 by a pitch P1a in the second direction Y. In some embodiments, since each conductive component pattern in the conductive component pattern group 230 is separated from another conductive component pattern in the conductive component pattern group 230 by the same pitch (e.g., pitch P1a) in the second direction Y, each row (e.g., rows 1-5) of the layout design 200 has the same height (e.g., height H1), and the layout design 200 has a uniform row height.

[0134] The conductive feature pattern group 230 overlaps with at least one of the active area pattern group 202 or 204 , or the contact pattern group 206 , 207 , or 208 .

[0135] The conductive component pattern set 230 may be used to fabricate a corresponding conductor set 330 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. The conductive component pattern 230a, 230b, 230c, 230d, 230e, or 230f may be used to fabricate a corresponding conductor 330a, 330b, 330c, 330d, 330e, or 330f of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, at least one conductor in the conductor set 330 is located on the front side 303a of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0136] In some embodiments, the conductive component pattern group 230 is located at a fourth layout level. In some embodiments, the fourth layout level is different from at least one of the first layout level, the second layout level, or the third layout level. In some embodiments, the fourth layout level corresponds to the M0 level of one or more of the layout design 200 or the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the M0 level is higher than the OD level, the POLY level, the MD level, the BMD level, and the BMO level.

[0137] In some embodiments, the conductive component pattern group 230 corresponds to 6 M0 routing tracks. Other numbers of M0 routing tracks are also within the scope of the present disclosure. Other M0 track allocations are within the scope of the present disclosure.

[0138] Other configurations, pitches, arrangements on other layout levels, or numbers of patterns in the conductive feature pattern group 230 are within the scope of the present disclosure.

[0139] The layout design 200 also includes one or more conductive feature patterns 232 a , 232 b , 232 c , 232 d , 232 e , or 232 f (collectively referred to as “conductive feature pattern group 232 ”) extending along the first direction X.

[0140] Each conductive component pattern in the conductive component pattern group 232 is spaced apart from another conductive component pattern in the conductive component pattern group 232 by a pitch P1b in the second direction Y. In some embodiments, since each conductive component pattern in the conductive component pattern group 232 is spaced apart from another conductive component pattern in the conductive component pattern group 232 by the same pitch (e.g., pitch P1b) in the second direction Y, each row (e.g., rows 1-5) of the layout design 200 has the same height (e.g., height H1), and the layout design 200 has a uniform row height.

[0141] Pitch P1b is the same as pitch P1a. In some embodiments, pitch P1b is different from pitch P1a.

[0142] The conductive feature pattern group 232 overlaps at least one of the active area pattern group 202 or 204 , the contact pattern group 206 , 207 or 208 , or the conductive feature pattern group 230 .

[0143] The conductive member pattern groups 230 and 232 are separated from each other in the third direction Z.

[0144] The conductive feature pattern set 232 may be used to fabricate a corresponding conductor set 332 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. The conductive feature pattern 232a, 232b, 232c, 232d, 232e, or 232f may be used to fabricate a corresponding conductor 332a, 332b, 332c, 332d, 332e, or 332f of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, at least one conductor in the conductor set 332 is located on the back side 303b of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0145] In some embodiments, conductive component pattern group 232 is located at a fifth layout level. In some embodiments, the fifth layout level is different from at least one of the first layout level, the second layout level, the third layout level, and the fourth layout level. In some embodiments, the fifth layout level corresponds to the BMO level of one or more of layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the BMO level is lower than the OD level, the POLY level, the MD level, the BMD level, and the M1 level.

[0146] In some embodiments, the conductive component pattern group 232 corresponds to 6 BMO routing tracks. Other numbers of BMO routing tracks are also within the scope of the present disclosure. Other BMO track allocations are within the scope of the present disclosure.

[0147] In some embodiments, the layout design 200 includes a front side power rail (e.g., conductive feature pattern group 230) and a back side power rail (e.g., conductive feature pattern group 232), as well as a first group of transistors (e.g., active area pattern group 202) and a second group of transistors (e.g., active area pattern group 204) having different sizes or widths, thereby forming a more flexible layout design 200.

[0148] Other configurations, pitches, arrangements on other layout levels, or numbers of patterns in the conductive feature pattern group 232 are within the scope of the present disclosure.

[0149] The via pattern group 270 includes one or more of the via patterns 270 a or 270 b .

[0150] In some embodiments, the via pattern group 270 is located between the conductive feature pattern group 230 and the contact pattern group 206 .

[0151] Other configurations, arrangements on other layout levels, or numbers of via patterns in at least one via pattern group 270 are within the scope of the present disclosure.

[0152] The via pattern group 272 includes one or more of via patterns 272 a , 272 b , 272 c , or 272 d .

[0153] In some embodiments, the via pattern group 272 is located between the conductive feature pattern group 230 and the contact pattern group 208 .

[0154] Other configurations, arrangements on other layout levels, or numbers of via patterns in at least one via pattern group 272 are within the scope of the present disclosure.

[0155] The layout design 200 further includes at least one of the cell layout patterns 212 a or 212 b extending in at least the first direction X or the second direction Y (collectively referred to as “cell layout group 212 ”).

[0156] The cell layout group 212 may be used to manufacture a corresponding cell group 312 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the cell layout pattern 212a or 212b may be used to manufacture a corresponding cell 312a or 312b in a cell group 310 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0157] Each cell layout 212a or 212b is located in two corresponding rows of layout design 200. For example, cell layout 212a is located in row 4 and row 5 of layout design 200, and cell layout 212b is located in row 3 and row 4 of layout design 200. Other rows or positions of cell layout 212a or 212b are within the scope of the present disclosure. Other numbers of cell layouts 212a or 212b are also within the scope of the present disclosure.

[0158] The cell layout 212 a includes at least a via pattern 220 a extending in the third direction Z.

[0159] The cell layout 212 b includes at least a via pattern 220 b extending in the third direction Z.

[0160] The via pattern group 220 includes at least one of the via patterns 220 a or 220 b .

[0161] Each via pattern of the via pattern group 220 is separated from adjacent via patterns of the via pattern group 220 in at least the first direction X or the second direction Y.

[0162] The via pattern group 220 may be used to fabricate a corresponding via group 320 of an integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0163] In some embodiments, the via pattern 220a or 220b of the via pattern group 220 may be used to fabricate a corresponding via 320a or 320b of the via pattern group 320. In some embodiments, the via pattern group 220 is also referred to as a feed-through via (FTV) pattern group.

[0164] In some embodiments, the via pattern group 220 overlaps the conductive feature pattern group 230. In some embodiments, the via pattern group 220 is between the conductive feature pattern group 230 and the conductive feature pattern group 232.

[0165] The via pattern 220a is located between the conductive component pattern 230e and the conductive component pattern 232e. The via pattern 220b is located between the conductive component pattern 230d and the conductive component pattern 232d.

[0166] The through hole pattern group 220 is located at the FTV level of one or more of the layout design 200 or the integrated circuit 300, 400, 500, 600, 700, 800, 900 or 1000. In some embodiments, the FTV level is higher than the BMO level. In some embodiments, the FTV level is lower than the M0 level, the M1 level, the M2 level and the M3 level. In some embodiments, the FTV level is between the M0 level and the BMO level. In some embodiments, the FTV level is between the fourth layout level and the fifth layout level. Other layout levels are also within the scope of the present disclosure.

[0167] In some embodiments, the via pattern group 220 is adjacent to or directly adjacent to the cell layout group 211. In some embodiments, the via pattern group 220 is positioned adjacent to or directly adjacent to the cell layout group 211, thereby reducing the resistance from the conductive feature pattern group 230 or 232 by reducing the distance between the cell layout group 211 and the corresponding power supply voltage VDD or reference power supply voltage VSS. In some embodiments, the layout design 200 has lower resistance than other methods, thereby improving performance.

[0168] Other configurations in the via pattern group 220 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0169] Other configurations in the unit pattern group 212 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0170] The layout design 200 further includes one or more conductive feature patterns 240 a or 240 b extending along the second direction Y (collectively referred to as “conductive feature pattern group 240 ”).

[0171] Each conductive component pattern in the conductive component pattern group 240 is separated in the first direction X from another conductive component pattern in the conductive component pattern group 240 .

[0172] The conductive feature pattern group 240 overlaps at least one of the active area pattern group 202 or 204 , the contact pattern group 206 , 207 or 208 , or the conductive feature pattern group 230 or 232 .

[0173] The conductive feature pattern set 240 may be used to fabricate a corresponding conductor set 340 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. The conductive feature pattern 240a or 240b may be used to fabricate a corresponding conductor 340a or 340b of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, at least one conductor in the conductor set 340 is located on the front side 303a of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0174] In some embodiments, conductive component pattern group 240 is located at a sixth layout level. In some embodiments, the sixth layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, or the fifth layout level. In some embodiments, the sixth layout level corresponds to the M1 level of one or more of layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the M1 level is higher than the OD level, the POLY level, the MD level, the M0 level, the BMD level, and the BMO level.

[0175] In some embodiments, the conductive feature pattern group 240 corresponds to 2 M1 routing tracks. Other numbers of M1 routing tracks are also within the scope of the present disclosure.

[0176] Other configurations in the conductive feature pattern group 240 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0177] The layout design 200 also includes one or more via patterns 242 a , 242 b , 242 c , 242 d , 242 e , or 242 f (collectively referred to as “via pattern group 242 ”).

[0178] The via pattern group 242 may be used to manufacture a corresponding via group 342 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the via pattern 242a, 242b, 242c, 242d, 242e, or 242f of the via pattern group 242 may be used to manufacture a corresponding via 342a, 342b, 342c, 342d, 342e, or 342f of the via pattern group 242.

[0179] In some embodiments, the via pattern group 242 is located between the conductive feature pattern group 240 and the conductive feature pattern group 230 .

[0180] The through hole pattern 242a is located between the conductive component pattern 240a and the conductive component pattern 230a. The through hole pattern 242b is located between the conductive component pattern 240a and the conductive component pattern 230c. The through hole pattern 242c is located between the conductive component pattern 240a and the conductive component pattern 230e. The through hole pattern 242d is located between the conductive component pattern 240b and the conductive component pattern 230b. The through hole pattern 242e is located between the conductive component pattern 240b and the conductive component pattern 230d. The through hole pattern 242f is located between the conductive component pattern 240b and the conductive component pattern 230f.

[0181] The through hole pattern group 242 is located at the through hole (V0) level on M0 of one or more of the layout design 200 or the integrated circuit 300, 400, 500, 600, 700, 800, 900 or 1000. In some embodiments, the V0 level is higher than the OD level, the POLY level, the MD level, the M0 level, the BMD level and the BMO level. In some embodiments, the V0 level is lower than the M1 level. In some embodiments, the V0 level is between the M0 level and the M1 level. In some embodiments, the V0 level is between the fourth layout level and the sixth layout level. Other layout levels are also within the scope of the present disclosure.

[0182] Other configurations in at least the via pattern group 242 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0183] The layout design 200 further includes conductive feature patterns 250 a extending at least along the first direction X (collectively referred to as “conductive feature pattern group 250 ”).

[0184] Each conductive component pattern in the conductive component pattern group 250 is separated in the second direction Y from another conductive component pattern in the conductive component pattern group 250 .

[0185] The conductive feature pattern group 250 overlaps at least one of the active area pattern group 202 or 204 , the contact pattern group 206 , 207 or 208 , or the conductive feature pattern group 230 , 232 or 240 .

[0186] The conductive feature pattern set 250 may be used to fabricate a corresponding conductor set 350 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. The conductive feature pattern 250a may be used to fabricate a corresponding conductor 350a of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, at least one conductor in the conductor set 350 is located on the front side 303a of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0187] In some embodiments, conductive component pattern group 250 is located at a seventh layout level. In some embodiments, the seventh layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, the fifth layout level, or the sixth layout level. In some embodiments, the seventh layout level corresponds to the M2 level of one or more of layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the M2 level is higher than the OD level, the POLY level, the MD level, the M0 level, the M1 level, the BMD level, and the BMO level.

[0188] In some embodiments, the conductive feature pattern group 250 corresponds to 1 M2 routing track. Other numbers of M2 routing tracks are also within the scope of the present disclosure.

[0189] Other configurations in the conductive feature pattern group 250 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0190] The layout design 200 also includes at least a via pattern 252 a (collectively referred to as a “via pattern group 252 ”).

[0191] The via pattern group 252 may be used to manufacture a corresponding via group 352 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the via pattern 252a of the via pattern group 252 may be used to manufacture a corresponding via 352a in the via group 352 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0192] In some embodiments, the via pattern group 252 is between the conductive feature pattern group 250 and the conductive feature pattern group 240 .

[0193] The via pattern 252 a is located between the conductive component pattern 250 a and the conductive component pattern 240 a .

[0194] The through hole pattern group 252 is located at the M1 through hole (V1) level of one or more of the layout design 200 or the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the V1 level is higher than the OD level, the POLY level, the MD level, the M0 level, the M1 level, the BMD level, and the BMO level. In some embodiments, the V1 level is lower than the M2 level. In some embodiments, the V1 level is between the M1 level and the M2 level. In some embodiments, the V1 level is between the sixth layout level and the seventh layout level. Other layout levels are also within the scope of the present disclosure.

[0195] Other configurations, arrangements on other layout levels, or numbers of patterns in at least the via pattern group 252 are within the scope of the present disclosure.

[0196] The layout design 200 further includes conductive feature patterns 260 a extending at least along the second direction Y (collectively referred to as “conductive feature pattern group 260 ”).

[0197] Each conductive component pattern in the conductive component pattern group 260 is separated in the first direction X from another conductive component pattern in the conductive component pattern group.

[0198] The conductive feature pattern group 260 overlaps at least one of the active area pattern group 202 or 204 , the contact pattern group 206 , 207 or 208 , or the conductive feature pattern group 230 , 232 , 240 or 250 .

[0199] The conductive feature pattern set 260 may be used to fabricate a corresponding conductor set 360 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. The conductive feature pattern 260a may be used to fabricate a corresponding conductor 360a of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, at least one conductor in the conductor set 360 is located on the front side 303a of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0200] In some embodiments, conductive component pattern group 260 is located at an eighth layout level. In some embodiments, the eighth layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, the fifth layout level, the sixth layout level, or the seventh layout level. In some embodiments, the eighth layout level corresponds to the M3 level of one or more of layout design 200 or integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the M3 level is higher than the OD level, the POLY level, the MD level, the M0 level, the M1 level, the M2 level, the BMD level, and the BMO level.

[0201] In some embodiments, the conductive feature pattern group 260 corresponds to 1 M3 routing track. Other numbers of M3 routing tracks are also within the scope of the present disclosure.

[0202] Other configurations in the conductive feature pattern group 260 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0203] The layout design 200 also includes at least a via pattern 262 a (collectively referred to as a “via pattern group 262 ”).

[0204] The via pattern group 262 may be used to manufacture a corresponding via group 362 of an integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the via pattern 262a of the via pattern group 262 may be used to manufacture a corresponding via 362a of the via group 362 of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0205] In some embodiments, the via pattern group 262 is located between the conductive feature pattern group 260 and the conductive feature pattern group 250 .

[0206] The via pattern 262a is located between the conductive component pattern 260a and the conductive component pattern 250a.

[0207] The through hole pattern group 262 is located at the M2 through hole (V2) level of one or more of the layout design 200 or the integrated circuit 300, 400, 500, 600, 700, 800, 900 or 1000. In some embodiments, the V2 level is higher than the OD level, the POLY level, the MD level, the M0 level, the M1 level, the M2 level, the BMD level and the BMO level. In some embodiments, the V2 level is lower than the M3 level. In some embodiments, the V2 level is between the M2 level and the M3 level. In some embodiments, the V2 level is between the seventh layout level and the eighth layout level. Other layout levels are also within the scope of the present disclosure.

[0208] Other configurations of at least the via pattern group 262 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0209] In some embodiments, by including at least one or more of conductive feature pattern group 240, via pattern group 242, conductive feature pattern group 250, via pattern group 252, via pattern group 262, or conductive feature pattern group 260, layout design 200 has lower resistance than other methods, thereby improving performance.

[0210] Other configurations in layout design 200 , other arrangements on layout levels, or numbers of patterns are within the scope of the present disclosure.

[0211] Figure 3A-3G is a diagram of an integrated circuit 300 according to some embodiments.

[0212] Figure 3A-3C 3 is a corresponding diagram of corresponding portions 300A- 300C of integrated circuit 300 , which are simplified for ease of explanation.

[0213] The portion 300A includes one or more components of the integrated circuit 300 at the OD level, MD level, M0 level, M1 level, M2 level, M3 level, V0 level, V1 level, V2 level, and FTV level. The portion 300A is manufactured from the portion 200A.

[0214] The portion 300B includes one or more components of the integrated circuit 300 at the OD level, the BMD level, the BMO level, and the FTV level. The portion 300B is manufactured from the portion 200B.

[0215] The portion 300C includes one or more components of the integrated circuit 300 at the OD level, the MD level, the M0 level, and the FTV level. The portion 300C is manufactured from the portion 200C.

[0216] Figure 3D-Figure 3G is a corresponding cross-sectional view of an integrated circuit 300 according to some embodiments. Figure 3D is a cross-sectional view of the integrated circuit 300 intersecting the plane AA′ according to some embodiments. Figure 3E is a cross-sectional view of the integrated circuit 300 intersecting the plane BB′ according to some embodiments. Figure 3F is a cross-sectional view of the integrated circuit 300 intersecting the plane CC′ according to some embodiments. Figure 3G is a cross-sectional view of the integrated circuit 300 intersecting the plane DD′ according to some embodiments.

[0217] and Figure 1A-1B , Figure 2A-2B , Figure 3A-3G , Figure 4A-4B , Figure 5A-Figure 5B , Figure 6A-6B , Figure 7A-7B , Figure 8A-B , Figure 9A-9B or Figure 10A-10B The same or similar components in one or more of the embodiments are given the same reference numerals, and thus their detailed descriptions are omitted.

[0218] Integrated circuit 300 is manufactured by layout design 200. Integrated circuit 300 is a unit 301. Unit 301 is manufactured by unit 201, and similar detailed description is omitted for brevity. The structural relationship (including alignment, length and width) and configuration and layers of integrated circuit 300, 400, 500, 600, 700, 800, 900 or 1000 are similar to Figure 2A-2B The structural relationship, configuration and layers of the layout design 200 are similar, and for the sake of simplicity, at least Figure 3A-3GSimilar detailed descriptions are not described in the following descriptions. For example, in some embodiments, at least one or more widths, lengths, or pitches of layout design 200 are similar to corresponding widths, lengths, or pitches of integrated circuits 300, 400, 500, 600, 700, 800, 900, or 1000, and similar detailed descriptions are omitted for the sake of brevity. For example, in some embodiments, at least cell boundaries 201a, 201b, 201c, or 201d are similar to at least corresponding cell boundaries 301a, 301b, 301c, or 301d of integrated circuit 300, and similar detailed descriptions are omitted for the sake of brevity.

[0219] Integrated circuit 300 includes at least one or more of active area groups 302 and 304, contact group 306, contact group 307, contact group 308, conductor group 330, conductor group 332, via group 320, conductor group 340, via group 342, conductor group 350, via group 352, conductor group 360, via group 362, substrate 380, or insulation region 382.

[0220] Unit 301 is manufactured from unit 201, and similar detailed description is omitted for brevity.

[0221] Integrated circuit 300 also includes portion 390 and portion 392 .

[0222] In some embodiments, portion 390 is composed of Figure 2A-2C Section 290 of Layout Design 200 or Figure 1A The standard cell layout designs 102a, 102b and 102c of the layout design 100A are manufactured, and similar detailed descriptions are omitted for the sake of brevity. In some embodiments, the portion 392 is composed of Figure 2A-2C Section 292 of Layout Design 200 or Figure 1A The standard cell layout designs 104a and 104b of the layout design 100A are manufactured, and similar detailed descriptions are omitted for the sake of brevity.

[0223] Integrated circuit 300 further includes at least one of cells 310 a , 310 b , or 310 c (collectively referred to as “cell group 310 ”) and at least one of cells 311 a or 311 b (collectively referred to as cell placement group 311 ).

[0224] Each cell of the cell group 310 includes at least one of the active regions 302 a or 302 b (collectively referred to as “active region group 302 ”).

[0225] Each cell of the cell group 311 includes at least one of the active regions 304 a or 304 b (collectively referred to as “active region group 304 ”).

[0226] Active area groups 302 and 304 are embedded in a substrate 380. The substrate 380 has a front side 303a and a back side 303b opposite to the front side 303a. In some embodiments, at least the active area groups 302 and 304 or the contact groups 306 and 308 are formed in the front side 303a of the substrate 380. In some embodiments, at least the contact group 307 is formed in the back side 303b of the substrate 380.

[0227] In some embodiments, active area groups 302 and 304 correspond to active areas of CFET transistors. In some embodiments, active area groups 302 and 304 correspond to nanosheet structures (not labeled) of nanosheet transistors. In some embodiments, active area groups 302 or 304 include drain and source regions grown by an epitaxial growth process. In some embodiments, active area groups 302 or 304 include drain and source regions grown with epitaxial material at corresponding drain and source regions.

[0228] Other transistor types are also within the scope of the present disclosure. For example, in some embodiments, active area group 302 or 304 corresponds to a nanowire structure (not shown) of a nanowire transistor. In some embodiments, active area group 302 or 304 corresponds to a planar structure (not shown) of a planar transistor. In some embodiments, active area group 302 or 304 corresponds to a fin structure (not shown) of a finFET.

[0229] In some embodiments, at least active region 302a is an N-type doped S / D region embedded in the dielectric material of substrate 380, and at least active region 302b is a P-type doped S / D region embedded in the dielectric material of substrate 380. In some embodiments, at least active region 304a is a P-type doped S / D region, and at least active region 304b is an N-type doped S / D region embedded in the dielectric material of substrate 380.

[0230] In some embodiments, at least active region 302a is a P-type doped S / D region and at least active region 302b is an N-type doped S / D region embedded in the dielectric material of substrate 380. In some embodiments, at least active region 304a is an N-type doped S / D region and at least active region 304b is a P-type doped S / D region embedded in the dielectric material of substrate 380.

[0231] Active regions 302a and 302b each have a width W1b in the second direction Y. In some embodiments, width W1b is referred to as a first size.

[0232] Active regions 304 a and 304 b each have a width W2 b in the second direction Y. In some embodiments, width W2 b is referred to as a second size.

[0233] In some embodiments, an increase in width W1b results in an increase in the corresponding speed and drive strength of the corresponding transistor. In some embodiments, a decrease in width W1a results in a decrease in the corresponding speed and drive strength of the corresponding transistor.

[0234] In some embodiments, an increase in width W2b results in an increase in the corresponding speed and drive strength of the corresponding transistor. In some embodiments, a decrease in width W2b results in a decrease in the corresponding speed and drive strength of the corresponding transistor.

[0235] In some embodiments, width W1b is greater than width W2b. In some embodiments, width W1a is greater than width W2a. In these embodiments, the corresponding speed and driving strength of the corresponding active area pattern 202a or 202b of the corresponding transistor are greater than the corresponding speed and driving strength of the corresponding active area pattern 204a or 204b of the corresponding transistor, and active area group 302 is referred to as a "large device" and active area group 304 is referred to as a "small device".

[0236] Other configurations, arrangements on other layout levels, or numbers of structures in active area groups 302 or 304 are within the scope of the present disclosure.

[0237] Insulation region 382 is configured to electrically isolate one or more elements of active area groups 302 and 304, contact group 306, contact group 307, contact group 308, conductor group 330, conductor group 332, via group 320, conductor group 340, via group 342, conductor group 350, via group 352, conductor group 360, and via group 362 from each other. In some embodiments, insulation region 382 includes the steps of method 1100A, 1100B, or Fig.11A , Fig. 11B ) during the deposition process at different times. In some embodiments, the insulating region 382 is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, and the like.

[0238] Other configurations in the insulation region 382 , arrangements on other layout levels, or other numbers of portions are within the scope of the present disclosure.

[0239] Each cell of the cell group 310 also includes one or more contacts 306a or 306b (collectively referred to as “contact group 306”).

[0240] In some embodiments, the contact sets 306 and 308 are located on the front side 303 a of the substrate 380 .

[0241] In some embodiments, at least one of the contacts 306 a or 306 b of the contact set 306 is a source terminal or a drain terminal of one of the N-type or P-type transistors of the integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0242] In some embodiments, the contact 306a is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 306a is a drain terminal of a P-type or N-type transistor.

[0243] In some embodiments, the contact 306b is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 306b is a drain terminal of a P-type or N-type transistor.

[0244] In some embodiments, one or more contacts of contact group 306 overlap with corresponding active areas of active area group 302 , thereby electrically coupling corresponding active areas of active area group 302 and a source or drain of a corresponding transistor.

[0245] In some embodiments, the set of contacts 306 enters the set of active areas 302 .

[0246] Other configurations in the contact set 306 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0247] Each cell of the cell group 310 also includes one or more contacts 307a or 307b (collectively referred to as "contact group 307").

[0248] In some embodiments, at least the contact set 307 is located in the back side 303 b of the substrate 380 .

[0249] In some embodiments, at least one of the contacts 307 a or 307 b of the contact set 307 is a source or drain terminal of one of the N-type or P-type transistors of the integrated circuit 300 , 400 , 500 , 600 , 700 , 800 , 900 , or 1000 .

[0250] In some embodiments, the contact 307a is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 307a is a drain terminal of a P-type or N-type transistor.

[0251] In some embodiments, the contact 307b is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 307b is a drain terminal of a P-type or N-type transistor.

[0252] Other configurations in the contact set 307 , arrangements on other layout levels, or numbers of contacts are also within the scope of the present disclosure.

[0253] Each cell of the cell group 311 also includes one or more contacts 308 a , 308 b , 308 c , or 308 d (collectively referred to as “contact group 308 ”).

[0254] In some embodiments, at least one of the contacts 308a, 308b, 308c, or 308d of the contact set 308 is a source or drain terminal of one of the N-type or P-type transistors of the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0255] In some embodiments, the contact 308a is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 308a is a drain terminal of a P-type or N-type transistor.

[0256] In some embodiments, the contact 308b is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 308b is a drain terminal of a P-type or N-type transistor.

[0257] In some embodiments, the contact 308c is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 308c is a drain terminal of a P-type or N-type transistor.

[0258] In some embodiments, the contact 308d is a source terminal of a P-type or N-type transistor. In some embodiments, the contact 308d is a drain terminal of a P-type or N-type transistor.

[0259] Other configurations in the contact set 308 , arrangements on other layout levels, or numbers of contacts are also within the scope of the present disclosure.

[0260] Conductor group 330 is an M0 routing track. In some embodiments, conductor group 330 corresponds to 6 M0 routing tracks.

[0261] Each conductor in conductor group 330 is separated from another conductor of conductor group 330 by pitch P1a' in the second direction Y. In some embodiments, since each conductor in conductor group 330 is separated from another conductor of conductor group 330 by the same pitch (e.g., pitch P1a') in the second direction Y, each row (e.g., rows 1-5) of integrated circuit 300 has the same height (e.g., height H1), and integrated circuit 300 has a uniform row height.

[0262] Conductor group 332 is a BMO routing track. In some embodiments, conductor group 332 corresponds to 6 BMO routing tracks.

[0263] Each conductor in conductor group 332 is spaced apart from another conductor of conductor group 332 by pitch P1b′ in the second direction Y. In some embodiments, since each conductor in conductor group 332 is spaced apart from another conductor of conductor group 332 by the same pitch (e.g., pitch P1b′) in the second direction Y, each row (e.g., rows 1-5) of integrated circuit 300 has the same height (e.g., height H1), and integrated circuit 300 has a uniform row height.

[0264] Pitch P1b' is the same as pitch P1a'. In some embodiments, pitch P1b' is different from pitch P1a'.

[0265] Conductor group 330 overlaps at least one of active area group 302 or 304 or contact group 306, 307 or 308. Conductor group 332 overlaps at least one of active area group 302 or 304, contact group 306, 307 or 308 or conductor group 330.

[0266] In some embodiments, conductor set 330 is located on front side 303a of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, conductor set 332 is located on back side 303b of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0267] At least one of the conductors 330a, 330c, or 330e is configured to provide a voltage VDD. In some embodiments, at least one of the conductors 330a, 330c, or 330e is configured to provide a reference supply voltage VSS.

[0268] At least one of the conductors 330b, 330d, or 330f is configured to provide a reference supply voltage VSS. In some embodiments, at least one of the conductors 330b, 330d, or 330f is configured to provide a voltage VDD.

[0269] At least one of the conductors 332a, 332c, or 332e is configured to provide a voltage VDD. In some embodiments, at least one of the conductors 332a, 332c, or 332e is configured to provide a reference supply voltage VSS.

[0270] At least one of the conductors 332b, 332d, or 332f is configured to provide a reference supply voltage VSS. In some embodiments, at least one of the conductors 332b, 332d, or 332f is configured to provide a voltage VDD.

[0271] In some embodiments, conductor sets 330 and 332 are referred to as respective power rail sets.

[0272] In some embodiments, conductor sets 330 and 332 are routing tracks in other layers.

[0273] In some embodiments, the integrated circuit 300 includes a front side power rail (e.g., conductor group 330) and a back side power rail (e.g., conductor group 332), as well as a first group of transistors (e.g., active area group 302) and a second group of transistors (e.g., active area group 304) having different sizes or widths, thereby forming a more flexible integrated circuit 300 and corresponding layout design 200.

[0274] Other configurations, arrangements at other layout levels, or numbers of conductors in conductor sets 330 and 332 are within the scope of the present disclosure.

[0275] The through-hole group 370 includes one or more of the through-holes 370 a or 370 b .

[0276] In some embodiments, the via set 370 is located between the conductor set 330 and the contact set 306 .

[0277] The via set 370 is configured to electrically couple one or more conductors of the conductor set 330 to one or more contacts of the contact set 306 , and vice versa.

[0278] Other configurations of at least via groups 370 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0279] The through-hole group 372 includes one or more of through-holes 372a, 372b, 372c, or 372d.

[0280] In some embodiments, the via set 372 is located between the conductor set 330 and the contact set 308 .

[0281] The via set 372 is configured to electrically couple one or more conductors of the conductor set 330 to one or more contacts of the contact set 308 , and vice versa.

[0282] Other configurations of at least via groups 372 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0283] The integrated circuit 300 also includes at least one of cells 312 a or 312 b (collectively referred to as “cell group 312 ”).

[0284] The unit 312a includes at least a through hole 320a.

[0285] The unit 312b includes at least a through hole 320b.

[0286] The through-hole group 320 includes at least one of the through-holes 320 a or 320 b .

[0287] The via group 320 extends through the substrate 380 along the third direction Z. The via group 320 is configured to electrically couple corresponding conductors in the conductor group 330 to corresponding conductors in the conductor group 332, and vice versa. The via group 320 is located between the conductor group 330 and the conductor group 332. The via group 320 overlaps the conductor group 330. The via group 320 is located above the conductor group 332.

[0288] Via 320a is located between conductor 330e and conductor 332e. Via 320a is configured to electrically couple conductor 330e and conductor 332e together. In some embodiments, via 320a is configured to provide power supply voltage VDD from back side 303b of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000 to front side 303a. For example, in some embodiments, via 320a is configured to provide power supply voltage VDD from conductor 332e to conductor 330e.

[0289] Via 320b is located between conductor 330d and conductor 332d. Via 320b is configured to electrically couple conductor 330d and conductor 332d together. In some embodiments, via 320b is configured to provide reference voltage VSS from back side 303b of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000 to front side 303a. For example, in some embodiments, via 320b is configured to provide reference voltage VSS from conductor 332d to conductor 330d.

[0290] In some embodiments, the via group 320 is adjacent to or directly adjacent to the cell group 311. In some embodiments, the via group 320 is positioned adjacent to or directly adjacent to the cell group 311, thereby reducing the resistance of the conductor group 330 or 332 by reducing the distance between the cell group 311 and the corresponding power supply voltage VDD or reference power supply voltage VSS. In some embodiments, the integrated circuit 300 has a lower resistance than other methods, thereby improving performance.

[0291] Other configurations in via group 320 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0292] Other configurations in cell group 312 , arrangements on other layout levels, or numbers of cells are within the scope of the present disclosure.

[0293] Conductor set 340 includes one or more of conductors 340a or 340b.

[0294] Conductor group 340 corresponds to 2 M1 routing tracks. Other numbers of M1 routing tracks are also within the scope of the present disclosure. In some embodiments, conductor group 340 is a routing track in other metal layers.

[0295] Conductor set 340 overlaps at least one of active area set 302 or 304 , contact set 306 , 307 , or 308 , or conductor set 330 or 332 .

[0296] In some embodiments, conductor 340a is electrically coupled to at least one of conductors 330a, 330c, or 330e to provide a supply voltage VDD, and is referred to as an "M1 VDD strap."

[0297] In some embodiments, conductor 340b is electrically coupled to at least one of conductors 330b, 330d, or 330f to provide a reference supply voltage VSS and is referred to as an "M1 VSS strap."

[0298] Other configurations in conductor set 340 , arrangements at other layout levels, or numbers of conductors are within the scope of the present disclosure.

[0299] The through-hole group 342 includes one or more of through-holes 342a, 342b, 342c, 342d, 342e, or 342f.

[0300] In some embodiments, via group 342 is located between conductor group 340 and conductor group 330 .

[0301] Via set 326 is configured to electrically couple one or more conductors of conductor set 330 to one or more conductors of conductor set 340 , and vice versa.

[0302] Via 342a is configured to electrically couple conductor 340a and conductor 330a together.

[0303] Via 342b is configured to electrically couple conductor 340a and conductor 330c together.

[0304] Via 342c is configured to electrically couple conductor 340a and conductor 330e together.

[0305] Via 342d is configured to electrically couple conductor 340b and conductor 330b together.

[0306] Via 342e is configured to electrically couple conductor 340b and conductor 330d together.

[0307] Via 342f is configured to electrically couple conductor 340b and conductor 330f together.

[0308] Other configurations of at least via groups 342 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0309] The conductor set 350 includes at least a conductor 350a.

[0310] Conductor set 350 overlaps at least one of active area set 302 or 304 , contact set 306 , 307 , or 308 , or conductor set 330 , 332 , or 340 .

[0311] In some embodiments, conductor 350a is electrically coupled to at least one of conductors 330a, 330c, or 330e through at least conductor 340a and is configured to provide a power supply voltage VDD, and is therefore referred to as an "M2 VDD stripe." In some embodiments, at least one conductor in conductor group 350 is electrically coupled to at least one of conductors 330b, 330d, or 330f through at least conductor 340a and is configured to provide a power supply voltage VDD, and is therefore referred to as an "M2 VSS stripe."

[0312] In some embodiments, conductor group 350 corresponds to 1M2 routing track. Other numbers or locations of M2 routing tracks are also within the scope of the present disclosure.

[0313] Other configurations in conductor set 350, arrangements at other layout levels, or numbers of conductors are within the scope of the present disclosure.

[0314] The through-hole group 352 includes one or more through-holes 352 a .

[0315] In some embodiments, via set 352 is located between conductor set 350 and conductor set 340 .

[0316] The via 352a is located between the conductor 350a and the conductor 340a.

[0317] Via set 352 is configured to electrically couple one or more conductors of conductor set 350 to one or more conductors of conductor set 340 , and vice versa.

[0318] Via 352a is configured to electrically couple conductor 350a and conductor 340a together.

[0319] Other configurations of at least via groups 352 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0320] The conductor set 360 includes at least a conductor 360a.

[0321] Conductor set 360 overlaps at least one of active area set 302 or 304 , contact set 306 , 307 , or 308 , or conductor set 330 , 332 , 340 , or 350 .

[0322] In some embodiments, conductor 360a is electrically coupled to at least one of conductors 330a, 330c, or 330e through at least conductor 340a or conductor 350a and is configured to provide a supply voltage VDD and is therefore referred to as an "M3 VDD stripe."

[0323] In some embodiments, at least one conductor in conductor group 360 is electrically coupled to at least one of conductors 330b, 330d, or 330f through at least conductor 340b or conductor 350a, and is configured to provide a reference supply voltage VSS, and is therefore referred to as an "M3 VSS strip."

[0324] In some embodiments, conductor group 360 corresponds to 1 M3 routing track. Other numbers or locations of M3 routing tracks are also within the scope of the present disclosure.

[0325] Other configurations in conductor set 360, arrangements at other layout levels, or numbers of conductors are within the scope of the present disclosure.

[0326] The through-hole group 362 includes one or more through-holes 362 a .

[0327] In some embodiments, via set 362 is located between conductor set 360 and conductor set 350 .

[0328] Via 362a is located between conductor 360a and conductor 350a.

[0329] Via set 362 is configured to electrically couple one or more conductors of conductor set 360 to one or more conductors of conductor set 350 , and vice versa.

[0330] Via 362a is configured to electrically couple conductor 360a and conductor 350a together.

[0331] Other configurations of at least via groups 362 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0332] In some embodiments, by including at least one or more of conductor group 340 , via group 342 , conductor group 350 , via group 352 , via group 362 , or conductor group 360 , integrated circuit 300 has lower resistance than other approaches, thereby improving performance.

[0333] In some embodiments, at least one contact in contact group 306, 307 or 308, or at least one conductor in conductor group 330, 332, 340, 350 or 360, or at least one via in via group 320, 342, 352, 362, 520 or 620 comprises one or more layers of conductive material, metal, metal compound or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, etc. or a combination thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials or a combination thereof. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSi x 、NiSi x , TiN, TaN, etc. In some embodiments, the doped semiconductor includes at least doped silicon, etc.

[0334] Other configurations or arrangements of integrated circuit 300 are within the scope of the present disclosure.

[0335] Figure 4A-4B is a corresponding diagram of an integrated circuit 400 according to some embodiments.

[0336] Integrated circuit 400 is manufactured by a corresponding layout design similar to integrated circuit 400. For simplicity, Figures 4A-10B are described as corresponding integrated circuits 400-1000, but in some embodiments, Figures 4A-10B Also corresponding to a layout design similar to layout design 100A-100B or 200, the structural elements of integrated circuit 400-1000 also correspond to the layout pattern, and the structural relationship including alignment, length and width as well as the configuration and layers of integrated circuit 400-1000 are similar to the structural relationship, configuration and layers of integrated circuit 400-1000. For the sake of brevity, similar detailed descriptions will not be described again.

[0337] In some embodiments, at least integrated circuit 400, 500, 600, 700, 800, 900, or 1000 is manufactured by a layout design similar to at least one of layout design 200, and thus similar detailed description is omitted. The structural relationship (including alignment, length, and width) and configuration and layers of at least integrated circuit 400, 500, 600, 700, 800, 900, or 1000 are similar to those of layout design 200. Figure 3A-3G The structural relationship, configuration and layers of the integrated circuit 300 are similar, and for the sake of simplicity, at least Figures 4A-10B A similar detailed description will not be described in .

[0338] Integrated circuit 400 is an integrated circuit 300 ( Figure 3A-3G ) is a variation of the present invention, and thus similar detailed description is omitted.

[0339] Integrated circuit 400 includes at least one or more of active area groups 302 and 304 , contact group 306 , contact group 307 , contact group 308 , conductor group 330 , conductor group 332 , via group 320 , substrate 380 , insulating region 382 , cell group 310 , cell group 311 , or cell group 312 .

[0340] and Figure 3A-3G Compared to the integrated circuit 300 of FIG. 4 , the integrated circuit 400 does not include the conductor group 340, the via group 342, the conductor group 350, the via group 352, the conductor group 360, and the via group 362, and thus similar detailed descriptions are omitted. In some embodiments, by not including the conductor group 340, the via group 342, the conductor group 350, the via group 352, the conductor group 360, and the via group 362, the integrated circuit 400 occupies less area than other methods.

[0341] In some embodiments, integrated circuit 400 achieves one or more of the advantages discussed herein.

[0342] Other configurations or arrangements of integrated circuit 400 are within the scope of the present disclosure.

[0343] Figure 5A-Figure 5B is a corresponding diagram of an integrated circuit 500 according to some embodiments.

[0344] Integrated circuit 500 is manufactured by a corresponding layout design similar to integrated circuit 500 .

[0345] Integrated circuit 500 is an integrated circuit 300 ( Figure 3A-3G ) or integrated circuit 400( Figure 4A-4B ) variant, so similar detailed description is omitted. Figure 4A-4B Compared with the integrated circuit 400 , the integrated circuit 500 includes a different number of cells in the cell group 512 or a different number of vias in the via group 520 , and thus similar detailed descriptions are omitted.

[0346] Integrated circuit 500 includes at least one or more of active area groups 302 and 304 , contact group 306 , contact group 307 , contact group 308 , via group 520 , conductor group 330 , conductor group 332 , substrate 380 , insulating region 382 , cell group 310 , cell group 311 , or cell group 512 .

[0347] and Figure 4A-4B Compared with the integrated circuit 400 , the cell group 512 of the integrated circuit 500 replaces the cell group 312 , and the via group 520 of the integrated circuit 300 replaces the via group 320 , and thus similar detailed descriptions are omitted.

[0348] The unit group 512 includes one or more of the units 312a, 312b, 512a, or 512b.

[0349] and Figure 3A-3G Compared with the integrated circuit 300, the unit 512a is similar to the unit 312a, and the unit 512b is similar to the unit 312b, so similar detailed descriptions are omitted.

[0350] The unit 512a includes a through hole 520a.

[0351] The unit 512b includes a through hole 520b.

[0352] The through-hole group 520 includes at least one of the through-holes 320 a , 320 b , the through-holes 520 a , or 520 b .

[0353] and Figure 3A-3G Compared to the integrated circuit 300, the via 520a is similar to the via 320a, and the via 520b is similar to the via 320b, and thus similar detailed descriptions are omitted.

[0354] Via 520a is located between conductor 330e and conductor 332e. Via 520a is configured to electrically couple conductor 330e and conductor 332e together. In some embodiments, via 520a is configured to provide power supply voltage VDD from back side 303b of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000 to front side 303a. For example, in some embodiments, via 520a is configured to provide power supply voltage VDD from conductor 332e to conductor 330e.

[0355] Via 520b is located between conductor 330d and conductor 332d. Via 520b is configured to electrically couple conductor 330d and conductor 332d together. In some embodiments, via 520b is configured to provide reference voltage VSS from back side 303b of integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000 to front side 303a. For example, in some embodiments, via 520b is configured to provide reference voltage VSS from conductor 332d to conductor 330d.

[0356] In some embodiments, via group 520 is adjacent to or directly adjacent to cell group 311. In some embodiments, via group 520 is positioned adjacent to or directly adjacent to cell group 311, thereby further reducing the resistance from conductor group 330 or 332 by reducing the distance between cell group 311 and the corresponding power supply voltage VDD or reference power supply voltage VSS. In some embodiments, integrated circuit 500 has lower resistance than other methods, thereby improving performance.

[0357] In some embodiments, integrated circuit 500 achieves one or more of the advantages discussed herein.

[0358] Other configurations or arrangements of integrated circuit 500 are within the scope of the present disclosure.

[0359] Figure 6A-6B is a corresponding diagram of an integrated circuit 600 according to some embodiments.

[0360] Integrated circuit 600 is manufactured by a corresponding layout design similar to integrated circuit 600 .

[0361] Integrated circuit 600 is an integrated circuit 300 ( Figure 3A-3G ) or integrated circuit 400( Figure 4A-4B ) variant, so similar detailed description is omitted. Figure 4A-4B Compared to the integrated circuit 400 , the integrated circuit 600 includes a different location for the cell group 612 or a different location for the via group 620 , and thus similar detailed descriptions are omitted.

[0362] Integrated circuit 600 includes at least one or more of active area groups 302 and 304 , contact group 306 , contact group 307 , contact group 308 , via group 620 , conductor group 330 , conductor group 332 , substrate 380 , insulating region 382 , cell group 310 , cell group 311 , or cell group 612 .

[0363] and Figure 4A-4B Compared with the integrated circuit 400 , the cell group 612 of the integrated circuit 600 replaces the cell group 312 , and the through-hole group 620 of the integrated circuit 600 replaces the through-hole group 320 , and thus similar detailed descriptions are omitted.

[0364] The cell group 612 includes one or more of the cells 612a or 612b.

[0365] and Figure 3A-3G Compared with the integrated circuit 300, the unit 612a is similar to the unit 312b, and the unit 612b is similar to the unit 312a, so similar detailed descriptions are omitted.

[0366] The unit 612a includes a through hole 620a.

[0367] The unit 612b includes a through hole 620b.

[0368] The through-hole group 620 includes at least one of the through-holes 620 a or 620 b .

[0369] and Figure 3A-3G Compared to the integrated circuit 300, the via 620a is similar to the via 320b, and the via 620b is similar to the via 320a, so similar detailed descriptions are omitted.

[0370] Via 620a is adjacent to unit 311b. Via 620a is located between conductor 330d and conductor 332d. Via 620a is configured to electrically couple conductor 330d and conductor 332d together. In some embodiments, via 620a is configured to provide reference voltage VSS from back side 303b of integrated circuit 300, 400, 600, 600, 700, 800, 900 or 1000 to front side 303a. For example, in some embodiments, via 620a is configured to provide reference voltage VSS from conductor 332d to conductor 330d.

[0371] Via 620b is adjacent to unit 311a. Via 620b is located between conductor 330e and conductor 332e. Via 620b is configured to electrically couple conductor 330e and conductor 332e together. In some embodiments, via 620b is configured to provide power supply voltage VDD from back side 303b of integrated circuit 300, 400, 600, 600, 700, 800, 900 or 1000 to front side 303a. For example, in some embodiments, via 620b is configured to provide power supply voltage VDD from conductor 332e to conductor 330e.

[0372] In some embodiments, the via group 620 is adjacent to or directly adjacent to the cell group 311. In some embodiments, the via group 620 is positioned adjacent to or directly adjacent to the cell group 311, thereby reducing the resistance of the conductor group 330 or 332 by reducing the distance between the cell group 311 and the corresponding power supply voltage VDD or reference power supply voltage VSS. In some embodiments, the integrated circuit 600 has a lower resistance than other methods, thereby improving performance.

[0373] In some embodiments, integrated circuit 600 achieves one or more of the advantages discussed herein.

[0374] Other configurations or arrangements of integrated circuit 600 are within the scope of the present disclosure.

[0375] Figure 7A-7B is a corresponding diagram of integrated circuit 700 according to some embodiments.

[0376] Integrated circuit 700 is manufactured by a corresponding layout design similar to integrated circuit 700 .

[0377] Integrated circuit 700 is an integrated circuit 300 ( Figure 3A-3G ) or integrated circuit 400( Figure 4A-4B ) variants, so similar detailed descriptions are omitted.

[0378] Integrated circuit 700 includes at least one or more of active area groups 302 and 304 , contact group 306 , contact group 307 , contact group 308 , conductor group 330 , conductor group 332 , substrate 380 , insulating region 382 , cell group 310 , or cell group 311 .

[0379] and Figure 4A-4B Compared to the integrated circuit 400, the integrated circuit 700 does not include the via group 320 and the cell group 312, so similar detailed descriptions are omitted. In some embodiments, by not including the via group 320 and the cell group 312, the integrated circuit 700 occupies less area than other methods.

[0380] In some embodiments, integrated circuit 700 achieves one or more of the advantages discussed herein.

[0381] Other configurations or arrangements of integrated circuit 700 are within the scope of the present disclosure.

[0382] Figure 8A-B is a corresponding diagram of integrated circuit 800 according to some embodiments.

[0383] Integrated circuit 800 is manufactured by a corresponding layout design similar to integrated circuit 800 .

[0384] Integrated circuit 800 is an integrated circuit 300 ( Figure 3A-3G ) or integrated circuit 700( Figure 7A-7B ) variant, so similar detailed description is omitted. Figure 7A-7B Compared with the integrated circuit 700, the integrated circuit 800 has rows of different heights (eg, H1 and H2), and thus similar detailed descriptions are omitted. Figure 7A-7B Compared to the integrated circuit 700, the pitches of the conductors 330d-330f and 332d-332f of the integrated circuit 800 are different from those of the corresponding conductors 330a-330c and 332a-332c, and thus similar detailed descriptions are omitted.

[0385] Integrated circuit 800 is manufactured by layout design 100B, and thus similar detailed description is omitted. Integrated circuit 800 includes rows of height H1 and height H2.

[0386] Integrated circuit 800 includes at least one or more of active area groups 302 and 304 , contact group 306 , contact group 307 , contact group 308 , via group 320 , conductor group 330 , conductor group 332 , substrate 380 , insulating region 382 , cell group 310 , cell group 311 .

[0387] and Figure 7A-7BCompared with the integrated circuit 700, the rows 4 and 5 of the integrated circuit 800 have a height H2, so similar detailed description is omitted. In some embodiments, since the height H2 of the rows 4 and 5 is different from the height H1 of the rows 1-3, the integrated circuit 800 has a mixed row design, which includes at least two rows with different heights.

[0388] and Figure 7A-7B Compared with the integrated circuit 700, the conductors 330d-330f of the integrated circuit 800 have a pitch P2a, and the conductors 332d-332f of the integrated circuit 800 have a pitch P2b, and thus similar detailed descriptions are omitted.

[0389] In some embodiments, pitch P2a is different from pitch P1a'.

[0390] In some embodiments, pitch P2b is different from pitch P1b'.

[0391] In some embodiments, because pitch P2a of conductors 330d-330f is different from pitch P1a' of conductors 330a-330c, height H2 of rows 4-5 of integrated circuit 800 is different from height H1 of rows 1-3 of integrated circuit 800 and integrated circuit 800 has mixed row heights.

[0392] In some embodiments, conductors 332d-332f have a pitch P2b that is different from pitch P1b' of conductors 332a-332c, rows 4-5 of integrated circuit 800 have a height H2 that is different from height H1 of rows 1-3 of integrated circuit 800, and integrated circuit 800 has mixed row heights. In some embodiments, by having mixed row heights, integrated circuit 800 occupies less area than other approaches.

[0393] In some embodiments, integrated circuit 800 achieves one or more of the advantages discussed herein.

[0394] Other configurations or arrangements of integrated circuit 800 are within the scope of the present disclosure.

[0395] Figure 9A-9B is a corresponding diagram of integrated circuit 900 according to some embodiments.

[0396] Integrated circuit 900 is manufactured by a corresponding layout design similar to integrated circuit 900 .

[0397] Integrated circuit 900 is an integrated circuit 300 ( Figure 3A-3G )、IC400( Figure 4A-4B ) or integrated circuit 800( Figure 8A-B ) variants, and thus similar detailed descriptions are omitted. For example, integrated circuit 900 replaces integrated circuit 400 ( Figure 4A-4B) features and integrated circuit 800( Figure 8A-B ) is combined with a mixed row height, so similar detailed description is omitted. Figure 4A-4B Compared with the integrated circuit 400, the integrated circuit 900 has rows of different heights (eg, H1 and H2), and thus similar detailed descriptions are omitted. Figure 4A-4B Compared to the integrated circuit 400, the pitches of the conductors 330d-330f and 332d-332f of the integrated circuit 900 are different from those of the corresponding conductors 330a-330c and 332a-332c, and thus similar detailed descriptions are omitted.

[0398] Integrated circuit 900 includes rows of height H1 and height H2.

[0399] In some embodiments, by having mixed row heights, integrated circuit 900 occupies less area than otherwise possible.

[0400] In some embodiments, integrated circuit 900 achieves one or more of the advantages discussed herein.

[0401] Other configurations or arrangements of integrated circuit 900 are within the scope of the present disclosure.

[0402] Figure 10A-10B is a corresponding diagram of integrated circuit 1000 according to some embodiments.

[0403] Integrated circuit 1000 is manufactured by a corresponding layout design similar to integrated circuit 1000 .

[0404] Integrated circuit 1000 is an integrated circuit 300 ( Figure 3A-3G ) or integrated circuit 800( Figure 8A-B ) variants, and thus similar detailed descriptions are omitted. For example, integrated circuit 1000 replaces integrated circuit 300 ( Figure 3A-3G ) features and integrated circuit 800( Figure 8A-B ) is combined with a mixed row height, so similar detailed description is omitted. Figure 3A-3G ), the integrated circuit 1000 has rows of different heights (eg, H1 and H2), and thus similar detailed descriptions are omitted. Figure 3A-3G ), the pitches of the conductors 330d-330f and 332d-332f of the integrated circuit 1000 are different from those of the corresponding conductors 330a-330c and 332a-332c, and thus similar detailed descriptions are omitted.

[0405] Integrated circuit 1000 includes rows of height H1 and height H2.

[0406] In some embodiments, by having mixed row heights, integrated circuit 1000 occupies less area than other approaches.

[0407] In some embodiments, integrated circuit 1000 achieves one or more of the advantages discussed herein.

[0408] Other configurations or arrangements of integrated circuit 1000 are within the scope of the present disclosure.

[0409] Figure 11A-11B is a functional flow chart of corresponding methods 1100A-1100B for manufacturing IC devices according to some embodiments. It should be understood that in Figure 11A-11B Additional operations may be performed before, during, and / or after the methods 1100A-1100B shown in FIG. 1 , and some other processes may only be briefly described herein.

[0410] In some embodiments, other operation sequences of methods 1100A-1300 are within the scope of the present disclosure. Methods 1100A-1300 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, replaced, reordered, and / or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more operations of methods 1100A, 1100B, 1200, or 1300 are not performed.

[0411] In some embodiments, methods 1100A-1100B are embodiments of operation 1204 of method 1200. In some embodiments, methods 1100A-1300 may be used to manufacture or fabricate at least integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000, or an integrated circuit having similar features to layout design 100A, 100B, or 200.

[0412] In operation 1102 of method 1100A, a first set of transistors and a second set of transistors are fabricated on the front side 303a of the semiconductor wafer or substrate. In some embodiments, the first set of transistors of methods 1100A-1100B includes at least one or more transistors in active area group 302. In some embodiments, the second set of transistors of methods 1100A-1100B includes at least one or more transistors in active area group 304. In some embodiments, the first set of transistors or the second set of transistors of methods 1100A-1100B includes one or more transistors described herein.

[0413] In some embodiments, operation 1102 further comprises fabricating source and drain regions of the transistor group in the first well. In some embodiments, the first well comprises a p-type dopant. In some embodiments, the p-type dopant comprises boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well comprises an epitaxial layer grown on a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during an epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after the epitaxial layer is formed. In some embodiments, the first well is formed by doping the substrate. In some embodiments, the doping is performed by ion implantation. In some embodiments, the dopant concentration of the first well is in the range of 1 x 10 12 Atom / cm 3 Up to 1x10 14 Atom / cm 3 .

[0414] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the concentration of the n-type dopant is in the range of about 1 x 10 12 Atom / cm 3 About 1x 10 14 Atom / cm 3 .

[0415] In some embodiments, the formation of the source / drain component includes removing a portion of the substrate to form a recess at the edge of the spacer, and then performing a filling process by filling the recess in the substrate. In some embodiments, after removing the pad oxide layer or the sacrificial oxide layer, the recess is etched, such as wet etching or dry etching. In some embodiments, an etching process is performed to remove a portion of the top surface of the active area adjacent to the isolation region (such as the STI region). In some embodiments, the filling process is performed by epitaxy or epitaxial (epi) process. In some embodiments, the recess is filled using a growth process performed simultaneously with the etching process, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the recess. For example, a layer of material is grown in the recess, and then the grown material is etched to remove part of the material. The etched material is then subjected to a subsequent growth process until the material in the recess reaches a desired thickness. In some embodiments, the growth process continues until the top surface of the material is higher than the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching or other suitable techniques. In some embodiments, semiconductor material is deposited in the recess to form a source / drain component. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the recess. In some embodiments, the epitaxial process includes a selective epitaxial growth (SEG) process, a CVD process, a molecular beam epitaxy (MBE), other suitable processes and / or combinations thereof. The epi process uses gaseous and / or liquid precursors that interact with substrate components. In some embodiments, the source / drain component includes epitaxially grown silicon (epi-Si), silicon carbide or silicon germanium. In some cases, the source / drain component of the IC device associated with the gate structure is in-situ doped or undoped during the epitaxial process. When the source / drain component is undoped during the epitaxial process, in some cases, the source / drain electrode component is doped during a subsequent process. The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes and / or combinations thereof. In some embodiments, after forming the source / drain features and / or after a subsequent doping process, the source / drain features are further exposed to an annealing process.

[0416] In some embodiments, operation 1102 further includes operation 1102a. In some embodiments, operation 1102a includes forming a first active region of a first set of transistors. In some embodiments, the first active region of the first set of transistors of methods 1100A-1100B includes active region set 302.

[0417] In some embodiments, operation 1102 further includes operation 1102b. In some embodiments, operation 1102b includes forming a second active region of the second set of transistors. In some embodiments, the second active region of the second set of transistors of methods 1100A-1100B includes active region group 304.

[0418] In some embodiments, operation 1102 further comprises operation 1102c. In some embodiments, operation 1102c comprises depositing a first conductive material on at least one of the first level or the second level, thereby forming at least one of the corresponding first set of contacts or the second set of contacts. In some embodiments, the first level is an MD level. In some embodiments, the second level is a BMD level.

[0419] In some embodiments, the first set of contacts and the second set of contacts are part of the first set of transistors and the second set of transistors.

[0420] In some embodiments, the first set of contacts includes contact set 306 or 308 .

[0421] In some embodiments, the second set of contacts includes contact set 307 .

[0422] In operation 1103a of method 1100B, at least a first set of conductors on the front side of the substrate are electrically coupled to at least the first set of transistors or the second set of transistors.

[0423] In some embodiments, the first set of conductors on the substrate front side of methods 1100A- 1100B includes one or more conductors in conductor set 330 .

[0424] In operation 1103b of method 1100B, at least a second set of conductors on the back side of the substrate are electrically coupled to at least the first set of transistors.

[0425] In some embodiments, the second set of conductors on the backside of the substrate of methods 1100A- 1100B includes one or more conductors in conductor set 332 .

[0426] Fig. 11B is a functional flow chart of a method 1100B for manufacturing an IC device according to some embodiments. It should be understood that Fig. 11B Additional operations may be performed before, during, and / or after the method 1100B shown in FIG. 110B , and some other processes may only be briefly described herein.

[0427] In some embodiments, method 1100B is an embodiment of operations 1103a and 1103b of method 1100A, and thus similar detailed description is omitted.

[0428] In operation 1104 of method 1100B, a first set of vias is formed on a VD level (eg, VD) on front side 303a of the wafer or substrate. In some embodiments, the first set of vias of method 1100B includes at least one or more portions of via groups 370 or 372 .

[0429] In some embodiments, operation 1104 includes forming a first set of self-aligned contacts (SACs) in an insulating layer over the front side 303a of the wafer. In some embodiments, the first set of vias is electrically coupled to at least the first set of transistors.

[0430] In operation 1106 of method 1100B, a second conductive material is deposited on the front side 303a of the substrate over the first metal layer (eg, M0) to form a first set of conductors on the front side 301a of the wafer or substrate.

[0431] In some embodiments, operation 1106 includes at least depositing a first set of conductive regions on front side 303 a of the integrated circuit. In some embodiments, the first set of conductors of method 1100B includes at least one or more portions of conductor set 330 .

[0432] In some embodiments, operation 1106 is an embodiment of operation 1103a, and thus similar detailed description is omitted.

[0433] In operation 1108 of method 1100B, the back side 303b of the wafer or substrate is thinned. In some embodiments, operation 1108 includes a thinning process performed on the back side 303b of the semiconductor wafer or substrate. In some embodiments, the thinning process includes a grinding operation and a polishing operation (such as chemical mechanical polishing (CMP)) or other suitable processes. In some embodiments, after the thinning process, a wet etching operation is performed to remove defects formed on the back side 303b of the semiconductor wafer or substrate.

[0434] In operation 1110 of method 1100B, a third conductive material is deposited on the second metal layer on the back side 303b of the substrate to form a second set of conductors (eg, BMO) on the back side 303b of the wafer or substrate.

[0435] In some embodiments, operation 1110 includes at least depositing a second set of conductive regions on back side 303 b of integrated circuit. In some embodiments, the second set of conductors of method 1100B includes at least one or more portions of conductor set 332 .

[0436] In some embodiments, operation 1110 is an embodiment of operation 1103b, and thus similar detailed description is omitted.

[0437] In operation 1112 of method 1100B, a second set of vias is formed.

[0438] In operation 1112 of method 1100B, a second set of vias is formed at a V0 level (eg, V0) on the back side 303b of the thinned wafer or substrate. In operation 1112 of method 1100B, a second set of vias is formed at a FTV level (eg, FTV) in the thinned wafer or substrate.

[0439] In some embodiments, the second group of vias of method 1100B includes at least one or more portions of via group 342. In some embodiments, the second group of vias of method 1100B includes at least one or more portions of via groups 320, 520, or 620.

[0440] In some embodiments, operation 1112 includes forming a second set of SACs in the insulating layer on the back side 303b of the wafer. In some embodiments, the second set of vias are electrically coupled to at least the first set of transistors or the second set of transistors.

[0441] In operation 1114 of method 1100B, a fourth conductive material is deposited on the third metal layer on the front side 303a of the substrate to form a third set of conductors on the third metal layer (eg, M1) on the front side 301a of the wafer or substrate.

[0442] In some embodiments, operation 1114 includes depositing a third set of conductive regions on at least front side 303 a of the integrated circuit. In some embodiments, the third set of conductors of method 1100B includes at least one or more portions of conductor set 340 .

[0443] In operation 1116 of method 1100B, a third set of vias is formed at a V1 level (eg, V1) on front side 303a of the wafer or substrate. In some embodiments, the third set of vias of method 1100B includes at least one or more portions of via group 352 .

[0444] In some embodiments, operation 1116 includes forming a third set of SACs in the insulating layer over the front side 303a of the wafer. In some embodiments, the third set of vias is electrically coupled to at least the first set of transistors.

[0445] In operation 1118 of method 1100B, a fifth conductive material is deposited on the fourth metal layer on the back side 303 b of the substrate to form a fourth set of conductors (eg, M2 ) on the back side 303 b of the wafer or substrate.

[0446] In some embodiments, operation 1118 includes at least depositing a fourth set of conductive regions on back side 303 b of integrated circuit. In some embodiments, the fourth set of conductors of method 1100B includes at least one or more portions of conductor set 350 .

[0447] In operation 1120 of method 1100B, a fourth set of vias is formed at level V2 (eg, V2) on back side 303b of the thinned wafer or substrate. In some embodiments, the fourth set of vias of method 1100B includes at least one or more portions of via group 362 .

[0448] In some embodiments, operation 1120 includes forming a fourth set of SACs in the insulating layer on the back side 303b of the wafer. In some embodiments, the fourth set of vias is electrically coupled to at least the first set of transistors or the second set of transistors.

[0449] In operation 1122 of method 1100B, a sixth conductive material is deposited on the fifth metal layer on the front side 303a of the substrate to form a fifth set of conductors on the fifth metal layer (eg, M3) on the front side 301a of the wafer or substrate.

[0450] In some embodiments, operation 1122 includes depositing at least a fifth set of conductive regions on front side 303 a of the integrated circuit. In some embodiments, the fifth set of conductors of method 1100B includes at least one or more portions of conductor set 360 .

[0451] In some embodiments, one or more of operations 1102, 1103a, 1103b, 1104, 1106, 1110, 1112, 1114, 1116, 1118, 1120, or 1122 of methods 1100A-1100B include forming an opening in an insulating layer (not shown) on a substrate using a combination of photolithography and material removal processes. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or another suitable photolithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling, or another suitable etching process. The opening is then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, the opening is filled using CVD, PVD, sputtering, ALD, or other suitable formation processes.

[0452] In some embodiments, at least one or more operations of methods 1100A-1100B are performed by Fig.15 In some embodiments, at least one method, such as the above methods 1100A-1100B, is performed in whole or in part by at least one manufacturing system including the system 1500. One or more operations of the methods 1100A-1100B are performed by an IC manufacturing plant 1540 ( Fig.15) to manufacture IC device 1560. In some embodiments, one or more operations of methods 1100A-1100B are performed by manufacturing tool 1552 to manufacture wafer 1542.

[0453] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, the openings and trenches are filled using CVD, PVD, sputtering, ALD, or other suitable formation processes. In some embodiments, after the conductive material is deposited in one or more of operations 1102c, 1106, 1110, 1114, 1118, or 1122, the conductive material is planarized to provide a flat surface for subsequent steps.

[0454] In some embodiments, one or more operations of methods 1100A, 1100B, 1200, or 1300 are not performed.

[0455] One or more operations of methods 1200-1300 are performed by a processing device configured to execute instructions for manufacturing an integrated circuit, such as at least integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, one or more operations of methods 1200-1300 are performed using the same processing device as used in different one or more operations of methods 1200-1300. In some embodiments, one or more operations of methods 1200-1300 are performed using a different processing device than a processing device used to perform different one or more operations of methods 1200-1300. In some embodiments, other orders of operations of methods 1100A, 1100B, 1200, or 1300 are within the scope of the present disclosure. Methods 1100A, 1100B, 1200, or 1300 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations in methods 1100A, 1100B, 1200, or 1300 may be added, substituted, changed in order, and / or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments.

[0456] Fig.12 is a flow chart of a method 1200 of forming or manufacturing an integrated circuit according to some embodiments. It should be understood that in Fig.12 Additional operations may be performed before, during, and / or after the method 1200 shown in , and some other operations may only be briefly described herein. In some embodiments, the method 1200 may be used to form an integrated circuit, such as at least the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the method 1200 may be used to form an integrated circuit having similar features and similar structural relationships as one or more of the layout designs 100A, 100B, or 200.

[0457] In operation 1202 of method 1200, a layout design of an integrated circuit is generated. Operation 1202 is performed by a processing device (e.g., processor 1402 ( Fig.14 )) is performed. In some embodiments, the layout design of method 1200 includes one or more patterns of layout design 100A, 100B, or 200, or one or more components similar to at least integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. In some embodiments, the layout design of the present application adopts a graphic database system (GDSII) file format. In some embodiments, operation 1202 corresponds to Fig.13 Method 1300.

[0458] In operation 1204 of method 1200, the integrated circuit is manufactured based on the layout design. In some embodiments, operation 1204 of method 1200 includes manufacturing at least one mask based on the layout design, and manufacturing the integrated circuit based on the at least one mask. In some embodiments, operation 1204 corresponds to Fig.11A , Fig. 11B Methods 1100A, 1100B.

[0459] Fig.13 is a flow chart of a method 1300 for generating a layout design for an integrated circuit according to some embodiments. It should be understood that Fig.13 Additional operations are performed before, during, and / or after the illustrated method 1300, and some other processes may only be briefly described herein. In some embodiments, method 1300 is an embodiment of operation 1202 of method 1200. In some embodiments, method 1300 may be used to generate one or more layout patterns of layout design 100A, 100B, or 200, or one or more components similar to at least integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0460] In some embodiments, method 1300 may be used to generate one or more layout patterns having the structural relationships (including arrangement, length, and width) and configuration and layers of layout design 100A, 100B, or 200, or one or more features similar to at least integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000, for simplicity. Fig.13 A similar detailed description will not be described in .

[0461] In operation 1302 of method 1300, a first set of active area patterns is generated or placed on the layout design. In some embodiments, the first set of active area patterns of method 1300 includes at least a portion of one or more patterns of active area pattern group 202. In some embodiments, the first set of active area patterns of method 1300 includes one or more regions similar to active area group 302. In some embodiments, the first set of active area patterns of method 1300 includes one or more patterns in the OD layer or similar patterns.

[0462] In operation 1304 of method 1300, a second set of active area patterns is generated or placed on the layout design. In some embodiments, the second set of active area patterns of method 1300 includes at least a portion of one or more patterns of active area pattern group 204. In some embodiments, the second set of active area patterns of method 1300 includes one or more regions similar to active area group 304. In some embodiments, the second set of active area patterns of method 1300 includes one or more patterns in the OD layer or similar patterns.

[0463] In operation 1306 of method 1300, a first set of contact patterns is generated or placed on the layout design. In some embodiments, the first set of contact patterns of method 1300 includes at least a portion of one or more patterns in contact pattern set 206 or 208. In some embodiments, the first set of contact patterns of method 1300 includes one or more patterns similar to contact set 306 or 308. In some embodiments, the first set of contact patterns of method 1300 includes one or more patterns in an MD layer or similar patterns.

[0464] In operation 1308 of method 1300, a second set of contact patterns is generated or placed on the layout design. In some embodiments, the second set of contact patterns of method 1300 includes at least a portion of one or more patterns of contact pattern set 207. In some embodiments, the second set of contact patterns of method 1300 includes one or more patterns similar to the contact set 307. In some embodiments, the second set of contact patterns of method 1300 includes one or more patterns in a BMD layer or similar patterns.

[0465] In operation 1310 of method 1300, a first set of conductive component patterns is generated or placed on the layout design. In some embodiments, the first set of conductive component patterns of method 1300 includes at least a portion of one or more patterns of conductive component patterns 230. In some embodiments, the first set of conductive component patterns of method 1300 includes one or more patterns similar to conductor set 330. In some embodiments, the first set of conductive component patterns of method 1300 includes one or more patterns in M0 layer or similar patterns.

[0466] In operation 1312 of method 1300, a second set of conductive component patterns is generated or placed on the layout design. In some embodiments, the second set of conductive component patterns of method 1300 includes at least a portion of one or more patterns of conductive component patterns 232. In some embodiments, the second set of conductive component patterns of method 1300 includes one or more patterns similar to conductor set 332. In some embodiments, the second set of conductive component patterns of method 1300 includes one or more patterns in the BMO layer or similar patterns.

[0467] In operation 1314 of method 1300, a first set of via patterns is generated or placed on the layout design. In some embodiments, the first set of via patterns of method 1300 includes at least a portion of one or more patterns of via pattern group 220. In some embodiments, the first set of via patterns of method 1300 includes at least a portion of one or more patterns of unit pattern group 212. In some embodiments, the first set of via patterns of method 1300 includes at least one or more via patterns similar to via groups 320, 520, or 620. In some embodiments, the first set of via patterns of method 1300 includes at least one or more via patterns similar to unit group 312. In some embodiments, the first set of via patterns of method 1300 includes one or more patterns in the FTV layer group or similar vias.

[0468] In operation 1316 of method 1300, a second set of via patterns is generated or placed on the layout design. In some embodiments, the second set of via patterns of method 1300 includes at least a portion of one or more patterns of via pattern 242. In some embodiments, the second set of via patterns of method 1300 includes one or more via patterns at least similar to via group 342. In some embodiments, the second set of via patterns of method 1300 includes one or more patterns in the V0 layer or similar vias.

[0469] In operation 1318 of method 1300, a third set of conductive component patterns is generated or placed on the layout design. In some embodiments, the third set of conductive component patterns of method 1300 includes at least a portion of one or more patterns of at least conductive component pattern 240. In some embodiments, the third set of conductive component patterns of method 1300 includes one or more conductive component patterns at least similar to conductor set 340. In some embodiments, the third set of conductive component patterns of method 1300 includes one or more patterns in the M1 layer or similar conductors.

[0470] In operation 1320 of method 1300, a third set of via patterns is generated or placed on the layout design. In some embodiments, the third set of via patterns of method 1300 includes at least a portion of one or more patterns of via pattern group 252. In some embodiments, the third set of via patterns of method 1300 includes one or more via patterns at least similar to via group 352. In some embodiments, the third set of via patterns of method 1300 includes one or more patterns in the V1 layer or similar vias.

[0471] In operation 1322 of method 1300, a fourth set of conductive component patterns is generated or placed on the layout design. In some embodiments, the fourth set of conductive component patterns of method 1300 includes at least a portion of one or more patterns of at least conductive component pattern 250. In some embodiments, the fourth set of conductive component patterns of method 1300 includes one or more conductive component patterns at least similar to conductor set 350. In some embodiments, the fourth set of conductive component patterns of method 1300 includes one or more patterns in the M2 layer or similar conductors.

[0472] In operation 1324 of method 1300, a fourth set of via patterns is generated or placed on the layout design. In some embodiments, the fourth set of via patterns of method 1300 includes at least a portion of one or more patterns of via pattern group 262. In some embodiments, the fourth set of via patterns of method 1300 includes one or more via patterns at least similar to via group 362. In some embodiments, the fourth set of via patterns of method 1300 includes one or more patterns in the V2 layer or similar vias.

[0473] In operation 1326 of method 1300, a fifth set of conductive component patterns is generated or placed on the layout design. In some embodiments, the fifth set of conductive component patterns of method 1300 includes at least a portion of one or more patterns of at least conductive component pattern group 260. In some embodiments, the fifth set of conductive component patterns of method 1300 includes one or more conductive component patterns at least similar to conductor group 360. In some embodiments, the fifth set of conductive component patterns of method 1300 includes one or more patterns in the M3 layer group or similar conductors.

[0474] Fig.14 is a schematic diagram of a system 1400 for designing an IC layout and fabricating IC circuits according to some embodiments.

[0475] In some embodiments, system 1400 generates or places one or more IC layout designs described herein. System 1400 includes a hardware processor 1402 and a non-transitory computer-readable storage medium 1404 (e.g., memory 1404) encoded with (i.e., stored with) a computer program code 1406, i.e., a set of executable instructions 1406. Computer-readable storage medium 1404 is configured to interface with a manufacturing machine that produces integrated circuits. Processor 1402 is electrically coupled to computer-readable storage medium 1404 via bus 1408. Processor 1402 is also electrically coupled to I / O interface 1410 via bus 1408. Network interface 1412 is also electrically connected to processor 1402 via bus 1408. Network interface 1412 is connected to network 1414 so that processor 1402 and computer-readable storage medium 1404 can be connected to external elements via network 1414. The processor 1402 is configured to execute computer program code 1406 (eg, non-transitory instructions) encoded in the computer-readable storage medium 1404 so that the system 1400 can be used to perform some or all of the operations described in the methods 1200 - 1300 .

[0476] In some embodiments, processor 1402 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0477] In some embodiments, the computer-readable storage medium 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1404 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 1404 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0478] In some embodiments, storage medium 1404 stores computer program code 1406 configured to cause system 1400 to perform methods 1200-1300. In some embodiments, storage medium 1404 also stores information required to perform methods 1200-1300 and information generated during the performance of methods 1200-1300, such as layout design 1416, user interface 1418, and fabrication unit 1420, and / or a set of executable instructions to perform the operations of methods 1200 and 1300. In some implementations, layout design 1416 includes one or more layout patterns of layout design 100A, 100B, or 200, or features similar to at least integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000.

[0479] In some embodiments, storage medium 1404 stores instructions (eg, computer program code 1406) for interfacing with a manufacturing machine. The instructions (eg, computer program code 1406) enable processor 1402 to generate manufacturing instructions readable by a manufacturing machine to effectively implement methods 1200-1300 in a manufacturing process.

[0480] System 1400 includes an I / O interface 1410. I / O interface 1410 is coupled to external circuits. In some embodiments, I / O interface 1410 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor direction keys for transmitting information and commands to processor 1402.

[0481] The system 1400 also includes a network interface 1412 coupled to the processor 1402. The network interface 1412 allows the system 1400 to communicate with a network 1414 to which one or more other computer systems are connected. The network interface 1412 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-2094. In some embodiments, the methods 1200-1300 are implemented in two or more systems 1400, and information such as layout design and user interface is exchanged between different systems 1400 via the network 1414.

[0482] The system 1400 is configured to receive information related to a layout design through the I / O interface 1410 or the network interface 1412. The information is transmitted to the processor 1402 through the bus 1408 to determine a layout design for producing at least the integrated circuit 300, 400, 500, 600, 700, 800, 900, or 1000. The layout design is then stored in the computer-readable storage medium 1404 as a layout design 1416. The system 1400 is configured to receive information related to a user interface through the I / O interface 1410 or the network interface 1412. The information is stored in the computer-readable storage medium 1404 as a user interface 1418. The system 1400 is configured to receive information related to a manufacturing unit 1420 through the I / O interface 1410 or the network interface 1412. The information is stored in the computer-readable storage medium 1404 as a manufacturing unit 1420. In some embodiments, the manufacturing unit 1420 includes manufacturing information used by the system 1400. In some embodiments, manufacturing unit 1420 corresponds to Fig.15 Mask manufacturing 1534.

[0483] In some embodiments, methods 1200-1300 are implemented as a stand-alone software application executed by a processor. In some embodiments, methods 1200-1300 are implemented as a software application that is part of an additional software application. In some embodiments, methods 1200-1300 are implemented as a plug-in to a software application. In some embodiments, methods 1200-1300 are implemented as a software application that is part of an EDA tool. In some embodiments, methods 1200-1300 are implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is stored using a computer readable medium such as that available from CADENCE DESIGN SYSTEMS, INC. 1400 or another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist, which is created based on a schematic design. In some embodiments, methods 1200-1300 are implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system 1400. In some embodiments, system 1400 is a manufacturing device configured to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, Fig.14 The system 1400 generates a layout design for an integrated circuit that is smaller than other methods. In some embodiments, Fig.14The system 1400 generates a layout design of an integrated circuit structure that occupies less area and provides better routing resources than other methods.

[0484] Fig.15 1 is a block diagram of an integrated circuit (IC) manufacturing system 1500 and its associated IC manufacturing process according to at least one embodiment of the present disclosure. In some embodiments, based on the layout diagram, at least one of the following is manufactured using the manufacturing system 1500: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0485] exist Fig.15 In the present invention, an IC manufacturing system 1500 (hereinafter referred to as "system 1500") includes entities, such as a design room 1520, a mask room 1530, and an IC manufacturing plant / manufacturer ("fab") 1540, which interact in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 1560. The entities in system 1500 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or fewer other entities. In some embodiments, one or more of the design room 1520, the mask room 1530, and the IC manufacturing plant 1540 are owned by a single larger company. In some embodiments, one or more of the design room 1520, the mask room 1530, and the IC manufacturing plant 1540 coexist in a common facility and use common resources.

[0486] The design office (or design team) 1520 generates an IC design layout 1522. The IC design layout 1522 includes various geometric patterns designed for the IC device 1560. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 1560 to be manufactured. The layers are combined to form various IC components. For example, a part of the IC design layout 1522 includes various IC components, such as active areas, gate electrodes, source electrodes and drain electrodes, metal lines or through holes for interlayer interconnection, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design company 1520 implements an appropriate design program to form the IC design layout 1522. The design process includes one or more of a logical design, a physical design, or a location and a route. The IC design layout 1522 is presented in one or more data files with geometric pattern information. For example, the IC design layout 1522 can be represented in a GDSII file format or a DFII file format.

[0487] The mask chamber 1530 includes data preparation 1532 and mask manufacturing 1534. The mask chamber 1530 uses the IC design layout 1522 to manufacture one or more masks 1545 for manufacturing various layers of the IC device 1560 according to the IC design layout 1520. The mask chamber 1530 performs mask data preparation 1532, wherein the IC design layout 1522 is converted into a representative data file (RDF). The mask data preparation 1532 provides the RDF to the mask manufacturing 1534. The mask manufacturing 1534 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1545 or a semiconductor wafer 1542. The IC design layout 1522 is manipulated by the mask data preparation 1532 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 1540. In Fig.15 , mask data preparation 1532 and mask manufacturing 1534 are shown as separate elements. In some embodiments, mask data preparation 1532 and mask manufacturing 1534 may be collectively referred to as mask data preparation.

[0488] In some embodiments, mask data preparation 1532 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1522. In some embodiments, mask data preparation 1532 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0489] In some embodiments, mask data preparation 1532 includes a mask rule checker (MRC) that checks the IC design layout processed by OPC using a set of mask creation rules that contain certain geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 1534, which may undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0490] In some embodiments, mask data preparation 1532 includes a lithography process check (LPC), which simulates a process to be performed by IC fabrication plant 1540 to fabricate IC device 1560. LPC simulates the process based on IC design layout 1522 to create a simulated fabricated device, such as IC device 1560. Process parameters in the LPC simulation may include parameters related to various processes of the IC fabrication cycle, parameters related to tools used to fabricate ICs, and / or other aspects of the fabrication process. LPC takes into account various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or combinations thereof. In some embodiments, after LPC creates a simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1522.

[0491] It should be understood that the above description of mask data preparation 1532 has been simplified for the sake of clarity. In some embodiments, data preparation 1532 includes additional features, such as modifying the logic operation (LOP) of the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 1522 during data preparation 1532 can be performed in a variety of different orders.

[0492] After mask data preparation 1532 and during mask fabrication 1534, a mask 1545 or a set of masks 1544 are fabricated based on the modified IC design layout 1522. In some embodiments, mask fabrication 1534 includes performing one or more photolithography exposures based on the IC design layout 1522. In some embodiments, a pattern is formed on a mask (photomask or reticle) 1545 using an electron beam (e-beam) or multiple electron beam mechanisms based on the modified IC design layout 1522. The mask 1545 can be formed using various techniques. In some embodiments, the mask 1545 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, the binary technique of the mask 1545 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque area of ​​the binary mask. In another example, a mask 1545 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1545, various features in the pattern formed on the mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 1534 is used for various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or for other suitable processes.

[0493] IC fabrication plant 1540 is an IC manufacturing entity that includes one or more fabrication facilities for manufacturing a variety of different IC products. In some embodiments, IC fabrication plant 1540 is a semiconductor foundry. For example, there may be one fabrication facility for front-end fabrication of multiple IC products (front-end of line (FEOL) fabrication), while a second fabrication facility may provide back-end fabrication for interconnection and packaging of IC products (back-end of line (BEOL) fabrication"), and a third fabrication facility may provide other services for the foundry entity.

[0494] IC fabrication facility 1540 includes wafer fabrication tools 1552 (hereinafter referred to as "fabrication tools 1552") configured to perform various fabrication operations on semiconductor wafer 1542 to fabricate IC devices 1560 according to masks (e.g., mask 1545). In various embodiments, fabrication tools 1552 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes described herein.

[0495] IC manufacturing plant 1540 uses mask 1545 manufactured by mask chamber 1530 to manufacture IC device 1560. Therefore, IC manufacturing plant 1540 at least indirectly uses IC design layout 1522 to manufacture IC device 1560. In some embodiments, semiconductor wafer 1542 is manufactured by IC manufacturing plant 1540 using mask 1545 to form IC device 1560. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 1522 at least indirectly. Semiconductor wafer 1542 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 1542 also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0496] System 1500 is shown with design room 1520, mask room 1530, or IC fabrication plant 1540 as separate components or entities. However, it should be understood that one or more of design room 1520, mask room 1530, or IC fabrication plant 1540 are part of the same component or entity.

[0497] One aspect of the specification relates to an integrated circuit. In some embodiments, the integrated circuit includes a first unit area, the first unit area including at least a first group of transistors, the first unit area extending in a first direction and having a first height in a second direction different from the first direction. In some embodiments, the first group of transistors includes a first active area extending in the first direction and located on a first level. In some embodiments, the integrated circuit also includes a second unit area, which includes at least a second group of transistors, the second unit area extending in the first direction and having a first height in the second direction. In some embodiments, the second group of transistors includes a second active area extending in the first direction, located on the first level, and separated from the first active area in the second direction. In some embodiments, the integrated circuit also includes a first group of conductors extending in the first direction, located on a first metal layer above the front side of the substrate, overlapping with the first active area or the second active area, and coupled to at least the first group of transistors or the second group of transistors, the first group of conductors being configured to provide at least a power supply voltage or a reference power supply voltage. In some embodiments, the integrated circuit also includes a second group of conductors extending in the first direction, located on a second metal layer below the back side of the substrate, coupled to at least the first group of transistors, and the second group of conductors being configured to provide at least a power supply voltage or a reference power supply voltage. In some embodiments, the first group of transistors has a first size and the second group of transistors has a second size different from the first size.

[0498] In some embodiments, the first group of transistors includes: a first transistor; and a first contact extending in the second direction, overlapping the first active region, and located on a third metal layer different from the first metal layer and the second metal layer, the first contact electrically coupled to a first source of the first transistor.

[0499] In some embodiments, the first group of transistors further includes: a second contact extending in the second direction, overlapping the first active area, and located on a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer, the second contact electrically coupled to the first source of the first transistor.

[0500] In some embodiments, the second group of transistors includes: a second transistor; and a third contact extending in the second direction, overlapping the second active region, and located on the third metal layer, the third contact electrically coupled to the first source of the second transistor.

[0501] In some embodiments, the first active region has a first width in the second direction, the first width being a first size; and the second active region has a second width in the second direction, the second width being a second size and different from the first width.

[0502] In some embodiments, the integrated circuit further includes: a first via located between a first conductor of the first group of conductors and a first conductor of the second group of conductors, the first via being adjacent to the second unit region.

[0503] In some embodiments, the integrated circuit further includes: a second via located between a first conductor of the first group of conductors and a first conductor of the second group of conductors, the second via being adjacent to the first via, and the first via being located between the second via and the second unit region.

[0504] In some embodiments, the integrated circuit also includes: a first conductor extending in the second direction and located on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, the first conductor overlapping the first group of conductors and the second group of conductors; and a first through-hole located between the first conductor and a first conductor in the first group of conductors, the first through-hole electrically coupling the first conductor with the first conductor of the first group of conductors.

[0505] In some embodiments, the integrated circuit also includes: a second conductor extending in the first direction and located on a fourth metal layer above the front side of the substrate, the fourth metal layer being different from the first metal layer, the second metal layer and the third metal layer, the second conductor overlapping the first conductor, the first group of conductors and the second group of conductors; and a second through hole located between the second conductor and the first conductor, the second through hole electrically coupling the second conductor with the first conductor.

[0506] In some embodiments, the integrated circuit further includes: a third conductor extending in the second direction and located on a fifth metal layer above the front side of the substrate, the fifth metal layer being different from the first metal layer, the second metal layer, the third metal layer and the fourth metal layer, the third conductor overlapping the first conductor, the second conductor, the first group of conductors and the second group of conductors; and a third through-hole located between the third conductor and the second conductor, the third through-hole electrically coupling the third conductor with the second conductor.

[0507] Another aspect of the specification relates to an integrated circuit. In some embodiments, the integrated circuit includes a first group of transistors located in a first region, the first region extending in a first direction and having a first height in a second direction different from the first direction. In some embodiments, the first group of transistors includes a first active area extending in the first direction and located on a first level. In some embodiments, the integrated circuit also includes a second group of transistors located in a second region, the second region extending in the first direction and having a second height in the second direction, the second height being different from the first height. In some embodiments, the second group of transistors includes a second active area extending in the first direction, located on the first level, and separated from the first active area in the second direction. In some embodiments, the integrated circuit also includes a first group of conductors extending in the first direction, located on a first metal layer above a front side of the substrate, overlapping the first active area, and coupled to at least the first group of transistors, the first group of conductors being configured to provide at least a power supply voltage or a reference power supply voltage, each conductor in the first group of conductors being separated from each other by a first pitch in the second direction. In some embodiments, the integrated circuit further comprises a second set of conductors extending in the first direction, located on the first metal layer, coupled to at least the second set of transistors, the second set of conductors being configured to at least provide a power supply voltage or a reference power supply voltage, each conductor in the second set of conductors being separated from each other in the second direction by a second pitch, the second pitch being different from the first pitch. In some embodiments, the first set of transistors has a first size, and the second set of transistors has a second size different from the first size.

[0508] In some embodiments, the integrated circuit also includes: a third group of conductors extending in the first direction, located on the second metal layer below the back side of the substrate, and coupled to at least the first group of transistors, the second group of conductors being configured to at least provide a power supply voltage or a reference power supply voltage, each conductor in the third group of conductors being separated from each other in the second direction by a first pitch; and a fourth group of conductors extending in the first direction, located on the second metal layer, and coupled to at least the second group of transistors, the fourth group of conductors being configured to at least provide a power supply voltage or a reference power supply voltage, each conductor in the fourth group of conductors being separated from each other in the second direction by a second pitch, and the fourth group of conductors being separated from the third group of conductors in the second direction.

[0509] In some embodiments, the integrated circuit further includes: a first via located between a first conductor in the second group of conductors and a first conductor in the fourth group of conductors, the first via being adjacent to the second region and electrically coupling the first conductor in the second group of conductors with the first conductor in the fourth group of conductors.

[0510] In some embodiments, the integrated circuit further includes: a second via located between a first conductor in the second group of conductors and a first conductor in the fourth group of conductors, the second via being adjacent to the first via and electrically coupling the first conductor in the second group of conductors with the first conductor in the fourth group of conductors, the first via being located between the second via and the second region.

[0511] In some embodiments, the first group of transistors includes: a first transistor; and a first contact extending in the second direction, overlapping the first active region, and located on a third metal layer different from the first metal layer and the second metal layer, the first contact electrically coupled to a first source of the first transistor.

[0512] In some embodiments, the first group of transistors further includes: a second contact extending in the second direction, overlapping the first active region, and located on a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer, the second contact electrically coupled to the first source of the first transistor.

[0513] In some embodiments, the second group of transistors includes: a second transistor; and a third contact extending in the second direction, overlapping the second active region, and located on the third metal layer, the third contact electrically coupled to the first source of the second transistor.

[0514] In some embodiments, the first active region has a first width in the second direction, the first width being a first size; and the second active region has a second width in the second direction, the second width being a second size and different from the first width.

[0515] In some embodiments, the integrated circuit also includes: a first conductor extending in the second direction and located on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, the first conductor overlapping the first group of conductors and the second group of conductors; and a first through-hole located between the first conductor and a first conductor in the first group of conductors, the first through-hole electrically coupling the first conductor with the first conductor in the first group of conductors.

[0516] Another aspect of the specification relates to a method of forming an integrated circuit. In some embodiments, the method includes manufacturing a first group of transistors in a first row on a front side of a substrate, the first row extending in a first direction, the first group of transistors including at least a first transistor, the first group of transistors having a first size. In some embodiments, the method also includes manufacturing a second group of transistors in a second row on the front side of the substrate, the second row extending in the first direction and separated from the first row in a second direction different from the first direction, the second group of transistors including a second transistor, the second group of transistors having a second size different from the first size. In some embodiments, the method also includes electrically coupling a first group of conductors on the front side of the substrate to at least the first group of transistors or the second group of transistors. In some embodiments, electrically coupling the first group of conductors on the front side of the substrate to at least the first group of transistors or the second group of transistors includes depositing a first conductive material on a first metal layer on the front side of the substrate to form a first group of conductors, the first group of conductors being electrically coupled to at least the first group of transistors or the second group of transistors. In some embodiments, the method also includes electrically coupling a second group of conductors on the back side of the substrate to at least the first group of transistors. In some embodiments, electrically coupling a second set of conductors on the back side of the substrate to at least the first set of transistors includes depositing a second conductive material on a second metal layer on the back side of the substrate to form a second set of conductors, the second set of conductors being electrically coupled to at least the first set of transistors.

[0517] A number of embodiments have been described. However, it should be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. For example, various transistors (e.g., N-type or P-type metal oxide semiconductor (NMOS or PMOS)) shown as specific dopant types are for illustrative purposes. The embodiments of the present disclosure are not limited to specific types. It is within the scope of various embodiments to select different dopant types for specific transistors. The low or high logic values ​​of the various signals used in the above description are also used for illustration. When the signal is activated and / or deactivated, the various embodiments are not limited to specific logic values. It is within the scope of various embodiments to select different logic values. In various embodiments, the transistor is used as a switch. A switch circuit used instead of a transistor is within the scope of various embodiments. In various embodiments, the source of the transistor can be configured as a drain, and the drain can also be configured as a source. Therefore, the terms source and drain can be used interchangeably. Various signals are generated by corresponding circuits, but for simplicity, the circuits are not shown.

[0518] Various figures show capacitive circuits using discrete capacitors. Equivalent circuits can be used. For example, capacitive devices, circuits, or networks (e.g., combinations of capacitors, capacitive elements, devices, circuits, etc.) can be used to replace discrete capacitors. The above illustrations include exemplary operations or steps, but these steps are not necessarily performed in the order shown. According to the spirit and scope of the disclosed embodiments, steps can be appropriately added, replaced, changed in order, and / or eliminated.

[0519] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, comprising: A first unit region includes at least a first group of transistors, the first unit region extends in a first direction and has a first height in a second direction different from the first direction, the first group of transistors includes: a first active region extending along the first direction and located on a first level; A second unit region includes at least a second group of transistors, the second unit region extends in the first direction and has the first height in the second direction, the second group of transistors includes: a second active region extending in the first direction, located on the first level, and separated from the first active region in the second direction; a first set of conductors extending in the first direction, located on a first metal layer over the front side of the substrate, overlapping the first active area or the second active area, and coupled to at least the first group of transistors or the second group of transistors, the first set of conductors being configured to provide at least a power supply voltage or a reference power supply voltage; and a second set of conductors extending in the first direction, located on a second metal layer below the back side of the substrate, coupled to at least the first set of transistors, the second set of conductors being configured to provide at least the power supply voltage or the reference power supply voltage; The first group of transistors has a first size, and the second group of transistors has a second size different from the first size.

2. The integrated circuit according to claim 1, wherein: The first group of transistors includes: a first transistor; and A first contact extends in the second direction, overlaps the first active region, and is located on a third metal layer different from the first metal layer and the second metal layer. The first contact is electrically coupled to a first source of the first transistor.

3. The integrated circuit according to claim 2, wherein: The first set of transistors also includes: A second contact extends in the second direction, overlaps the first active region, and is located on a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer, and is electrically coupled to the first source of the first transistor.

4. The integrated circuit according to claim 1, wherein: The first active region has a first width in the second direction, and the first width is the first size; as well as The second active region has a second width in the second direction, the second width being the second size and different from the first width.

5. The integrated circuit of claim 1 , further comprising: a first conductor extending in the second direction and located on a third metal layer over the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, the first conductor overlapping the first group of conductors and the second group of conductors; as well as The first through hole is located between the first conductor and a first conductor in the first group of conductors, and the first through hole electrically couples the first conductor and the first conductor in the first group of conductors together.

6. The integrated circuit of claim 5, further comprising: a second conductor extending in the first direction and located on a fourth metal layer over the front side of the substrate, the fourth metal layer being different from the first metal layer, the second metal layer and the third metal layer, the second conductor overlapping the first conductor, the first group of conductors and the second group of conductors; as well as The second through hole is located between the second conductor and the first conductor, and the second through hole electrically couples the second conductor and the first conductor together.

7. An integrated circuit comprising: A first group of transistors is located in a first region, the first region extends in a first direction and has a first height in a second direction different from the first direction, the first group of transistors comprising: a first active region extending in the first direction and located on a first level; A second group of transistors is located in a second region, the second region extends in the first direction and has a second height in the second direction, the second height is different from the first height, the second group of transistors comprising: a second active region extending in the first direction, located on the first level, and separated from the first active region in the second direction; a first set of conductors extending in the first direction, located on a first metal layer over the front side of the substrate, overlapping the first active area, and coupled to at least the first set of transistors, the first set of conductors being configured to provide at least a power supply voltage or a reference power supply voltage, each conductor of the first set of conductors being separated from each other by a first pitch in the second direction; and a second group of conductors extending in the first direction, located on the first metal layer, and coupled to at least the second group of transistors, the second group of conductors being configured to at least provide a power supply voltage or a reference power supply voltage, each conductor in the second group of conductors being separated from each other by a second pitch in the second direction, the second pitch being different from the first pitch, The first group of transistors has a first size, and the second group of transistors has a second size different from the first size.

8. The integrated circuit of claim 7, further comprising: a third group of conductors extending in the first direction, located on a second metal layer below the back side of the substrate, coupled to at least the first group of transistors, the second group of conductors being configured to provide at least a power supply voltage or a reference power supply voltage, each conductor in the third group of conductors being separated from each other by a first pitch in the second direction; as well as A fourth group of conductors extends in the first direction, is located on the second metal layer, and is coupled to at least the second group of transistors. The fourth group of conductors is configured to provide at least the power supply voltage or the reference power supply voltage. Each conductor in the fourth group of conductors is separated from each other in the second direction by a second pitch. The fourth group of conductors is separated from the third group of conductors in the second direction.

9. The integrated circuit of claim 8, further comprising: a first conductor extending in the second direction and located on a third metal layer over the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, the first conductor overlapping the first group of conductors and the second group of conductors; as well as The first through hole is located between the first conductor and a first conductor in the first group of conductors, and the first through hole electrically couples the first conductor and the first conductor in the first group of conductors together.

10. A method of forming an integrated circuit, the method comprising: fabricating a first group of transistors in a first row on the front side of the substrate, the first row extending in a first direction, the first group of transistors including at least a first transistor, the first group of transistors having a first size; fabricating a second group of transistors in a second row on the front side of the substrate, the second row extending in the first direction and separated from the first row in a second direction different from the first direction, the second group of transistors including second transistors, the second group of transistors having a second size different from the first size; Electrically coupling a first set of conductors on a front side of the substrate to at least the first set of transistors or the second set of transistors, wherein electrically coupling the first set of conductors on the front side of the substrate to at least the first set of transistors or the second set of transistors comprises: depositing a first conductive material on a first metal layer on the front side of the substrate to form the first set of conductors, the first set of conductors being electrically coupled to at least the first set of transistors or the second set of transistors; and Electrically coupling a second set of conductors on a back side of the substrate to at least the first set of transistors, wherein electrically coupling the second set of conductors on the back side of the substrate to at least the first set of transistors comprises: A second conductive material is deposited on the second metal layer on the back side of the substrate to form the second set of conductors electrically coupled to at least the first set of transistors.

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