DWRR Scheduling Optimization Method for Multi-Terminal Data Transceiving in Wind Farms

Abstract

The present invention discloses a DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm, which is characterized in that it includes: multi-terminals realize real-time data transceiver in the wind farm based on memory management; and clear the management linked list in the memory according to the scheduling bandwidth of the DWRR scheduling algorithm; wherein, the management linked list is used to centrally store real-time data of the same size. Although memory management is efficient and saves memory in data transmission, its recycling is extremely troublesome. The present invention creatively introduces DWRR to clear the management linked list in memory management, enabling the efficient cooperation and mutual support between DWRR and memory management, and further jointly realizing the scheduling optimization of multi-terminal data transceiver in the wind farm.

Description

Technical Field

[0001] This application relates to the technical field of data scheduling optimization, and particularly to a DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm. Background Art

[0002] With the continuous expansion of the scale of wind farms and the improvement of the degree of intelligence, the demand for real-time monitoring and data collection in wind farms is increasing day by day. Each terminal needs to frequently send and receive a large amount of real-time data, such as wind speed, wind direction, blade pitch angle, generator speed, active power output, etc. These data are crucial for optimizing the operating state of wind turbines and improving power generation efficiency.

[0003] In the prior art, in order to fairly allocate resources among multiple tasks or terminals, the DWRR (Deficit Weighted Round Robin) algorithm is usually adopted. This algorithm dynamically adjusts the bandwidth allocation according to the weights and deficits of tasks to achieve fair scheduling among multiple tasks. However, when setting the scheduling bandwidth, the DWRR scheduling algorithm does not consider the actual remaining memory of each terminal, but uses a fixed or memory-status-independent scheduling bandwidth.

[0004] This defect leads to unreasonable scheduling in high-frequency data transceiver scenarios: since the DWRR scheduling algorithm fails to dynamically adjust the scheduling bandwidth according to the memory status of the terminal, too much data may be allocated to the terminal with tight memory, resulting in memory congestion; while the terminal with sufficient memory is not fully utilized, causing unbalanced resource allocation and unable to meet the actual needs of each terminal. Summary of the Invention

[0005] This application provides a DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm to solve the technical problem of insufficient actual memory allocation.

[0006] The present invention adopts the following technical solutions.

[0007] A first aspect of the present invention discloses a DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm, including: multiple terminals realize real-time data transceiver in the wind farm based on memory management; and clear the management linked list in the memory based on the scheduling bandwidth of the DWRR scheduling algorithm; wherein, the management linked list is used to centrally store real-time data of the same size.

[0008] Further, based on the frequency of real-time data, determine the type of real-time data received by each terminal, and initialize the linked list in the terminal based on the size of the real-time data.

[0009] Further, initialize each input parameter of the DWRR scheduling algorithm, including: the number of queues is equal to the sum of the total number of linked lists of each terminal; the weights of all queues are the same; the scheduling bandwidth of each queue is set to the remaining available memory of the linked list corresponding to the queue.

[0010] Further, the remaining available memory of the linked list is equal to the remaining memory in the first terminal minus the memory occupied by all data blocks corresponding to the second queue, and then plus the memory occupied by the data in the second queue; wherein, the first terminal is the terminal where the linked list is located, and the second queue is the set of other queues in the first terminal whose head node values are all less than those of the linked list.

[0011] Further, during the execution of the DWRR algorithm, set the weight of the queue to be proportional to the vacancy rate of the queue; the vacancy rate is the ratio of the actually occupied memory in the queue to the memory of the data block.

[0012] Further, if the scheduling bandwidths of the queues of a certain category are all less than a preset threshold, sort the third queues in descending order of the vacancy rate, and execute step S1 to step S3;

[0013] Step S1, obtain the fourth queue with the highest vacancy rate from the third queues, and remove the fourth queue from the third queues;

[0014] Step S2, perform output merging on all data in the fourth queue, and at the same time empty the data blocks in the linked list corresponding to the fourth queue;

[0015] Step S3, recalculate the scheduling bandwidth of the queues of this category. If the scheduling bandwidths of the queues of this category are all less than the preset threshold, return to step S1; otherwise, the step ends;

[0016] Among them, the categories of queues are distinguished according to the values of the head nodes of the linked lists. The third queues refer to the set of other queues in all terminals whose head node values are all less than those of the queues of a certain category.

[0017] The second aspect of the present invention discloses a terminal, including a processor and a storage medium; characterized in that:

[0018] The storage medium is used to store instructions;

[0019] The processor is used to operate according to the instructions to execute the steps of the method described in the first aspect.

[0020] The third aspect of the present invention discloses a computer-readable storage medium, on which a computer program is stored, characterized in that when the program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0021] Compared with the prior art, the present application has the following beneficial effects:

[0022] (1) Although memory management is efficient and saves memory in data transmission, its recycling is extremely troublesome. The present invention creatively introduces DWRR to clear the management linked list in memory management. DWRR and memory management both play their respective roles and cooperate efficiently, supporting each other, and thus jointly realizing the scheduling optimization of multi-terminal data transceiver in wind farms.

[0023] (2) In the DWRR scheduling algorithm of the present invention, the scheduling bandwidth of each queue is set to be proportional to its actual remaining memory, enabling the scheduler to dynamically adjust the data allocation amount according to the memory status of each terminal. By adjusting the scheduling bandwidth based on the actual remaining memory, it avoids allocating too much data to terminals with insufficient memory, preventing memory congestion; at the same time, it makes full use of terminals with sufficient memory, improving resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0025] Figure 1 is the form of a single data in memory.

[0026] Figure 2 is the form of multiple data in memory.

[0027] Figure 3 is a schematic diagram of multi-terminal data transceiver in wind farms in memory.

[0028] Figure 4A is a schematic diagram of the memory of the first terminal before data transceiver.

[0029] Figure 4B is a schematic diagram of the memory of the first terminal after data transceiver.

[0030] Figure 5 is a flowchart of the DWRR scheduling optimization method for multi-terminal data transceiver in wind farms according to an embodiment of the present invention.

[0031] Through the above drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0033] The DWRR (Deficit Weighted Round Robin) algorithm is a weighted round-robin algorithm for network scheduling, mainly used to fairly allocate bandwidth among multiple tasks sharing network resources. While allocating bandwidth, the DWRR scheduling algorithm dynamically adjusts the resource allocation according to the weights and deficits of the tasks, ensuring efficient and fair resource utilization even when there are differences in bandwidth requirements among different tasks.

[0034] In the application scenario of the present invention, the key consideration is not network congestion in data transmission, but memory congestion in the data transceiver terminals of each wind farm. Therefore, the present invention actually draws on the core principle of the DWRR scheduling algorithm to reasonably achieve traffic scheduling and load balancing among each terminal.

[0035] It can be understood that when dealing with the problem of network congestion, the scheduling bandwidth of each queue can be set to be directly proportional to the current smoothness of the network. Therefore, it is not difficult to imagine and expand that in the application scenario of the present invention, the scheduling bandwidth of each queue can be set to be proportional to the remaining memory of the corresponding terminal. However, this approach is not reasonable during the peak data reception and transmission period. This is because in the usage scenario of the present invention, the remaining memory and the available remaining memory (corresponding to real-time data of different sizes) are actually two completely different concepts.

[0036] To understand the above problem, it is first necessary to clarify the specific form of real-time data reception and transmission in the usage scenario of the present invention. As Figure 1 shown, when receiving a piece of data, the memory space occupied by the data at least includes: two upper and lower cookies, debugger, pad, and data. The cookie is used to record the memory size occupied by the data; the debugger is used for debugging, usually with a size of 0; the pad need not be considered and cannot be improved, and its function is to make the memory space occupied by the data exactly an integer multiple of 8 bytes; the data is the real-time data itself for reception and transmission.

[0037] Among them, the real-time data transmitted and received by multiple terminals in the wind farm can be: wind speed data: used to monitor the change of wind speed to determine the optimal operating state and power generation efficiency of the wind turbine; wind direction data: used to determine the yaw angle of the wind turbine so as to keep the wind turbine facing the wind direction directly and improve the energy capture rate; blade pitch angle data: used to adjust the angle of the wind turbine blades to adapt to different wind speeds and optimize the energy conversion efficiency; generator speed data: to monitor the speed of the generator in real time to ensure its operation within a safe range and avoid efficiency loss or equipment damage caused by overspeed or low speed; active power output data: used to monitor the real-time power output of the wind turbine to analyze the performance of the wind turbine and the system efficiency; reactive power output data: used to balance the reactive power demand of the power grid and ensure the voltage stability of the power system; nacelle temperature data: to monitor the temperature inside the wind turbine nacelle to prevent equipment damage or efficiency reduction caused by overheating; vibration data: to monitor the vibration of the wind turbine tower and nacelle for early warning of potential mechanical failures; power grid frequency data: to monitor the frequency of the power grid to ensure that the output frequency of the wind turbine is consistent with the power grid, thus maintaining the stability of the power system; fault alarm data: to receive the fault alarm information of the wind turbine in real time, including abnormal vibration, overheating, abnormal current, etc., so as to maintain and handle problems in time; and so on.

[0038] These real-time data are usually not large, but the frequency is very high. Therefore, the terminal must manage the memory to reduce the transmission and merging pressure.

[0039] Among them, transmission refers to the data of these real-time data input from the on-site sensors or the unit itself to the terminal, and merging refers to the external output of these real-time data. In the scenario of the present invention, merging usually refers to centrally outputting these real-time data to the database.

[0040] It is not difficult to understand that in memory management, it is usually inclined to merge data of the same size together, thereby reducing the overhead of cookies, which not only serves the purpose of saving memory but also can greatly speed up the transmission and merging speed. As Figure 2 shown.

[0041] On Figure 2 this basis, as Figure 3 shown, first assume that the sizes of the wind speed data d1 and the wind direction data d2 are both 32, the sizes of the blade pitch angle data d3 and the generator speed data d4 are both 16, the sizes of the active power output data d5 and the reactive power output data d6 are both 40, and there are exactly 2 terminals. Then, according to the output frequency, data of the same size can be allocated to the same terminal as much as possible. In Figure 3In this case, taking terminal 1 as an example, position 32 or position 40 can be understood as a management linked list, that is, linked list 32 and linked list 40. 32 or 40 can be regarded as the value of the head node of the linked list. For convenience, the linked list and the management linked list in this article have the same meaning. The management linked list is used to centrally store real-time data of the same size.

[0042] Since cookies are cancelled between data of the same size, usually, data of the same size will group together to form a data block (for example: Figure 2 is a data block with a length of 3, that is, it contains 3 data). Generally, the length of the data block must be a fixed value, usually it can be 20 - 50, depending on the frequency of data sending and receiving. For convenience, Figure 3 the length of the data block in it is drawn as 4, and each data block is equivalent to a node in the linked list.

[0043] After the terminal receives data, it usually needs to store the received data in the database. However, in practice, when a certain terminal receives one or two pieces of data, it will not rush to compete for the control of the database, but wait until a certain type of received data is sufficient, and then store it centrally. In fact, different types but same-sized data can also be stored under the same-length linked list, which results in the data entry and exit logic in the memory not being simply first-in-last-out or first-out-last-in.

[0044] Specifically, taking terminal 1 as an example, as Figure 4A shown, it is not difficult for us to see the first defect of this memory management method, that is: in the reception of a certain real-time data, addresses 32EA2918, 78BC623F, 78BC626F, 78BC629F are used to receive data with a size of 32. On the surface, 78BC623F, 78BC626F, 78BC629F, as empty and continuous small pieces of memory, should be able to store real-time data with a size of at most 96, but in fact they cannot be used. As the data sending and receiving increase, empty small pieces of memory similar to 78BC623F, 78BC626F, 78BC629F may gradually increase, eventually resulting in memory shortage.

[0045] This paragraph further explains "but in fact they cannot be used" in the previous paragraph. When data is continuously received and continuously destroyed, the pointers of each small piece of memory will be completely randomized, which means that you cannot even find 2 continuous empty small pieces of memory in the memory, and thus cannot create data larger than the size of this small piece of memory (but can create data smaller than or equal to the size of this small piece of memory). Taking Figure 4AFor example, on this basis, respectively: create data data21, create data data22, create data data23, destroy data data22, destroy data data5, destroy data data23. The final result will be as Figure 4B shown. It is not difficult to see that only 7 data have been created in total under the linked list 32, and the pointers are already in a complete mess. At this time, in Figure 4B , although the three small memory blocks 78BC623F, 78BC626F, and 78BC629F are all empty, they no longer belong to continuous empty small memory blocks in terms of law. That is to say, although from our perspective as bystanders, they are actually continuous empty small memory blocks, unfortunately, it is extremely difficult for us to prove this: due to the loss of the "protection" of the cookie, when judging the small memory block at, for example, 78BC626F, is it an empty small memory block or a data whose values are all exactly 0? This is extremely difficult to prove. In addition, when the pointers become increasingly chaotic, these data blocks themselves cannot be recycled because they cannot be stripped from the linked list.

[0046] It is understandable that the technical solutions and technical defects mentioned above are all common knowledge. In summary, the essence of overcoming the above problems lies in adjusting the weights of the DWRR scheduling algorithm so that it is truly proportional to the remaining available memory. Based on this, the DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm proposed by the present invention is essentially that multiple terminals realize real-time data transceiver based on memory management; and the scheduling bandwidth based on the DWRR scheduling algorithm clears the management linked list in the memory.

[0047] In some embodiments, not every terminal needs to receive all types of real-time data, that is, the "allocate data of the same size to the same terminal as much as possible" mentioned above. Therefore, the type of real-time data received by each terminal can be determined based on the frequency of the real-time data, and the linked list in the terminal can be initialized based on the size of the real-time data, as Figure 3 shown.

[0048] More specifically, initialize each input parameter of the DWRR scheduling algorithm, including: the number of queues is equal to the sum of the total number of linked lists of each terminal; the weights of all queues are the same; the scheduling bandwidth of each queue is set to the remaining available memory of the linked list corresponding to the queue.

[0049] In some embodiments, the weights of all queues can be initialized to 1.

[0050] Due to the existence of the first defect, the number of queues should not be the number of terminals, but the sum of the total number of linked lists of all terminals. That is, each queue corresponds to a linked list of a certain terminal.

[0051] Based on the above first defect, regarding the scheduling bandwidth of each queue, it is not difficult to infer that: the available memory remaining in the linked list is equal to the memory remaining in the first terminal minus the memory occupied by all data blocks corresponding to the second queue, and then plus the memory occupied by the data in the second queue; where the first terminal is the terminal where the linked list is located, and the second queue is a set of queues within the first terminal where the values of the head nodes are all smaller than those of other queues in the linked list.

[0052] In addition, it is not difficult to infer that during the execution of the DWRR algorithm (i.e., during the data sending and receiving process), if the vacancy rate in a certain queue is relatively high, the weight corresponding to this queue should be increased. Therefore, the weight of the queue can be set to be proportional to the vacancy rate of the queue. Here, the vacancy rate refers to the ratio of the actually occupied memory in the queue to the memory of the data block.

[0053] After all these input parameters are determined, the problem to be considered is how to clear the management linked list in the memory. In the embodiment of the present invention, if the scheduling bandwidth of a certain type of queue is less than a preset threshold, the third queues are sorted in descending order of the vacancy rate, and steps S1 to S3 are executed.

[0054] Step S1, obtain the fourth queue with the highest vacancy rate from the third queue, and remove the fourth queue from the third queue.

[0055] Step S2, perform output merging on all the data in the fourth queue, and at the same time clear the data blocks in the linked list corresponding to the fourth queue.

[0056] Step S3, recalculate the scheduling bandwidth of the queues of this type. If the scheduling bandwidth of the queues of this type is less than the preset threshold, return to Step S1; otherwise, the step ends.

[0057] Among them, the types of queues are distinguished according to the values of the head nodes of the linked list. The third queue refers to a set of other queues within all terminals where the values of the head nodes are all smaller than those of the queues of a certain type. The fourth queue is one of the queues in the third queue with the highest vacancy rate. In the present invention, performing output merging on all the data in the fourth queue may mean that the DWRR algorithm actively competes for the right to use the database based on the scheduling bandwidth, and then clears all the data in the fourth queue from the memory.

[0058] It should be noted that the DWRR scheduling algorithm is a known algorithm. Therefore, in the application scenario of the present invention, only the input parameters of the DWRR scheduling algorithm need to be explained, and the specific changes of each input parameter during the execution process are clarified, then its execution process is determined. Based on this, the execution process of realizing data sending and receiving of multiple terminals in a wind farm based on the DWRR scheduling algorithm will not be elaborated.

[0059] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0060] Furthermore, it should be noted that although the steps in the flowchart are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0061] It should be understood that the above device embodiments are merely illustrative, and the devices of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0062] In addition, unless otherwise specified, in each embodiment of this application, each functional unit / module can be integrated in one unit / module, or each unit / module can exist physically alone, or two or more units / modules can be integrated together. The above integrated unit / module can be implemented in the form of hardware or in the form of a software program module.

[0063] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not conflict, it should be considered as the scope recorded in this specification.

[0064] Other embodiments of the present application will be readily contemplated by those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0065] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm, characterized in that Including: Multiple terminals manage memory to achieve real-time data transceiver of a wind farm; and clear the management linked list in the memory according to the scheduling bandwidth of the DWRR scheduling algorithm; wherein, the management linked list is used to centrally store real-time data of the same size; Initialize each input parameter of the DWRR scheduling algorithm, including: the number of queues is equal to the sum of the total number of linked lists of each terminal; the weights of all queues are the same; the scheduling bandwidth of each queue is set to the available remaining memory of the linked list corresponding to the queue; The available remaining memory of the linked list is equal to the remaining memory in the first terminal minus the memory occupied by all data blocks corresponding to the second queue, and then plus the memory occupied by the data in the second queue; wherein, the first terminal is the terminal where the linked list is located, and the second queue is the set of other queues in the first terminal whose head node values are all smaller than those of the linked list; During the execution of the DWRR algorithm, set the weight of the queue to be proportional to the vacancy rate of the queue; the vacancy rate is the ratio of the actually occupied memory in the queue to the memory of the data block; If the scheduling bandwidths of a certain type of queues are all less than a preset threshold, sort the third queue in descending order according to the vacancy rate, and execute step S1 to step S3; Step S1, obtain the fourth queue with the highest vacancy rate from the third queue, and remove the fourth queue from the third queue; Step S2, perform output merging on all data in the fourth queue, and at the same time clear the data blocks in the linked list corresponding to the fourth queue; Step S3, recalculate the scheduling bandwidth of the queues of this type. If the scheduling bandwidths of the queues of this type are all less than the preset threshold, return to step S1; otherwise, the step ends; Wherein, the types of queues are distinguished according to the values of the head nodes of the linked lists, and the third queue refers to the set of other queues in all terminals whose head node values are all smaller than those of the queues of a certain type.

2. The DWRR scheduling optimization method for multi-terminal data transceiver in a wind farm according to claim 1, characterized in that Determine the type of real-time data received by each terminal based on the frequency of the real-time data, and initialize the linked list in the terminal based on the size of the real-time data.

3. A terminal, including a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is used to operate according to the instructions to execute the steps of the method according to any one of claims 1-2.

4. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method according to any one of claims 1-2.

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