Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a pixel circuit and a light-emitting element, the pixel circuit comprises a driving module, a data writing module, a compensation module and a reset module. The driving module comprises a driving transistor; the data write-in module is connected to the first electrode of the driving transistor; the compensation module is connected between the grid electrode and the second electrode of the driving transistor; the reset module is connected to the grid electrode or the second electrode of the driving transistor; wherein the working process of the pixel circuit comprises a first bias adjustment stage, and the first bias adjustment stage comprises a first stage; in the first stage, the data write-in module and the reset module are turned off, and the compensation module is turned on. According to the technical scheme, different degrees of bias adjustment can be performed on the driving transistor under different gray scales, so that the display uniformity of the display panel is improved.

Description

[0001] This application is a divisional application with the application date of August 25, 2022, application number 202211028570.2, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] A display panel is usually provided with a pixel circuit and a light-emitting element. The driving transistor in the pixel circuit can provide a driving current to the light-emitting element according to the data signal it receives, so as to drive the light-emitting element to emit light, so that the display panel presents a corresponding display picture.

[0004] However, as time goes by, the internal characteristics of the driving transistor in the pixel circuit slowly change, causing the threshold voltage of the driving transistor to drift. In addition, the threshold drift of the driving transistor also varies under different display brightness, thereby affecting the display uniformity of the display panel. Summary of the invention

[0005] The present invention provides a display panel and a display device to improve display abnormalities under different display brightness and improve display uniformity of the display panel.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising:

[0007] Pixel circuit and light emitting element;

[0008] The pixel circuit includes a driving module, a data writing module, a compensation module and a reset module;

[0009] The driving module includes a driving transistor;

[0010] The data writing module is connected to the first electrode of the driving transistor;

[0011] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0012] The reset module is connected to the gate or the second electrode of the driving transistor; wherein,

[0013] The operation process of the pixel circuit includes a first bias adjustment stage, and the first bias adjustment stage includes a first stage;

[0014] In the first stage, the data writing module and the reset module are turned off, and the compensation module is turned on.

[0015] According to another aspect of the present invention, a display device is provided, comprising the above display panel.

[0016] The technical solution of the embodiment of the present invention controls the compensation module to be turned on, and controls the data writing module and the reset module to be turned off in the first stage of bias adjustment, so that the gate potential of the driving transistor carrying the data signal is transmitted to its second electrode, so that the driving transistor can be biased to different degrees for different gray scales, so that the threshold drift phenomenon caused by the voltage difference between the gate of the driving transistor and its second electrode can be improved or eliminated at each gray scale, thereby improving the display uniformity of the display panel and improving the display effect of the display panel.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a structural schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0020] Figure 2 is a structural schematic diagram of another pixel circuit in a display panel provided by an embodiment of the present invention;

[0021] Figure 3 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0022] Figure 4 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0023] Figure 5 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0024] Figure 6 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0025] Figure 7 is a working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0026] Figure 8is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0027] Fig. 9 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0028] Fig.10 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0029] Fig.11 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0030] Fig.12 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0031] Fig.13 is a structural schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0032] Fig.14 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0033] Fig.15 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0034] Fig.16 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0035] Fig.17 This is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention.

[0036] Fig.18 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0037] Fig.19 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0038] Fig. 20 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0039] Fig.21 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0040] Fig. 22 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0041] Fig.23 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0042] Fig.24 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0043] Fig.25 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0044] Fig.26 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] The self-luminous display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor. By providing a data signal to the gate of the driving transistor, the driving transistor converts the data signal into a driving current to drive the light-emitting element to emit light. However, when the driving transistor is turned on, for a PMOS-type driving transistor, there may be a situation where its gate potential is higher than its drain potential, and for an NMOS-type driving transistor, there may be a situation where its gate potential is lower than its drain potential. If this state is maintained for a long time, the ions inside the driving transistor are polarized, and then a built-in electric field is formed inside the driving transistor, causing the threshold voltage of the driving transistor to drift continuously, causing the driving transistor to be biased, thereby affecting the stability of the driving current provided by the driving transistor, and then affecting the light-emitting stability of the light-emitting element.

[0048] In the prior art, a fixed bias adjustment signal is provided to the driving transistor to improve the influence of the bias of the driving transistor on the display effect of the display panel. However, since the data signal provided to the gate of the driving transistor is different at different gray scales, the gate potential of the driving transistor is different, so that the potential difference between the gate and the drain of the driving transistor is different, that is, the bias degree of the driving transistor is different. When the same bias adjustment signal is provided to the driving transistors with different gate-drain potential differences, the recovery speed and recovery degree of the driving transistors with different bias degrees are different. Therefore, only using a fixed bias adjustment signal cannot take into account the different bias conditions of the driving transistors at different gray scales, thereby affecting the display uniformity of the display panel.

[0049] In order to solve the above technical problems, the embodiment of the present invention controls the data writing module and the reset module to be turned off in the first stage of the first bias adjustment stage, and only controls the compensation module to be turned on, so that a path is formed between the gate of the driving transistor and its second electrode, and the gate potential of the driving transistor is loaded to its second electrode. In this way, under different gray scales, the gate potential of the driving transistor is different, and the potential loaded to its second electrode is also different, so that under each gray scale, the gate potential of the driving transistor can be consistent with the potential of its second electrode, so that targeted adjustment can be performed for different bias degrees of the driving transistor under different gray scales.

[0050] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0051] Figure 1 is a schematic structural diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, Figure 2is a schematic diagram of the structure of another pixel circuit in a display panel provided by an embodiment of the present invention, such as Figure 1 As shown in FIG. 2 , the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a driving module 11, a data writing module 12, a compensation module 13 and a reset module 14; the driving module 11 includes a driving transistor T; the data writing module 12 is connected to the first electrode of the driving transistor T; the compensation module 13 is connected between the gate and the second electrode of the driving transistor T; and the reset module 14 is connected to the gate or the second electrode of the driving transistor T. The working process of the pixel circuit 10 includes a first bias adjustment stage, which includes a first stage; in the first stage, the data writing module 12 and the reset module 14 are turned off, and the compensation module 13 is turned on.

[0052] Specifically, the reset module 14 can control the reset signal Vref to be written into the second electrode of the gate of the driving transistor T to reset the gate and / or the second electrode of the driving transistor T to prevent the potential of the gate or the second electrode of the driving transistor T in the previous working cycle from affecting the writing of the data signal Vdata in the next working cycle; the data writing module 12 can control the data signal Vdata to be written into the gate of the driving transistor T; the compensation module 13 can compensate for the threshold voltage Vth of the driving transistor T so that the driving current provided by the driving transistor T to the light-emitting element 20 can be independent of its own threshold voltage. Among them, the time period in which the driving transistor T provides the driving current to the light-emitting element 20 is the light-emitting stage, the data writing module 12 writes the data signal Vdata to the gate of the driving transistor T and the compensation module 11 performs threshold voltage compensation on the driving transistor T is the data writing stage, and the reset module 14 writes the reset signal to the gate of the driving transistor T is the reset stage; that is, the working process of the pixel circuit at least includes the reset stage, the data writing stage and the light-emitting stage, and in a driving cycle of the pixel circuit, the reset stage, the data writing stage and the light-emitting stage are usually performed in sequence, that is, after resetting the driving transistor T in the reset stage, the data writing stage will be entered to write the data signal to the driving transistor T. After the data writing stage is completed, the light-emitting stage will be entered, and the driving transistor T will provide the driving current to the light-emitting element 20 to drive the light-emitting element to emit light; after the light-emitting stage ends, the next driving cycle will be entered. When the pixel circuit 10 passes through the light-emitting phase of the previous driving cycle and before entering the reset phase of the current driving cycle, the gate potential of the driving transistor T carries the data signal of the previous working process, and because the data signals corresponding to the driving transistor T at different gray scales are different, the bias degrees of the driving transistor T at different gray scales are different when the light-emitting phase ends.

[0053] Exemplarily, in the case where the driving transistor T is a PMOS transistor, the gate of the driving transistor is electrically connected to the first node N1, the first electrode of the driving transistor T is electrically connected to the second node N2, and is coupled to the positive power supply PVDD through the second node N2, the second electrode of the driving transistor T is electrically connected to the third node N3, and is coupled to the anode of the light-emitting element 20 through the third node N3, and the cathode of the light-emitting element 20 is electrically connected to the negative power supply PVEE, so that in the light-emitting stage, the potential of the second electrode of the driving transistor T is low, and the higher the display brightness of the light-emitting element 20 is required to present, the higher its grayscale is, and the lower the voltage of the corresponding data signal is; for example, in a white screen, the corresponding The voltage of the corresponding data signal is relatively low, so that the gate potential written to the driving transistor T is relatively low. In the light-emitting stage, the potential difference between the gate of the driving transistor T and the second electrode is relatively small, and the bias degree of the driving transistor T is relatively low at this time; while in the black screen, the voltage of the corresponding data signal is relatively high, so that the gate potential written to the driving transistor T is relatively high. In the light-emitting stage, the potential difference between the gate of the driving transistor T and the second electrode is relatively large, and the bias degree of the driving transistor T is relatively serious at this time; in this way, the bias degrees of the driving transistor T in the black screen and the white screen are different, and different degrees of bias adjustment need to be performed for the black screen and the white screen according to their respective different bias degrees.

[0054] In this embodiment, in the first stage of the first bias adjustment stage, the control compensation module 13 is turned on, and the control data writing module 12 and the reset module 14 are turned off, so that the potential of the gate of the driving transistor T flows to its second electrode. For a white screen, the gate potential of the driving transistor T is relatively low, and the potential loaded to the second electrode is also a relatively low potential. At this time, the potential difference between the gate and the second electrode of the driving transistor is still small; for a black screen, the potential of the gate of the driving transistor is relatively high, and the potential loaded to the second electrode is also a relatively high potential. At this time, the potential difference between the gate and the second electrode of the driving transistor can also be relatively reduced, so that different degrees of bias adjustment can be achieved for different gray scales (i.e., black screens and white screens), so that the driving transistor T can be biased in a targeted manner under each gray scale, thereby improving or eliminating the threshold drift phenomenon caused by the voltage difference between the gate of the driving transistor T and the second electrode, thereby improving the display uniformity of the display panel and improving the display effect of the display panel. Among them, the first bias adjustment stage can be located after the end of the light-emitting stage of the previous driving cycle of the pixel circuit and before the beginning of the reset stage of the current driving cycle. Under the premise of performing different degrees of bias adjustment on the driving transistor in a targeted manner at different gray scales, the embodiment of the present invention does not specifically limit the time period in which the first bias adjustment stage is located in a driving cycle.

[0055] Understandably, Figure 1 and Figure 2The driving transistor T is a PMOS transistor. In the embodiment of the present invention, the driving transistor T may also be an NMOS transistor. Figure 3 or Figure 4 As shown, when the driving transistor T is an NMOS transistor, the second electrode of the driving transistor T is coupled to the positive power supply PVDD, the first electrode of the driving transistor T is coupled to the anode of the light-emitting element 20, and the cathode of the light-emitting element 20 is electrically connected to the negative power supply PVEE; at this time, the potential of the second electrode of the driving transistor T is higher in the light-emitting stage, and the higher the display brightness required to be presented by the light-emitting element 20, the higher its grayscale, and the higher the voltage of the corresponding data signal; for example, under a white screen, the voltage of the corresponding data signal is higher, and the gate potential of the driving transistor T is higher. In the light-emitting stage, the potential difference between the gate of the driving transistor T and its second electrode is still small. At this time, the bias degree of the driving transistor T is relatively low. By controlling the compensation module 13 to be turned on in the first stage of the first bias adjustment stage, And control the data writing module 12 and the reset module 14 to be turned off, so that the potential of the gate of the driving transistor T flows to its second pole, so as to load a higher potential to the second pole of the driving transistor T, so that the potential difference between the gate of the driving transistor T and its second pole remains small; similarly, under the black screen, the voltage of the corresponding data signal is low, the gate potential of the driving transistor T is low, and the potential difference between it and the second pole is large during the light-emitting stage. By controlling the compensation module 13 to be turned on in the first stage of the first bias adjustment stage, and controlling the data writing module 12 and the reset module 14 to be turned off, so that the potential of the gate of the driving transistor T flows to its second pole, so as to load a lower potential to the second pole of the driving transistor T, the potential difference between the gate of the driving transistor and the second pole can also be relatively reduced. In this way, different degrees of bias adjustment can be performed for black and white screens, so that under different grayscales, the driving transistor T can quickly recover to a state tending to be non-biased.

[0056] In an exemplary embodiment, referring to Figure 1-4In any of the accompanying drawings, the reset module 14 can be turned on or off under the control of the scan signal S1, and when the scan signal S1 controls the reset module 14 to be turned on, the reset module 14 can control the reset signal Vref to be written to the gate and / or the second electrode of the driving transistor T to reset the driving transistor T, and when the scan signal S1 controls the reset module 14 to be turned off, the writing of the reset signal Vref can be prevented; at this time, the reset module 14 may include a reset transistor M1, the gate of which can receive the scan signal S1, the first electrode of the reset transistor M1 receives the reset signal Vref, and the second electrode of the reset transistor M1 is electrically connected to the gate or the second electrode of the driving transistor T. The reset transistor M1 may be an NMOS transistor or a PMOS transistor. When the reset transistor M1 is an NMOS transistor, the reset transistor M1 is turned on when the scan signal S1 is at a high level, and the reset transistor M1 is turned off when the scan signal S1 is at a low level. On the contrary, when the reset transistor M1 is a PMOS transistor, the reset transistor M1 is turned on when the scan signal S1 is at a low level, and the reset transistor M1 is turned off when the scan signal S1 is at a high level. The embodiment of the present invention does not specifically limit the type of the reset transistor M1.

[0057] It should be noted that, in the embodiment of the present invention, the reset module 14 can be connected to the gate or the second electrode of the driving transistor T, that is, Figure 1 and 3 As shown, the reset module 14 is connected to the gate of the driving transistor T. At this time, the reset module 14 can directly reset the gate of the driving transistor T. In some special cases, the reset module 14 can also indirectly reset the second electrode of the driving transistor T. At this time, the reset module 14 and the compensation module 13 need to be turned on at the same time; or Figure 2 and 4 As shown, the reset module 14 is connected to the second electrode of the driving transistor T. At this time, the reset module 14 can directly reset the second electrode of the driving transistor T, or indirectly reset the gate of the driving transistor T. At this time, the reset module 14 and the compensation module 13 also need to be turned on at the same time.

[0058] In other embodiments, Figure 5As shown in FIG. 6 , the reset module 14 may also be electrically connected to the gate and the second electrode of the driving transistor T, respectively. In this case, the reset module 14 may include a first reset transistor M11 and a second reset transistor M12. The first electrode of the first reset transistor M11 may receive the reset signal Vref, and the second electrode of the first reset transistor M11 may be electrically connected to the gate of the driving transistor T, so that the first reset transistor M11 can directly reset the gate of the driving transistor T; the first electrode of the second reset transistor M12 may receive the reset signal Vref, and the second electrode of the second reset transistor M12 may be electrically connected to the second electrode of the driving transistor T, so that the second reset transistor M12 can directly reset the first electrode of the driving transistor T. When the gate and the second electrode of the driving transistor T are reset at the same time, and the types of the first reset transistor M11 and the second reset transistor M12 are the same, the gate of the first reset transistor M11 and the gate of the second reset transistor M12 can receive the same scan signal S1, and when the gate and the second electrode of the driving transistor T are reset at different times, or, when the types of the first reset transistor M11 and the second reset transistor M12 are different, the gate of the first reset transistor M11 and the gate of the second reset transistor M12 can receive the scan signals S11 and S12 respectively, and the scan signals S11 and S12 respectively have different opening times for the gate of the first reset transistor M11 and the second reset transistor M12. Among them, the reset signal Vref received by the first reset transistor M11 and the second reset transistor M12 can be the same or different, and the embodiment of the present invention does not specifically limit this.

[0059] For the convenience of description, without any special limitation, the embodiments of the present invention all take the case where the reset module is connected to the gate of the driving transistor T as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0060] Optional, continue to refer to Figure 1-4In any of the accompanying drawings, the data writing module 12 can be turned on or off under the control of the scanning signal S2, and the compensation module 13 can be turned on or off under the control of the scanning signal S3; when the scanning signal S2 controls the data writing module 12 to turn on, and the scanning signal S3 controls the compensation module 13 to also start, the data signal Vdata can be written to the gate of the driving transistor T through the data writing module 12, the driving transistor T, and the compensation module 13 in sequence; and when the scanning signal S2 controls the data writing module 12 to turn off, the writing of the data signal Vdata can be prevented; at this time, the data writing module 12 can include a data writing transistor M2, the gate of the data writing transistor M2 can receive the scanning signal S2, the first electrode of the data writing transistor M2 receives the data signal Vdata, and the second electrode of the data writing transistor M2 is electrically connected to the first electrode of the driving transistor T. The data writing transistor M2 may be an NMOS transistor or a PMOS transistor. When the data writing transistor M2 is an NMOS transistor, the data writing transistor M2 is turned on when the scanning signal S2 is at a high level, and the data writing transistor M2 is turned off when the scanning signal S2 is at a low level. On the contrary, when the data writing transistor M2 is a PMOS transistor, the data writing transistor M2 is turned on when the scanning signal S2 is at a low level, and the data writing transistor M2 is turned off when the scanning signal S2 is at a high level. The embodiment of the present invention does not specifically limit the type of the data writing transistor M2.

[0061] Similarly, the compensation module 13 may include a compensation transistor M3, the gate of which may receive the scan signal S3, the first electrode of the compensation transistor M3 and the second electrode of the driving transistor T being electrically connected to the third node N3, and the second electrode of the compensation transistor M3 and the gate of the driving transistor T being electrically connected to the first node N1. The compensation transistor M3 may be an NMOS transistor or a PMOS transistor. When the compensation transistor M3 is an NMOS transistor, the compensation transistor M3 is turned on when the scan signal S3 is at a high level, and the compensation transistor M3 is turned off when the scan signal S3 is at a low level; on the contrary, when the compensation transistor M3 is a PMOS transistor, the compensation transistor M3 is turned on when the scan signal S3 is at a low level, and the compensation transistor M3 is turned off when the scan signal S3 is at a high level. The embodiment of the present invention does not specifically limit the type of the compensation transistor M3.

[0062] Optional, continue to refer to Figure 1-4In any of the accompanying drawings, the pixel circuit 10 may also include a light-emitting control module 15. The light-emitting control module 15 can be turned on or off under the control of a light-emitting control signal EM. The light-emitting control module 15, the driving transistor T, and the light-emitting element 20 are connected in series between the positive power supply PVDD and the negative power supply PVEE. When the light-emitting control signal EM controls the light-emitting control module 15 to turn on, a current path can be formed between the positive power supply PVDD and the negative power supply PVEE, so that the driving transistor T can provide the driving current generated by it to the light-emitting element 20 to drive the light-emitting element 20 to emit light; and when the light-emitting control signal EM controls the light-emitting control module 15 to turn off, the driving transistor T cannot provide the driving current to the light-emitting element 20, and the light-emitting element 20 does not emit light.

[0063] Exemplarily, the light-emitting control module 15 may include a first light-emitting control transistor M4 and a second light-emitting control transistor M5, wherein the first electrode of the first light-emitting control transistor M4 is electrically connected to the positive power supply PVDD, the second electrode of the first light-emitting control transistor M4 is electrically connected to the first electrode of the driving transistor T and the second node N2, the second light-emitting control transistor M5 is electrically connected to the second electrode of the driving transistor T at a third node N3, and the second light-emitting control transistor M5 is electrically connected to the anode of the light-emitting element 20; when the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are of the same type and are turned on or off at the same time, the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 can receive the same light-emitting control signal EM; and in some special cases, if the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are of different types or one of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 needs to be in a conductive state during the non-light-emitting stage of the light-emitting element 20, the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 need to receive different light-emitting control signals. Taking the first light-emitting control transistor M4 and the second light-emitting control transistor M5 as an example, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 can be both NMOS transistors or PMOS transistors. When the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are both NMOS transistors, when the light-emitting control signal EM is at a high level, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are simultaneously turned on, and when the light-emitting control signal EM is at a low level, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are simultaneously turned off; on the contrary, when the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are both PMOS transistors, when the light-emitting control signal EM is at a low level, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are simultaneously turned on, and when the light-emitting control signal EM is at a high level, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are simultaneously turned off. The embodiment of the present invention does not specifically limit the types of the first light-emitting control transistor M4 and the second light-emitting control transistor M5.

[0064] Optional, continue to refer to Figure 1-4In any of the figures, the pixel circuit 10 may further include an initialization module 16, which is connected to the anode of the light-emitting element 20, so that before the light-emitting element 20 emits light, the anode of the light-emitting element 20 can be initialized and the anode potential of the light-emitting element 20 can be cleared to prevent the anode potential of the light-emitting element 20 in the light-emitting stage of the previous driving cycle from affecting the display luminous brightness of the light-emitting element 20 in the current driving cycle. Wherein, the initialization module 16 can be turned on or off under the control of the scanning signal S4, and when the scanning signal S4 controls the initialization module 16 to turn on, the initialization signal Vini can be written to the anode of the light-emitting element 20 through the initialization module 16 to initialize the anode of the light-emitting element 20, and when the scanning signal S4 controls the initialization module 16 to turn off, the initialization module 16 can prevent the writing of the initialization signal Vini. Wherein, the initialization signal Vini can be the same as or different from the reset signal Vref, and the embodiment of the present invention does not specifically limit this.

[0065] Exemplarily, the initialization module 16 may include an initialization transistor M6, the gate of which may receive the scan signal S4, the first electrode of the initialization transistor M6 may receive the initialization signal Vini, and the second electrode of the initialization transistor M6 may be electrically connected to the anode of the light-emitting element 20. The initialization transistor M6 may be an NMOS transistor or a PMOS transistor. When the initialization transistor M6 is an NMOS transistor, the initialization transistor M6 is turned on when the scan signal S4 is at a high level, and the initialization transistor M6 is turned off when the scan signal S4 is at a low level; on the contrary, when the initialization transistor M6 is a PMOS transistor, the initialization transistor M6 is turned on when the scan signal S4 is at a low level, and the initialization transistor M6 is turned off when the scan signal S4 is at a high level. The embodiment of the present invention does not specifically limit the type of the initialization transistor M6.

[0066] In an optional embodiment, the type of the initialization transistor M6 can be the same as the type of the data writing transistor M2. In this case, since the data writing transistor M2 controls the writing of the data signal Vdata before the light-emitting element 20 emits light, the initialization transistor M6 also initializes the anode of the light-emitting element 20 before the light-emitting element 20 emits light. Therefore, the scanning signal S2 received by the gate of the data writing transistor M2 can be multiplexed as the scanning signal S4 received by the gate of the initialization transistor M6, so that the initialization transistor M6 and the data writing transistor M2 can be turned on or off at the same time.

[0067] In addition, the pixel circuit 10 may further include a storage capacitor C1, which is connected between a fixed power supply (e.g., a positive power supply PVDD or a negative power supply PVEE) and the gate of the driving transistor T. The storage capacitor C1 is used to store the potential of the gate of the driving transistor T (i.e., the first node N1) to ensure that the driving transistor T can continuously provide a driving current to the light-emitting element 20 during the light-emitting stage.

[0068] For ease of description, the working process of the pixel circuit is exemplified by taking the initialization transistor, data writing transistor, driving transistor, first light-emitting control transistor and second light-emitting control transistor as PMOS transistors, and the reset transistor and compensation transistor as NMOS transistors.

[0069] For example, Figure 7 is a working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Figure 1 and Figure 7 As shown, because a certain voltage difference is maintained between the gate and the second electrode of the driving transistor T for a long time in the light-emitting phase of the previous driving cycle, the driving transistor T is in a biased state for a long time. After the light-emitting phase of the previous driving cycle ends and the current driving cycle begins, the light-emitting control signal EM jumps from a low level to a high level, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are both turned off, and the light-emitting element 20 no longer emits light.

[0070] When entering the first stage T11 of the first bias adjustment stage T1 of the current driving cycle, the scanning signal S1 remains at a low level, the reset transistor M1 is turned off, the reset signal Vref is not transmitted to the gate of the driving transistor T, and the gate of the driving transistor T still carries the data signal of the previous driving cycle; the scanning signal S2 is at a high level, the data writing transistor M2 is turned off, and the data signal Vdata is not transmitted to the first electrode of the driving transistor T; the scanning signal S3 jumps from a low level to a high level, the compensation transistor M3 is turned on, and the gate of the driving transistor T is connected to its second electrode, that is, the first node N1 is connected to the third node N3, so that the gate electrode of the driving transistor T is connected to the gate electrode of the driving transistor T. The bit flow to its second pole, so that the potential of the second pole of the driving transistor T approaches its gate potential, reducing the potential difference between the gate of the driving transistor T and its second pole, so that the driving transistor T tends to a non-biased state, preparing for the subsequent working process; because when the compensation transistor M3 is turned on, the gate potential of the driving transistor T carries the data signal Vdata of the previous driving cycle, so when the gate potential of the driving transistor T flows to its second pole, it can be biased according to the data signal provided to the gate of the driving transistor T in the previous driving cycle. , So that under different gray scales, the driving transistor T can be quickly restored to a non-biased state. After the first stage T11 of the first bias adjustment stage T1 ends, the scanning signal S3 will jump to a low level, so that the compensation transistor M3 is turned off.

[0071] After entering the reset phase T2, the scanning signal S1 jumps from a low level to a high level, so that the reset transistor M1 is turned on, and the reset signal Vref is transmitted to the gate of the driving transistor T to reset the gate of the driving transistor T and the storage capacitor C1 to clear the data signal written to the gate of the driving transistor T in the previous driving cycle. At the same time, after writing the reset signal Vref, the gate of the driving transistor T has a lower potential, thereby ensuring that when the data writing transistor M2 provides the data signal Vdata to the first electrode of the driving transistor T, the driving transistor T can be in a conductive state to prepare for the writing of the data signal Vdata. After the reset phase T2 ends, the scanning signal S1 jumps to a low level, and the reset transistor M1 is turned off.

[0072] After entering the data writing stage T3, the scan signal S3 jumps to a high level again, the compensation transistor M3 is turned on again, and at the same time, the scan signal S2 jumps from a high level to a low level, the data writing transistor M2 is turned on, and the data writing transistor M2 controls the data signal Vdata to be written to the first electrode of the driving transistor T, and then sequentially transmitted to the gate of the driving transistor T through the driving transistor T and the compensation transistor M3, until the voltage difference between the gate of the driving transistor T and its first electrode is the threshold voltage Vth of the driving transistor T, the driving transistor T is turned off, and the data signal Vdata is no longer written. At this time, the gate potential VN1 of the driving transistor T is Vdata+Vth. In this stage, the scan signal S4 can also jump to a low level, so that the initialization transistor M6 is turned on, and the initialization transistor M6 transmits the initialization signal Vini to the anode of the light-emitting element 20 to initialize the anode of the light-emitting element 20. After the data writing stage T3 ends, the scan signal S3 jumps to a low level again, the scan signal S2 and the scan signal S4 both jump to a high level, and the compensation transistor M3, the data writing transistor M2, and the initialization transistor M6 are all turned off.

[0073] After entering the light-emitting stage T4, the light-emitting control signal EM jumps from a high level to a low level again, so that the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are both turned on, and a current path is formed between the positive power supply PVDD and the negative power supply PVEE. The first electrode potential of the driving transistor T will become PVDD due to the turning on of the first light-emitting control transistor M4, and the gate potential of the driving transistor T is Vdata+Vth. At this time, the driving current Id generated by the driving transistor T is K*(Vdata-PVDD) 2 , that is, the driving current generated by the driving transistor T is independent of its own threshold voltage, so that the threshold voltage of the driving transistor T can be prevented from affecting the driving current Id generated by it, so that when the driving current Id is provided to the light-emitting element 20, the light-emitting element 20 can emit light accurately. Wherein, K is a coefficient related to the size and material of the driving transistor T, etc.

[0074] It is understandable that the working process of the above-mentioned pixel circuit is only an exemplary working process. Under the premise that the bias adjustment of the driving transistor can be carried out in a targeted manner in the first stage of the first bias adjustment stage, the embodiment of the present invention does not specifically limit the working process of the pixel circuit.

[0075] Optional, continue to refer to Figure 1-4 In any of the figures, the first bias adjustment stage also includes a second stage, and the first stage and the second stage are performed in sequence; wherein, in the second stage, the compensation module 13 is turned off, and the reset module 14 is turned on.

[0076] Specifically, when the compensation module 13 is turned off and the reset module 14 is turned on, the reset signal Vref can be transmitted to the gate or the second electrode of the driving transistor T to reset the gate or the second electrode of the driving transistor T. In the case where the driving transistor T is a PMOS transistor and the reset module 14 is connected to the gate of the driving transistor T, in the light-emitting stage, the gate potential of the driving transistor T is usually higher than the potential of its second electrode, so that the driving transistor T is in a biased state for a long time; in the first stage, the gate potential of the driving transistor T carrying the data signal corresponding to different pictures is input to the second electrode of the driving transistor T, so that the driving transistor T is biased to different degrees according to different pictures, so that the second electrode potential of the driving transistor T and its gate potential tend to be consistent; after the first stage, the second stage is carried out, the compensation module 13 is turned off, and after the reset module 14 is turned on, the reset signal Vref can be written to the driving transistor T. The gate of the driving transistor T is reset to a lower level after the reset signal Vref is written, and since the reset signal Vref is lower than any data signal Vdata, the gate of the driving transistor can be reset to a lower level after the reset signal Vref is written. At this time, since the gate potential originally carrying the data signal Vdata has been input into the second electrode of the driving transistor T, the potential of the second electrode of the driving transistor T is also the potential carrying the data signal Vdata. At this time, the gate potential of the driving transistor T is lower than the potential of its second electrode, which is opposite to the situation that the gate potential of the driving transistor T is higher than the potential of its second electrode during the light emitting stage. Therefore, the bias state of the driving transistor T can be further corrected by reverse biasing the driving transistor, thereby further improving the display effect.

[0077] For example, the reset module 14 and the compensation module 14 are both turned on under the control of a high-level scanning signal, and are turned off under the control of a low-level scanning signal. Figure 8 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, Figure 8 Zhongyu Figure 7 The same points can be referred to above. Figure 7 The description of Figure 8 Zhongyu Figure 7 The differences are described in detail below. Figure 1 and Figure 8As shown, after the first stage T11 of the first bias adjustment stage T1, the second stage T12 of the first bias adjustment stage T1 is performed, so that the scanning signal S3 jumps to a low level, and the scanning signal S1 jumps to a high level, so that the compensation module 13 is turned off under the control of the low level of the scanning signal S3, and the reset module 14 is turned on under the control of the high level of the scanning signal S1, and the reset signal Vref is transmitted to the gate of the driving transistor T through the turned-on reset module 14, so that the gate of the driving transistor T can have a sufficiently low potential, and the gate potential of the driving transistor T will be lower than the potential of its second electrode, thereby achieving the purpose of bias adjustment of the driving transistor T.

[0078] It can be understood that when the signals for controlling the turning on and off of each module are in other situations, the scanning signals, light-emitting control signals, and reset signals can be adjusted as appropriate. The embodiment of the present invention does not make specific limitations on this, provided that the first stage and the second stage of the first bias adjustment stage can be executed sequentially and the reverse bias of the driving transistor can be controlled in the second stage.

[0079] In an optional embodiment, continue to combine with reference Figure 1 and Figure 8 , since in the first stage T11 of the first bias adjustment stage T1, only the compensation module 13 is turned on, so that the gate potential of the driving transistor T flows into its second pole, that is, the potential of the first node N1 flows into the third node N3, and the first node N1 and the second node N3 are not externally connected to other electrical signals, so that this process is similar to the charging and discharging process of the capacitor, and this process is relatively slow. If the gate of the driving transistor T and the potential of its second pole are to be consistent, the first stage T11 of the first bias adjustment stage T1 requires a longer time; and in the second stage T12 of the first bias adjustment stage T1, only the reset module 14 is turned on, so that the external reset signal Vref is input to the gate of the driving transistor T. This process is a writing process of the reset signal Vref of a fixed potential, so that the gate of the driving transistor T can be charged to the reset signal Vref without too much time.

[0080] In addition, since the display brightness of the display panel is related to the driving current provided to the light-emitting element and the light-emitting time of the light-emitting element, that is, when the driving current is constant, the longer the light-emitting time of the light-emitting element in a driving cycle is, the more conducive it is to improve the display brightness of the display panel, and because when the driving cycle of the pixel circuit is constant, the longer the light-emitting time of the light-emitting element is, the shorter the non-light-emitting time needs to be, and in the first bias adjustment stage T1, the light-emitting element 20 does not emit light, that is, the first bias adjustment stage T1 is the non-light-emitting stage of the light-emitting element 20, and the time length of the first bias adjustment stage T1 needs to be shortened as much as possible. In this way, on the basis of ensuring that both the first stage T11 and the second stage T12 can perform good bias adjustment on the driving transistor T, the time length of the first stage T11 can be made greater than the time length of the second stage T12, so as to shorten the time length of the first bias adjustment stage T1 as much as possible, thereby ensuring that the display panel has sufficient display brightness, which is conducive to improving the display effect of the display panel.

[0081] In other embodiments of the present invention, the time length of the first stage may also be shorter than the time length of the second stage. In this case, in the second stage, the reset signal can be fully written to the gate of the driving transistor through the turned-on reset module to fully reset the gate of the driving transistor, thereby being suitable for display modes that have very high requirements for the reset effect.

[0082] It is understandable that if Figure 8 As shown, since the first bias adjustment stage T1 is a non-luminous stage, under the premise of a certain driving cycle of the pixel circuit, when the duration of the non-luminous stage is long, the duration of its luminous stage T4 will be relatively shortened, and the display luminous brightness of the display panel is related to its luminous duration. When the duration of the luminous stage T4 is short, the display luminous brightness of the display panel will be relatively low, thereby affecting the overall display luminous brightness of the display panel. For a display panel operating at a higher frequency, the driving cycle of its pixel circuit is relatively short. When the duration of its non-luminous stage is long, the duration of its luminous stage T4 will be limited to a shorter duration, thereby seriously affecting the display luminous brightness of the display panel. In this way, the second stage T12 can be started at the same time as the first stage T11 ends, that is, the termination time of the first stage T11 and the start time of the second stage T12 are the same time, so as to shorten the duration of the first bias adjustment stage T1 as much as possible, that is, shorten the duration of the non-luminous stage in a driving cycle, so as to relatively increase the duration of the luminous stage T4, thereby facilitating the improvement of the display brightness of the display panel and the improvement of the display effect of the display panel.

[0083] In other embodiments of the present invention, Fig. 9 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Figure 1 and Fig. 9 Since the compensation module 13 is turned on in the first stage T11, the gate of the driving transistor T is connected to its second electrode, and the gate potential of the driving transistor T is input to its second electrode, and the reset module 14 is turned on in the second stage T12, and the reset signal Vref is written to the gate of the driving transistor T, so that the gate of the driving transistor T can have a lower potential. If the start time of the reset module 14 and the compensation module 13 overlaps, the reset signal Vref will be transmitted to the gate of the driving transistor T and the second electrode of the driving transistor T at the same time, so that the gate potential of the driving transistor T cannot be lower than the potential of its second electrode, so that the bias adjustment of the driving transistor T cannot be performed by reverse biasing the driving transistor T. In this way, when the display panel operates at a lower frequency and the driving cycle of the pixel circuit is long enough, the time length of the non-luminous stage in a driving cycle can be appropriately extended, so that the time length of the first bias adjustment stage T1 in the non-luminous stage can be relatively increased. At this time, a first interval stage T01 can be set between the first stage T11 and the second stage T12, so that after the first stage T11 ends, it will not immediately enter the second stage T12, but will enter the second stage T12 after experiencing the first interval T01, so as to ensure that the reset module 14 and the compensation module 13 are not turned on at the same time, and then the driving transistor T can be biased by reverse biasing it.

[0084] Optional, continue to combine references Figure 1 and Fig. 9 , the time length of the first interval stage T01 is shorter than the time length of the first stage T11; and / or, the time length of the first interval stage T01 is shorter than the time length of the second stage T12.

[0085] Specifically, since the first interval stage T01 is set to isolate the first stage T11 and the second stage T12, in the first interval stage T01, the compensation module 13 can be completely turned off, and the process does not need a long time; and the first stage T11 is a process of balancing the potential of the gate of the driving transistor T and its second pole, and the process requires a certain length of time to keep the potential between the gate of the driving transistor T and its second pole consistent; therefore, the time length of the first interval stage T01 can be less than the total time length of the first stage T11, so as to shorten the time length of the first bias adjustment stage T1 as much as possible. Similarly, the second stage T12 is a process of writing the reset signal Vref to the gate of the driving transistor T, and a certain time is required to make the gate of the driving transistor T charged to the reset signal Vref; therefore, the time length of the first interval stage T01 can also be less than the time length of the second stage T12, so as to ensure that the driving transistor T is well biased, and the total time length of the first bias adjustment stage T1 can be shortened as much as possible, thereby improving the display effect of the display panel.

[0086] Optionally, based on the above embodiment, refer to Fig.10 or Fig.11 The pixel circuit 10 further includes a bias adjustment module 17, which is connected to the first electrode or the second electrode of the driving transistor T, and in the first stage, the bias adjustment module 17 is turned off.

[0087] Specifically, the bias adjustment module 17 can provide a bias adjustment signal V0 for the driving transistor T to perform bias adjustment on the driving transistor T. Since the compensation module 13 is turned on in the first stage of the first bias adjustment stage, the gate potential of the driving transistor T is input to its second pole to balance the potential between the gate of the driving transistor T and its second pole, and the driving transistor T is biased in a targeted manner; at this time, the bias adjustment module 17 does not need to provide a bias adjustment signal to the first pole or the second pole of the driving transistor T, so in the first stage, the bias adjustment module 17 is turned off, and only the compensation module 13 is ensured to be turned on.

[0088] In addition, although the compensation module 13 is turned on in the first stage of the first bias adjustment stage, and the bias adjustment of the driving transistor T can be targeted, it is limited by the gate potential of the driving transistor T, so that the bias adjustment is performed only by relying on the gate potential of the driving transistor T to flow to the second pole of the driving transistor T, which cannot meet the higher bias adjustment requirements. At this time, before or after the first stage of the first bias adjustment stage, the bias adjustment module 17 can be controlled to be turned on, and the bias adjustment signal can be provided to the first pole or the second pole of the driving transistor T to bias the driving transistor T, so as to improve the situation where the bias adjustment is insufficient due to relying only on the gate potential of the driving transistor T to flow to the second pole of the driving transistor T, thereby further improving the display uniformity of the display panel, and then improving the display effect of the display panel.

[0089] Exemplarily, the bias adjustment module 17 can be turned on or off under the control of the scanning signal SV, and when the scanning signal SV controls the bias adjustment module 17 to be turned on, the bias adjustment module 17 can directly write the bias adjustment signal V0 to the first electrode or the second electrode of the driving transistor T. In some special cases, the bias adjustment module 17 can also indirectly write the bias adjustment signal V0 to the gate of the driving transistor T. At this time, the bias adjustment module 17 and the compensation module 13 need to be turned on at the same time. Among them, the bias adjustment module 17 can include a bias adjustment transistor M7, the gate of the bias adjustment transistor M7 can receive the scanning signal SV, the first electrode of the bias adjustment transistor M7 receives the bias adjustment signal V0, and the second electrode of the bias adjustment transistor M7 is electrically connected to the first electrode or the second electrode of the driving transistor T. In the embodiment of the present invention, the bias adjustment transistor M7 can be an NMOS transistor or a PMOS transistor. When the bias adjustment transistor M7 is an NMOS transistor, the bias adjustment transistor M7 is turned on when the scan signal SV is at a high level, and the bias adjustment transistor M7 is turned off when the scan signal SV is at a low level; on the contrary, when the bias adjustment transistor M7 is a PMOS transistor, the bias adjustment transistor M7 is turned on when the scan signal SV is at a low level, and the bias adjustment transistor M7 is turned off when the scan signal SV is at a high level. The embodiment of the present invention does not specifically limit the type of the bias adjustment transistor M7.

[0090] It should be noted that Fig.10 and Fig.11 Only the case where the driving transistor T is a PMOS transistor is shown as an example. In this case, when the bias adjustment module 17 is connected to the first electrode of the driving transistor T, the bias adjustment module 17 and the first electrode of the driving transistor T are both coupled to the positive power supply PVDD; and when the bias adjustment module 17 is connected to the first electrode of the driving transistor T, the bias adjustment module 17 and the first electrode of the driving transistor T are both coupled to the anode of the light emitting element 20. In other embodiments of the present invention, such as Fig.12or Fig.13 , the driving transistor T can also be an NMOS transistor. In this case, when the bias adjustment module 17 is connected to the first electrode of the driving transistor T, the bias adjustment module 17 and the first electrode of the driving transistor T are both coupled to the anode of the light-emitting element 20; and when the bias adjustment module 17 is connected to the first electrode of the driving transistor T, the bias adjustment module 17 and the first electrode of the driving transistor T are both coupled to the positive power supply PVDD. The embodiment of the present invention does not specifically limit the type of the driving transistor T. For ease of description, the following takes the driving transistor T as a PMOS transistor as an example to exemplarily illustrate the working process of the pixel circuit of this embodiment.

[0091] For example, the bias adjustment module 17 is turned on under the control of the low-level scanning signal SV, and is turned off under the control of the high-level scanning signal SV. Fig.14 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention. Fig.14 and Figure 7 For similarities, please refer to the above Figure 7 The description of Fig.14 and Figure 7 The differences are described exemplarily. Fig.10 and Fig.14, since the bias adjustment signal V0 is usually a higher level, such as 5V, and the data signal Vdata written to the gate of the driving transistor T is usually a lower level, for example, the data signal Vdata written to the gate of the driving transistor T under a black screen is 3V, which makes it impossible for the bias adjustment signal V0 to be directly written to the gate of the driving transistor T; therefore, the working process of the pixel circuit 10 can also include a second bias adjustment stage T20 located in the time period between the end of the first bias adjustment stage T1 and the beginning of the reset stage T2. In the second bias adjustment stage T20, the bias adjustment module 17 and the compensation module 14 can be controlled to be turned on at the same time, so that the bias adjustment signal V0 can be transmitted to the first electrode, the second electrode and the gate of the driving transistor T in sequence, so that the potentials of the first electrode, the second electrode and the gate of the driving transistor T tend to be consistent, improving or eliminating the phenomenon that the threshold value of the driving transistor T drifts due to the potential difference between the gate of the driving transistor T and its first electrode and second electrode. In this way, in the first bias adjustment stage T1, the compensation module 13 is turned on to balance the potential difference between the gate and the second electrode of the driving transistor T under different screens, so as to achieve the purpose of preliminary bias adjustment of the driving transistor T, and then in the second bias adjustment stage T20, the bias adjustment signal V0 with a higher level is used to further bias adjust the driving transistor T, thereby ensuring that the driving transistor T can be fully bias adjusted, eliminating or improving the phenomenon that the light-emitting accuracy of the light-emitting element 20 driven by the driving transistor T is affected by the long-term voltage difference between the gate and the first electrode or the second electrode of the driving transistor T, thereby improving the display effect of the display panel.

[0092] In addition, continue to combine reference Fig.10 and Fig.14, because in the data writing stage T3, different data signals are provided to the driving transistor T of the pixel circuit 10 according to the display screen of the display panel, and the data signal Vdata is not directly written to the gate of the driving transistor T, but is written to the first electrode of the driving transistor T through the data writing module 12, and is transmitted to the second electrode of the driving transistor T, and then written to the gate of the driving transistor T through the compensation module 13, so at the end of the data writing stage, the first electrode and the second electrode of the driving transistor T both carry the data signal Vdata written in the data writing stage T3, and for different gray scales, the data signal Vdata is different, so that at the end of the data writing stage, the potential of the first electrode and the second electrode of the driving transistor T is different, which will affect the driving current generated in the light emitting stage T4. At this time, the working process of the pixel circuit 10 can also include a third bias adjustment stage T30 located in the time period between the end of the data writing stage T3 and the beginning of the light emitting stage T4. In the third bias adjustment stage T30, the bias adjustment module 17 is turned on, and the data writing module 12, the compensation module 13 and the reset module 14 are all turned off, so that the bias adjustment signal V0 can be transmitted to the first electrode and / or the second electrode of the driving transistor T through the bias adjustment module 17, so that the first electrode and / or the second electrode of the driving transistor T is changed from the data signal Vdata to the bias adjustment signal V0, thereby eliminating or improving the situation in which the driving current generated in the light-emitting stage T4 is affected by the different potentials of the first electrode and the second electrode of the driving transistor T due to the different data signals written under different gray scales.

[0093] It should be noted that Fig.14 This is only an exemplary working process of the pixel circuit in the embodiment of the present invention. In the embodiment of the present invention, under the premise that the bias adjustment of the driving transistor T can be carried out in a targeted manner, the second bias adjustment stage T20 and / or the third bias adjustment stage T30 can be set as appropriate, and the embodiment of the present invention does not make any specific limitation on this.

[0094] Optional, reference Figure 10-13 In any of the figures, the first bias adjustment stage also includes a third stage, and the third stage is performed in sequence with the first stage, or the first stage and the third stage are performed in sequence; wherein, in the third stage, the bias adjustment module 17 is turned on, and the compensation module 13 is turned off.

[0095] For example, Fig.10 Taking the pixel circuit shown in the figure as an example, Fig.15 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.15Although the gate potential of the driving transistor T in the first stage T11 is input to the second electrode thereof to balance the potential difference between the gate of the driving transistor T and the second electrode thereof, the bias adjustment of the driving transistor T can only be performed within a limited range due to the limited gate potential of the driving transistor T. At this time, before the gate potential of the driving transistor T is controlled to be input to its second electrode, that is, before the first stage T11, the third stage T13 can be performed, so that the compensation module 13 is turned off, the bias adjustment module 17 is turned on, and the bias adjustment signal V0 is sequentially input to the first electrode and the second electrode of the driving transistor T through the turned-on bias adjustment module 17, so that the second electrode of the driving transistor T carries the bias adjustment signal V0; after the third stage T13 ends and enters the first stage T11, the compensation module 13 is turned on, the bias adjustment module 17 is turned off, and the gate potential of the driving transistor will flow to its second electrode, so that the second electrode of the driving transistor T carries both the bias adjustment signal V0 and the data signal Vdata related to the gray scale. In this way, the driving transistor T can be biased to different degrees for different gray scales, and the driving transistor T can meet higher bias adjustment requirements, which is beneficial to improving the display effect of the display panel.

[0096] In an optional embodiment, continue to combine with reference Fig.10 and Fig.15 Since the first bias adjustment stage T1 is a non-luminous stage, under the premise that the driving cycle of the pixel circuit is certain, when the time length of the non-luminous stage is long, the time length of its luminous stage T4 will be relatively shortened, thereby affecting the overall display luminous brightness of the display panel, and for a display panel operating at a higher frequency, the driving cycle of its pixel circuit 10 is relatively short. In order to ensure that the display panel has sufficient display brightness, the time length of the non-luminous stage in a driving cycle can be shortened as much as possible. At this time, the first stage T11 can be started at the same time as the third stage T13 ends, that is, the end time of the third stage T13 is the same as the start time of the first stage T11, so as to relatively increase the time length of the luminous stage T4, which is beneficial to improve the display brightness of the display panel and improve the display effect of the display panel.

[0097] In other optional embodiments, Fig.16 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.16 When the third stage T13 and the first stage T11 are performed sequentially, a second interval stage T02 may be included between the end of the third stage T13 and the beginning of the first stage T11.

[0098] Specifically, when the bias adjustment module 17 and the compensation module 14 are turned on at the same time, the bias adjustment signal V0 will be written to the first electrode, the second electrode and the third electrode of the driving transistor T at the same time, thereby affecting the gate potential of the driving transistor T, which may cause the data signal Vdata carried by the gate of the driving transistor T to be cleared, thereby making it impossible to perform different degrees of bias adjustment on the driving transistor T according to different gray scales. In this way, when the display panel operates at a lower frequency and the driving cycle of the pixel circuit is long enough, the time length of the non-luminous stage in a driving cycle can be appropriately increased, that is, the time length of the first bias adjustment stage T1 can be appropriately increased, and there is extra time in the first bias adjustment stage T1 to set the second interval stage T02, and the third stage T13 and the first stage T11 are isolated by the second interval stage T02, that is, after the third stage T13 ends, it will not immediately enter the first stage T11, but will experience the second interval stage T02 before entering the first stage T11, so as to ensure that the bias adjustment module 17 and the compensation module 13 are not turned on at the same time, so that the bias adjustment of the driving transistor T can be carried out in a targeted manner, and higher bias adjustment requirements can be met.

[0099] Optional, continue to combine references Fig.10 and Fig.16 , the time length of the second interval stage T02 is shorter than the time length of the third stage T13; and / or, the time length of the second interval stage T02 is shorter than the time length of the first stage T11.

[0100] Specifically, since the second interval stage T02 is set to isolate the third stage T13 and the first stage T11, in the second interval stage T02, the bias adjustment module 17 can be completely turned off, and the process does not need a long time; and the third stage T13 is a process of providing the bias adjustment signal V0 to the first and second poles of the driving transistor T. In order to make the bias adjustment signal V0 fully written to the first and second poles of the driving transistor T, the process needs to go through a long time; therefore, the time length of the second interval stage T02 should be less than the time length of the third stage T13, so as to shorten the total time length of the first bias adjustment stage T1 as much as possible. Similarly, the first stage T11 is a process of balancing the potential of the gate of the driving transistor T and its second pole, and the process requires a certain time length to keep the potential between the gate of the driving transistor T and its second pole consistent; therefore, the time length of the second interval stage T02 should be less than the time length of the first stage T11, so as to shorten the time length of the first bias adjustment stage T1 as much as possible.

[0101] In other exemplary embodiments, Fig.17 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.17In the first stage T11, the gate potential of the driving transistor T is input to its second electrode to balance the potential difference between the gate of the driving transistor T and its second electrode. In the first stage T11, although the potential difference between the gate of the driving transistor T and its second electrode can be balanced, the bias adjustment of the driving transistor T is limited; at this time, after the first stage T11, the third stage T13 can be entered, so that the bias adjustment signal V0 is written to the second electrode of the driving transistor T, and the bias adjustment signal V0 is usually a signal of a higher level, so that after the bias adjustment signal V0 is written to the second electrode of the driving transistor T, the potential of the second electrode of the driving transistor T will be higher than its gate potential, which is opposite to the situation in which the gate potential of the driving transistor T is higher than the potential of its second electrode in the light-emitting stage T4, so that the driving transistor T can be quickly restored to a non-biased state.

[0102] In an optional embodiment, continue to combine with reference Fig.10 and Fig.17 Since the first bias adjustment stage T1 is a non-luminous stage, under the premise that the driving cycle of the pixel circuit is certain, when the time length of the non-luminous stage is long, the time length of its luminous stage T4 will be relatively shortened, thereby affecting the overall display luminous brightness of the display panel, and for a display panel operating at a higher frequency, the driving cycle of its pixel circuit 10 is relatively short. In order to ensure that the display panel has sufficient display brightness, the time length of the non-luminous stage in a driving cycle can be shortened as much as possible. At this time, the third stage T13 can be started at the same time as the first stage T11 ends, that is, the end time of the first stage T11 and the start time of the third stage T13 are the same time, so as to relatively increase the time length of the luminous stage T4, which is beneficial to improve the display brightness of the display panel and improve the display effect of the display panel.

[0103] In other optional embodiments, Fig.18 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.18 When the first stage T11 and the third stage T13 are performed sequentially, a third interval stage T03 may be included between the end of the first stage T11 and the beginning of the third stage T13.

[0104] In this way, when the display panel operates at a lower frequency and the driving cycle of the pixel circuit is long enough, the time length of the non-luminous stage in a driving cycle can be appropriately increased, that is, the time length of the first bias adjustment stage T1 can be appropriately increased. There is extra time in the first bias adjustment stage T1 to set the third interval stage T03, and the first stage T11 and the third stage T13 are isolated by the third interval stage T03, that is, after the first stage T11 ends, it will not immediately enter the third stage T13, but will enter the third stage T13 after experiencing the third interval stage T03, so as to ensure that the first stage T11 and the third stage T13 do not affect each other.

[0105] Optional, continue to combine references Fig.10 and Fig.16 , the time length of the third interval stage T03 is shorter than the time length of the first stage T11; and / or, the time length of the third interval stage T03 is shorter than the time length of the third stage T13.

[0106] Among them, since the third interval stage T03 is set to isolate the first stage T11 and the third stage T13, the time length of the third interval stage T03 does not need to be longer; at this time, by making the time length of the third interval stage T03 shorter than the time length of the first stage T11; and / or the time length of the third interval stage T03 shorter than the time length of the third stage T13, the total time length of the first bias adjustment stage T1 is shortened as much as possible under the premise of ensuring that the first stage T11 and the third stage T13 do not affect each other.

[0107] It can be understood that, since in the first stage T11, only the compensation module 13 is turned on, so that the gate potential of the driving transistor T flows into its second pole, that is, the potential of the first node N1 flows into the third node N3, and the first node N1 and the second node N3 are not externally connected to other electrical signals, so that this process is similar to the charging and discharging process of the capacitor, and this process is relatively slow. If the gate potential of the driving transistor T and its second pole are to be consistent, the first stage T11 of the first bias adjustment stage T1 requires a longer time; and in the third stage T13, only the bias adjustment module 17 is turned on, so that the external bias adjustment signal V0 is input to the gate of the driving transistor T. This process is a writing process of the fixed potential bias adjustment signal V0, so that the process does not take too long to charge the first and second poles of the driving transistor T to the bias adjustment signal V0. In this way, on the basis of ensuring that both the first stage T11 and the third stage T13 can perform good bias adjustment on the driving transistor T, the time length of the first stage T11 can be made greater than the time length of the third stage T13, so as to shorten the time length of the first bias adjustment stage T1 as much as possible, thereby ensuring that the display panel has sufficient display brightness, which is beneficial to improving the display effect of the display panel.

[0108] In other embodiments of the present invention, the time length of the first stage may also be shorter than the time length of the third stage. At this time, in the third stage, the bias adjustment signal can be fully written to the first and second electrodes of the driving transistor through the turned-on bias adjustment module to fully bias the first and second electrodes of the driving transistor T, thereby being suitable for display modes that have very high requirements for the bias adjustment effect.

[0109] It can be understood that the above only exemplifies the situations in which the first bias adjustment stage only includes the first stage, or the first bias adjustment stage includes both the first stage and the second stage, or the first bias adjustment stage includes both the first stage and the third stage. In other embodiments of the present invention, the first bias adjustment stage may include the first stage, the second stage and the third stage at the same time.

[0110] Optional, continue to refer to Figure 10-13 In any of the accompanying drawings, when the first bias adjustment stage includes the first stage, the second stage and the third stage at the same time, the third stage, the first stage and the second stage can be performed in sequence; wherein, in the first stage, the bias adjustment module 17, the data writing module 12 and the reset module 14 are turned off, and the compensation module 13 is turned on; in the second stage, the compensation module 13 is turned off, and the reset module 14 is turned on; in the third stage, the bias adjustment module 17 is turned on, and the compensation module 13 is turned off; the first interval stage is included from the end of the first stage to the beginning of the second stage, and the second interval stage is included from the end of the third stage to the beginning of the first stage; and when the time length of the first interval stage is t1 and the time length of the second interval stage is t2, t1≠t2.

[0111] For example, continue with Fig.10 Taking the pixel circuit shown in the figure as an example, Fig.19 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.19, the third stage T13 of the first bias adjustment stage T1 is located before the first stage T11, and the first stage T11 is located before the second stage T12. In the third stage T13, the bias adjustment module 17 is turned on, and the bias adjustment signal V0 is sequentially input to the first and second electrodes of the driving transistor T through the turned-on bias adjustment module 17, so that the second electrode of the driving transistor T carries the bias adjustment signal V0; after the third stage T13 ends and enters the first stage T11, the compensation module 13 is turned on, the bias adjustment module 17 is turned off, and the gate potential of the driving transistor will flow to its second electrode, so that the second electrode of the driving transistor T carries both the bias adjustment signal V0 and the data signal Vdata related to the grayscale; after the first stage T11 ends and enters the second stage T12, the compensation module 13 is turned off, and after the reset module 14 is turned on, the reset signal Vref can be written to the gate of the driving transistor T, so that the gate of the driving transistor is reset to a lower level. At this time, the gate potential of the driving transistor T is lower than the potential of its second electrode, so that the bias state of the driving transistor T can be further corrected. In this way, by sequentially performing the third stage T13 , the first stage T11 , and the second stage T12 , a higher bias adjustment requirement can be met, thereby further improving the display effect of the display panel.

[0112] In addition, by setting the second interval stage T02 between the third stage T13 and the first stage T11, the third stage T13 and the first stage T11 can be made not to affect each other; at the same time, by setting the first interval stage T01 between the first stage T11 and the second stage T12, the first stage T11 and the second stage T12 can be made not to affect each other, so that under the premise of targeted bias adjustment of the driving transistor T, higher bias adjustment requirements can be met. Among them, the time length t1 of the first interval stage T01 can be the same as or different from the time length t2 of the second interval stage T02. When the time length t1 of the first interval stage T01 is different from the time length t2 of the second interval stage T02, the time length t1 of the first interval stage T01 and the time length t2 of the second interval stage T02 can be set separately as needed.

[0113] In an optional embodiment, when the time length t1 of the first interval stage T01 is different from the time length t2 of the second interval stage T02, the time length t1 of the first interval stage T01 may be smaller than the time length t2 of the second interval stage T02, that is, t1<t2.

[0114] In other optional embodiments of the present invention, when the time length t1 of the first interval stage T01 is different from the time length t2 of the second interval stage T02, the time length t1 of the first interval stage T01 may also be greater than the time length t2 of the second interval stage T02, that is, t1>t2. The embodiment of the present invention does not specifically limit the relationship between the time length t1 of the first interval stage T01 and the time length t2 of the second interval stage T02.

[0115] It is understandable that when the first bias adjustment stage includes the first stage, the second stage and the third stage at the same time, the order of the first stage, the second stage and the third stage can be interchanged, and the embodiment of the present invention does not specifically limit this.

[0116] In an optional embodiment, continue to refer to Figure 10-13 In any of the accompanying drawings, when the first bias adjustment stage includes the first stage, the second stage and the third stage at the same time, and in the first stage, the bias adjustment module 17, the data writing module 12 and the reset module 14 are turned off, and the compensation module 13 is turned on, and in the second stage, the compensation module 13 is turned off, and the reset module 14 is turned on, and in the third stage, the bias adjustment module 17 is turned on, and the compensation module 13 is turned off, the first stage, the third stage, and the second stage can be performed in sequence; wherein, a third interval stage can also be included between the end of the first stage and the beginning of the third stage, and a fourth interval stage can also be included between the end of the third stage and the beginning of the second stage, and when the time length of the third interval stage is t3 and the time length of the fourth interval stage is t4, t3≠t4 can be made.

[0117] Specifically, continue with Fig.10 Taking the pixel circuit shown in the figure as an example, Fig. 20 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig. 20, the first stage T11 of the first bias adjustment stage T1 is located before the third stage T13, and the third stage T13 is located before the second stage T12. In the first stage T11, the compensation module 13 is turned on, and the gate potential of the driving transistor will flow to its second electrode, so as to balance the potential difference between the gate of the driving transistor T and its second electrode for different gray scales, so that at the end of the first stage T11, the gate and the second electrode of the driving transistor T both carry data signals; after the first stage T11 ends and enters the third stage T13, the compensation module 13 is turned off, the bias adjustment module 17 is turned on, and the bias adjustment signal V0 is sequentially input to the first electrode and the second electrode of the driving transistor T through the turned-on bias adjustment module 17, so that the second electrode of the driving transistor T has a higher level of the bias adjustment signal V0, and at this time, the gate of the driving transistor T also No other signals are written, and the driving transistor T is a lower potential carrying the data signal, so that the gate potential of the driving transistor T is lower than its second-node potential, so that the driving transistor T is reverse biased. Under the action of the reverse bias, the driving transistor T can further tend to a non-biased state; after the third stage T13 ends and enters the second stage T12, the bias adjustment module 17 is turned off, and after the reset module 14 is turned on, the reset signal Vref can be written to the gate of the driving transistor T, so that the gate of the driving transistor is reset to a lower level. At this time, the gate potential of the driving transistor T will be further lower than the potential of its second pole, so that the bias state of the driving transistor T can be further corrected. In this way, by sequentially performing the first stage T11, the third stage T13 and the second stage T12, a higher bias adjustment requirement can be met, so that the display effect of the display panel is further improved.

[0118] In addition, by setting the third interval stage T03 between the first stage T11 and the third stage T13, the first stage T11 and the third stage T13 can be made not to affect each other; at the same time, by setting the fourth interval stage T04 between the third stage T13 and the second stage T12, the third stage T13 and the second stage T12 can be made not to affect each other, so that under the premise of targeted bias adjustment of the driving transistor T, higher bias adjustment requirements can be met. Among them, the time length t3 of the third interval stage T03 can be the same as or different from the time length t4 of the fourth interval stage T04. When the time length t3 of the third interval stage T03 is different from the time length t4 of the fourth interval stage T04, the time length t3 of the third interval stage T03 can be set separately according to needs. It can be set to the time length t4 of the fourth interval stage T04.

[0119] In an optional embodiment, when the time length t3 of the third interval stage T03 may be different from the time length t4 of the fourth interval stage T04, the time length t3 of the third interval stage T03 may be smaller than the time length t4 of the fourth interval stage T04, that is, t3<t4.

[0120] In other optional embodiments of the present invention, when the time length t3 of the third interval stage T03 may be different from the time length t4 of the fourth interval stage T04, the time length t3 of the third interval stage T03 may also be greater than the time length t4 of the fourth interval stage T04, that is, t3>t4. The embodiment of the present invention does not specifically limit the size relationship between the time length t3 of the third interval stage T03 and the time length t4 of the fourth interval stage T04.

[0121] It can be understood that, for the case where the third stage, the first stage, and the second stage are performed in sequence, a first interval stage is provided between the first stage and the second stage, and a second interval stage is provided between the third stage and the first stage, and, for the case where the first stage, the third stage, and the second stage are performed in sequence, a third interval stage is provided between the first stage and the third stage, and a fourth interval stage is provided between the third stage and the second stage, that is, an interval stage is provided between two adjacent stages of the first bias adjustment stage, so that the two adjacent stages are isolated from each other. In this way, for a display panel operating at a lower frequency, a better bias adjustment effect can be achieved. However, for a display panel operating at a higher frequency, the time of the first bias adjustment stage needs to be further limited.

[0122] Optional, continue to refer to Figure 10-13 In any of the figures, the first bias adjustment stage includes the first stage, the second stage and the third stage at the same time, and in the first stage, the bias adjustment module 17, the data writing module 12 and the reset module 14 are turned off, and the compensation module 13 is turned on. In the second stage, the compensation module 13 is turned off and the reset module 14 is turned on. In the third stage, the bias adjustment module 17 is turned on and the compensation module 13 is turned off. At least part of the time of the second stage overlaps with that of the third stage.

[0123] For example, Fig.10 Taking the pixel circuit shown in the figure as an example, Fig.21 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.21The third stage T13 and the second stage T12 have an overlapping time T05. During the overlapping time T05, the bias adjustment module 17 and the reset module 14 are turned on at the same time, that is, the process of the reset module 14 writing the reset signal to the gate of the driving transistor T and the process of the bias adjustment module 17 writing the bias adjustment signal V0 to the first and second electrodes of the driving transistor T are carried out simultaneously, and because the compensation module 14 is in the off state at this time, the gate reset of the driving transistor T and the bias adjustment process of the first and second electrodes of the driving transistor T do not affect each other. In this way, under the premise that the time length of the third stage T13 and the second stage T12 is certain, by making the third stage T13 overlap with the second stage T12 at least partially, the total time of the first bias adjustment stage T1 can be shortened, which is beneficial to shorten the time length of the non-luminous stage, and then the display brightness of the display panel can be improved; or, under the premise that the time length of the first bias adjustment stage T1 is certain, by making the third stage T13 overlap with the second stage T12 at least partially, the time length of the third stage T13 and / or the second stage T12 can be relatively increased, thereby meeting higher bias adjustment requirements.

[0124] In an optional embodiment, when the second stage T12 overlaps with at least part of the third stage T13, the start time of the second stage T12 can be the same as or earlier than the start time of the third stage T13; and / or, the end time of the second stage T12 can be the same as or later than the end time of the third stage T13.

[0125] For example, Fig. 22 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig. 22 , the start time of the second stage T12 is the same as the start time of the third stage T13, and the end time of the second stage T12 is later than the end time of the third stage T13. At this time, the third stage T13 will be entered at the same time as the second stage T12, so that the reset signal Vref is written into the gate of the driving transistor T, and the bias adjustment signal V0 is written into the first and second poles of the driving transistor T at the same time; at the same time, since the end time of the second stage T12 is later than the end time of the third stage T13, that is, when the bias adjustment module 17 is turned off and stops writing the bias adjustment signal V0 to the first and second poles of the driving transistor T, the reset module 14 will still remain in the on state, so that the reset signal Vref continues to be written, so as to ensure that the gate of the driving transistor T can be fully reset, so that the gate potential of the driving transistor T is much lower than its second pole potential, and ensure that the driving transistor T can quickly recover to the non-biased state. In this way, the time length of the second stage T12 will be greater than the time length of the third stage T13.

[0126] In another exemplary embodiment, Fig.23 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.23 , the start time of the second stage T12 is earlier than the start time of the third stage T13, and the end time of the second stage T12 is the same as the end time of the third stage T13. At this time, after entering the second stage T12, the reset module 14 will first write the reset signal Vref to the gate of the driving transistor T, reset the gate of the driving transistor T, and enter the third stage T13 after a period of reset; at this time, the bias adjustment module 17 and the reset module 14 are turned on at the same time, so that the reset signal Vref continues to be charged into the gate of the driving transistor T, and at the same time, the bias adjustment signal V0 is written into the first and second poles of the driving transistor T; at the end of the second stage T12, the third stage T13 ends synchronously, and the writing of signals to the gate, the first pole and the second pole of the driving transistor T is stopped at the same time. In this way, the time length of the second stage T12 will still be greater than the time length of the third stage T13.

[0127] In yet another exemplary embodiment, Fig.24 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.24 , the start time of the second stage T12 is earlier than the start time of the third stage T13, and the end time of the second stage T12 is later than the end time of the third stage T13. At this time, after entering the second stage T12, the reset module 14 will first write the reset signal Vref to the gate of the driving transistor T, reset the gate of the driving transistor T, and enter the third stage T13 after a period of reset; at this time, the bias adjustment module 17 and the reset module 14 are turned on at the same time, so that the reset signal Vref continues to be charged into the gate of the driving transistor T, and at the same time, the bias adjustment signal V0 is written into the first and second electrodes of the driving transistor T; at the end of the third stage T13, the second stage T12 will continue, that is, after the bias adjustment module 17 is turned off, the reset module 14 remains in the turned-on state; after the second stage T2 ends, the reset module 14 is turned off and no longer provides the reset signal Vref to the driving transistor. In this way, the time length of the second stage T12 will also be greater than the time length of the third stage T13.

[0128] It can be understood that the above is only an exemplary description of the case where the time length of the second stage T12 is greater than the time length of the third stage T13. In the embodiment of the present invention, the time length of the second stage T12 may also be equal to the time length of the third stage T13. In this case, the start time of the second stage T12 is the same as the start time of the third stage T13, and the end time of the second stage T12 is the same as the end time of the third stage T13.

[0129] In other embodiments of the present invention, the start time of the second stage may be earlier than the start time of the third stage, and the end time of the second stage may also be earlier than the end time of the third stage.

[0130] For example, continue with Fig.10 Taking the pixel circuit shown in the figure as an example, Fig.25 is another working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, combined with reference Fig.10 and Fig.25 , when the start time of the second stage T12 is earlier than the start time of the third stage T13, and the end time of the second stage T12 is earlier than the end time of the third stage T13, after entering the second stage T12, the reset module 14 is turned on, the bias adjustment module 17 is turned off, and the reset module 14 will first write the reset signal Vref to the gate of the driving transistor T to reset the gate of the driving transistor T; after a period of reset, it will enter the third stage T13; at this time, the bias adjustment module 17 and the reset module 14 are turned on at the same time, so that the reset signal Vref continues to be charged into the gate of the driving transistor T, and at the same time, the bias adjustment signal V0 is written into the first electrode and the second electrode of the driving transistor T; after the bias adjustment module 17 and the reset module 14 are synchronously turned on for a period of time, the second stage T12 ends, and the third stage T13 continues; at this time, the reset module 14 is turned off, the bias adjustment module 17 remains turned on, and continues to provide the bias adjustment signal V0 to the first electrode and the second electrode of the driving transistor T until the third grounding T13 ends, and the bias adjustment module 17 is turned off.

[0131] It should be noted that the above is only Fig.10 The working process of the pixel circuit under different conditions is illustrated by way of example. When the pixel circuit is in other conditions, the scanning signals, light emitting control signals, bias adjustment signals, data signals and reset signals can be adaptively adjusted to achieve the above-mentioned beneficial effects, which will not be described one by one here.

[0132] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention. Therefore, the display device has the technical features of the display panel and the driving method thereof provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by the embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0133] For example, Fig.26 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.26As shown, the display device 200 includes the display panel 100 provided in the embodiment of the present invention. The display device 200 provided in the embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0134] It should be understood that the various forms of pixel circuit operation processes shown above can be used to reorder, add or delete stages. For example, the stages in the operation processes of the pixel circuits described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0135] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Pixel circuit and light emitting element; The pixel circuit includes a driving module, a data writing module, a compensation module, a reset module and a bias adjustment module; The driving module includes a driving transistor; The data writing module is connected to the first electrode of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; The reset module is connected to the gate or the second electrode of the driving transistor; The bias adjustment module is connected to the first electrode or the second electrode of the driving transistor; wherein, The working process of the pixel circuit includes a first bias adjustment stage and a third bias adjustment stage, wherein the first bias adjustment stage includes a first stage; In the first stage, the data writing module and the reset module are turned off, and the compensation module is turned on; in the third bias adjustment stage, the bias adjustment module is turned on, and the data writing module, the compensation module and the reset module are turned off.

2. The display panel according to claim 1, characterized in that: The working process of the pixel circuit includes a data writing stage and a light emitting stage. In the data writing stage, the data writing module and the compensation module are turned on, and the reset module is turned off; The third bias adjustment stage is located between the data writing stage and the light emitting stage.

3. The display panel according to claim 1, characterized in that: The operation process of the pixel circuit also includes a second bias adjustment stage; In the second bias adjustment stage, the bias adjustment module and the compensation module are turned on, and the data writing module is turned off.

4. The display panel according to claim 3, characterized in that: The working process of the pixel circuit includes a reset phase; In the reset phase, the data writing module and the bias adjustment module are turned off, and the reset module is turned on; The second bias adjustment phase is located between the first bias adjustment phase and the reset phase.

5. The display panel according to claim 1, characterized in that: The first bias adjustment stage also includes a second stage. In the second stage, the data writing module and the compensation module are turned off, and the reset module is turned on.

6. The display panel according to claim 5, characterized in that: A first interval stage is included between the first stage and the second stage.

7. The display panel according to claim 6, characterized in that: The duration of the first interval phase is shorter than the duration of the first phase; and / or, The time length of the first interval phase is shorter than the time length of the second phase.

8. The display panel according to claim 5, characterized in that: The time length of the first stage is greater than the time length of the second stage.

9. The display panel according to claim 5, characterized in that: The time length of the first stage is shorter than the time length of the second stage.

10. The display panel according to claim 5, characterized in that: When the first stage ends, the second stage begins.

11. The display panel according to claim 1, characterized in that: The compensation module includes a compensation transistor, a first electrode of the compensation transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the compensation transistor is electrically connected to a gate of the driving transistor.

12. The display panel according to claim 11, characterized in that: The gate of the compensation transistor receives a scanning signal; When entering the first stage, the scanning signal jumps from a low level to a high level.

13. The display panel according to claim 11, characterized in that: The compensation transistor is an NMOS transistor or a PMOS transistor.

14. The display panel according to claim 1, characterized in that: The reset module includes a reset transistor, a first electrode of the reset transistor receives a reset signal, and a second electrode of the reset transistor is electrically connected to a gate or a second electrode of the driving transistor.

15. The display panel according to claim 14, characterized in that: The reset transistor is an NMOS transistor or a PMOS transistor.

16. The display panel according to claim 1, characterized in that: The data writing module comprises a data writing transistor, a first electrode of the data writing transistor receives a data signal, and a second electrode of the data writing transistor is electrically connected to a first electrode of a driving transistor.

17. The display panel according to claim 1, characterized in that: The driving transistor is an NMOS transistor or a PMOS transistor.

18. A display device, comprising the display panel according to any one of claims 1 to 17.

Images