High-reliability 21T radiation-resistant SRAM cell circuit and equipment based on triple redundancy feedback

Abstract

This invention provides a high-reliability 21T radiation-hardened SRAM cell circuit and device based on triple redundancy feedback. The SRAM cell includes twelve NMOS transistors N1-N12 and nine PMOS transistors P1-P9. The gates of N7-N12 are connected to word lines WL and are controlled by WL. P4-P9 act as pull-up transistors, N1-N6 as pull-down transistors, and P1-P3 as latch control transistors. Their connection method is mutually latched and forms a feedback loop. Six memory nodes S0-S5 are connected to bit lines BL and BLB via transmission transistors N7-N12, respectively. During the writing process, the radiation-hardened SRAM cell of this invention transmits data simultaneously through three pairs of transmission transistors, improving write stability and reducing write latency. At the same time, it constructs mutually feedback redundant node pairs, which have the ability to completely resist single-node flips and double-node flips, and have fault tolerance capability for partial three-node flips.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular, to a high-reliability 21T anti-radiation SRAM cell circuit based on three-redundancy feedback and equipment. BACKGROUND

[0002] At present, spacecrafts are running in harsh and complex space radiation environment, and electronic devices in space systems are easily affected by radiation particles to cause radiation effects, which affects the normal work of spacecrafts, and greatly increases the demand for high-performance anti-radiation hardened integrated circuits. Single event effect (SEE) is one of the main reliability problems faced by aerospace electronic devices.

[0003] Static random access memory (SRAM) is the most important and most used storage unit in space microprocessors and special integrated circuits, and the cross-coupled structure makes it very sensitive to space radiation. When a radiation particle hits a sensitive node of SRAM, the charge accumulated in the sensitive node can cause single event upset (SEU) of another sensitive node through the cross-coupled inverter. Single event upset will not directly damage the circuit, but since the storage unit captures the wrong timing information and transmits it, if the data is not discovered and recovered in time, it will cause logic failure or failure of the electronic system.

[0004] With the continuous reduction of semiconductor process size, the working frequency of the circuit is continuously improved, and the power voltage and node capacitance are continuously reduced, and the upset threshold charge of the SRAM cell is also continuously reduced. The progress of process technology promotes the density of integrated circuits to greatly improve, resulting in that the distance between the sensitive nodes of a single storage unit is getting smaller and smaller, and the electron cloud generated by single particle incidence can cover multiple transistors, so that the charge induced by radiation particles can be collected by multiple nodes, that is, the charge sharing effect occurs, and multiple node upset (SEMNU) occurs. Among them, the double node upset (DNU) and triple node upset (TNU) caused by the charge sharing effect become new challenges to the reliability of the storage unit.

[0005] The existing technology has few studies on SRAM resisting double-node flipping, and current anti-radiation SRAM design is reinforced by increasing circuit redundancy nodes, most of which do not have high DNU resistance, and have some sacrifices in read stability, write ability and read-write delay. Therefore, when designing anti-radiation reinforcement, the anti-DNU capability of the storage unit needs to be considered, so as to design an SRAM unit anti-radiation reinforcement design with high fault tolerance and low performance loss. SUMMARY

[0006] In view of the defects in the prior art, the purpose of the present application is to provide a high-reliability 21T anti-radiation SRAM cell circuit and equipment based on three-redundancy feedback.

[0007] The high-reliability 21T anti-radiation SRAM cell circuit based on three-redundancy feedback provided by the present application comprises nine PMOS transistors P1-P9 and twelve NMOS transistors N1-N12.

[0008] The sources of P4-P9 are electrically connected to the power supply VDD; the drains of P1, P2 and P3 are electrically connected to the drains of N3, N2 and N6 respectively; the sources of N1-N6 are electrically connected to ground; N7-N12 are access transistors, wherein the drains of N6, P3 and N7 are electrically connected to the gates of P6 and N5 to form a storage node S0; the drains of P6, N4 and N8 are electrically connected to the gates of N3, P3 and P8 to form a storage node S1; the drains of P2, N2 and N9 are electrically connected to the gates of P5 and N4 to form a redundant storage node S2; the drains of P5, N1 and N10 are electrically connected to the gates of P2, N9 and N6 to form a redundant storage node S3; the drains of P1, N3 and N11 are electrically connected to the gates of P4 and N1 to form a redundant storage node S4; the drains of P4, N5 and N12 are electrically connected to the gates of P1, N2 and P7 to form a redundant storage node S5; the gates of the six N-type transistors N7-N12 are electrically connected to a word line WL; the sources of N7, N9 and N11 are electrically connected to a bit line BL; the sources of N8, N10 and N12 are electrically connected to a bit line BLB.

[0009] In the normal working mode of the SRAM cell, when the word line WL is low, the cell enters a holding state; when the word line WL is high, all the access transistors N7-N12 are opened, at which time the read operation or the write operation is performed.

[0010] Preferably, the gate length of P1-P9 is 40nm; the gate width of P4, P5 and P6 is 360nm; the gate width of P7, P8 and P9 is 225nm; and the gate width of the remaining P-type transistors is 240nm.

[0011] Preferably, the gate length of N1-N12 is 40nm; the gate length of N7-N12 is 360nm; the gate length of N1-N6 is 150nm.

[0012] Preferably, the SRAM unit is in a holding state, the WL is a logic low level, N7-N12 are in an off state, and the bit line BL and the bit line BLB are both pre-charged to a high level, and there is no path to the internal node of the circuit.

[0013] Preferably, the SRAM unit is in a reading operation, the bit line BL and the bit line BLB are both pre-charged to a high level, and the word line WL is a logic high level, and the access transistors N7-N12 are all turned on.

[0014] Preferably, when the stored value is 1, if a write 0 operation is performed, the value of the bit line BL is 0, the value of BLB is 1, the WL is pre-charged to a logic high level, 0 is written to the storage node S0 and the redundant storage nodes S2 and S4 through N7, N9 and N11 respectively, and 1 is written to the storage node S1 and the redundant storage nodes S3 and S5 through N8, N10 and N12 respectively.

[0015] Preferably, when the stored value is 1, if a write 1 operation is performed, the value of the bit line BL is 1, the value of BLB is 0, 1 is written to the storage node S0 and the redundant nodes S2 and S4 through N7, N9 and N11 respectively, and 0 is written to the storage node S1 and the redundant nodes S3 and S5 through N8, N10 and N12 respectively.

[0016] Preferably, when the stored data of the SRAM unit is 1, i.e. S0=S2=S4=1 and S1=S3=S5=0, the bit line BLB is discharged to GND through the access tubes N8, N10 and N12 due to the turned-on states of N1, N4 and N5, so that the voltage of BLB gradually decreases, and the voltage of the bit line BL is not affected, and when the voltage difference between the bit lines reaches a preset threshold, the data 1 reading is completed.

[0017] Preferably, when the stored data of the SRAM unit is 0, i.e. S0=S2=S4=0 and S1=S3=S5=1, the bit line BL is discharged to GND through the access tubes N7, N9 and N11 due to the turned-on states of N2, N3 and N6, so that the voltage of BL gradually decreases, and the voltage of the bit line BLB is not affected, and when the voltage difference between the bit lines reaches a preset threshold, the data 0 reading is completed.

[0018] According to the present application, an electronic device is provided, which is equipped with the high-reliability 21T anti-radiation SRAM unit circuit based on three-redundancy feedback.

[0019] Compared with the prior art, the present application has the following beneficial effects:

[0020] The application provides a high-reliability 21T anti-radiation SRAM cell circuit based on three-redundancy feedback, three pairs of storage nodes are constructed, wherein the potentials of three nodes S1, S3 and S5 are controlled by one N tube and one P tube respectively, the potentials of the remaining nodes S0, S2 and S4 are controlled by one N tube and two P tubes respectively, and the six nodes are controlled by different feedback paths, when single-node or double-node single-event upsets occur in the cell, the latch control tube can cut off the transient pulse transmission path, eliminate the glitch generated by the single-event upset, and the un-upset nodes can be restored through the feedback loop, the 21T anti-radiation SRAM cell circuit has complete DNU resistance and partial TNU resistance; meanwhile, four access transistors are added on the basis of the traditional SRAM, so that the read-write access time and the read-write stability are improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-restrictive embodiments, made with reference to the attached drawings:

[0022] Figure 1 It is a 21T anti-radiation SRAM cell structure of the present application;

[0023] Figure 2 It is a timing waveform schematic diagram of the 21T anti-radiation SRAM memory cell circuit of the present application;

[0024] Figure 3 It is a waveform schematic diagram of the 21T anti-radiation SRAM cell anti-SEU of the present application;

[0025] Figure 4 It is a waveform schematic diagram of the 21T anti-radiation SRAM cell anti-DNU of the present application;

[0026] Figure 5 It is a waveform schematic diagram of the 21T anti-radiation SRAM cell anti-TNU of the present application. DETAILED DESCRIPTION

[0027] The application will be described in detail below with specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be pointed out that, for those skilled in the art, without departing from the concept of the present application, a number of changes and improvements can be made. These all belong to the protection scope of the present application.

[0028] EMBODIMENT

[0029] The 21T anti-radiation SRAM cell structure based on three-redundancy feedback of the present application is as follows: Figure 1As shown, it comprises: twelve NMOS transistors and nine PMOS transistors, the twelve NMOS transistors are sequentially recorded as N1-N12, and the nine PMOS transistors are sequentially recorded as N1-N9, wherein:

[0030] The transistors P1, P2 and P3 are latch control tubes, and the drain electrodes of the transistors P1, P2 and P3 are electrically connected with the drain electrodes of the transistors N3 and N2 respectively;

[0031] The transistors N6, P3 and P7, the transistors N2, P2 and P8, the transistors N3, P1 and P9 are three groups of 3-input simplified C cells, and the latch control tubes are used to cut off the spur transmission path;

[0032] The transistors P4, P4 and P6 are pull-up tubes of the storage points S1, S3 and S5, and the transistors N5, N1 and N4 are pull-down tubes of the storage points S1, S3 and S5;

[0033] The transistors P1 and P9 are pull-up tubes of the storage node S4, the transistor N3 is a pull-down tube of the storage node S4, the transistors P2 and P8 are pull-up tubes of the storage node S2, the transistor N2 is a pull-down tube of the storage node S2, the transistors P3 and P7 are pull-up tubes of the storage node S0, and the transistor N6 is a pull-down tube of the storage node S0;

[0034] The gate electrodes of the six transistors N7-N12 are electrically connected with the word line WL, the source electrodes of N7, N9 and N11 are electrically connected with the bit line BL, and the source electrodes of N8, N10 and N12 are electrically connected with the bit line BLB;

[0035] Please refer to Figure 1 As shown, Figure 1 The specific connection relationship of each transistor in the high-reliability 21T anti-radiation SRAM cell circuit based on three-redundancy feedback of the application is shown, wherein the word line is recorded as WL, two bit lines are recorded as BL and BLB, three pairs of storage nodes are recorded as S0, S1, S2, S3, S4 and S5, the first node pair is recorded as S0 and S1, the second node pair is recorded as S2 and S3, the third node pair is recorded as S4 and S5, the power supply end is recorded as VDD, and the ground end is recorded as GND.

[0036] The source electrodes of P4-P9 are electrically connected to a power supply VDD. The drain electrodes of P1, P2 and P3 are electrically connected to the drain electrodes of N3, N2 and N6 respectively. The source electrodes of N1-N6 are electrically connected to GND. The drain electrodes of N6, P3 and N7 are electrically connected to the gate electrodes of P6 and N5 to form a storage node S0. The drain electrodes of P6, N4 and N8 are electrically connected to the gate electrodes of N3, P3 and P8 to form a storage node S1. The drain electrodes of P2, N2 and N9 are electrically connected to the gate electrodes of P5 and N4 to form a redundant storage node S2. The drain electrodes of P5, N1 and N10 are electrically connected to the gate electrodes of P2, N9 and N6 to form a redundant storage node S3. The drain electrodes of P1, N3 and N11 are electrically connected to the gate electrodes of P4 and N1 to form a redundant storage node S4. The drain electrodes of P4, N5 and N12 are electrically connected to the gate electrodes of P1, N2 and P7 to form a redundant storage node S5. The gate electrodes of N7-N12 are electrically connected to a word line WL. The source electrodes of N7, N9 and N11 are electrically connected to a bit line BL. The source electrodes of N8, N10 and N12 are electrically connected to a bit line BLB.

[0037] Further, the 21T anti-radiation SRAM cell circuit provided by the embodiment of the present application has the following characteristics: the gate length of N1-N12 and P1-P9 is 40 nm; the gate width of P4, P5 and P6 is 360 nm; the gate width of P7, P8 and P9 is 225 nm; the gate length of N7-N12 is 360 nm; the gate length of N1-N6 is 150 nm; and the gate width of the rest P-type transistors is 240 nm.

[0038] The principle of the 21T anti-radiation SRAM cell circuit provided by the embodiment of the present application is as follows:

[0039] In the data retention phase, the word line WL is at a logic low level, the access transistors N7-N12 are all closed, and the bit lines BL and BLB are all charged to a high level.

[0040] In the data write phase, the word line WL is pre-charged to a logic high level, the access transistors N7-N12 are opened, and in the case of storing a value of '1', a write '0' operation is performed. When the value of the bit line BL is '0' and the value of the bit line BLB is '1', '0' is written to the storage node S0 and the redundant storage nodes S2 and S4 through N7, N9 and N11 respectively, and '1' is written to the storage node S1 and the redundant storage nodes S3 and S5 through N8, N10 and N12 respectively. Conversely, if a write '1' operation is performed, when the value of the bit line BL is '1' and the value of the bit line BLB is '0', '1' is written to the storage node S0 and the redundant nodes S2 and S4 through N7, N9 and N11 respectively, and '0' is written to the storage node S1 and the redundant nodes S3 and S5 through N8, N10 and N12 respectively.

[0041] In the data reading stage, the bit lines BL and BLB are pre-charged to high level, the word line WL is pre-charged to logic high level, the access transistors N7-N12 are turned on, the read '1' operation is performed, the storage value is '1', and then "S0=S2=S4=1, S1=S3=S5=0" is obtained. The bit line BLB is discharged to GND through the access transistors N8, N10 and N12, and the discharge path is N1, N4 and N5. The voltage of the bit line BL is not affected. When the bit line voltage difference reaches a certain threshold, the data '1' reading is completed through the sense amplifier. Conversely, if the read '0' operation is performed, the storage value is '0', and then "S0=S2=S4=0, S1=S3=S5=1" is obtained. The bit line BL is discharged to GND through the access transistors N7, N9 and N11, and the discharge path is N2, N3 and N6. The voltage of the bit line BLB is not affected. When the bit line voltage difference reaches a certain threshold, the data '0' reading is completed through the sense amplifier.

[0042] As shown in Figure 2 , it is a timing waveform diagram of the 21T anti-radiation SRAM storage unit circuit provided by the embodiment of the present application, and the specific simulation conditions are as follows: Corner: TT, Temperature: 27℃, VDD: 1.1V. It can be known from Figure 2 that the data '1' is written at 3-5ns, the data '1' is read out at 8-10ns, the data '0' is written at 13-15ns, and the data '0' is read out at 18-20ns. It can be seen that the 18T anti-radiation SRAM unit circuit provided by the present application can realize the operations of writing '1', reading '1', writing '0' and reading '0'.

[0043] As shown in Figure 3 , it is a transient waveform simulation diagram of a single node of the 21T anti-radiation SRAM unit circuit provided by the embodiment of the present application subjected to double exponential current pulse injection at different time. It can be known from Figure 3 that at the time of 5.5ns, the storage node S0 is subjected to single particle impact, and the data is flipped from '0' to '1'. After the feedback structure of the three-redundancy circuit, the data is recovered to the correct value in a short time. At the time of 7ns, the storage node S1 is subjected to single particle impact, and the data is flipped from '1' to '0'. After the feedback structure of the three-redundancy circuit, the data is recovered to the correct value in a short time. At the time of 8.5ns, the storage node S2 is subjected to single particle impact, and the data is flipped from '0' to '1'. After the feedback structure of the three-redundancy circuit, the data is recovered to the correct value in a short time. At the time of 10ns, the storage node S3 is subjected to single particle impact, and the data is flipped from '1' to '0'. After the feedback structure of the three-redundancy circuit, the data is recovered to the correct value in a short time. Similarly, at the times of 11.5ns and 13ns, the double exponential current pulse is injected to the storage nodes S4 and S5 respectively, and the simulation result shows that the data is recovered to the correct value in a short time.

[0044] Further combiningFigure 1 and Figure 3 The process of the 21T anti-radiation SRAM anti-SEU provided by the embodiment of the application is analyzed:

[0045] When the storage '0' node S0 is illegally changed after current injection, the logic value of the node S0 changes from '0' to '1', at this time, the transistor N5 is turned on, the storage node S5 outputs a weak '0', and the transistor P1 is weakly turned on, wherein the semi-C unit composed of the transistors P9, P1 and N3 controls the potential of S4, and the S4 potential is pulled up by S3 and S5, and since the storage value of S3 is not affected (S3 = 1), the transistor P9 remains in a strong off state, so the value of S4 is still '0', and the influence of the current glitch on other storage nodes is eliminated. At this time, the strong '0' of S4 controls the transistor P4 to output a strong '1', and the strong '1' of S5 neutralizes the weak 0 caused by S0, so the storage value of S5 is still '0'. At the same time, the value of S0 changes to '1', which makes the transistor P6 off, and the storage value of S1 is temporarily not affected, and S1 and S5 simultaneously control the off of the transistors P3 and P7, and the storage node S3 which is not affected will control the transistor N6 to be strongly turned on, and the storage value of S0 changes to '0'. Therefore, the node S0 can restore the correct value.

[0046] When the storage '1' node S1 is illegally changed after current injection, the logic value of the node S1 changes from '1' to '0', at this time, the transistors P3 and P8 are turned on, and the transistor N3 is turned off, and since the input of the simplified semi-C unit exists, the transistors P2 and P7 controlled by the storage nodes S3 and S5 are still in the off state, therefore, the turning on of the transistors P3 and P8 will not cause the flipping of the storage nodes S2 and S0, and the error is not transmitted to S0 and S2, at this time, the S0 and S2 which are not affected store '0' and '1' respectively, and will simultaneously control the transistors P6 and N2, so that the transistor P6 is turned on and the transistor N4 is turned off, and the storage value of the node S1 changes to '1'. Therefore, the node S1 can restore the correct value. Since the circuit structure and the feedback structure of the three pairs of storage nodes are symmetrical, similarly, when the nodes S2 and S4 are illegally changed after current injection, according to the fault tolerance principle of the node S0, the storage values of S2 and S4 can also be self-recovered; when the nodes S3 and S5 are illegally changed after current injection, according to the fault tolerance principle of the node S1, the storage values of S3 and S5 can also be self-recovered, that is, the nodes S0, S1, S2, S3, S4, S5 and S6 can be self-recovered from SEU.

[0047] As shown in Figure 4 , it is a transient waveform simulation diagram of two storage nodes of the 21T anti-radiation SRAM unit circuit storage node S0, S1 and redundant storage nodes S2, S3, S4, S5 simultaneously receiving a single particle transient current pulse simulation injection provided by the embodiment of the application.

[0048] like Figure 4 The figure shown is a simulation diagram of the transient waveforms of the two nodes of the 21T radiation-resistant SRAM cell circuit provided in this embodiment of the invention, subjected to double exponential current pulse injections at different times. Figure 4 It can be seen that at 4ns, storage nodes S0 and S1 are simultaneously subjected to a single-event impact. The data at node S0 flips from '0' to '1', and the data at node S1 flips from '1' to '0'. Through the triple redundancy feedback structure, the data recovers to the correct value in a short time. At 5ns, storage nodes S0 and S2 are simultaneously subjected to a single-event impact. The data at node S0 flips from '0' to '1', and the data at node S2 flips from '0' to '1'. Through the triple redundancy feedback structure, the data recovers to the correct value in a short time. At 6ns, storage nodes S0 and S3 are simultaneously subjected to a single-event impact. The data at node S0 flips from '0' to '1'. At time 7 ns, storage nodes S0 and S4 are simultaneously subjected to a single-event impact. At time 8 ns, storage nodes S0 and S5 are simultaneously subjected to a single-event impact. At time 9 ns, 10 ns, 11 ns, 12 ns, 13 ns, and 14 ns, respectively, the data at node S3 flips from '1' to '0'. Through the triple-redundant feedback structure, the data recovers to the correct value in a short time.<S2,S3> ,<S1,S3> ,<S4,S5> ,<S1,S5> ,<S2,S5> ,<S3,S5> Simulation results show that, after injecting a double exponential current pulse, the data recovers to the correct value in a short time through a triple redundant feedback structure.

[0049] The DNU fault-tolerant principle of the 21T radiation-hardened SRAM memory cell provided by this invention will now be further explained:

[0050] When the storage value of the 21T radiation-resistant SRAM cell is '0', that is, the data values ​​of storage nodes S0, S2, and S4 are '0', and the data values ​​of storage nodes S1, S3, and S5 are '1'. There are seven mutually controlling feedback loops in the structure: S0-P6-P1-S1-P3-S0 (feedback loop 1), S0-N5-S5-P7-S0 (feedback loop 2), S1-P8-S2-N4-S1 (feedback loop 3), S2-P5-S3-P2-S2 (feedback loop 4), S3-P9-S4-N1-S3 (feedback loop 5), S4-P4-S5-P1-S4 (feedback loop 6), and S5-P7-S0-N5-S5 (feedback loop 7). Based on the relationship between nodes and feedback loops, all node pairs in the 21T radiation-resistant SRAM cell can be divided into the following two cases: the two nodes in a node pair are located in the same feedback loop: such as...<S0,S1><S0,S5><S1,S2><S2,S3><S1,S3><S4,S5><S3,S4><S0,S5> The two nodes in a node pair are located in different feedback loops: such as<S0,S2><S0,S3><S0,S4><S1,S4><S1,S5><S2,S4><S2,S5><S3,S5> Next, we will examine representative node pairs from the two scenarios described above.<S0,S1><S0,S4> An analysis of the DNU self-recovery principle was conducted.

[0051] When node pair<S0,S1> When a flip occurs simultaneously, the stored value of S0 flips from '0' to '1', and the stored value of S1 flips from '1' to '0'. At this time, P6 and N3 become closed, while N5, P3, and P8 become open, and S5 outputs a weak '0'. Since the values ​​of nodes S2, S3, and S4 are not affected (S2 = S4 = 0, S3 = 1), P4 and N6 remain open, N4 remains closed, and S5 outputs a strong '1'. The strong '1' of S5 neutralizes the weak '0', so the data value of S5 remains unchanged (S5 = 1), and P7 remains closed. Meanwhile, because N6, controlled by S3, remains open, the strong '0' pulled down by N6 neutralizes the flipped weak '1', causing the value of S0 to be pulled back to '0'. S0 then controls P6 to conduct, pulling S1 back to '1'. At this point, both S0 and S1 automatically recover to their correct stored values.

[0052] When node pair<S0,S4> When the flips occur simultaneously, the stored value of S0 flips from '0' to '1', and the stored value of S1 flips from '0' to '1'. S0 and S4 are not in the same feedback loop, so their respective feedback loops are not immediately and completely destroyed. Furthermore, a half-C control unit exists between S0 and S4, which can cut off the transmission of current pulses, remove glitches, and ultimately recover the data through redundant feedback. After S0 and S4 flip simultaneously, P6 and P4 become off, N1 and N5 temporarily become on, and S3 and S5 output a weak '0'. Due to the presence of the half-C control unit, the current spike is not transmitted to other feedback loops. Therefore, storage nodes S1 and S2 are temporarily unaffected (S1=1, S2=0). The P5 transistor controlled by S2 remains on, causing S3 to output a strong '1', neutralizing the weak '0' of S3 and restoring S3 to its initial value '1'. After S3 is restored, the control transistor N6 remains on, pulling the state of S0 back to its initial value '0'. The N3 controlled by S1 remains on, outputting a strong '0', neutralizing the weak '0' caused by the current pulse, causing S4 to be restored to its initial value '0'. After S4 and S0 are restored, they jointly control transistors P4 and N5, pulling the state of S5 back to its initial value '1'. At this point, both S0 and S4 are restored to their correct stored values.

[0053] like Figure 5 The figure shown is a transient waveform simulation diagram of three consecutive storage nodes S0, S1 and redundant storage nodes S2, S3, S4 and S5 of the 21T radiation-resistant SRAM cell circuit provided in the embodiment of the present invention, which are simultaneously subjected to a single-particle transient current pulse injection.

[0054] like Figure 5 The figure shown is a transient waveform simulation diagram of the 21T radiation-resistant SRAM cell circuit provided in this embodiment of the invention, where three consecutive nodes are injected with double exponential current pulses at different times. Figure 5It can be seen that at 4.5 ns, storage nodes S0, S1, and S2 are simultaneously subjected to a single-event impact. The data at node S0 flips from '0' to '1', the data at node S1 flips from '1' to '0', and the data at node S2 flips from '0' to '1'. Through the triple redundancy feedback structure, the data recovers to the correct value in a short time. At 5.5 ns, storage nodes S1, S2, and S3 are simultaneously subjected to a single-event impact. The data at node S1 flips from '1' to '0', the data at node S2 flips from '0' to '1', and the data at node S3 flips from '1' to '0'. Through the triple redundancy feedback structure, the data recovers to the correct value in a short time. At 6.5 ns, storage nodes S2, S3, and S4 are simultaneously subjected to a single-event impact. The data at node S2 flips from '0' to '1', and the data at node S3 flips from '1' to '0'. After passing through a triple-redundant feedback circuit, the data recovers to its correct value within a short time. At 7.5 ns, storage nodes S3, S4, and S5 are simultaneously subjected to a single-event impact. The data at node S3 flips from '1' to '0', the data at node S4 flips from '0' to '1', and the data at node S5 flips from '1' to '0'. After passing through a triple-redundant feedback structure, the data recovers to its correct value within a short time. Simulation results show that, after being subjected to a current pulse injection, the data at all three nodes recovers to its correct value within a short time using the triple-redundant feedback structure.

[0055] Now combined Figure 1 , Figure 5 The TNU fault-tolerant principle of the 21T radiation-resistant SRAM memory cell provided by this invention is further explained as follows:

[0056] When the storage value of the 21T radiation-resistant SRAM cell is '0', that is, the data values ​​of storage nodes S0, S2, and S4 are '0', and the data values ​​of storage nodes S1, S3, and S5 are '1'. There are seven mutually controlling feedback loops in the structure: S0-P6-P1-S1-P3-S0 (feedback loop 1), S0-N5-S5-P7-S0 (feedback loop 2), S1-P8-S2-N4-S1 (feedback loop 3), S2-P5-S3-P2-S2 (feedback loop 4), S3-P9-S4-N1-S3 (feedback loop 5), S4-P4-S5-P1-S4 (feedback loop 6), and S5-P7-S0-N5-S5 (feedback loop 7). Based on the relationship between nodes and feedback loops, all three-node pairs in the 21T radiation-resistant SRAM cell can be divided into the following two cases: consecutive three nodes: such as...<S0,S1,S2><S1,S2,S3><S2,S3,S4><S3,S4,S5> Discontinuous three nodes: such as<S0,S1,S2><S0,S1,S3><S0,S1,S4><S0,S1,S5><S1,S2,S4><S1,S2,S5><S2,S3,S5> Since charge sharing occurs between nodes that are physically close, the following discussion will focus only on representative three-node pairs from the two scenarios described above.<S0,S1,S2><S1,S2,S3> An analysis of the TNU self-healing principle was conducted.

[0057] When three consecutive nodes are paired<S0,S1,S2> When a flip occurs simultaneously, the stored value of S0 flips from '0' to '1', while the stored value of S1 flips from '1' to '0', and the stored value of S2 flips from '0' to '1'. At this time, P6, N3, and P5 become closed, while N5, P3, P8, and N4 become open. S1 and S5 output a weak '0'. Since the values ​​of nodes S3 and S4 are not affected (S4 = 0, S3 = 1), P4 and N6 remain open. The data '0' of S0 controls the output of S5 to be a strong '1'. The strong '1' of S5 can neutralize the weak '0', so the data value of S5 remains unchanged (S5 = 1). S5 controls P7 to remain closed. Meanwhile, since N6, controlled by S3, remains open, the strong '0' pulled down by N6 neutralizes the weak '1' flip, causing the value of S0 to be pulled back to '0'. S0 then turns on P6, pulling S1 back to '1'. At this point, both S0 and S1 automatically recover to their correct stored values. Simultaneously, since the data value of S3 remains unchanged, S3 keeps P2 closed to prevent the conduction of P8 from pulling the state of S2 towards VDD. After S5 is recovered, N2, controlled by S5, remains open. The strong '0' of S2 neutralizes the weak '1' flip, causing the value of S2 to be pulled back to '0'. At this point, all three consecutive nodes...<S0,S1,S2> All of them automatically restore to the correct stored values.

[0058] When three consecutive nodes are paired<S1,S2,S3> When a flip occurs simultaneously, the stored value of S1 flips from '1' to '0', the stored value of S2 flips from '0' to '1', and the stored value of S3 flips from '1' to '0'. At this time, P5, N3, and N6 become closed, while P3, P8, P9, P2, and N4 become open, and S1 outputs a weak '0'. Since the values ​​of nodes S0, S4, and S5 are unaffected (S0 = S4 = 0, S5 = 1), P4, P6, and N2 remain open. The data '0' of S0 and S4 controls the output of strong '1' of S1 and S5. The strong '1' of S1 neutralizes the weak '0' of the flip, so the data value of S1 remains unchanged (S1 = 1). S5 keeps P1 and P7 closed to prevent the flip of S1 and S3 data from pulling S0 and S4 towards VDD. At the same time, since N2 controlled by S5 remains open, the strong '0' pulled down by S5 neutralizes the weak '1' of the flip, causing the value of S2 to be pulled back to '0'. At this point, S1 and S2 return to their correct values. Since the state of S4 is unaffected, S4 keeps N1 off to prevent S3 from being pulled towards GND. At the same time, since the data of S2 recovers to '1', S2 controls P5 to turn on, pulling S3 back to its original state of '1'. At this point, the three consecutive nodes...<S1,S2,S3> All nodes automatically recover to their correct stored values. Similarly, the recovery principle after a flip of three consecutive node pairs is the same as that for node pairs.<S0,S1,S2><S1,S2,S3> same.

[0059] When the stored value is '1', the 21T radiation-resistant SRAM is similar in principle to SEU, DNU and TNU.

[0060] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0061] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0062] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A high-reliability 21T radiation-hardened SRAM cell circuit based on triple-redundant feedback, characterized by, Comprise: Nine PMOS transistors P1~P9, twelve NMOS transistors N1~N12; The sources of P4~P9 are electrically connected to the power supply VDD; the drains of P1, P2 and P3 are electrically connected to the drains of N3, N2 and N6 respectively; the sources of N1~N6 are electrically connected to ground; N7~N12 are access transistors, wherein the drains of N6, P3 and N7 are electrically connected to the gates of P6 and N5 to form a storage node S0; the drains of P6, N4 and N8 are electrically connected to the gates of N3, P3 and P8 to form a storage node S1; the drains of P2, N2 and N9 are electrically connected to the gates of P5 and N4 to form a redundant storage node S2; the drains of P5, N1 and N10 are electrically connected to the gates of P2, P9 and N6 to form a redundant storage node S3; the drains of P1, N3 and N11 are electrically connected to the gates of P4 and N1 to form a redundant storage node S4; the drains of P4, N5 and N12 are electrically connected to the gates of P1, N2 and P7 to form a redundant storage node S5; the gates of N7~N12 are electrically connected to a word line WL; the sources of N7, N9 and N11 are electrically connected to a bit line BL; the sources of N8, N10 and N12 are electrically connected to a bit line BLB; In a normal working mode, when the word line WL is at a low level, the SRAM cell enters a holding state; when the word line WL is at a high level, the access transistors N7~N12 are all turned on, at which time the SRAM cell has the ability to perform a read operation or a write operation.

2. The triple-redundancy feedback based high reliability 21T radiation hardening SRAM cell circuit of claim 1, wherein, The gate length of P1~P9 is 40nm; the gate width of P4, P5 and P6 is 360nm; the gate width of P7, P8 and P9 is 225nm; and the gate width of the remaining P-type transistors is 240nm.

3. The triple-redundancy feedback based high reliability 21T radiation-hardened SRAM cell circuit of claim 1, wherein, The gate length of N1~N12 is 40nm; the gate length of N7~N12 is 360nm; and the gate length of N1~N6 is 150nm.

4. The triple-redundancy feedback based high reliability 21T radiation hardening SRAM cell circuit of claim 1, wherein, In the holding state, the WL is at a logic low level, N7~N12 are in a closed state, and the bit line BL and the bit line BLB are both pre-charged to a high level, and there is no path to the internal nodes of the circuit.

5. The triple-redundancy feedback based high reliability 21T radiation hardening SRAM cell circuit of claim 1, wherein, In the read operation, the bit line BL and the bit line BLB are both pre-charged to a high level, and the word line WL is at a logic high level, and the access transistors N7~N12 are all turned on.

6. The triple-redundancy feedback based high reliability 21T radiation-hardened SRAM cell circuit of claim 1, wherein, When the storage value is 1, if a write 0 operation is performed, the value of the bit line BL is 0, the value of the bit line BLB is 1, the WL is pre-charged to a logic high level, 0 is written to the storage node S0 and the redundant storage nodes S2, S4 through N7, N9 and N11 respectively, and 1 is written to the storage node S1 and the redundant storage nodes S3, S5 through N8, N10 and N12 respectively.

7. The triple-redundancy feedback based high reliability 21T radiation hardening SRAM cell circuit of claim 1, wherein, When the storage value is 1, if a write 1 operation is performed, the value of the bit line BL is 1, the value of the bit line BLB is 0, 1 is written to the storage node S0 and the redundant nodes S2, S4 through N7, N9 and N11 respectively, and 0 is written to the storage node S1 and the redundant nodes S3, S5 through N8, N10 and N12 respectively.

8. The triple-redundancy feedback based high reliability 21T radiation hardening SRAM cell circuit of claim 1, wherein, When the data stored in the SRAM cell is 1, that is, S0=S2=S4=1, S1=S3=S5=0, since N1, N4, N5 are in the open state, the bit line BLB discharges to GND through access tubes N8, N10, N12, causing the BLB voltage to gradually decrease, the bit line BL voltage is not affected, when the bit line voltage difference reaches the preset threshold, the data 1 reading is completed.

9. The triple-redundancy feedback based high reliability 21T radiation hardening SRAM cell circuit of claim 1, wherein, When the data stored in the SRAM cell is 0, that is, S0=S2=S4=0, S1=S3=S5=1, N2, N3, N6 are in the open state, the bit line BL discharges to GND through access tubes N7, N9, N11, causing the BL voltage to gradually decrease, the bit line BLB voltage is not affected, when the bit line voltage difference reaches the preset threshold, the data 0 reading is completed.

10. An electronic device, comprising: A high-reliability 21T anti-radiation SRAM cell circuit based on three-redundancy feedback according to any one of claims 1 to 9 is carried.

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