A self-loading memory structure suitable for non-volatile memory cells
The self-loading storage structure solves the problem of easy loss of FPGA configuration information, realizes high reliability and high flexibility of non-volatile storage, improves device size and erase/write cycles, and solves the security and performance deficiencies of existing FPGA technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2024-11-28
- Publication Date
- 2026-04-28
AI Technical Summary
Existing FPGA technology suffers from problems such as easy loss of configuration information, low security, small device size, and limited number of erase/write cycles. In particular, SRAM-based FPGAs require external non-volatile memory, which reduces security and reduces radiation resistance. Flash-based FPGAs have limited erase/write cycles and are manufactured using outdated technology.
A self-loading memory structure suitable for non-volatile memory cells is adopted, including programming, loading, reset and reading structures. The non-volatile memory cells are used as programming devices, configuration data is stored through the programming path, data is loaded through the loading structure, reset through the reset structure, and data is read out through the reading structure, thereby realizing the self-loading of data in the non-volatile memory cells.
It ensures that configuration information is not lost after FPGA power failure, improves data reliability and confidentiality, increases device size and erase/write cycles, reduces static power consumption, and accelerates startup.
Smart Images
Figure CN119763631B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a self-loading memory structure suitable for non-volatile memory cells. Background Technology
[0002] With the development of my country's communications and medical fields, the demand for highly reliable programmable logic devices (PLDs) is becoming increasingly prominent. How to develop next-generation high-performance, high-reliability, low-power non-volatile FPGA core configuration units has become one of the hot research topics in the integrated circuit field.
[0003] There are two types of FPGAs: one is a volatile FPGA based on SRAM that requires external non-volatile memory, and the other is a non-volatile FPGA that stores the configuration in memory and does not require external non-volatile memory.
[0004] FPGAs based on SRAM technology are volatile FPGAs. They use internal SRAM cells to store configuration information and can be configured and erased an unlimited number of times. This is currently the mainstream FPGA configuration technology. However, after configuration, all configuration information will be lost when power is turned off and restarted. External non-volatile memory, such as Flash or EEPROM, is required to store configuration information. However, the configuration information of external memory is very likely to be stolen, which reduces its security. In addition, the radiation resistance of external memory also needs to be considered.
[0005] FPGAs based on non-volatile memory cell technology do not require external non-volatile memory. Configuration information is stored in the internal FPGA configuration memory cell switches, and the configuration information is not lost after power failure and restart. Flash FPGAs are a typical type of non-volatile FPGA, possessing the reprogrammable characteristics of SRAM FPGAs. Furthermore, the Flash switch structure significantly reduces the number of transistors in Flash FPGAs, resulting in lower static power consumption. However, Flash FPGAs have certain limitations. The number of erase / write cycles for Flash FPGA memory cells is limited, only around a few hundred times. Secondly, compared to SRAM FPGAs, Flash FPGAs use more advanced manufacturing processes, and their device size and density are much lower. Summary of the Invention
[0006] The purpose of this invention is to provide a self-loading memory structure suitable for non-volatile memory cells, so as to solve the problems in the background art.
[0007] To address the aforementioned technical problems, this invention provides a self-loading memory structure suitable for non-volatile memory cells, comprising: a programming structure, a loading structure, a reset structure, and a readout structure;
[0008] The programming structure is used to store configuration data into a non-volatile storage unit through a programming path;
[0009] The loading structure is used to load data stored in the programming structure;
[0010] The reset structure is used to reset the loading structure before loading;
[0011] The readout structure is used to read data from the load structure.
[0012] In one embodiment, the programming structure includes a left non-volatile memory cell and a right non-volatile memory cell, a first programming transistor and a second programming transistor; a first terminal of the left non-volatile memory cell is connected to the drain of the first programming transistor to form a first transmission node, and a second terminal of the left non-volatile memory cell is connected to a power supply voltage VDD; a first terminal of the right non-volatile memory cell is connected to the drain of the second programming transistor to form a second transmission node, and a second terminal of the right non-volatile memory cell is connected to a power supply voltage VDD; the gate of the first programming transistor is connected to a first input node, its source is connected to a third input node, and its drain is connected to the first transmission node; the gate of the second programming transistor is connected to a second input node, its source is connected to a fourth input node, and its drain is connected to the second transmission node.
[0013] In one embodiment, the loading structure includes a first isolation transistor and a second isolation transistor, a first closed-circuit transistor and a second closed-circuit transistor; the first closed-circuit transistor and the second closed-circuit transistor constitute a bistable circuit, forming a first storage node and a second storage node; the gate of the first closed-circuit transistor is connected to the first storage node, its source is grounded, and its drain is connected to the second storage node; the gate of the second closed-circuit transistor is connected to the second storage node, its source is grounded, and its drain is connected to the first storage node; the gate of the first isolation transistor is connected to the fifth input node, its source is connected to the first transmission node, and its drain is connected to the second storage node; the gate of the second isolation transistor is connected to the fifth input node, its source is connected to the second transmission node, and its drain is connected to the first storage node.
[0014] In one embodiment, the reset structure includes a first reset transistor and a second reset transistor; wherein the gate of the first reset transistor is connected to a sixth input node, the source is grounded, and the drain is connected to a second memory node; the gate of the second reset transistor is connected to the sixth input node, the source is grounded, and the drain is connected to a first memory node.
[0015] In one embodiment, the readout structure includes a first inverter and a second inverter; wherein the input of the first inverter is connected to a first storage node and the output is connected to a first output node; the input of the second inverter is connected to a second storage node and the output is connected to a second output node.
[0016] In one embodiment, the self-loading storage structure includes a programming sequence and a loading sequence; wherein the programming sequence programs the left and right non-volatile storage units through a programming path, storing data in the left and right non-volatile storage units; the loading sequence loads the data stored in the non-volatile storage units into the first and second storage nodes in the loading structure; the programming path includes a left non-volatile storage unit programming path and a right non-volatile storage unit programming path; wherein the first input node, the first programming tube, the third input node, and the left non-volatile storage unit constitute the left non-volatile storage unit programming path; and the second input node, the second programming tube, the fourth input node, and the right non-volatile storage unit constitute the right non-volatile storage unit programming path.
[0017] In one implementation, the programming timing includes four states: power-on, encoding "1", holding, and encoding "0".
[0018] Upon power-up, the first and second input nodes are both at a low level, the fifth input node is at a high level, and the power supply voltage VDD rises to the programming voltage.
[0019] When programming to "1", the third input node = "0", the fourth input node = "1", the first and second input nodes are pulled high, and the two programming transistors are turned on. When the voltage difference across the left non-volatile memory cell is higher than the threshold voltage of the left non-volatile memory cell, the left non-volatile memory cell changes from a high-resistance state to a low-resistance state. At the same time, because the fourth input node = "1", the voltage difference across the right non-volatile memory cell is less than the threshold voltage of the right non-volatile memory cell, and the right non-volatile memory cell remains in a high-resistance state.
[0020] During the holding period, the power supply voltage VDD remains at the programming voltage level, the third and fourth input nodes go low, the first and second input nodes also go low, the two programming transistors are turned off, and the programming path is disconnected.
[0021] When programming to "0", the third input node = "1", the fourth input node = "0", the first input node and the second input node are pulled high, and the two programming transistors are turned on. When the voltage difference across the right non-volatile memory cell is higher than the threshold voltage of the right non-volatile memory cell, the right non-volatile memory cell changes from a high-resistance state to a low-resistance state. At the same time, since the third input node = "1", the voltage difference across the left non-volatile memory cell is less than the threshold voltage of the left non-volatile memory cell, and the left non-volatile memory cell remains in a high-resistance state.
[0022] In one embodiment, the loading sequence includes three states: power-on, reset, and loading.
[0023] When powered on, the first input node, the second input node, and the sixth input node are all at low level, the fifth input node is at high level, and the power supply voltage is the normal operating voltage.
[0024] During reset, the first and second input nodes remain at a low level, the fifth input node remains at a high level, and the sixth input node becomes high, thus resetting the first and second storage nodes to a low level.
[0025] During loading, the sixth input node is first brought to a low level to cancel the reset state, and then the fifth input node is brought to a low level to open the data loading path. At this time, due to the different resistance values of the non-volatile memory cells on the left and right sides, the voltage division of the non-volatile memory cell on the side with the lower resistance is smaller, and the voltage of the memory node on this side is higher than that of the memory node on the other side. At the same time, due to the bistable structure formed by the first and second closed transistors, the memory node on the side with the higher voltage is pulled up to a high level, and the memory node on the side with the lower voltage is pulled down to a low level. The data in the non-volatile memory cells will be loaded into the memory node of the loading structure. At the same time, the first inverter and the second inverter in the readout structure invert the signal of the memory node and output it to the output node, completing the data loading process.
[0026] The present invention provides a self-loading memory structure suitable for non-volatile memory cells, which has the following beneficial effects:
[0027] (1) By using non-volatile memory cells as programming devices, the data configured in the non-volatile memory cell group will not be lost after the FPGA is powered off;
[0028] (2) Compared with traditional SRAM-type FPGAs, based on the characteristics of non-volatile memory cells, it does not need to read data from external configuration memory to run when powered on, resulting in fast startup speed and high data reliability and confidentiality.
[0029] (3) Compared with Flash FPGA, it has a higher number of erase and write cycles and greater flexibility due to the characteristics of non-volatile memory cells. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of a self-loading storage structure suitable for non-volatile memory cells provided by the present invention.
[0031] Figure 2 This is a schematic diagram of the programming principle of MRAM type non-volatile memory cell.
[0032] Figure 3 This is a schematic diagram illustrating the programming operation of a self-loading memory structure applicable to non-volatile memory units.
[0033] Figure 4This is a schematic diagram of a loading operation method for a self-loading storage structure applicable to non-volatile memory cells. Detailed Implementation
[0034] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a self-loading memory structure suitable for non-volatile memory cells proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0035] This invention provides a self-loading memory structure suitable for non-volatile memory cells, the implementation of which is as follows: Figure 1 As shown, it includes a programming structure, a loading structure, a reset structure, and a read structure. The programming structure is used to store configuration data into a non-volatile memory unit through a programming path; the loading structure is used to load the data stored in the programming structure; the reset structure is used to reset the loading structure before loading; and the read structure is used to read the data from the loading structure.
[0036] The programming structure includes: two non-volatile memory cells and two programming transistors; the two non-volatile memory cells are a left non-volatile memory cell M1 and a right non-volatile memory cell M2, and the two programming transistors are a first programming transistor N1 and a second programming transistor N2; the first terminal of the left non-volatile memory cell M1 is connected to the drain of the first programming transistor N1 to form a first transmission node T1, and the second terminal of the left non-volatile memory cell M1 is connected to VDD; the first terminal of the right non-volatile memory cell M2 is connected to the drain of the second programming transistor N2 to form a second transmission node T2, and the second terminal of the right non-volatile memory cell M2 is connected to VDD; the gate of the first programming transistor N1 is connected to the first input node A1, the source is connected to the third input node BL, and the drain is connected to the first transmission node T1; the gate of the second programming transistor N2 is connected to the second input node A2, the source is connected to the fourth input node BLB, and the drain is connected to the second transmission node T2.
[0037] The loading structure includes two isolation transistors and two closed-circuit transistors; the two isolation transistors are the first isolation transistor P1 and the second isolation transistor P2, and the two closed-circuit transistors are the first closed-circuit transistor N5 and the second closed-circuit transistor N6; the first closed-circuit transistor N5 and the second closed-circuit transistor N6 form a bistable circuit, forming the first storage node B1 and the second storage node B2; the gate of the first closed-circuit transistor N5 is connected to the first storage node B1, the source is grounded, and the drain is connected to the second storage node B2; the gate of the second closed-circuit transistor N6 is connected to the second storage node B2, the source is grounded, and the drain is connected to the first storage node B1; the gate of the first isolation transistor P1 is connected to the fifth input node A4, the source is connected to the first transmission node T1, and the drain is connected to the second storage node B2; the gate of the second isolation transistor P2 is connected to the fifth input node A4, the source is connected to the second transmission node T2, and the drain is connected to the first storage node B1.
[0038] The reset structure includes two reset transistors, namely the first reset transistor N3 and the second reset transistor N4; wherein the gate of the first reset transistor N3 is connected to the sixth input node A3, the source is grounded, and the drain is connected to the second memory node B2; the gate of the second reset transistor N4 is connected to the sixth input node A3, the source is grounded, and the drain is connected to the first memory node B1.
[0039] The readout structure includes two inverters, namely the first inverter X1 and the second inverter X2; wherein the input terminal of the first inverter X1 is connected to the first storage node B1 and the output terminal is connected to the first output node Z1; the input terminal of the second inverter X2 is connected to the second storage node B2 and the output terminal is connected to the second output node Z2.
[0040] This invention provides a programming timing diagram for a self-loading memory structure applicable to non-volatile memory cells, including four states: power-on, encoding "1", holding, and encoding "0". Programming is performed by programming the left non-volatile memory cell M1 and the right non-volatile memory cell M2 through a programming path, storing data in the left non-volatile memory cell M1 and the right non-volatile memory cell M2.
[0041] The programming path includes a left non-volatile memory cell M1 programming path and a right non-volatile memory cell M2 programming path; wherein the left non-volatile memory cell M1 programming path includes: a first input node A1, a first programming tube N1, a third input node BL, and a left non-volatile memory cell M1; the right non-volatile memory cell M2 programming path includes: a second input node A2, a second programming tube N2, a fourth input node BLB, and a right non-volatile memory cell M2.
[0042] Non-volatile memory cells include types such as flash, MRAM, and PCM. Those skilled in the art will understand that flash is a type of non-volatile memory cell based on a floating-gate transistor, storing data as charge in the floating gate; even after power is off, the charge remains in the floating gate. MRAM is a type of non-volatile memory cell that uses the magnetization direction of a magnetic material to store data; data writing and reading are achieved by controlling the magnetization direction of the magnetic layer in the magnetic tunnel junction. PCM is a type of non-volatile memory cell that stores data through the principle of phase change materials transitioning between crystalline and amorphous states.
[0043] Non-volatile memory cells, such as MRAM, are programmed according to the following principles: Figure 2 As shown. Those skilled in the art will understand that an MRAM element is a magnetic memory based on electron spin torque. By changing the direction of the write current, the magnetoresistance state of the MTJ (Magnetic Tunneling Junction) can be altered, placing it in a "high" or "low" resistance state. When current passes from the fixed layer through the isolation layer, it changes the direction of the magnetic field in the free layer. Since the magnetic field direction of the fixed layer remains constant, when the magnetization direction of the free layer is in the same direction as that of the fixed layer, the MTJ exhibits a "low" resistance state. When the current direction is changed, and the magnetization direction of the free layer is opposite to that of the fixed layer, the MTJ exhibits a "high" resistance state.
[0044] In this embodiment, there are two non-volatile memory units (i.e., left non-volatile memory unit M1 and right non-volatile memory unit M2). One end of the left non-volatile memory unit M1 is connected to the first transmission node T1, and the other end is connected to VDD. The first transmission node T1 is connected to the third input node BL through the first programming tube N1. One end of the right non-volatile memory unit M2 is connected to the second transmission node T2, and the other end is connected to VDD. The second transmission node T2 is connected to the fourth input node BLB through the second programming tube N2.
[0045] Programming sequence such as Figure 3 As shown, there are four main states: power on, set to "1", hold, and set to "0".
[0046] Upon power-up, the first input node A1 and the second input node A2 are both at low level, the fifth input node A4 is at high level, and the power supply voltage VDD rises to the programming voltage.
[0047] When programming to "1", the third input node BL line = "0", the fourth input node BLB line = "1", the first input node A1 and the second input node A2 are pulled high, turning on the two programming transistors. When the voltage difference across the left non-volatile memory cell M1 is higher than the threshold voltage of the left non-volatile memory cell, the left non-volatile memory cell M1 will change from a "high" resistance state to a "low" resistance state. At the same time, because the fourth input node BLB line = "1", the voltage difference across the right non-volatile memory cell M2 is less than the threshold voltage of the right non-volatile memory cell, and the right non-volatile memory cell M2 will remain in a "high" resistance state.
[0048] During the holding period, the power supply voltage VDD remains at the programming voltage level, the third input node BL line and the fourth input node BLB line go low, the first input node A1 and the second input node A2 also go low, turning off the two programming transistors and disconnecting the programming path;
[0049] When programming to "0", the third input node BL line is set to "1", the fourth input node BLB line is set to "0", and the first input node A1 and the second input node A2 are pulled high, turning on the two programming transistors. When the voltage difference across the right non-volatile memory cell M2 is higher than the threshold voltage of the right non-volatile memory cell, the right non-volatile memory cell M2 will change from a "high" resistance state to a "low" resistance state. At the same time, because the third input node BL line is set to "1", the voltage difference across the left non-volatile memory cell M1 is lower than the threshold voltage of the left non-volatile memory cell, and the left non-volatile memory cell M1 will remain in a "high" resistance state.
[0050] In this embodiment, the programming timing includes four states: power-on, encoding "1", holding, and encoding "0". The timing configuration can be determined based on the programming data, and the configuration data is stored in a non-volatile memory unit. The data in the non-volatile memory unit can be used through the self-loading timing to load the data into the first storage node B1 and the second storage node B2 in the loading structure.
[0051] Furthermore, this invention provides a self-loading timing sequence for a self-loading memory structure applicable to non-volatile memory cells, loading data stored in the non-volatile memory cells into the first storage node B1 and the second storage node B2 in the loading structure, such as... Figure 4 As shown, it includes three states: power-on, reset, and load.
[0052] When powered on, the first input node A1, the second input node A2 and the sixth input node A3 are all at low level, the fifth input node A4 is at high level, and the power supply voltage is the normal operating voltage.
[0053] During reset, the first input node A1 and the second input node A2 remain at a low level, the fifth input node A4 remains at a high level, and the sixth input node A3 becomes high, causing the first storage node B1 and the second storage node B2 to reset to a low level.
[0054] During loading, the sixth input node A3 is first set to low level to cancel the reset state, and then the fifth input node A4 is set to low level to open the data loading path. At this time, due to the different resistance values of the non-volatile memory cell M1 on the left and the non-volatile memory cell M2 on the right, the voltage division of the non-volatile memory cell on the side with the lower resistance is small, and the voltage of the memory node on this side is higher than that of the memory node on the other side. At the same time, due to the bistable structure formed by the first closed tube N5 and the second closed tube N6, the memory node on the side with the higher voltage will be pulled up to high level, and the memory node on the side with the lower voltage will be pulled down to low level. The data in the non-volatile memory cell will be loaded into the memory nodes of the loading structure (i.e., the first memory node B1 and the second memory node B2). At the same time, the first inverter X1 and the second inverter X2 in the read structure will invert the signal of the memory node and output it to the output node, completing the data loading process.
[0055] The self-loading timing sequence includes three states: power-on, reset, and loading. It can load data from non-volatile memory cells into the storage nodes of the loading structure.
[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A self-loading memory structure suitable for non-volatile memory cells, characterized in that, include: Programming structure, loading structure, reset structure, read structure; The programming structure is used to store configuration data into a non-volatile storage unit through a programming path; The loading structure is used to load data stored in the programming structure; The reset structure is used to reset the loading structure before loading; The readout structure is used to read data from the loading structure; The programming structure includes a left non-volatile memory cell and a right non-volatile memory cell, a first programming tube and a second programming tube; The first end of the left non-volatile memory cell is connected to the drain of the first programming transistor to form the first transmission node, and the second end of the left non-volatile memory cell is connected to the power supply voltage VDD. The first terminal of the right non-volatile memory cell is connected to the drain of the second programming transistor to form the second transmission node, and the second terminal of the right non-volatile memory cell is connected to the power supply voltage VDD; the gate of the first programming transistor is connected to the first input node, the source is connected to the third input node, and the drain is connected to the first transmission node. The gate of the second programming transistor is connected to the second input node, the source is connected to the fourth input node, and the drain is connected to the second transmission node. The loading structure includes a first isolation tube and a second isolation tube, a first closed-circuit tube and a second closed-circuit tube; the first closed-circuit tube and the second closed-circuit tube constitute a bistable circuit to form a first memory node and a second memory node; the gate of the first closed-circuit tube is connected to the first memory node, the source is grounded, and the drain is connected to the second memory node. The gate of the second closed transistor is connected to the second memory node, the source is grounded, and the drain is connected to the first memory node. The gate of the first isolation transistor is connected to the fifth input node, the source is connected to the first transmission node, and the drain is connected to the second memory node. The gate of the second isolation transistor is connected to the fifth input node, the source is connected to the second transmission node, and the drain is connected to the first memory node.
2. The self-loading memory structure applicable to non-volatile memory cells as described in claim 1, characterized in that, The reset structure includes a first reset transistor and a second reset transistor; wherein the gate of the first reset transistor is connected to the sixth input node, the source is grounded, and the drain is connected to the second memory node; the gate of the second reset transistor is connected to the sixth input node, the source is grounded, and the drain is connected to the first memory node.
3. The self-loading memory structure applicable to non-volatile memory cells as described in claim 2, characterized in that, The readout structure includes a first inverter and a second inverter; wherein the input terminal of the first inverter is connected to the first storage node and the output terminal is connected to the first output node; the input terminal of the second inverter is connected to the second storage node and the output terminal is connected to the second output node.
4. The self-loading memory structure applicable to non-volatile memory cells as described in claim 3, characterized in that, The self-loading storage structure includes programming timing and loading timing; The programming timing involves programming the left and right non-volatile memory units through a programming path, and storing the data in the left and right non-volatile memory units. The loading sequence involves loading data stored in non-volatile memory cells into the first and second memory nodes in the loading structure; the programming path includes a left non-volatile memory cell programming path and a right non-volatile memory cell programming path. The first input node, the first programming tube, the third input node, and the left non-volatile memory cell constitute the programming path of the left non-volatile memory cell; the second input node, the second programming tube, the fourth input node, and the right non-volatile memory cell constitute the programming path of the right non-volatile memory cell.
5. The self-loading memory structure applicable to non-volatile memory cells as described in claim 4, characterized in that, The programming timing includes four states: power-on, encoding "1", holding, and encoding "0". Upon power-up, the first and second input nodes are both at a low level, the fifth input node is at a high level, and the power supply voltage VDD rises to the programming voltage. When programming "1", the third input node is "0", the fourth input node is "1", the first and second input nodes are pulled high, and the two programming transistors are turned on. When the voltage difference across the left non-volatile memory cell is higher than the threshold voltage of the left non-volatile memory cell, the left non-volatile memory cell changes from a high-resistance state to a low-resistance state. At the same time, because the fourth input node is "1", the voltage difference across the right non-volatile memory cell is less than the threshold voltage of the right non-volatile memory cell, and the right non-volatile memory cell remains in a high-resistance state. During the holding period, the power supply voltage VDD remains at the programming voltage level, the third and fourth input nodes go low, the first and second input nodes also go low, the two programming transistors are turned off, and the programming path is disconnected. When programming to "0", the third input node is "1", the fourth input node is "0", the first input node and the second input node are pulled high, and the two programming transistors are turned on. When the voltage difference across the right non-volatile memory cell is higher than the threshold voltage of the right non-volatile memory cell, the right non-volatile memory cell changes from a high-resistance state to a low-resistance state. At the same time, because the third input node is "1", the voltage difference across the left non-volatile memory cell is less than the threshold voltage of the left non-volatile memory cell, and the left non-volatile memory cell remains in a high-resistance state.
6. The self-loading memory structure applicable to non-volatile memory cells as described in claim 5, characterized in that, The loading sequence includes three states: power-on, reset, and loading. When powered on, the first input node, the second input node, and the sixth input node are all at low level, the fifth input node is at high level, and the power supply voltage is the normal operating voltage. During reset, the first and second input nodes remain at a low level, the fifth input node remains at a high level, and the sixth input node becomes high, thus resetting the first and second storage nodes to a low level. During loading, the sixth input node is first brought to a low level to cancel the reset state, and then the fifth input node is brought to a low level to open the data loading path. At this time, due to the different resistance values of the non-volatile memory cells on the left and right sides, the voltage division of the non-volatile memory cell on the side with the lower resistance is smaller, and the voltage of the memory node on this side is higher than that of the memory node on the other side. At the same time, due to the bistable structure formed by the first and second closed transistors, the memory node on the side with the higher voltage is pulled up to a high level, and the memory node on the side with the lower voltage is pulled down to a low level. The data in the non-volatile memory cells will be loaded into the memory node of the loading structure. At the same time, the first inverter and the second inverter in the readout structure invert the signal of the memory node and output it to the output node, completing the data loading process.
Citation Information
Patent Citations
Self-loading storage structure suitable for phase change storage
CN117727352A