Method for reducing ohmic contact resistance and application thereof
By thinning and ion implantation activation in the heterostructure of GaN HEMT radio frequency devices, a heavily doped ohmic contact layer is formed, which solves the problem of high ohmic contact resistance in the prior art and achieves the effect of low ohmic contact resistance.
Patent Information
- Application Number
- CN202411792733.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-07
- Publication Date
- 2025-04-04
AI Technical Summary
In the manufacturing process of GaN HEMT radio frequency devices, it is difficult for the prior art to effectively reduce the ohmic contact resistance, especially when the activation rate of the AlGaN surface ions is low and the work function is low, it is difficult to form efficient ohmic contact.
The combination method of heterostructures includes thinning in the ohmic region of the heterostructure, retaining the carrier channel, and epitaxially growing the third semiconductor layer on the second semiconductor layer, followed by ion implantation activation to form a heavily doped ohmic contact layer.
Through this method, the carrier density of the ohmic contact layer is achieved to reach 3E20/cm^3-5E21/cm^3, and the square resistance is between 10Ω/□-50Ω/□, which significantly reduces the ohmic contact resistance.
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Figure CN119764165A_ABST
Abstract
Description
Technical Field
[0001] The present invention particularly relates to a method for reducing ohmic contact resistance and application thereof, belonging to the technical field of micro-nano manufacturing. Background Art
[0002] In the manufacturing process of GaN HEMT RF devices, the characteristics of ohmic contact directly affect the RF performance of the device. Currently, the commonly used methods to achieve low ohmic contact are secondary epitaxy and ion implantation. Their common feature is that they form a heavily doped area under the ohmic metal, increasing the carrier concentration in the semiconductor, making it easier to form ohmic contact with the ohmic metal.
[0003] like Figure 1 As shown in the figure, the secondary epitaxial growth process mainly includes: growing SiO2 mask, etching off the mask of the regenerated ohmic area, epitaxial n + GaN, using chemical to remove mask and excess n + GaN. Figure 2 The ion implantation process shown in the figure mainly includes: substrate cleaning, device isolation, SiO2 as hard mask, etching the implantation area, depositing the buffer layer, Si + Injection, activation protection, high temperature activation, removal of activation protection layer.
[0004] For secondary epitaxial technology, the difficulties lie in material matching and lattice mismatch, doping control, and the selection of growth temperature and growth rate. For ion implantation technology, when the surface is AlGaN, the activation rate of ions in it is not high, and AlGaN has a lower work function, making it difficult to form ohmic contact with ohmic metals. Summary of the invention
[0005] The main purpose of the present invention is to provide a method for reducing ohmic contact resistance and its application, so as to overcome the deficiencies in the prior art.
[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes: A first aspect of an embodiment of the present invention provides a method for reducing ohmic contact resistance, characterized by comprising: Providing a heterojunction structure, the heterojunction structure comprising a first semiconductor layer and a second semiconductor layer stacked, the first semiconductor layer having a carrier channel at an interface close to the second semiconductor layer; Thinning the second semiconductor layer located in the ohmic region, and retaining the carrier channel below the second semiconductor layer located in the ohmic region; epitaxially growing a third semiconductor layer on the second semiconductor layer located in the ohmic region; Ion implantation is performed on the third semiconductor layer, and the implanted impurity ions are activated, thereby converting the third semiconductor layer into a heavily doped ohmic contact layer, wherein the ohmic contact layer is used to form an ohmic contact structure with an ohmic metal, and the carrier density corresponding to the ohmic contact layer is 3E20 / cm^3-5E21 / cm^3, and the square resistance of the ohmic contact layer is 10Ω / □-50Ω / □.
[0007] A second aspect of an embodiment of the present invention provides a method for preparing an ohmic contact structure with low ohmic contact resistance, comprising: An epitaxial structure is obtained by adopting the method for reducing ohmic contact resistance, wherein the epitaxial structure comprises a heterostructure and an ohmic contact layer, and the ohmic contact layer is arranged in an ohmic region of the heterostructure; And, an ohmic metal is formed on the ohmic contact layer, and the ohmic metal and the ohmic contact layer form an ohmic contact structure.
[0008] A third aspect of the embodiments of the present invention provides an ohmic contact structure with low ohmic contact resistance obtained by the method for preparing the ohmic contact structure with low ohmic contact resistance.
[0009] A fourth aspect of an embodiment of the present invention provides a HEMT radio frequency device with low ohmic contact resistance, comprising: An epitaxial structure obtained by the method for reducing ohmic contact resistance, wherein the epitaxial structure comprises a heterostructure and an ohmic contact layer, wherein the ohmic contact layer is arranged in an ohmic region of the heterostructure; And, a source, a drain and a gate, wherein the source and the drain are arranged on the ohmic contact layer and form an ohmic contact with the ohmic contact layer, and the gate is arranged on the heterostructure and located between the source and the drain.
[0010] Compared with the prior art, the advantages of the present invention include: the present invention adopts a combination of secondary epitaxy and ion implantation to obtain an ohmic contact layer, which reduces the process difficulty. At the same time, the present invention retains part of the barrier layer in the ohmic region, so that there is a two-dimensional electron gas with a high concentration under the ohmic metal. In this way, a lower ohmic contact resistance can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a schematic diagram of the process flow of forming an ohmic contact layer by secondary epitaxy in the prior art; Figure 2 It is a schematic diagram of the process flow of forming an ohmic contact layer by ion implantation in the prior art; Figure 3 It is a schematic diagram of a preparation process of a HEMT radio frequency device provided in a typical implementation case of the present invention; Figure 4 It is the resistance diagram of each part after the ohmic contact resistance is refined; Figure 5 is the energy of the ion implantation used in Example 1 and the distribution of the implanted ions in the sample, Figure 6 is the energy of the ion implantation used in Comparative Example 3 and the distribution of the implanted ions in the sample, Figure 7 The ion implantation energy used in Example 4 and the distribution of the implanted ions in the sample are shown. DETAILED DESCRIPTION
[0012] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.
[0013] A first aspect of an embodiment of the present invention provides a method for reducing ohmic contact resistance, characterized by comprising: Providing a heterojunction structure, the heterojunction structure comprising a first semiconductor layer and a second semiconductor layer stacked, the first semiconductor layer having a carrier channel at an interface close to the second semiconductor layer; Thinning the second semiconductor layer located in the ohmic region, and retaining the carrier channel below the second semiconductor layer located in the ohmic region; epitaxially growing a third semiconductor layer on the second semiconductor layer located in the ohmic region; Ion implantation is performed on the third semiconductor layer, and the implanted impurity ions are activated, thereby converting the third semiconductor layer into a heavily doped ohmic contact layer, wherein the ohmic contact layer is used to form an ohmic contact structure with an ohmic metal, and the carrier density corresponding to the ohmic contact layer is 3E20 / cm^3-5E21 / cm^3, and the square resistance of the ohmic contact layer is 10Ω / □-50Ω / □.
[0014] Furthermore, the thickness of the second semiconductor layer remaining below the third semiconductor layer is 5nm-10nm.
[0015] Furthermore, the concentration of impurity ions in a surface region of the third semiconductor layer away from the second semiconductor layer is greater than the concentration of impurity ions in a bottom region close to the second semiconductor layer.
[0016] In a more specific embodiment, the method for reducing ohmic contact resistance specifically includes: first covering the third semiconductor layer with an injection buffer layer, and then performing ion implantation on the third semiconductor layer so that the concentration of impurity ions in the surface area of the third semiconductor layer away from the second semiconductor layer is greater than the concentration of impurity ions in other areas, and removing the injection buffer layer after the ion implantation is completed.
[0017] Furthermore, the thickness of the injection buffer layer is 30nm-100nm.
[0018] Furthermore, the material of the injection buffer layer includes silicon nitride.
[0019] In a more specific embodiment, the method for reducing ohmic contact resistance specifically includes: performing two ion implantations on the third semiconductor layer, the implantation energy of the first ion implantation is less than the implantation energy of the second ion implantation, and the implantation dose of the first ion implantation is less than the implantation dose of the second ion implantation.
[0020] Furthermore, the first ion implantation has an implantation energy of 30keV-50keV and an implantation dose of 5E14cm -2 -6E15cm -2 The second ion implantation energy is 70keV-200keV and the implantation dose is 1E15cm -2 -8E15cm -2 .
[0021] Furthermore, the impurity ions include Si ions, Mg ions or Al ions.
[0022] Furthermore, the first semiconductor layer serves as a channel layer, the second semiconductor layer serves as a barrier layer, and the carrier channel may be a two-dimensional electron gas.
[0023] Furthermore, the material of the first semiconductor layer includes GaN or GaAs, the material of the second semiconductor layer includes AlGaN or AlGaAs, and the material of the third semiconductor layer includes GaN or GaAs.
[0024] A second aspect of an embodiment of the present invention provides a method for preparing an ohmic contact structure with low ohmic contact resistance, comprising: An epitaxial structure is obtained by adopting the method for reducing ohmic contact resistance, wherein the epitaxial structure comprises a heterostructure and an ohmic contact layer, and the ohmic contact layer is arranged in an ohmic region of the heterostructure; And, an ohmic metal is formed on the ohmic contact layer, and the ohmic metal and the ohmic contact layer form an ohmic contact structure.
[0025] A third aspect of the embodiments of the present invention provides an ohmic contact structure with low ohmic contact resistance obtained by the method for preparing the ohmic contact structure with low ohmic contact resistance.
[0026] A fourth aspect of an embodiment of the present invention provides a HEMT radio frequency device with low ohmic contact resistance, comprising: An epitaxial structure obtained by the method for reducing ohmic contact resistance, wherein the epitaxial structure comprises a heterostructure and an ohmic contact layer, wherein the ohmic contact layer is arranged in an ohmic region of the heterostructure; And, a source, a drain and a gate, wherein the source and the drain are arranged on the ohmic contact layer and form an ohmic contact with the ohmic contact layer, and the gate is arranged on the heterostructure and located between the source and the drain.
[0027] The technical solution, its implementation process and principles, etc. will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial growth process and equipment thereof, secondary epitaxial growth process and equipment thereof, photolithography / etching process and equipment thereof, ion implantation equipment, annealing activation process and equipment thereof, etc. used in the embodiments of the present invention may all be known in the art and are not specifically limited here.
[0028] See also Figure 3 In a more specific embodiment, a method for preparing a GaN HEMT radio frequency device comprises the following steps: (a) Providing an epitaxial wafer and growing a SiO2 mask on the epitaxial wafer. The epitaxial wafer comprises a GaN channel layer (i.e., the aforementioned first semiconductor layer) and an AlGaN barrier layer (i.e., the aforementioned second semiconductor layer) stacked in sequence on a SiC substrate, the GaN channel layer and the AlGaN barrier layer forming a heterostructure, a two-dimensional electron gas (2DEG) being formed at the interface of the GaN channel layer near the AlGaN barrier layer, and the SiO2 mask covering the AlGaN barrier layer; (b) Removing the SiO2 mask located in the ohmic region. Specifically, the SiO2 mask located in the ohmic region may be removed by dry etching or the like.
[0029] (c) The AlGaN barrier layer located in the ohmic region and not covered by the SiO2 mask is etched along the thickness direction to remove the surface portion of the AlGaN barrier layer, and an AlGaN barrier layer with a thickness of 5nm-10nm is retained in the ohmic region to retain the two-dimensional electron gas below the ohmic region. If the thickness of the remaining AlGaN barrier layer is less than 5nm, the two-dimensional electron gas below it cannot be maintained. If the thickness of the AlGaN barrier layer is greater than 10nm, the probability of electrons passing through the AlGaN barrier layer will be greatly increased.
[0030] (d) A secondary epitaxial GaN contact layer (i.e., the aforementioned third semiconductor layer) is grown on the surface of the sample obtained in step (c), and the thickness of the GaN contact layer is less than 500 nm.
[0031] (e) The SiO2 mask and the GaN contact layer on the SiO2 mask are removed, leaving only the GaN contact layer on the AlGaN barrier layer in the ohmic region.
[0032] (f) A SiO2 mask is grown on the surface of the sample obtained in step (e), and the SiO2 mask continuously covers the GaN contact layer in the ohmic region and the AlGaN barrier layer in the non-ohmic region.
[0033] (g) Removal of the SiO2 mask located in the ohmic region.
[0034] (h) A SiNx implantation buffer layer is grown on the surface of the sample obtained in step (g), wherein the thickness of the SiNx implantation buffer layer is 30 nm-100 nm.
[0035] (i) Ion implantation was performed twice into the GaN contact layer. The first ion implantation had an implantation energy of 30keV-50keV and an implantation dose of 5E14cm -2 -6E15cm -2 The second ion implantation energy is 70keV-200keV and the implantation dose is 1E15cm -2 -8E15cm -2 The impurity ions implanted are Si ions.
[0036] It should be noted that, since a SiNx injection buffer layer is provided on the GaN contact layer, after ion injection, the concentration of Si ions in the surface region of the n++GaN contact layer away from the AlGaN barrier layer is greater than the concentration of Si ions in other regions, so that the resistance of the surface portion of the n++GaN contact layer away from the AlGaN barrier layer is lower, making it easier for electrons to pass. Specifically, the impurity ion distribution in the n++GaN contact layer is a Gaussian distribution, and the injection buffer layer can control the ion concentration on the surface of the n++GaN contact layer to reach the expected concentration. Although the distribution after ion injection is non-uniform, the peak value of the Gaussian distribution can be determined. The present invention can control the thickness of the injection buffer layer to make the peak position on the sample surface. The electron concentration in the metal body is about 5E22 / cm^3. In order to reduce the resistance at the contact as much as possible, the electron concentration at the contact of the ohmic contact layer reaches 3E20-5E21 / cm^3, and the square resistance of the ohmic contact layer is 10Ω / □-50Ω / □.
[0037] (j) Removal of SiO2 mask and SiNx implantation buffer layer.
[0038] (k) growing a high temperature activated protection structure on the surface of the sample obtained in step (j), and performing a high temperature annealing activation treatment to activate Si ions in the GaN contact layer, thereby converting the GaN contact layer into an n++GaN contact layer.
[0039] (l) An ohmic metal is deposited on the n++GaN contact layer to form an ohmic contact with the n++GaN contact layer, and a gate metal is deposited on the AlGaN barrier layer.
[0040] Specifically, the ohmic contact layer has a square resistance of for:
[0041] Among them, x1 is the effective depth of ion implantation (i.e., the thickness of the ohmic contact layer), which is related to the energy used during ion implantation. is the specific distribution of ions after ion implantation, which is generally a Gaussian distribution. This is related to the dose used during ion implantation and can also be obtained through simulation. P is the activation rate of impurity ions after subsequent high-temperature activation. is the carrier mobility, q is a constant, and the value of q is .
[0042] The semiconductor material at the ohmic metal contact in the present invention is GaN or GaAs. GaN or GaAs has a higher work function than the AlGaN or AlGaAs barrier layer and can form a low-ohmic contact with the ohmic metal. In addition, when the barrier layer is etched and thinned before the secondary epitaxy of GaN or GaAs, since part of the barrier layer is retained in the ohmic region, there is a relatively high concentration of two-dimensional electron gas under the remaining barrier layer, so that more electrons tunnel through the barrier layer, thereby achieving a lower ohmic contact effect.
[0043] Figure 4 The resistance of each part after the ohmic contact resistance is refined is shown, where R1 is the resistance of the ohmic metal, R2 is the resistance at the contact, R3 is the resistance below the contact, and R4 is the channel resistance. Since the ohmic contact is generally a symmetrical structure, the diagram only shows half of the resistance composition. R1 and R4 cannot be changed, because R1 is only related to the structure and thickness of the ohmic metal, and R4 is only related to the semiconductor epitaxial wafer. The strategy to effectively reduce R2 is to have a higher concentration of carriers on the semiconductor surface, and the way to effectively reduce R3 is to make the square resistance here as small as possible. The purpose of retaining a higher concentration of carriers on the surface after ion implantation in the present invention is to reduce R2, and the purpose of high-energy implantation is to form a lower square resistance below the contact.
[0044] Example 1 A method for preparing a low-ohmic contact comprises the following steps: (a) An Fe-GaN buffer layer with a thickness of about 200 nm, an unintentionally doped GaN layer with a thickness of about 300 nm, a GaN channel layer with a thickness of about 80 nm, an AlN space layer with a thickness of about 0.7 nm, and an AlGaN barrier layer with a thickness of about 26 nm are sequentially grown on a silicon carbide substrate by an MOCVD process to form a semiconductor epitaxial wafer, and a SiO2 mask is covered on the AlGaN barrier layer of the semiconductor epitaxial wafer.
[0045] (b) Etching removes the SiO2 mask located in the ohmic area.
[0046] (c) The AlGaN barrier layer located in the ohmic region and not covered by the SiO2 mask is etched along the thickness direction to remove the surface portion of the AlGaN barrier layer and retain the AlGaN barrier layer with a thickness of 5 nm in the ohmic region.
[0047] (d) A GaN contact layer with a thickness of 150 nm is grown on the surface of the sample obtained in step (c).
[0048] (e) The SiO2 mask and the GaN contact layer on the SiO2 mask are removed by wet etching, leaving only the GaN contact layer on the AlGaN barrier layer in the ohmic region.
[0049] (f) A SiO2 mask is grown on the surface of the sample obtained in step (e), and the SiO2 mask continuously covers the GaN contact layer in the ohmic region and the AlGaN barrier layer in the non-ohmic region.
[0050] (g) Etching removes the SiO2 mask located in the ohmic area.
[0051] (h) A SiNx implantation buffer layer with a thickness of 50 nm is grown on the surface of the sample obtained in step (g).
[0052] (i) The GaN contact layer is ion-implanted twice. The first ion implantation has an implantation energy of 30 keV and an implantation dose of 6E15 cm -2 The second ion implantation has an implantation energy of 120keV and an implantation dose of 8E15cm -2 The impurity ions implanted are Si ions.
[0053] (j) Wet etching removes the SiO2 mask and SiNx implant buffer layer.
[0054] (k) A stacked Al2O3 protective layer and a SiNx protective layer are grown on the surface of the sample obtained in step (j) as a high temperature activation protection structure, and a high temperature annealing activation treatment is performed to activate Si ions in the GaN contact layer, thereby converting the GaN contact layer into an n++GaN contact layer.
[0055] (l) Use a wet etching process to remove the high temperature activated protection structure.
[0056] (m) depositing an ohmic metal on the n++GaN contact layer so that the ohmic metal forms an ohmic contact with the n++GaN contact layer, and depositing a gate metal on the AlGaN barrier layer.
[0057] Figure 5 The energy of ion implantation used in Example 1 and the distribution of implanted ions in the sample are shown. The buffer layer is set to 50nm, i.e., the position shown by the dotted line. It can be seen that the concentration of impurity ions on the surface of the n++GaN contact layer is above 2E20 / cm^3, which has a relatively high concentration. The square resistance of the n++GaN contact layer in Example 1 is obtained by calculation to be 50Ω / □.
[0058] Comparative Example 1 A low-ohmic contact preparation method (secondary epitaxy) comprises the following steps: (a) An Fe-GaN buffer layer with a thickness of about 200 nm, an unintentionally doped GaN layer with a thickness of about 300 nm, a GaN channel layer with a thickness of about 80 nm, an AlN space layer with a thickness of about 0.7 nm, and an AlGaN barrier layer with a thickness of about 26 nm are sequentially grown on a silicon carbide substrate by an MOCVD process to form a semiconductor epitaxial wafer, and a SiO2 mask is then covered on the AlGaN barrier layer of the semiconductor epitaxial wafer.
[0059] (b) Etching removes the barrier layer and SiO2 mask in the ohmic region.
[0060] (c) An n+GaN ohmic contact layer with a thickness of 150 nm was grown using MOCVD.
[0061] (d) Use BOE to remove the SiO2 mask and excess n+GaN.
[0062] Since the secondary epitaxy requires etching away the barrier layer in the ohmic region, there is no two-dimensional electron gas under the n+GaN ohmic contact layer after the barrier layer is etched. It is difficult for the n+GaN ohmic contact layer after the secondary epitaxy to form a good contact with the channel, and the technical requirements for epitaxy are relatively high. This process results in a large resistance R2.
[0063] Comparative Example 2 A low-ohmic contact preparation method (ion implantation) comprises the following steps: (a) An Fe-GaN buffer layer with a thickness of about 200 nm, an unintentionally doped GaN layer with a thickness of about 300 nm, a GaN channel layer with a thickness of about 80 nm, an AlN space layer with a thickness of about 0.7 nm, and an AlGaN barrier layer with a thickness of about 26 nm are sequentially grown on a silicon carbide substrate by an MOCVD process to form a semiconductor epitaxial wafer, and a SiO2 mask is then covered on the AlGaN barrier layer of the epitaxial wafer.
[0064] (b) The sample is photolithographically processed to expose the ohmic area, and the ohmic window is etched using a dry etching + wet etching method using photoresist as a mask.
[0065] (c) A SiNx implantation buffer layer is grown on the surface of the sample obtained in step (b), and the thickness of the SiNx implantation buffer layer is 50 nm.
[0066] (d) The contact layer is ion-implanted twice. The first ion implantation has an implantation energy of 30 keV and an implantation dose of 6E15 cm-2. The second ion implantation has an implantation energy of 120 keV and an implantation dose of 8E15 cm-2. The impurity ions implanted are Si ions.
[0067] (e) growing a high temperature activated protection structure on the surface of the sample obtained in step (d), the high temperature protection structure may be a combination of Al2O3 and SiNx, the thickness of Al2O3 may be 30nm, and the thickness of SiNx may be 400nm. performing a high temperature annealing activation treatment to activate Si ions in the contact layer.
[0068] (f) The high temperature protection layer is removed using a wet etching process.
[0069] (g) depositing an ohmic metal on the contact layer so that the ohmic metal forms an ohmic contact with the contact layer, and depositing a gate metal on the AlGaN barrier layer.
[0070] In comparative example 2, the ohmic contact layer of the ohmic metal is on the upper surface of the barrier layer, and the work function of AlGaN is lower than that of GaN. Therefore, after AlGaN and the metal form an alloy, it is not easy for electrons to pass through the contact, and thus the process causes a large resistance R2.
[0071] Comparative Example 3 A method for preparing a low-ohmic contact, the steps of Example 1 are basically the same, the only difference is that no injection buffer layer is added, and the ion distribution is obtained by simulation as shown in Figure 6 As shown, it can be seen that the carrier concentration at the ohmic contact surface is less than 2E19 / cm^3. This results in a large resistance value of R2 at the contact.
[0072] Comparative Example 4 A method for preparing a low-ohmic contact, the steps of Example 1 are basically the same, the only difference is that the energy injected is different, and the energy used in Comparative Example 4 is smaller than that in Example 1. The ion distribution is obtained by simulation as shown in Figure 7 As shown, it can be seen that the ion concentration at the ohmic contact has reached more than 2E20 / cm^3, which has a high concentration. However, due to the decrease in injection energy, the depth of the ions below the ohmic contact area is small. After calculation, it is found that the square resistance below the contact is about 120Ω / □. In this comparative example, the resistance of R3 is large, which affects the formation of low ohmic contact.
[0073] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for reducing ohmic contact resistance, characterized in that: include: Providing a heterojunction structure, the heterojunction structure comprising a first semiconductor layer and a second semiconductor layer stacked, the first semiconductor layer having a carrier channel at an interface close to the second semiconductor layer; Thinning the second semiconductor layer located in the ohmic region, and retaining the carrier channel below the second semiconductor layer located in the ohmic region; epitaxially growing a third semiconductor layer on the second semiconductor layer located in the ohmic region; Ion implantation is performed on the third semiconductor layer, and the implanted impurity ions are activated, thereby converting the third semiconductor layer into a heavily doped ohmic contact layer, wherein the ohmic contact layer is used to form an ohmic contact structure with an ohmic metal, and the carrier density corresponding to the ohmic contact layer is 3E20 / cm^3-5E21 / cm^3, and the square resistance of the ohmic contact layer is 10Ω / □-50Ω / □.
2. The method for reducing ohmic contact resistance according to claim 1, characterized in that: Features: The thickness of the second semiconductor layer remaining under the third semiconductor layer is 5nm-10nm.
3. The method for reducing ohmic contact resistance according to claim 1, characterized in that: The concentration of impurity ions in a surface region of the third semiconductor layer away from the second semiconductor layer is greater than the concentration of impurity ions in a bottom region close to the second semiconductor layer.
4. The method for reducing ohmic contact resistance according to claim 3, characterized in that: Features: Firstly, covering the third semiconductor layer with an injection buffer layer, and then performing ion implantation on the third semiconductor layer, so that the concentration of impurity ions in the surface region of the third semiconductor layer away from the second semiconductor layer is greater than the concentration of impurity ions in other regions, and removing the injection buffer layer after the ion implantation is completed; Preferably, the impurity ions in the third semiconductor layer are Gaussian distributed.
5. The method for reducing ohmic contact resistance according to claim 4, characterized in that: The injection buffer layer has a thickness of 30 nm-100 nm; and / or the injection buffer layer is made of silicon nitride.
6. The method for reducing ohmic contact resistance according to claim 1, 3, 4 or 5, characterized in that: include: Performing ion implantation twice on the third semiconductor layer, wherein the implantation energy of the first ion implantation is less than the implantation energy of the second ion implantation, and the implantation dose of the first ion implantation is less than the implantation dose of the second ion implantation; Preferably, the first ion implantation has an implantation energy of 30keV-50keV and an implantation dose of 5E14cm -2 -6E15cm -2 The second ion implantation energy is 70keV-200keV and the implantation dose is 1E15cm -2 -8E15cm -2 ; Preferably, the impurity ions include Si ions, Mg ions or Al ions.
7. The method for reducing ohmic contact resistance according to claim 1, characterized in that: The material of the first semiconductor layer includes GaN or GaAs, the material of the second semiconductor layer includes AlGaN or AlGaAs, and the material of the third semiconductor layer includes GaN or GaAs.
8. A method for preparing an ohmic contact structure with low ohmic contact resistance, characterized in that: include: An epitaxial structure is obtained by adopting the method for reducing ohmic contact resistance according to any one of claims 1 to 7, wherein the epitaxial structure comprises a heterostructure and an ohmic contact layer, and the ohmic contact layer is arranged in an ohmic region of the heterostructure; And, an ohmic metal is formed on the ohmic contact layer, and the ohmic metal and the ohmic contact layer form an ohmic contact structure. 9 . An ohmic contact structure with low ohmic contact resistance obtained by the method for preparing an ohmic contact structure with low ohmic contact resistance according to claim 8 .
10. A HEMT radio frequency device with low ohmic contact resistance, characterized in that: include: An epitaxial structure obtained by the method for reducing ohmic contact resistance according to any one of claims 1 to 7, wherein the epitaxial structure comprises a heterostructure and an ohmic contact layer, and the ohmic contact layer is arranged in an ohmic region of the heterostructure; And, a source, a drain and a gate, wherein the source and the drain are arranged on the ohmic contact layer and form an ohmic contact with the ohmic contact layer, and the gate is arranged on the heterostructure and located between the source and the drain.