Semiconductor device and manufacturing method

Abstract

The invention provides a semiconductor device and a manufacturing method, and relates to the technical field of semiconductors. According to the semiconductor manufacturing method provided by the invention, the protection layer can be formed on the inner wall of the isolation groove, so that when the substrate is etched, the complete groove structure of the isolation groove is maintained by the protection layer based on the fact that the etching rate of the protection layer is smaller than that of the substrate; therefore, the basic structure of the isolation groove is not damaged along with the etching of the substrate. Therefore, based on the protection of the protective layer, the germanium-silicon accommodating structure formed in the source and drain regions of the semiconductor unit does not damage the adjacent isolation groove, so that both the isolation groove and the germanium-silicon accommodating structure have complete structures, and the performance of the semiconductor unit is ensured. Besides, in consideration that the germanium-silicon accommodating structure does not damage the adjacent isolation groove, when the germanium-silicon accommodating structure is prepared, the distance between the germanium-silicon accommodating structure and the isolation groove can be reduced, so that the integration level of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In semiconductor devices (especially P-type semiconductor devices), the source region and the drain region can adopt an embedded SiGe process to form a SiGe containing structure and fill it with SiGe material, so as to utilize the compressive stress generated by the different lattice constants of germanium and silicon to improve the mobility and saturation current of holes in the P-type semiconductor device.

[0003] However, due to the special shape of the SiGe containment structure, it is easy to affect other structures of the semiconductor device (such as isolation trenches) during its formation. Therefore, how to ensure the device integrity of the semiconductor device when forming the SiGe containment structure is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a semiconductor device and a manufacturing method. Before executing the embedded silicon-germanium process, a protective layer is formed at the isolation trench to prevent the isolation trench from being damaged when executing the embedded silicon-germanium process, thereby ensuring the integrity of the semiconductor device.

[0005] In a first aspect, the present application provides a method for manufacturing a semiconductor device, the manufacturing method comprising: providing a substrate, wherein the substrate comprises a plurality of semiconductor units and isolation trenches separating the semiconductor units; forming a protective layer along the inner walls of the isolation trenches; etching the substrate to form a germanium-silicon containment structure in the source and drain regions of the semiconductor units, wherein when the substrate is etched, the etching rate of the protective layer is lower than the etching rate of the substrate so that the protective layer maintains the complete trench structure of the isolation trench; filling the germanium-silicon containment structure with germanium-silicon material; and forming the source and / or drain of the semiconductor unit in the source and drain regions based on the germanium-silicon containment structure.

[0006] In a second aspect, the present application provides a semiconductor device, comprising a plurality of semiconductor units provided in a substrate and isolation trenches separating the semiconductor units, the isolation trenches being used to separate adjacent semiconductor units; the source and drain regions of the semiconductor units comprising a silicon germanium containment structure and a source and / or drain formed on the silicon germanium containment structure; the isolation trench comprising a protective layer formed along an inner wall of the isolation trench, wherein the protective layer is used to maintain the complete trench structure of the isolation trench when the substrate is etched.

[0007] Based on the semiconductor manufacturing method provided by the present application, a protective layer can be formed at the inner wall of the isolation trench, so that when the substrate is etched, the protective layer maintains the complete trench structure of the isolation trench based on the fact that the etching rate of the protective layer is lower than the etching rate of the substrate, so as to retain the basic structure of the isolation trench so that it will not be destroyed as the substrate is etched. Thus, based on the protection of the aforementioned protective layer, the silicon-germanium containment structure formed in the source and drain region of the semiconductor unit will not damage the isolation trench adjacent thereto, so that the isolation trench and the silicon-germanium containment structure both have a complete structure, thereby ensuring the performance of the semiconductor unit. In addition, considering that the silicon-germanium containment structure will not damage the isolation trench adjacent thereto, when preparing the silicon-germanium containment structure, the distance between the silicon-germanium containment structure and the isolation trench can be reduced, thereby improving the integration of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 It is a schematic diagram of the effect of the reactive embedded germanium silicon process on the isolation trench provided in some embodiments of the present application.

[0010] Figure 2 It is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application.

[0011] Figure 3 is an exemplary flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present application.

[0012] Figure 4 It is a schematic diagram of the structure of a substrate provided in some embodiments of the present application.

[0013] Figure 5 It is a schematic diagram of the structure of another substrate provided in some embodiments of the present application.

[0014] Figure 6 It is a schematic diagram of the structure of a semiconductor device with a protective layer provided in some embodiments of the present application.

[0015] Figure 7 Some embodiments of the present application provide Figure 6 The schematic diagram of the structure of the semiconductor device shown is when a buffer layer is formed.

[0016] Figure 8 Some embodiments of the present application provide Figure 6 The schematic diagram of the structure of the semiconductor device shown is when a filling layer is formed.

[0017] Fig. 9 It is a schematic structural diagram of another semiconductor device with a protective layer provided in some embodiments of the present application.

[0018] Fig.10 Some embodiments of the present application provide Fig. 9 The schematic diagram of the structure of the semiconductor device shown is when a filling layer is formed.

[0019] Fig.11 It is a schematic diagram of the structure of a semiconductor device with a gate provided in some embodiments of the present application.

[0020] Fig.12 It is a schematic structural diagram of a semiconductor device with an initial trench provided in some embodiments of the present application.

[0021] Fig.13 It is a schematic diagram of the structure of a semiconductor device with a silicon-germanium containment structure provided in some embodiments of the present application.

[0022] Fig.14 It is a schematic diagram of the structure of a semiconductor device after the source and drain are formed, provided in some embodiments of the present application.

[0023] Among them, 100, semiconductor device; 120, isolation trench; 130, germanium silicon containment structure; 110, semiconductor unit; 111, P-type semiconductor unit; 112, N-type semiconductor unit; 131, source germanium silicon containment structure; 132, drain germanium silicon containment structure; 141, source; 142, drain; 121, protective layer; 143, gate; 144, metal wire; 122, buffer layer; 123, filling layer; 133, initial trench. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0026] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0027] Application Overview: As mentioned above, when the embedded silicon-germanium process is executed, the silicon-germanium containment structure formed therein often presents a sigma structure that first grows larger and then shrinks toward the inside of the substrate. When preparing the sigma structure, a groove is often first opened, and then the sidewalls of the groove are laterally etched to form a sigma-structured silicon-germanium containment structure. In this process, considering that the internal dimensions of the silicon-germanium containment structure are often larger than its opening dimensions, even if the isolation groove is avoided during the groove opening, the silicon-germanium containment structure can extend to the isolation groove when the sidewalls are laterally etched. When the silicon-germanium containment structure contacts the isolation groove, part of the sidewalls of the silicon-germanium containment structure and the isolation groove will fall off due to etching, destroying the integrity of the contact between the silicon-germanium containment structure and the isolation groove.

[0028] To further illustrate the damage of the aforementioned SiGe containing structure to the isolation trench, this application Figure 1 A schematic diagram is provided to reflect the effect of the embedded SiGe process on the isolation trench. Figure 1 It can be an electron microscope scanning image of a slice of a semiconductor device after an embedded silicon germanium process is performed to form a silicon germanium receiving structure.

[0029] like Figure 1 As shown, the semiconductor device 100 has an isolation trench 120 and a plurality of SiGe containing structures 130. As for the SiGe containing structures 130 near the isolation trench 120, the SiGe containing structures 130 are connected to the isolation trench 120, resulting in the sidewalls separating the isolation trench 120 and the SiGe containing structures 130 being etched away, destroying the complete structures of the SiGe containing structures 130 and the isolation trench 120. When the SiGe material (also called SiGe bulk layer) is subsequently filled, the SiGe material cannot fill the complete SiGe containing structures 130 due to the damage to the sidewalls, affecting the stress generated.

[0030] In addition, based on the aforementioned incomplete structure, in the subsequent silicide formation process, nickel material (Ni) may contact germanium silicon material with a high germanium concentration along the gap, thereby increasing nickel loss in subsequent metal lines and affecting the yield of semiconductor devices.

[0031] Therefore, in order to avoid the damage to the isolation trench caused by the preparation process of the aforementioned silicon-germanium containment structure, the present application provides a semiconductor device and a manufacturing method. Specifically, the semiconductor manufacturing method provided by the present application can form a protective layer at the inner wall of the isolation trench, so that when the substrate is etched, the protective layer maintains the complete trench structure of the isolation trench based on the fact that the etching rate of the protective layer is less than the etching rate of the substrate, so as to retain the basic structure of the isolation trench so that it will not be destroyed with the etching of the substrate. Therefore, based on the protection of the aforementioned protective layer, the silicon-germanium containment structure formed in the source and drain region of the semiconductor unit will not damage the isolation trench adjacent to it, so that the isolation trench and the silicon-germanium containment structure have a complete structure, ensuring the performance of the semiconductor unit. In addition, considering that the silicon-germanium containment structure will not damage the isolation trench adjacent to it, when preparing the silicon-germanium containment structure, the distance between the silicon-germanium containment structure and the isolation trench can be reduced, thereby improving the integration of the semiconductor device.

[0032] The semiconductor device and manufacturing method provided by the present application will be described in detail below with reference to the accompanying drawings.

[0033] Exemplary semiconductor devices: In order to prevent the aforementioned preparation process of the silicon germanium containment structure from damaging the isolation trench, a protective layer can be formed at the isolation trench before the silicon germanium containment structure is formed. After the silicon germanium containment structure is formed, the protective layer will maintain the integrity of the isolation trench structure, so that the silicon germanium containment structure and the isolation trench of the semiconductor device formed thereby both have a complete structure.

[0034] To further illustrate the semiconductor device formed thereby, the present application Figure 2 A semiconductor device based on a protective layer is also provided.

[0035] like Figure 2 As shown, the semiconductor device 100 may include a plurality of semiconductor units 110 , and each semiconductor unit 110 is separated by an isolation trench 120 .

[0036] Taking complementary metal oxide semiconductor (CMOS) as an example, the aforementioned semiconductor device 100 may include a complementary P-type semiconductor unit 111 (i.e., PMOS) and an N-type semiconductor unit 112 (i.e., NMOS). A silicon germanium containing structure 130 containing silicon germanium material may be formed in the P-type semiconductor unit 111. Specifically, the silicon germanium containing structure 130 may include a source silicon germanium containing structure 131 formed in the source region of the P-type semiconductor unit 111 and a drain silicon germanium containing structure 132 formed in the drain region of the P-type semiconductor unit 111. Among them, the source 141 of the silicon germanium containing structure 130 may be formed on the source silicon germanium containing structure 131, and the drain 142 may be formed on the drain silicon germanium containing structure 132.

[0037] Considering that the aforementioned source silicon germanium containing structure 131 and the drain silicon germanium containing structure 132 are both adjacent to the isolation trench 120, the semiconductor device 100 may further include a protective layer 121 formed along the inner wall of the isolation trench 120. Based on the protective effect of the protective layer 121, the protective layer 121 can maintain the complete trench structure of the isolation trench 120 when the substrate is etched (especially when the silicon germanium containing structure 130 is formed).

[0038] Taking into account that the silicon germanium containment structure 130 often appears as a groove with an internal size larger than the opening size, taking into account the protection of the isolation trench 120 structure by the aforementioned protective layer 121 and in order to improve the integration of the semiconductor device 100, for the target silicon germanium containment structure close to the target isolation trench, the orthographic projection range of the target silicon germanium containment structure along the stacking direction of the semiconductor device at least partially overlaps with the orthographic projection range of the target isolation trench along the stacking direction of the semiconductor device 100.

[0039] The target isolation trench and the target silicon germanium containing structure can refer to the isolation trench and silicon germanium containing structure that are adjacent to each other. That is, when the two are adjacent, they can be regarded as the target isolation trench and the target silicon germanium containing structure. For example, the aforementioned source silicon germanium containing structure 131 and the isolation trench 120 adjacent to it can be regarded as the target silicon germanium containing structure and the target isolation trench. For another example, the aforementioned drain silicon germanium containing structure 132 and the isolation trench 120 adjacent to it can be regarded as the target silicon germanium containing structure and the target isolation trench. Then the aforementioned target silicon germanium containing structure close to the target isolation trench can be understood as the target silicon germanium containing structure close to the target isolation trench in the silicon germanium containing structure, wherein the target isolation trench is any isolation trench. Specifically, considering that P-type semiconductor units often need to be implanted with silicon germanium, the aforementioned target silicon germanium containing structure can be the silicon germanium containing structure close to the isolation trench in the source silicon germanium containing structure and the drain silicon germanium containing structure in the P-type semiconductor unit.

[0040] Taking the source SiGe containing structure 131 and its adjacent isolation trench 120 as an example, the projection range of the source SiGe containing structure 131 in the direction of the semiconductor device 100 may be S1, and the projection range of the isolation trench 120 in the direction of the semiconductor device 100 may be S2. Figure 2 As shown, there is a partial overlap between S1 and S2.

[0041] Therefore, the SiGe containing structure 130 and the isolation trench 120 may have only a small distance on the substrate surface, so as to improve the integration of the semiconductor device 100 .

[0042] Furthermore, considering that the SiGe containment structure 130 generally extends toward the inside of the substrate and the inner size of the SiGe containment structure 130 first increases and then decreases, it is presented as Figure 1 and Figure 2The sigma structure shown in FIG. The isolation trench 120 also generally extends toward the inside of the substrate and the inner size of the isolation trench 120 generally gradually decreases.

[0043] As for the aforementioned target isolation trench and target SiGe containment structure, the two can share some structures. Specifically, part of the protection layer of the target isolation trench is exposed in the target SiGe containment structure and reused as the sidewall of the target SiGe containment structure, and the internal size of the target SiGe containment structure at the part of the protection layer gradually increases.

[0044] Specifically, taking the source silicon germanium containment structure 131 and its adjacent isolation trench 120 as an example, a target protective layer can be reused between the source silicon germanium containment structure 131 and its adjacent isolation trench 120. The target protective layer can be used as a part of the isolation trench 120 in the isolation trench 120 to maintain the basic structure of the isolation trench 120, and the target protective layer can be used as a side wall of the source silicon germanium containment structure 131 close to the isolation trench 120 and with a larger internal size in the source silicon germanium containment structure 131. It should be noted that part of the substrate can be retained between the source silicon germanium containment structure 131 and its adjacent isolation trench 120. Whether to retain the substrate and the size of the substrate retained can vary according to the distance between the source silicon germanium containment structure 131 and its adjacent isolation trench 120 and the morphological requirements of the source silicon germanium containment structure 131 itself.

[0045] Considering the filling requirement of the SiGe material in the SiGe containing structure 130 , when the target protection layer is reused as the sidewall of the SiGe containing structure 130 , the target protection layer can be made of silicon-rich material to provide a silicon source when the SiGe material is filled and grown.

[0046] In addition, in order to protect the isolation trench 120 when the substrate is etched, when the substrate is etched, the etching rate of the protection layer 121 is lower than the etching rate of the substrate so that the protection layer 121 maintains the complete trench structure of the isolation trench 120 .

[0047] Taking into account the etching conditions of the substrate material and the growth requirements of the germanium-silicon material, for a substrate formed of silicon material, the material of the protective layer 121 can be germanium-silicon material.

[0048] In addition to the structures described above, the semiconductor device 100 / semiconductor unit 110 may also include other necessary structures. For example, the semiconductor device 100 may include a gate 143 formed between a source 141 and a drain 142 and a metal line 144 connecting the source and drain to a metal layer.

[0049] It should be noted that the semiconductor device 100 in the present application can be adjusted according to actual needs. For example, when the semiconductor device 100 is used as a memory, the semiconductor unit 110 can also include a floating gate. For another example, when the semiconductor device 100 is used as an image sensor, the semiconductor device 100 can also include a deep isolation trench on the substrate to separate each semiconductor unit 110. In addition, the silicon germanium containment structure 130 is generally formed on the P-type semiconductor unit 111, and a similar structure can be formed if the N-type semiconductor unit 112 has similar requirements. This application does not limit this.

[0050] Exemplary method of manufacturing a semiconductor device: To illustrate the preparation process of the aforementioned semiconductor device, the present application also provides an exemplary flow chart of the manufacturing method of the aforementioned semiconductor device ( Figure 3 ) and schematic diagrams of the structures of multiple manufacturing intermediates in the manufacturing process ( Figures 4 to 14 ).

[0051] Combine the following Figure 3~Figure 14 The method for preparing the semiconductor device provided in the present application is described in detail.

[0052] like Figure 3 As shown, the method P300 for preparing a semiconductor device may include the following steps: S310, providing a substrate.

[0053] S320 , forming a protection layer along the inner wall of the isolation trench.

[0054] S330, etching the substrate to form a silicon-germanium containing structure in the source and drain regions of the semiconductor unit.

[0055] S340, filling the silicon germanium material in the silicon germanium containing structure.

[0056] S350 , forming a source and / or a drain of the semiconductor unit in the source and drain region based on the silicon germanium containing structure.

[0057] In the aforementioned S310, the substrate may be the processing object of the aforementioned method P300, that is, the substrate may be processed by P300 to form the aforementioned Figure 2 The semiconductor structure shown.

[0058] In some embodiments, the substrate provided in the aforementioned S310 should include a plurality of semiconductor units and isolation trenches separating the semiconductor units, so as to perform subsequent steps.

[0059] In some embodiments, the substrate provided in S310 may not include a structure (such as a gate) formed on the substrate, and then it may be presented as Figure 4As an optional other embodiment, the substrate provided in S310 may also have other structures, which may be presented as Figure 5 The substrate shown.

[0060] like Figure 4 As shown, the substrate may include a plurality of semiconductor units 110 and isolation trenches 120 separating the semiconductor units. To avoid damage to the substrate surface in subsequent steps, a silicon nitride layer (PAD SIN) may be formed on the substrate surface where the isolation trenches 120 are not formed to protect the substrate. Further considering the lattice mismatch between the silicon substrate and the silicon nitride layer, a pad oxide layer (PAD OX) may be formed between the substrate surface and the silicon nitride layer. Figure 5 In the embodiment, the substrate may further include a gate 143 .

[0061] Considering that the process of forming the protective layer often involves a vapor deposition process or an oxidation process, it is preferred Figure 4 It serves as the substrate of the aforementioned P300, and a gate 143 is formed in a subsequent step.

[0062] Below Figure 4 The substrate shown is taken as an example to illustrate the subsequent steps.

[0063] In the aforementioned S320 , the protection layer 121 can be formed along the inner wall of the isolation trench 120 so that its shape matches the shape of the isolation trench 120 , and when the substrate forming the isolation trench 120 is etched, the protection layer 121 can still present a shape similar to the isolation trench 120 .

[0064] As mentioned above, the protection layer 121 may be made of germanium silicon material so that after the substrate is etched, it is retained due to its slow etching rate to maintain the complete trench structure of the isolation trench 120 .

[0065] Considering that the protective layer 121 is formed of germanium silicon material, it can be formed by a vapor deposition process or an ion implantation process during preparation. Figure 6~Figure 8 It can reflect the process of forming the protective layer 121 based on the vapor deposition process. Fig. 9 , Fig.10 The process of forming the protection layer 121 based on the ion implantation process may be reflected.

[0066] like Figure 6 As shown, a vapor deposition process can be used to deposit a germanium silicon material on the isolation trench 120 to form a protection layer 121 covering the inner wall of the isolation trench 120. At this time, due to the isolation of the aforementioned silicon nitride layer, the germanium silicon material will not be deposited on the substrate surface.

[0067] Furthermore, considering that the isolation trench 120 is often filled with an interlayer dielectric (generally silicon oxide) and silicon oxide is difficult to be directly filled on the protective layer 121. Figure 6 The semiconductor device shown can first form a buffer layer on the protective layer 121, and then form a filling layer matching the interlayer dielectric, so as to perform dielectric filling. That is, silicon material can be first deposited on the protective layer 121 to form a buffer layer, and then a filling layer can be formed based on the buffer layer.

[0068] Figure 7 Some embodiments of the present application provide Figure 6 The schematic diagram of the structure of the semiconductor device when the buffer layer is formed is shown in FIG. Figure 7 As shown, a silicon material vapor deposition process can be further performed on the protective layer 121 to form a buffer layer 122 composed of silicon material. When forming a subsequent filling layer, the buffer layer 122 composed of silicon material can be directly oxidized to form a filling layer, or an oxide vapor deposition process can be used to form the filling layer, so as to fill the interlayer dielectric based on the filling layer.

[0069] Figure 8 Can be right Figure 7 The schematic diagram of the structure when the buffer layer is oxidized to form a filling layer is shown. Figure 8 As shown, the filling layer 123 can be formed by the buffer layer 122 at the position of the buffer layer 122. Based on the oxide vapor deposition process, the filling layer 123 can be deposited on the buffer layer 122. Based on the filling layer 123, the interlayer dielectric can be filled to fill the isolation trench 120. In addition, the filling layer 123 can also be based on remove Figure 6~Figure 8 In addition to the deposition method shown, the protection layer 121 can also be formed based on an ion implantation process, that is, a germanium ion implantation process can be performed on the isolation trench 120 to form the protection layer 121 at a target depth inside the isolation trench 120 .

[0070] Fig. 9 It can be a schematic diagram of the structure of a semiconductor device having a protective layer formed based on an ion implantation process. Figure 6 The protective layer shown, Fig. 9 The illustrated protection layer 121 may be formed inside the isolation trench 120 .

[0071] The ion implantation process can generally implant ions into a target depth of the substrate. When the ion implantation process is performed based on the isolation trench, the germanium ions will also accumulate at the target depth of the isolation trench so that the distribution of the germanium ions matches the morphology of the isolation trench. After the implantation, subsequent processes (such as annealing process) can be performed to combine the germanium ions with silicon to form a germanium silicon material to serve as the aforementioned protective layer 121.

[0072] Further considering that the aforementioned ion implantation process generally implants ions inside the isolation trench, the surface thereof generally presents a silicon material. Therefore, when forming the filling layer 123, it is not necessary to form the buffer layer 122, and the filling layer 123 can be formed on the protective layer 121 by directly performing an oxidation process on the inner wall of the trench. For details, see Fig.10 .

[0073] Based on the aforementioned protection layer 121 and the filling layer 123, the interlayer dielectric can be filled and the gate 143 can be formed. Fig.11 Considering that the material of the aforementioned filling layer 123 is the same as that of the interlayer dielectric, after the interlayer dielectric is filled, the filling layer 123 is no longer shown in the drawings.

[0074] Wherein, the filling layer 123 is formed based on the aforementioned process, and an interlayer dielectric (such as SiO 2 ). Considering that the subsequent process involves processing the substrate surface, after filling the interlayer dielectric, isolation trench mechanical polishing (STI CMP) can be performed to remove the aforementioned silicon nitride layer to expose the substrate surface.

[0075] In addition, ion implantation may be performed after the aforementioned leakage out of the substrate surface to form a doped substrate.

[0076] To form Fig.11 The gate 143 shown can be formed by growing silicon oxide (such as SiO2) with a high dielectric constant on the implanted region as a gate dielectric layer. This step is usually completed by a thermal oxidation process. Then, polysilicon (Poly) and spacers are grown and etched to form the gate 143 and expose the substrate surface outside the gate 143.

[0077] In the aforementioned S330, the substrate having a protective layer (such as Fig.11 The semiconductor structure shown in FIG. 1 is etched to form a germanium silicon containing structure. In this process, the protective layer 121 maintains the complete trench structure of the isolation trench 120, considering that the etching rate of the protective layer 121 is lower than the etching rate of the substrate. Figure 8 , 10 The semiconductor device shown is etched, and a gate 143 is formed in a subsequent step.

[0078] Furthermore, considering that the germanium silicon containment structure often presents a sigma structure, during preparation, a groove can be formed first, and then the sidewall of the groove can be etched to form the germanium silicon containment structure. That is, a first etching operation can be performed on the source and drain regions to form an initial groove in the source and drain regions. A second etching operation is then performed on the interior of the initial groove to form a germanium silicon containment structure in the source and drain regions, wherein the germanium silicon containment structure extends toward the interior of the substrate and the internal size of the germanium silicon containment structure first increases and then decreases.

[0079] To further illustrate this situation, this application Fig.11 A schematic diagram of a semiconductor device having a gate is provided, Fig.12 A schematic structural diagram of a semiconductor device with an initial trench is provided. Fig.13 A schematic structural diagram of a semiconductor device having a silicon germanium containing structure is provided.

[0080] like Fig.11 , Fig.12 As shown, trench etching can be performed in the source and drain regions of the P-type semiconductor unit 111 to form Fig.12 The initial trench 133 is generally in the form of a conventional trench (its cross section is a rectangle or an inverted trapezoid). To form a sigma structure, the sidewall of the initial trench 133 may be further etched to form Fig.13 The SiGe containment structure 130 is shown as a Sigma Cavity.

[0081] like Fig.13 As shown, when the SiGe containing structure 130 is close to the isolation trench 120 , the target protection layer can serve as the sidewall of the SiGe containing structure 130 , so that the size of the SiGe containing structure 130 gradually increases within this range.

[0082] Specifically, in the actual preparation process, the first etching operation may be a dry etching process, and the second etching operation may be a wet etching process based on TMAH (tetramethylammonium hydroxide). In the wet etching process based on TMAH, TMAH has a high etching selectivity to silicon materials, so that the etching rate of the protective layer 121 is lower than the etching rate of the substrate, and the protective layer 121 is retained to maintain the complete trench structure of the isolation trench 120.

[0083] In addition, in the aforementioned Fig.11 , Fig.12 , Fig.13 In the structure, considering that the N-type semiconductor unit 112 often does not need to be etched, a photoresist (PR) may be coated on the surface of the N-type semiconductor unit 112 to protect the surface of the N-type semiconductor unit 112 .

[0084] In the aforementioned S340, a germanium-silicon material growth process may be used to sequentially form a buffer layer, a bulk layer, and a cap layer in the germanium-silicon containment structure 130. In particular, in the case where the aforementioned target protection layer is used as the sidewall of the germanium-silicon containment structure 130, considering that the target protection layer is formed of a silicon-rich material, the germanium-silicon material may be generated based on the material, so that the germanium-silicon material can still grow normally near the edge of the isolation trench 120 to fill the complete sigma structure.

[0085] In the aforementioned S350, based on the aforementioned SiGe containing structure 130 filled with SiGe material, MVGOX ETCH (polysilicon oxide etching), LDD (light doping process), and deep and shallow doping process (S&D IMP) can be further performed to form the following on the SiGe containing structure 130: Fig.14 The source 141 and the drain 142 are shown.

[0086] After the source 141 and the drain 142 are formed, the semiconductor device 100 can be formed by SMT / SAB / RMG / HIR / CT processes. Figure 2 In addition, in forming the semiconductor device Figure 2 After the semiconductor device is shown, subsequent processes may be further performed to form multiple metal layers and perform interlayer wiring.

[0087] Unexpected technical effects: In summary, the semiconductor device and manufacturing method provided by the present application have the following unexpected effects: ① Before forming the silicon germanium containment structure, the present application forms a protective layer at the isolation trench. Based on the protection of the protective layer, the silicon germanium containment structure formed in the source and drain regions of the semiconductor unit will not damage the isolation trench adjacent to it, so that the isolation trench and the silicon germanium containment structure have a complete structure, thereby ensuring the performance of the semiconductor unit.

[0088] ② Considering that the SiGe containment structure will not damage the isolation trench adjacent to it, when preparing the SiGe containment structure, the distance between the SiGe containment structure and the isolation trench can be reduced, thereby improving the integration of the semiconductor device.

[0089] ③ Based on the complete isolation trench formed above, the nickel material will not contact the germanium silicon material with a high germanium concentration along the gap in the subsequent process, thereby increasing the nickel loss of the subsequent metal line, thereby affecting the yield rate of the semiconductor device.

[0090] ④ For the target SiGe containment structure close to the target isolation trench, the orthographic projection range of the target SiGe containment structure along the semiconductor device stacking direction at least partially overlaps with the orthographic projection range of the target isolation trench along the semiconductor device stacking direction, thereby improving the device integration. In addition, part of the protective layer of the target isolation trench is exposed in the target SiGe containment structure and reused as the side wall of the target SiGe containment structure, and the internal size of the target SiGe containment structure at the part of the protective layer gradually increases.

[0091] ⑤ Considering that the protective layer can be prepared with silicon-rich material, when the aforementioned protective layer is exposed in the target germanium silicon containment structure, during the growth process of the germanium silicon material, the protective layer can serve as a seed layer of the germanium silicon material to ensure that the germanium silicon material can completely fill the germanium silicon containment structure.

[0092] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a substrate, wherein the substrate comprises a plurality of semiconductor units and isolation trenches separating the semiconductor units; forming a protective layer along the inner wall of the isolation trench; Etching the substrate to form a germanium silicon containing structure in the source and drain regions of the semiconductor unit, wherein when the substrate is etched, the etching rate of the protection layer is lower than the etching rate of the substrate so that the protection layer maintains the complete trench structure of the isolation trench; Filling the silicon germanium material in the silicon germanium containing structure; A source and / or a drain of the semiconductor unit is formed in the source-drain region based on the silicon germanium receiving structure.

2. The manufacturing method according to claim 1, characterized in that: The material of the protection layer is germanium silicon material, and the material of the substrate is silicon material.

3. The manufacturing method according to claim 2, characterized in that: The forming of a protective layer along the inner wall of the isolation trench comprises: A germanium silicon material is deposited on the isolation trench to form the protection layer covering the inner wall of the isolation trench.

4. The manufacturing method according to claim 3, characterized in that: The manufacturing method further comprises: Depositing silicon material on the protective layer to form a buffer layer; A filling layer is formed based on the buffer layer.

5. The manufacturing method according to claim 2, characterized in that: The forming of a protective layer along the inner wall of the isolation trench comprises: A germanium ion implantation process is performed on the isolation trench to form the protection layer at a target depth inside the isolation trench.

6. The manufacturing method according to claim 2, characterized in that: The manufacturing method further comprises: An oxidation process is performed on the inner wall of the trench to form a filling layer on the protection layer.

7. The manufacturing method according to claim 1, characterized in that: The etching of the substrate to form a germanium silicon containing structure in the source and drain regions of the semiconductor unit includes: Performing a first etching operation on the source-drain region to form an initial trench in the source-drain region; A second etching operation is performed on the interior of the initial trench to form the silicon-germanium containment structure in the source and drain region, wherein the silicon-germanium containment structure extends toward the interior of the substrate and the internal size of the silicon-germanium containment structure first increases and then decreases.

8. A semiconductor device, characterized in that: The semiconductor device includes a plurality of semiconductor units disposed in a substrate and isolation trenches separating the semiconductor units, wherein the isolation trenches are used to separate adjacent semiconductor units; The source-drain region of the semiconductor unit includes a silicon-germanium containing structure and a source and / or a drain formed on the silicon-germanium containing structure; The isolation trench comprises a protection layer formed along an inner wall of the isolation trench, wherein the protection layer is used to maintain a complete trench structure of the isolation trench when the substrate is etched.

9. The semiconductor device according to claim 8, characterized in that For a target SiGe accommodation structure close to a target isolation trench, an orthographic projection range of the target SiGe accommodation structure along the semiconductor device stacking direction at least partially overlaps with an orthographic projection range of the target isolation trench along the semiconductor device stacking direction.

10. The semiconductor device according to claim 9, characterized in that The germanium-silicon containing structure extends toward the inside of the substrate, and the inner size of the germanium-silicon containing structure first increases and then decreases, and the isolation trench extends toward the inside of the substrate, and the inner size of the isolation trench gradually decreases; Part of the protection layer of the target isolation trench is exposed in the target SiGe containing structure and reused as the sidewall of the target SiGe containing structure. The internal size of the target SiGe containing structure at the part of the protection layer gradually increases.

Images