A semiconductor device and a manufacturing method thereof

Abstract

The present application provides a semiconductor device and a manufacturing method thereof, relating to the field of semiconductor technology. The semiconductor manufacturing method provided by the present application can form a protective layer on the inner wall of the isolation trench, so that when the substrate is etched, based on the etching rate of the protective layer being less than that of the substrate, the protective layer maintains the complete trench structure of the isolation trench, so as to retain the basic structure of the isolation trench and prevent it from being damaged along with the etching of the substrate. Thus, based on the protection of the aforementioned protective layer, the germanium-silicon accommodating structure formed in the source-drain region of the semiconductor cell will not damage the adjacent isolation trench, enabling both the isolation trench and the germanium-silicon accommodating structure to have a complete structure, and ensuring the performance of the semiconductor cell. In addition, considering that the germanium-silicon accommodating structure will not damage the adjacent isolation trench, when preparing the germanium-silicon accommodating structure, the distance between the germanium-silicon accommodating structure and the isolation trench can be reduced, thereby improving the integration degree of the semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In semiconductor devices (especially P-type semiconductor devices), source regions and drain regions can adopt an embedded SiGe process to form SiGe accommodating structures and fill them with SiGe materials, so as to utilize the compressive stress generated by the different lattice constants of germanium and silicon to improve the hole mobility and saturation current of P-type semiconductor devices.

[0003] However, due to the special morphology of the SiGe accommodating structure, it is easy to affect other structures (such as isolation trenches) of the semiconductor device during its formation. Therefore, how to ensure the device integrity of the semiconductor device when forming the SiGe accommodating structure is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor device and a manufacturing method thereof. Before performing the embedded SiGe process, a protective layer is formed at the isolation trenches to prevent the isolation trenches from being damaged during the execution of the embedded SiGe process, thereby ensuring the integrity of the semiconductor device.

[0005] In a first aspect, this application provides a manufacturing method of a semiconductor device. The manufacturing method includes: providing a substrate, where the substrate includes a plurality of semiconductor units and isolation trenches separating the semiconductor units; forming a protective layer along the inner wall of the isolation trenches; etching the substrate to form SiGe accommodating structures in the source and drain regions of the semiconductor units. When the substrate is etched, the etching rate of the protective layer is less than that of the substrate, so that the protective layer maintains the complete trench structure of the isolation trenches; filling the SiGe accommodating structures with SiGe materials; and forming the source and / or drain of the semiconductor units in the source and drain regions based on the SiGe accommodating structures.

[0006] In a second aspect, this application provides a semiconductor device. The semiconductor device includes a plurality of semiconductor units provided in a substrate and isolation trenches separating the semiconductor units. The isolation trenches are used to separate adjacent semiconductor units; the source and drain regions of the semiconductor units include SiGe accommodating structures and a source and / or a drain formed on the SiGe accommodating structures; the isolation trenches include a protective layer formed along the inner wall of the isolation trenches, where the protective layer is used to maintain the complete trench structure of the isolation trenches when the substrate is etched.

[0007] Based on the semiconductor manufacturing method provided by this application, a protective layer can be formed on the inner wall of the isolation trench. Thus, when the substrate is etched, the protective layer maintains the complete trench structure of the isolation trench because the etching rate of the protective layer is less than that of the substrate, so as to retain the basic structure of the isolation trench and prevent it from being damaged along with the etching of the substrate. Therefore, due to the protection of the aforementioned protective layer, the germanium-silicon accommodating structure formed in the source-drain region of the semiconductor cell will not damage the adjacent isolation trench, enabling both the isolation trench and the germanium-silicon accommodating structure to have a complete structure and ensuring the performance of the semiconductor cell. In addition, considering that the germanium-silicon accommodating structure will not damage the adjacent isolation trench, the distance between the germanium-silicon accommodating structure and the isolation trench can be reduced during the preparation of the germanium-silicon accommodating structure, thereby improving the integration degree of the semiconductor device. Description of the Drawings

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0009] Figure 1 It is a schematic diagram showing the influence of the reaction-embedded germanium-silicon process on the isolation trench provided by some embodiments of this application.

[0010] Figure 2 It is a schematic diagram of the structure of a semiconductor device provided by some embodiments of this application.

[0011] Figure 3 It is an exemplary flowchart of the manufacturing method of a semiconductor device provided by some embodiments of this application.

[0012] Figure 4 It is a schematic diagram of the structure of a substrate provided by some embodiments of this application.

[0013] Figure 5 It is a schematic diagram of the structure of another substrate provided by some embodiments of this application.

[0014] Figure 6 It is a schematic diagram of the structure of a semiconductor device with a protective layer provided by some embodiments of this application.

[0015] Figure 7 It is provided by some embodiments of this application Figure 6 A schematic diagram of the structure of the semiconductor device shown when forming a buffer layer.

[0016] Figure 8 It is provided by some embodiments of this application Figure 6 A schematic diagram of the structure of the semiconductor device shown when forming a filling layer.

[0017] Figure 9 It is a schematic structural diagram of another semiconductor device with a protective layer provided by some embodiments of the present application.

[0018] Figure 10 It is provided by some embodiments of the present application Figure 9 Schematic structural diagram when forming a filling layer of the semiconductor device shown.

[0019] Figure 11 It is a schematic structural diagram of a semiconductor device with a gate provided by some embodiments of the present application.

[0020] Figure 12 It is a schematic structural diagram of a semiconductor device with an initial trench provided by some embodiments of the present application.

[0021] Figure 13 It is a schematic structural diagram of a semiconductor device with a germanium-silicon accommodating structure provided by some embodiments of the present application.

[0022] Figure 14 It is a schematic structural diagram of a semiconductor device after forming source and drain electrodes provided by some embodiments of the present application.

[0023] Among them, 100 is a semiconductor device; 120 is an isolation trench; 130 is a germanium-silicon accommodating structure; 110 is a semiconductor cell; 111 is a P-type semiconductor cell; 112 is an N-type semiconductor cell; 131 is a source germanium-silicon accommodating structure; 132 is a drain germanium-silicon accommodating structure; 141 is a source electrode; 142 is a drain electrode; 121 is a protective layer; 143 is a gate; 144 is a metal wire; 122 is a buffer layer; 123 is a filling layer; 133 is an initial trench. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The forms, numbers, and proportions of the components in actual implementation can be arbitrarily changed, and the layout form of the components may also be more complex.

[0026] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be construed as indicating or implying relative importance.

[0027] Application Overview:

[0028] As mentioned above, when the embedded germanium-silicon process is executed, the germanium-silicon accommodation structure formed often presents a sigma structure that first becomes larger and then smaller towards the inside of the substrate. When preparing this sigma structure, a groove is often opened first, and then the side walls of the groove are etched laterally to form a sigma-structured germanium-silicon accommodation structure. In this process, considering that the internal size of the germanium-silicon accommodation structure is often larger than its opening size, even if the isolation trench is avoided during grooving, the germanium-silicon accommodation structure can extend to the isolation trench during the lateral etching of the side walls. When the germanium-silicon accommodation structure contacts the isolation trench, part of the side walls of the germanium-silicon accommodation structure and the isolation trench will fall off due to etching, destroying the integrity of the contact between the germanium-silicon accommodation structure and the isolation trench.

[0029] To further illustrate the damage of the aforementioned germanium-silicon accommodation structure to the isolation trench, the present application Figure 1 provides a schematic diagram that can reflect the influence of the embedded germanium-silicon process on the isolation trench. Among them, Figure 1 it can be a scanning electron microscope image of a semiconductor device slice after the embedded germanium-silicon process is executed to form the germanium-silicon accommodation structure.

[0030] As Figure 1 shown, the semiconductor device 100 has an isolation trench 120 and a plurality of germanium-silicon accommodation structures 130. For the germanium-silicon accommodation structures 130 close to the isolation trench 120, the germanium-silicon accommodation structures 130 communicate with the isolation trench 120, resulting in the side walls separating the isolation trench 120 and the germanium-silicon accommodation structures 130 being etched away, destroying the complete structure of the germanium-silicon accommodation structures 130 and the isolation trench 120. When filling germanium-silicon materials (also called SiGe bulk layer) subsequently, due to the damage of the aforementioned side walls, the germanium-silicon materials cannot fill the complete germanium-silicon accommodation structures 130, affecting the stress generated.

[0031] In addition, based on the aforementioned incomplete structure, in the subsequent silicide formation process, nickel material (Ni) may contact the germanium-silicon material with a high germanium concentration along the gap, thereby increasing the nickel loss of the subsequent metal wires, and thus affecting the yield rate of the semiconductor device.

[0032] Therefore, to avoid the damage to the isolation trench caused by the preparation process of the foregoing germanium-silicon containing structure, the present application provides a semiconductor device and a manufacturing method. Specifically, the semiconductor manufacturing method provided by the present application can form a protective layer on the inner wall of the isolation trench, so that when the substrate is etched, the protective layer maintains the complete trench structure of the isolation trench based on the etching rate of the protective layer being less than that of the substrate, so as to retain the basic structure of the isolation trench and prevent it from being damaged along with the etching of the substrate. Thus, based on the protection of the foregoing protective layer, the germanium-silicon containing structure formed in the source-drain region of the semiconductor cell will not damage the adjacent isolation trench, enabling both the isolation trench and the germanium-silicon containing structure to have a complete structure and ensuring the performance of the semiconductor cell. In addition, considering that the germanium-silicon containing structure will not damage the adjacent isolation trench, when preparing the germanium-silicon containing structure, the distance between the germanium-silicon containing structure and the isolation trench can be reduced, thereby improving the integration degree of the semiconductor device.

[0033] The semiconductor device and manufacturing method provided by the present application will be described in detail below with reference to the accompanying drawings.

[0034] Exemplary semiconductor device:

[0035] As described above, to avoid the damage to the isolation trench caused by the preparation process of the foregoing germanium-silicon containing structure, a protective layer can be formed at the isolation trench before forming the germanium-silicon containing structure. After forming the germanium-silicon containing structure, the protective layer will maintain the integrity of the isolation trench structure, and thus the germanium-silicon containing structure and the isolation trench of the formed semiconductor device both have a complete structure.

[0036] To further illustrate the semiconductor device formed thereby, the present application Figure 2 also provides a semiconductor device based on the protective layer.

[0037] As Figure 2 shown, the semiconductor device 100 may include a plurality of semiconductor cells 110, and each semiconductor cell 110 is separated by an isolation trench 120.

[0038] Taking complementary metal oxide semiconductor (CMOS) as an example, the foregoing semiconductor device 100 may include complementary P-type semiconductor cells 111 (i.e., PMOS) and N-type semiconductor cells 112 (i.e., NMOS). A germanium-silicon containing structure 130 for accommodating germanium-silicon materials can be formed in the P-type semiconductor cell 111. Specifically, the germanium-silicon containing structure 130 may include a source germanium-silicon containing structure 131 formed in the source region of the P-type semiconductor cell 111 and a drain germanium-silicon containing structure 132 formed in the drain region of the P-type semiconductor cell 111. Among them, the source 141 of the germanium-silicon containing structure 130 can be formed on the source germanium-silicon containing structure 131, and the drain 142 can be formed on the drain germanium-silicon containing structure 132.

[0039] Considering that both the aforementioned source germanium-silicon accommodating structure 131 and the drain germanium-silicon accommodating structure 132 are adjacent to the isolation trench 120, the semiconductor device 100 may further include a protective layer 121 formed along the inner wall of the trench of the isolation trench 120. Based on the protective effect of the protective layer 121, the protective layer 121 can maintain the complete trench structure of the isolation trench 120 when the substrate is etched (especially when forming the germanium-silicon accommodating structure 130).

[0040] Considering that the germanium-silicon accommodating structure 130 often presents as a groove with an internal size larger than the opening size, and considering the protection of the structure of the isolation trench 120 by the aforementioned protective layer 121 and to improve the integration of the semiconductor device 100, for the target germanium-silicon accommodating structure close to the target isolation trench, at least part of the positive projection range of the target germanium-silicon accommodating structure along the stacking direction of the semiconductor device coincides with the positive projection range of the target isolation trench along the stacking direction of the semiconductor device 100.

[0041] The target isolation trench and the target germanium-silicon accommodating structure can refer to the isolation trench and the germanium-silicon accommodating structure that are adjacent to each other. That is, when the two are adjacent, they can be regarded as the target isolation trench and the target germanium-silicon accommodating structure. For example, the aforementioned source germanium-silicon accommodating structure 131 and its adjacent isolation trench 120 can be regarded as the target germanium-silicon accommodating structure and the target isolation trench. For another example, the aforementioned drain germanium-silicon accommodating structure 132 and its adjacent isolation trench 120 can be regarded as the target germanium-silicon accommodating structure and the target isolation trench. Then the aforementioned target germanium-silicon accommodating structure close to the target isolation trench can be understood as the target germanium-silicon accommodating structure in the germanium-silicon accommodating structure that is close to the target isolation trench, where the target isolation trench is any isolation trench. Specifically, considering that P-type semiconductor units often need to inject germanium-silicon, the aforementioned target germanium-silicon accommodating structure can be the germanium-silicon accommodating structure in the source germanium-silicon accommodating structure and the drain germanium-silicon accommodating structure in the P-type semiconductor unit that is close to the isolation trench.

[0042] Taking the source germanium-silicon accommodating structure 131 and its adjacent isolation trench 120 as an example, the projection range of the source germanium-silicon accommodating structure 131 in the direction of the semiconductor device 100 can be S1, and the projection range of the isolation trench 120 in the direction of the semiconductor device 100 can be S2. As Figure 2 shown, there is a partial area overlap between S1 and S2.

[0043] Thus, the germanium-silicon accommodating structure 130 and the isolation trench 120 can have only a small spacing on the substrate surface to improve the integration of the semiconductor device 100.

[0044] Furthermore, considering that the germanium-silicon accommodating structure 130 generally extends towards the inside of the substrate and the internal size of the germanium-silicon accommodating structure 130 first increases and then decreases, and presents as Figure 1 andFigure 2 The sigma structure shown in . The isolation trench 120 generally extends inwardly towards the substrate, and the internal dimension of the isolation trench 120 generally gradually decreases.

[0045] For the aforementioned target isolation trench and the target germanium-silicon accommodating structure, the two can share some structures. Specifically, a part of the protective layer of the target isolation trench is exposed within the target germanium-silicon accommodating structure and reused as the sidewall of the target germanium-silicon accommodating structure. The internal dimension of the target germanium-silicon accommodating structure gradually increases at the part of the protective layer.

[0046] Specifically, taking the source germanium-silicon accommodating structure 131 and its adjacent isolation trench 120 as an example, a target protective layer can be reused between the source germanium-silicon accommodating structure 131 and its adjacent isolation trench 120. The target protective layer can be used as a part of the isolation trench 120 within the isolation trench 120 to maintain the basic structure of the isolation trench 120, and the target protective layer can be used as the sidewall of the part where the internal dimension of the source germanium-silicon accommodating structure 131 near the isolation trench 120 increases within the source germanium-silicon accommodating structure 131. It should be noted that between the source germanium-silicon accommodating structure 131 and its adjacent isolation trench 120, a part of the substrate can be retained. Whether to retain the substrate and the size of the retained substrate can vary according to the distance between the source germanium-silicon accommodating structure 131 and its adjacent isolation trench 120 and the morphological requirements of the source germanium-silicon accommodating structure 131 itself.

[0047] Considering the filling requirement of the germanium-silicon material within the germanium-silicon accommodating structure 130, when the target protective layer is reused as the sidewall of the germanium-silicon accommodating structure 130, the target protective layer can be made of a silicon-rich material to provide a silicon source during the filling growth of the germanium-silicon material.

[0048] In addition, to protect the isolation trench 120 when the substrate is etched, during the etching of the substrate, the etching rate of the protective layer 121 is less than that of the substrate, so that the protective layer 121 maintains the complete trench structure of the isolation trench 120.

[0049] Taking into comprehensive consideration the etching situation of the material of the aforementioned substrate and the growth requirement of the aforementioned germanium-silicon material. For a substrate formed of a silicon material, the material of the aforementioned protective layer 121 can be selected as a germanium-silicon material.

[0050] In addition to the structures described above, the semiconductor device 100 / semiconductor unit 110 may also include other necessary structures. For example, the semiconductor device 100 may include a gate 143 formed between the source 141 and the drain 142 and a metal wire 144 connecting the source-drain to a metal layer.

[0051] It should be noted that the semiconductor device 100 in this application can be adjusted according to actual needs. For example, when the semiconductor device 100 is used as a memory, the semiconductor cell 110 may further include a floating gate. As another example, when the semiconductor device 100 is used as an image sensor, the semiconductor device 100 may further include deep isolation trenches for separating the semiconductor cells 110 on the substrate. In addition, the germanium-silicon accommodating structure 130 is generally formed on the P-type semiconductor cell 111, and a similar structure can also be formed on the N-type semiconductor cell 112 if there is a similar need. This application does not limit this.

[0052] Exemplary manufacturing method of a semiconductor device:

[0053] To illustrate the preparation process of the foregoing semiconductor device, this application also provides an exemplary flowchart of the manufacturing method of the foregoing semiconductor device ( Figure 3 ), and a schematic structural diagram of multiple manufacturing intermediates during the manufacturing process ( Figures 4 to 14 ).

[0054] The following will be combined with Figures 3 to 14 to describe in detail the manufacturing method of the semiconductor device provided in this application.

[0055] As Figure 3 shown, the manufacturing method P300 of the semiconductor device may include the following steps:

[0056] S310: Provide a substrate.

[0057] S320: Form a protective layer along the inner wall of the isolation trench.

[0058] S330: Etch the substrate to form a germanium-silicon accommodating structure in the source and drain regions of the semiconductor cell.

[0059] S340: Fill germanium-silicon material in the germanium-silicon accommodating structure.

[0060] S350: Form the source and / or drain of the semiconductor cell in the source and drain regions based on the germanium-silicon accommodating structure.

[0061] In the foregoing S310, the substrate can be the processing object of the foregoing method P300, that is, the substrate is processed by P300 to form the semiconductor structure as shown in the foregoing Figure 2 .

[0062] In some embodiments, the substrate provided in the foregoing S310 should include multiple semiconductor cells and isolation trenches for separating the semiconductor cells, so as to perform subsequent steps.

[0063] In some embodiments, the substrate provided in S310 may not include structures (such as gates) formed on the substrate. In this case, it may be presented as Figure 4The substrate shown. As an alternative other embodiment, the substrate provided in S310 may also have other structures, and may be presented as Figure 5 The substrate shown.

[0064] As Figure 4 shown, the substrate may include a plurality of semiconductor units 110 and isolation trenches 120 separating the semiconductor units. To avoid damage to the substrate surface in subsequent steps, a silicon nitride layer (PAD SIN) may be formed in the area where the isolation trenches 120 are not formed on the substrate surface to protect the substrate. Further considering the lattice mismatch between the silicon substrate and the silicon nitride layer, a pad oxide layer (PAD OX) may be formed between the substrate surface and the silicon nitride layer. And in Figure 5 it, the aforementioned substrate may further include a gate 143.

[0065] Considering that the process of forming the protective layer often involves a chemical vapor deposition process or an oxidation process, it may be preferred Figure 4 as the substrate for the aforementioned P300, and the gate 143 is formed in subsequent steps.

[0066] Next, taking the Figure 4 substrate shown as an example, the subsequent steps will be described.

[0067] In the aforementioned S320, the protective layer 121 may be formed along the inner wall of the isolation trench 120 so that its shape matches the shape of the isolation trench 120, and when the substrate on which the isolation trench 120 is formed is etched, the protective layer 121 can still present a shape similar to the isolation trench 120.

[0068] Continuing from the above, the aforementioned protective layer 121 may be made of a silicon-germanium material so that after the substrate is etched, it is retained due to its slower etching rate to maintain the complete trench structure of the isolation trench 120.

[0069] Considering that the protective layer 121 is made of a silicon-germanium material, during preparation, it can be formed by a chemical vapor deposition process or an ion implantation process. Among them, Figures 6 to 8 can reflect the process of forming the protective layer 121 based on the chemical vapor deposition process. And Figure 9 , Figure 10 can reflect the process of forming the protective layer 121 based on the ion implantation process.

[0070] As Figure 6 shown, a chemical vapor deposition process can be used to deposit a silicon-germanium material on the isolation trench 120 to form a protective layer 121 covering the inner wall of the isolation trench 120. At this time, due to the isolation of the aforementioned silicon nitride layer, the silicon-germanium material will not be deposited on the substrate surface.

[0071] Further, considering that the isolation trench 120 is often filled with an interlayer dielectric (generally silicon oxide) and it is difficult to directly fill silicon oxide on the protective layer 121. Then for Figure 6 the semiconductor device shown, a buffer layer can be formed on the protective layer 121 first, and then a filling layer matching the interlayer dielectric can be formed, so as to perform dielectric filling. That is, a silicon material can be deposited on the protective layer 121 first to form a buffer layer. Then a filling layer is formed based on the buffer layer.

[0072] Figure 7 This is provided by some embodiments of the present application Figure 6 a schematic structural diagram of the semiconductor device shown when forming a buffer layer. As Figure 7 shown, a silicon material chemical vapor deposition process can be further performed on the protective layer 121 to form a buffer layer 122 composed of silicon material. For the buffer layer 122 composed of silicon material, when forming the subsequent filling layer, it can be directly oxidized to form the filling layer, or an oxide chemical vapor deposition process can be used to form the filling layer, so as to fill the interlayer dielectric based on the filling layer.

[0073] Figure 8 It can be Figure 7 a schematic structural diagram of the buffer layer shown when forming a filling layer by oxidation treatment. As Figure 8 shown, the filling layer 123 can be formed from the buffer layer 122 at the position of the foregoing buffer layer 122. Among them, based on the oxide chemical vapor deposition process, the foregoing filling layer 123 can be deposited on the foregoing buffer layer 122. Based on the filling layer 123, the interlayer dielectric can be filled to fill the isolation trench 120. In addition, the foregoing filling layer 123 can also be based on

[0074] In addition to Figures 6 to 8 the deposition method shown, the protective layer 121 can also be formed based on an ion implantation process. That is, a germanium ion implantation process can be performed on the isolation trench 120 to form a protective layer 121 at a target depth inside the isolation trench 120.

[0075] Figure 9 It can be a schematic structural diagram of a semiconductor device having a protective layer formed based on an ion implantation process. Different from Figure 6 the protective layer shown, Figure 9 the protective layer 121 shown can be formed inside the isolation trench 120.

[0076] The ion implantation process generally can implant ions to a target depth of the substrate. When performing an ion implantation process based on the isolation trench, germanium ions will also accumulate at the target depth of the isolation trench, so that the distribution of germanium ions matches the morphology of the isolation trench. After implantation, subsequent processes (such as an annealing process) can be performed to combine germanium ions with silicon to form a germanium-silicon material as the foregoing protective layer 121.

[0077] Further considering that ions are generally implanted inside the isolation trench in the aforementioned ion implantation process, its surface generally presents as silicon material. Then, when forming the filling layer 123, there is no need to form the buffer layer 122 anymore. By directly performing an oxidation process on the inner wall of the trench, the filling layer 123 can be formed on the protective layer 121. Specifically, reference can be made to Figure 10 .

[0078] Based on the aforementioned protective layer 121 and its filling layer 123, the interlayer dielectric can be filled and the gate 143 can be formed. Specifically, reference can be made to Figure 11 the structure shown. Among them, considering that the material of the aforementioned filling layer 123 is the same as that of the interlayer dielectric, after filling the interlayer dielectric, the filling layer 123 is no longer shown in the drawings.

[0079] Among them, based on the aforementioned process of forming the filling layer 123, the high aspect ratio process (HARP) can be used to deposit the interlayer dielectric (such as SiO2) in the isolation trench 120. Considering that the subsequent process involves the treatment of the substrate surface, after filling the interlayer dielectric, the isolation trench chemical mechanical polishing (STI CMP) can be performed to remove the aforementioned silicon nitride layer to expose the substrate surface.

[0080] In addition, ion implantation can be performed after the aforementioned substrate surface is exposed to form a doped substrate.

[0081] To form Figure 11 the gate 143 shown, a high-k dielectric silicon oxide (such as SiO2) can be grown on the implantation region as the gate dielectric layer. This step is usually completed by a thermal oxidation process. Then, the growth and etching of polysilicon (Poly) and spacer are carried out to form the gate 143 and expose the substrate surface outside the gate 143.

[0082] In the aforementioned S330, the substrate with the protective layer (such as Figure 11 the semiconductor structure shown) can be etched to form a germanium silicon accommodating structure. During this process, considering that the etching rate of the protective layer 121 is less than that of the substrate, the protective layer 121 maintains the complete trench structure of the isolation trench 120. In addition, Figure 8 , 10 the semiconductor device shown can also be etched, and the gate 143 is formed in the subsequent steps.

[0083] Further, considering that the germanium-silicon accommodating structure often presents a sigma structure, during fabrication, a groove can be formed first, and then the sidewalls of the groove can be etched to form the germanium-silicon accommodating structure. That is, a first etching operation can be performed on the source / drain region to form an initial trench in the source / drain region. Then, a second etching operation can be performed on the interior of the initial trench to form the germanium-silicon accommodating structure in the source / drain region, where the germanium-silicon accommodating structure extends towards the interior of the substrate and the internal dimension of the germanium-silicon accommodating structure first increases and then decreases.

[0084] To further illustrate this situation, this application Figure 11 provides a schematic structural diagram of a semiconductor device with a gate. Figure 12 provides a schematic structural diagram of a semiconductor device with an initial trench. Figure 13 provides a schematic structural diagram of a semiconductor device with a germanium-silicon accommodating structure.

[0085] As Figure 11 、 Figure 12 shown, trench etching can be performed in the source / drain region of the P-type semiconductor cell 111 to form Figure 12 the initial trench 133 shown. Among them, the initial trench 133 generally takes the form of a traditional trench (its cross-section is rectangular or inverted trapezoidal). To form the sigma structure, the sidewalls of the initial trench 133 can be further etched to form Figure 13 the germanium-silicon accommodating structure 130 shown presenting a sigma structure (Sigma Cavity).

[0086] As Figure 13 shown, when the germanium-silicon accommodating structure 130 is adjacent to the isolation trench 120, the target protective layer can serve as the sidewall of the germanium-silicon accommodating structure 130, so that the size of the germanium-silicon accommodating structure 130 gradually increases within this range.

[0087] Specifically, during the actual fabrication process, the aforementioned first etching operation can be a dry etching process, and the second etching operation can be a wet etching process based on TMAH (tetramethylammonium hydroxide). In the wet etching process based on TMAH, TMAH has a high etching selectivity for silicon materials, so that the etching rate of the protective layer 121 is less than the etching rate of the substrate, and the protective layer 121 is retained to maintain the complete trench structure of the isolation trench 120.

[0088] In addition, in the aforementioned Figure 11 、 Figure 12 、 Figure 13 structure, considering that the N-type semiconductor cell 112 often does not need to be etched, a photoresist (PR) can be coated on the surface of the N-type semiconductor cell 112 to protect the surface of the N-type semiconductor cell 112.

[0089] In the foregoing S340, a germanium-silicon material growth process can be adopted to sequentially form a buffer layer, a bulk layer, and a cap layer in the germanium-silicon accommodating structure 130. Among them, for the case where the foregoing target protective layer serves as the sidewall of the germanium-silicon accommodating structure 130, considering that the target protective layer is formed of a silicon-rich material, the germanium-silicon material can be generated based on this material, so that near the edge of the isolation trench 120, the germanium-silicon material can still grow normally to fill the complete sigma structure.

[0090] In the foregoing S350, based on the germanium-silicon accommodating structure 130 filled with the germanium-silicon material, MVGOX ETCH (polysilicon oxide etching), LDD (lightly doped process), and shallow and deep doping processes (S&D IMP) can be further performed to form a source electrode 141 and a drain electrode 142 as shown in Figure 14 the figure on the germanium-silicon accommodating structure 130.

[0091] For the semiconductor device 100 after forming the source electrode 141 and the drain electrode 142, processes such as SMT / SAB / RMG / HIR / CT can be performed to form Figure 2 the semiconductor device as shown in the figure. In addition, after forming Figure 2 the semiconductor device as shown in the figure, subsequent processes can be further performed to form a multi-layer metal layer and perform interlayer wiring.

[0092] Unexpected technical effects:

[0093] In summary, the semiconductor device and manufacturing method provided in this application have formed the following unexpected effects:

[0094] ① Before forming the germanium-silicon accommodating structure in this application, a protective layer is formed at the isolation trench. Based on the protection of the protective layer, the germanium-silicon accommodating structure formed in the source-drain region of the semiconductor cell will not damage the adjacent isolation trench, so that both the isolation trench and the germanium-silicon accommodating structure have a complete structure, ensuring the performance of the semiconductor cell.

[0095] ② Considering that the germanium-silicon accommodating structure will not damage the adjacent isolation trench, when preparing the germanium-silicon accommodating structure, the distance between the germanium-silicon accommodating structure and the isolation trench can be reduced, thereby improving the integration of the semiconductor device.

[0096] ③ Based on the foregoing formed complete isolation trench, in the subsequent process, the nickel material will not contact the germanium-silicon material with a high germanium concentration along the gap, thereby increasing the nickel loss of the subsequent metal wire and affecting the yield of the semiconductor device.

[0097] ④For the target germanium-silicon containing structure close to the target isolation trench, the positive projection range of the target germanium-silicon containing structure along the semiconductor device stacking direction and the positive projection range of the target isolation trench along the semiconductor device stacking direction at least partially overlap, thereby improving the device integration. In addition, a part of the protective layer of the target isolation trench is exposed inside the target germanium-silicon containing structure and reused as the side wall of the target germanium-silicon containing structure, and the internal dimension of the target germanium-silicon containing structure gradually increases at the part of the protective layer.

[0098] ⑤Considering that the protective layer can be prepared from a silicon-rich material, when the aforementioned protective layer is exposed inside the target germanium-silicon containing structure, during the growth process of the germanium-silicon material, the protective layer can serve as a seed layer for the germanium-silicon material to ensure that the germanium-silicon material can completely fill the germanium-silicon containing structure.

[0099] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: Providing a substrate, wherein the substrate includes a plurality of semiconductor units and isolation trenches separating the semiconductor units, the material of the substrate is silicon material, the isolation trenches extend towards the interior of the substrate and the internal dimensions of the isolation trenches gradually decrease; Forming a protective layer along the inner wall of the isolation trenches, wherein the material of the protective layer is germanium silicon material; etching the substrate to form germanium silicon accommodating structures in the source-drain regions of the semiconductor units, wherein when the substrate is etched, the etching rate of the protective layer is less than that of the substrate so that the protective layer maintains the complete trench structure of the isolation trenches, the germanium silicon accommodating structures extend towards the interior of the substrate and the internal dimensions of the germanium silicon accommodating structures first increase and then decrease; for the target germanium silicon accommodating structure close to the target isolation trench, a part of the protective layer of the target isolation trench is exposed in the target germanium silicon accommodating structure and is reused as the side wall of the target germanium silicon accommodating structure, and the internal dimension of the target germanium silicon accommodating structure gradually increases at the part of the protective layer; Filling germanium silicon material in the germanium silicon accommodating structures by using a germanium silicon material growth process, wherein the protective layer is configured as a seed layer in the germanium silicon accommodating structures to ensure that the germanium silicon material can completely fill the germanium silicon accommodating structures; Forming the source and / or drain of the semiconductor unit in the source-drain region based on the germanium silicon accommodating structures.

2. The manufacturing method according to claim 1, wherein, The forming a protective layer along the inner wall of the isolation trenches includes: Depositing germanium silicon material on the isolation trenches to form the protective layer covering the inner wall of the isolation trenches.

3. The manufacturing method according to claim 2, characterized in that, The manufacturing method further includes: Depositing silicon material on the protective layer to form a buffer layer; Forming a filling layer based on the buffer layer.

4. The manufacturing method according to claim 1, characterized in that, The forming a protective layer along the inner wall of the isolation trenches includes: Performing a germanium ion implantation process on the isolation trenches to form the protective layer at a target depth inside the isolation trenches.

5. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: Performing an oxidation process on the inner wall of the trenches to form a filling layer on the protective layer.

6. The manufacturing method according to claim 1, characterized in that, The etching the substrate to form germanium silicon accommodating structures in the source-drain regions of the semiconductor units includes: Performing a first etching operation on the source-drain regions to form initial trenches in the source-drain regions; Performing a second etching operation on the interior of the initial trenches to form the germanium silicon accommodating structures in the source-drain regions.

7. A semiconductor device, characterized in that, The semiconductor device includes a plurality of semiconductor units provided in a substrate and isolation trenches separating the semiconductor units, the isolation trenches being used to separate adjacent semiconductor units, wherein the material of the substrate is silicon material, the isolation trenches extend towards the interior of the substrate and the internal dimensions of the isolation trenches gradually decrease; The source-drain regions of the semiconductor units include germanium silicon accommodating structures and a source and / or drain formed on the germanium silicon accommodating structures, wherein the germanium silicon accommodating structures extend towards the interior of the substrate and the internal dimensions of the germanium silicon accommodating structures first increase and then decrease; The isolation trench includes a protective layer formed along the inner wall of the trench of the isolation trench. Wherein, the protective layer is used to maintain the complete trench structure of the isolation trench when the substrate is etched. For the target germanium-silicon accommodating structure close to the target isolation trench, a part of the protective layer of the target isolation trench is exposed in the target germanium-silicon accommodating structure and reused as the side wall of the target germanium-silicon accommodating structure, and the internal dimension of the target germanium-silicon accommodating structure gradually increases at the part of the protective layer; the part of the protective layer exposed in the target germanium-silicon accommodating structure is configured as a seed layer in the germanium-silicon material growth process to ensure that the germanium-silicon material can completely fill the germanium-silicon accommodating structure.

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