High-performance chip and manufacturing method thereof

Abstract

The invention discloses a high-performance chip and a manufacturing method thereof, the high-performance chip comprises a chip body, the chip body comprises a substrate, and a device layer, a bridging part and an I / O port layer which are sequentially added along the direction far away from the substrate; a main device region and an auxiliary device region are additionally arranged on the device layer; the I / O port layer comprises a heat dissipation area and a port area, the heat dissipation area is located in the middle of the I / O port layer, the port area is of an annular structure and surrounds the peripheral side of the heat dissipation area, and I / O ports are arrayed in the port area; the bridging part comprises a plurality of bridging circuit layers which are stacked together, bridging tracks for connecting the main device and the auxiliary device into a circuit and leads for connecting the I / O ports are additionally arranged in the bridging circuit layers, and each bridging track is covered with an insulating layer, so that the chip has more transistors, lower heat productivity and higher heat dissipation capability.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular to a high-performance chip and a manufacturing method thereof. Background Art

[0002] High-end general-purpose chips have always been the commanding heights of competition among countries in cutting-edge fields, and their manufacturing technology represents the highest level of ultra-precision manufacturing in the world. In the process of digital transformation, the importance of high-performance chips as carriers for high-performance computing, 5G communications, artificial intelligence, big data, etc. is self-evident.

[0003] The high performance of a chip itself depends mainly on the operating frequency and transistor density.

[0004] Intel spent more than ten years developing a chip that could achieve higher performance by increasing the operating frequency, but failed in the end due to serious heating problems. Chip heating and heat dissipation have been a problem that has plagued the industry for many years. Without solving the heat dissipation problem and finding the heating mechanism, it is impossible to achieve higher performance by increasing the operating frequency. Summary of the invention

[0005] The purpose of the present invention is to provide a high-performance chip and a method for manufacturing the same to solve the problems existing in the above-mentioned prior art, so that the chip has more transistors, generates less heat and has a stronger heat dissipation capacity.

[0006] To achieve the above object, the present invention provides the following solution: The present invention provides a high-performance chip, characterized in that it includes a chip body, the chip body includes a substrate and a device layer, a bridge portion and an I / O port layer sequentially added in a direction away from the substrate;

[0007] A main device area and an auxiliary device area are added to the device layer;

[0008] The I / O port layer includes a heat dissipation area and a port area, wherein the heat dissipation area is located in the middle of the I / O port layer, the port area is in a ring structure and surrounds the outer periphery of the heat dissipation area, and the port area is arrayed with I / O ports;

[0009] The bridge portion includes a plurality of bridge circuit layers stacked together, wherein the bridge circuit layers are additionally provided with bridge tracks for connecting the main device and the auxiliary device into a circuit and leads connecting the I / O port, and each of the bridge tracks is covered with an insulating layer.

[0010] Preferably, the device layer includes a main device area and an auxiliary device area which are respectively distributed corresponding to the heat dissipation area and the port area. The main device area is located in the middle position of the device layer, and the main device is additionally provided. The auxiliary device area has a ring structure and surrounds the outer periphery of the main device area, and the auxiliary device is additionally provided.

[0011] Preferably, the auxiliary components include but are not limited to capacitors, inductors, resistors and diodes.

[0012] Preferably, the I / O port near the outer edge of the port area is used as a power port and is connected to a power lead;

[0013] The I / O port located on the inner circumference side of the power port and close to the power port serves as a ground port and is connected to a ground lead.

[0014] Preferably, the I / O port located on the inner peripheral side of the ground port serves as a signal port and is connected to the corresponding connection circuits of the main device and the auxiliary device by nearby leads.

[0015] Preferably, the chip body is additionally provided with a heat dissipation cover, and inner walls of the heat dissipation cover respectively connected to the front and back surfaces of the chip body are provided with grooves, and the grooves are filled with thermal conductive adhesive.

[0016] Preferably, the heat dissipation cover is made of a copper-aluminum alloy cover.

[0017] A method for high-performance chip is also provided, comprising the following steps:

[0018] S1. Prepare a chip body, add a device layer, a bridge portion and an I / O port layer on the substrate in sequence, add a heat dissipation area and a port area surrounding the outer periphery of the heat dissipation area on the I / O port layer, the heat dissipation area corresponds to the main device area on the device layer, the port area corresponds to the auxiliary device area on the device layer, the port area array adds I / O ports, and the bridge portion includes a plurality of bridge circuit layers stacked together;

[0019] The I / O port near the outer edge of the port area is used as a power port and is connected to a power lead; the I / O port located on the inner side of the power port and close to the power port is used as a ground port and is connected to a ground lead; the I / O port located on the inner side of the ground port is used as a signal port and is distributed close to the corresponding main device and the auxiliary device;

[0020] Starting from the device layer to the bridge circuit layer adjacent to the I / O port layer, adjacent contacts at the same node of the circuit are connected and then wired to the signal port nearby until all circuit connections are completed;

[0021] S2, adding the main device to the main device area, adding some auxiliary devices to the auxiliary device area, and the auxiliary devices in the auxiliary device area surround the outer periphery of the main device;

[0022] S3. When the chip body is packaged, a corresponding heat dissipation cover is installed according to product positioning.

[0023] Preferably, in step S3, before installing the heat dissipation cover, grooves are formed on the inner walls of the heat dissipation cover respectively connected to the front and back surfaces of the chip body, and the grooves are filled with thermal conductive adhesive.

[0024] Preferably, the thermally conductive adhesive is made of resin mixed with copper powder.

[0025] Compared with the prior art, the present invention has achieved the following technical effects:

[0026] The present invention liberates the front and back end surfaces of the chip body by adding an edge area for I / O terminal layout outside the main device area, incorporates both sides of the chip body into the device manufacturing area, and greatly increases the number of transistors; this method is used to make a single side into a dual-core or multi-core chip with stronger computing power after reintegration; chips with different functions can also be reintegrated on the front and back sides, such as SoC; and heat can be dissipated to the front and back sides of the chip body simultaneously, the heat dissipation area is greatly increased while leaving no heat dissipation dead corners; the distance of heat conduction outward is shorter than that of a single side; and the freedom of lead wires is released all around, the connection is more efficient and convenient, the flattened bridge circuit structure shortens the connection distance, and at the same time reduces the number of manufacturing layers of the bridge layer, making the chip thinner. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0028] Figure 1 It is the I / O port layout diagram at the port area of ​​the present invention;

[0029] Figure 2 is a side view of the chip body of the present invention;

[0030] Figure 3 A diagram showing the node connection model in the bridge circuit layer of the present invention;

[0031] Figure 4 This is a schematic diagram of the internal device distribution of the chip body of the present invention;

[0032] Figure 5 The chip body and the heat dissipation cover joint structure of the present invention;

[0033] Figure 6 for Figure 5 An enlarged view of the junction between the chip body and the heat sink;

[0034] Figure 7 It is the heat flow form inside the chip body in the prior art;

[0035] Figure 8 The heat flow pattern inside the chip body of the present invention;

[0036] Fig. 9 The temperature distribution diagram of the chip body in the thickness direction of the present invention;

[0037] Fig.10 This is a schematic diagram of the structure of the chip body of the present invention after a heat dissipation cover is added;

[0038] Fig.11 It is a schematic diagram of the structure of the first sub-cover and the second sub-cover of the present invention;

[0039] Fig.12 This is a schematic diagram of the structure of the chip body combined with the PCB board of the present invention;

[0040] Among them, 1-signal port, 2-heat dissipation area, 3-power port, 4-I / O interface, 5-port area, 6-insulation layer, 7-bridge circuit layer, 8-lead, 9-auxiliary device area, 10-substrate, 11-main device area, 12-heat dissipation cover, 13-chip body, 14-thermal conductive adhesive, 15-groove, 16-second tooth-shaped structure, 17-first sub-cover, 18-second sub-cover, 19-boss structure, 20-first tooth-shaped structure, 21-locking screw hole, 22-PCB board. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] The purpose of the present invention is to provide a high-performance chip and a method for manufacturing the same to solve the problems existing in the above-mentioned prior art, so that the chip has more transistors, generates less heat and has a stronger heat dissipation capacity.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] like Figures 1 to 12 As shown, this embodiment provides a high-performance chip, including a chip body 13, the chip body 13 includes a substrate 10 and a device layer, a bridge part and an I / O port layer added in sequence along a direction away from the substrate 10; main devices and auxiliary devices are added on the device layer, preferably, the main devices include but are not limited to transistors, and the auxiliary devices include but are not limited to capacitors, inductors, resistors and diodes; the I / O port layer includes a heat dissipation area 2 and a port area 5, the heat dissipation area 2 is located in the middle position of the I / O port layer, the port area 5 is a ring structure and surrounds the outer peripheral side of the heat dissipation area 2, and the port area 5 is arrayed with I / O ports to realize the addition of I / O ports to the periphery of the main device; the bridge part includes a plurality of bridge circuit layers 7 stacked together, and the bridge circuit layer 7 is provided with a bridge track for connecting the main device and the auxiliary device into a circuit and a lead 8 connecting the I / O port, each bridge track is covered with an insulating layer 6, and the lead 8 added in the bridge circuit layer 7 is preferably a copper lead 8. The present invention liberates the front and back end surfaces of the chip body 13 by adding an edge area for I / O terminal layout outside the main device area 11, incorporates both sides of the chip body 13 into the device manufacturing area, and greatly increases the number of transistors; this method is used to make a single side into a dual-core or multi-core chip with stronger computing power after reintegration; chips with different functions can also be reintegrated on the front and back sides, such as SoC; and heat can be dissipated to the front and back sides of the chip body 13 simultaneously, the heat dissipation area is greatly increased while leaving no heat dissipation dead corners; the distance of heat conduction outward is shorter than that of a single side; and 8 degrees of freedom of the leads are released to the surrounding areas, making the connection more efficient and convenient, and the flattened bridge circuit structure shortens the connection distance, while reducing the number of manufacturing layers of the bridge layer, making the chip thinner.

[0045] In this specific embodiment, the device layer includes a main device area 11 and an auxiliary device area 9 respectively distributed corresponding to the heat dissipation area 2 and the port area 5. The main device area 11 is located in the middle of the device layer and is additionally provided with a main device. The auxiliary device area 9 is an annular structure and surrounds the outer peripheral side of the main device area 11, and is additionally provided with an auxiliary device. The lead 8 added in the bridge circuit layer 7 transfers part of the heat energy out of the main device area 11, which is equivalent to opening up a fast channel for heat dissipation from the main device area 11 to the surroundings; while greatly shortening the connection distance, more leads 8 and nodes are moved out of the main device area 11, the purpose of which is to eliminate the environment for the generation of electromagnetic heating as much as possible, and to move the electromagnetic heating of part of the leads 8 out of the main device area 11.

[0046] It is further necessary to explain that: from the perspective of current desktop computer CPUs, the pursuit of higher chip output rates, manufacturing more transistors in a limited space on the wafer, and maximizing profits are the fundamentals of enterprise survival. As a result, heat dissipation considerations give way to the number of transistors: the front of the chip is used as an I / O interface 4, and the back is used for heat dissipation. The dense bridge circuit on the front side makes its physical properties tend to be metallized. The dense wires interact with each other, and the electromagnetic heat caused by each other and themselves creates the largest heat source; the heat energy is preferentially transferred to the front through the copper lead 8 with strong thermal conductivity, and the front heat dissipation capacity is insufficient, resulting in heat energy accumulation, so the highest temperature in the chip is formed in the middle area of ​​the area. The existence of the temperature gradient causes part of the heat energy to return to the back and transfer out of the chip. Therefore, the increasing number of pin designs of high-performance chips, in addition to shunting to make the current less than 1A, are important factors for using dense pins to export the large amount of heat energy accumulated on the front; therefore, the front has a stronger and more realistic heat dissipation layout demand than the back.

[0047] After comprehensive consideration, the present invention places the I / O ports on the edges of the four sides, so that both sides of the chip body 13 can be included in the device manufacturing, which greatly increases the number of transistors and allows the front and back sides to be used for heat dissipation; the freedom of the lead 8 is released outside the main device area 11, which greatly shortens the lengthy connection and reduces the number of manufacturing layers; the wiring is radiated to the surrounding areas, and copper leads 8 are preferably used, and the copper leads 8 themselves can be used. The large heat capacity and fast heat conduction characteristics of the copper leads 8 can be used to open up a fast channel for heat dissipation from the main device area 11 to the surrounding areas; especially for double-sided manufacturing (or single-sided manufacturing, grinding and thinning, bonding graphene and other heat dissipation layers and then packaging pseudo-double-sided) products.

[0048] In a specific embodiment, the I / O port near the outer edge of the port area 5 serves as the power port 3 and is connected to a power lead 8; the I / O port located on the inner side of the power port 3 and close to the power port 3 serves as the ground port and is connected to a ground lead 8, so that the four edges of the chip body 13 are preferentially powered and secondarily grounded.

[0049] In a specific embodiment, the I / O port located on the inner side of the ground port is used as the signal port 1, so that the signal port 1, the ground port and the power port 3 are arranged in sequence in the direction away from the main device area 11, and are connected to the corresponding main device and auxiliary device connection circuits by the nearest lead 8. Specifically, each auxiliary device is distributed according to the arrangement position of each I / O port, so that when the I / O port is led to the outer periphery 8, it is connected to the auxiliary device located below, and the path is more reasonable.

[0050] In a specific embodiment, a heat sink 12 is installed on the chip body 13. Preferably, the heat sink 12 is a copper-aluminum alloy cover. The inner walls of the heat sink 12 that are respectively connected to the front and back of the chip body 13 are both provided with grooved channels 15, and the grooved channels 15 are filled with thermal conductive glue 14. By providing the heat sink 12, the heat dissipation of the chip is ensured, and its ability to work efficiently and stably is improved.

[0051] Specifically, it should be noted that: by installing the heat sink 12, the heat dissipation path of the chip is simplified. The chip is in close contact with the first heat-receiving environment, the heat sink 12. When the heat capacity is large enough, the disturbances of the heat source and the second heat-receiving environment can even be ignored. Moreover, it has the effect of indirectly suppressing the fluctuation of the highest temperature inside the chip; in the prior art, due to the dense bridging circuits on the front side of T3, the heat conduction ability is very strong, but there are front I / O ports, and it does not have the condition for active heat dissipation. Therefore, a large amount of heat energy will be accumulated, resulting in a high temperature; the highest temperature inside the chip appears on this side, which is the biggest problem in chip heat dissipation; in the present invention, Ta and Tc connected to the heat sink 12 are basically the same, dissipating heat to both sides, with a short distance, a small thermal resistance, and a strong heat-receiving ability. In this way, Ta < T1, Tb < T2, Tc < T3, and it is much more stable; further, it provides a convenient and efficient interface basis for different heat dissipation requirements of the chip. Specifically, for example: The first type is a desktop CPU, which is equipped with a heat sink 12 with a heat capacity ten times that of the chip, and is externally connected to a radiator through a toothed joint surface with a larger surface area. The heat capacity can reach a hundred times, which is equivalent to equipping the chip with a heat storage pool (heat-receiving environment) with a relatively stable temperature; using the stronger specific heat capacity and thermal conductivity of copper alloy, when quickly absorbing the heat energy of the chip, it also has a strong heat dissipation ability, and its own temperature change is more stable. The chip has different temperature gradients under different load working conditions (such as working frequency, voltage, etc.), which indirectly ensures the stability of the highest temperature inside the chip. The second type is a server, which is equipped with a high-performance re-integrated chip and provides an efficient, compact, integral, and easy-to-implement heat dissipation interface; through the预埋管 (pre-buried pipe) of the heat sink 12, it is connected to the equipped refrigeration system for forced refrigeration to meet higher-performance heat dissipation requirements. In addition, by using an alloy cover as the heat sink 12, the chip is provided with an electromagnetic radiation resistance function, providing an electromagnetic radiation-proof chip for special environments such as space, nuclear power plants, and battlefields.

[0052] It should be noted that there is an unclear expression "预埋管" in the original text, which is directly translated as "pre-buried pipe" here. You may need to check and correct it according to the actual situation.In a specific embodiment, the heat dissipation cover 12 includes a first sub-cover 17 and a second sub-cover 18 respectively installed on the front and back surfaces of the chip body 13, and the first sub-cover 17 and the second sub-cover 18 are respectively provided with a groove 15 on one side combined with the chip body 13, and the first sub-cover 17 and the second sub-cover 18 are provided with a joint surface for connecting the two, and the joint surface is located on the outside of the chip body 13, and the joint surfaces of the first sub-cover 17 and the second sub-cover 18 are arrayed with a first tooth-shaped structure 20 to ensure the bonding strength between the two, and the surfaces of the first sub-cover 17 and the second sub-cover 18 facing away from the chip body 13 are arrayed with a second tooth-shaped structure 16, and the joint surfaces of the first sub-cover 17 and the second sub-cover 18 are opened with locking screw holes 21, so that the two locking screw holes 21 are connected by bolts, thereby realizing the connection between the first sub-cover 17 and the second sub-cover 18, so that the chip body 13 is embedded between the first sub-cover 17 and the second sub-cover 18. Preferably, the first sub-cover 17 and the second sub-cover 18 are respectively provided with a boss structure 19 at the positions where they are combined with the chip body 13, the chip body 13 is embedded between the two boss structures 19, and the groove 15 is correspondingly opened on the surface of the boss structure 19 close to the chip body 13. After the heat dissipation cover 12 is added, the chip body 13 is installed on the PCB board 22.

[0053] Furthermore, a method for producing a high-performance chip is provided, comprising the following steps:

[0054] S1, prepare a chip body 13, add a device layer, a bridge part and an I / O port layer on the substrate 10 in sequence, add a heat dissipation area 2 and a port area 5 surrounding the outer peripheral side of the heat dissipation area 2 on the I / O port layer, the heat dissipation area 2 corresponds to the main device area 11 on the device layer, the port area 5 corresponds to the auxiliary device area 9 on the device layer, and the port area 5 array adds I / O ports. According to the principle of topology, the lead 8 degrees of freedom are released to the surroundings, and the node connection is completed efficiently and conveniently with shorter connection lines and fewer bridge layers; the bridge part includes a plurality of bridge circuit layers 7 stacked together;

[0055] The I / O port near the outer edge of the port area 5 is used as the power port 3 and is connected to the power lead 8; the I / O port located on the inner side of the power port 3 and close to the power port 3 is used as the ground port and is connected to the ground lead 8, so that the edges of the chip body 13 are connected to the power first and then to the ground, and the I / O port located on the inner side of the ground port is used as the signal port 1 and is distributed nearby with the corresponding main device and auxiliary device, so that when the I / O port leads to the outer periphery 8, it is connected to the auxiliary device located below, and the path is more reasonable;

[0056] From the device layer to the bridge circuit layer 7 adjacent to the I / O port layer, adjacent contacts at the same node of the circuit are connected and then wired to the signal port 1 nearby the periphery until all circuit connections are completed; Figure 3This is the node connection model diagram after the I / O port is expanded, where A, B, and C are the same node positions in the bridge circuit layer, and F is a peripheral auxiliary device;

[0057] S2, adding the main device to the main device area 11, adding some auxiliary devices to the auxiliary device area 9, the auxiliary devices in the auxiliary device area 9 surround the outer periphery of the main device; manufacturing some auxiliary devices matching the main device area 11 on the outer periphery of the main device area 11, separating the auxiliary devices from the main device area 11 to the periphery, generally maintaining the manufacturing area of ​​the device while increasing the density of the transistors in the main device area 11, and incidentally moving the connecting wires and auxiliary devices out of the main device area 11, that is, reducing the environment of electromagnetic heating;

[0058] S3, when the chip body 13 is packaged, according to the product positioning, the corresponding heat dissipation cover 12 is installed. Preferably, in step S3, before the heat dissipation cover 12 is installed, grooves 15 are formed on the inner wall of the heat dissipation cover 12 respectively connected to the front and back sides of the chip body 13, and the grooves 15 are filled with thermal conductive adhesive 14, and the thermal conductive adhesive 14 is made of resin mixed with copper powder. The heat dissipation cover 12 is provided to ensure the heat dissipation of the chip and improve its ability to work efficiently and stably.

[0059] Adaptive changes made according to actual needs are all within the protection scope of the present invention.

[0060] It should be noted that it is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any reference numerals in the claims should not be regarded as limiting the claims involved.

[0061] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A high-performance chip, characterized in that: The chip body includes a substrate and a device layer, a bridge portion and an I / O port layer which are sequentially added in a direction away from the substrate; A main device area and an auxiliary device area are added to the device layer; The I / O port layer includes a heat dissipation area and a port area, wherein the heat dissipation area is located in the middle of the I / O port layer, the port area is in a ring structure and surrounds the outer periphery of the heat dissipation area, and the port area is arrayed with I / O ports; The bridge portion includes a plurality of bridge circuit layers stacked together, wherein the bridge circuit layers are additionally provided with bridge tracks for connecting the main device and the auxiliary device into a circuit and leads connecting the I / O port, and each of the bridge tracks is covered with an insulating layer.

2. The high-performance chip according to claim 1, characterized in that: The device layer includes a main device area and an auxiliary device area respectively distributed corresponding to the heat dissipation area and the port area. The main device area is located in the middle position of the device layer and is additionally provided with the main device. The auxiliary device area is an annular structure and surrounds the outer periphery of the main device area and is additionally provided with the auxiliary device.

3. The high-performance chip according to claim 2, characterized in that: The auxiliary devices include but are not limited to capacitors, inductors, resistors and diodes.

4. The high performance chip according to claim 2 or 3, characterized in that: The I / O port near the outer edge of the port area is used as a power port and is connected to a power lead; The I / O port located on the inner circumference side of the power port and close to the power port serves as a ground port and is connected to a ground lead.

5. The high-performance chip according to claim 4, characterized in that: The I / O port located on the inner peripheral side of the ground port is used as a signal port and is connected to the corresponding connection circuit node positions of the main device and the auxiliary device by wires.

6. The high-performance chip according to claim 5, characterized in that: The chip body is additionally provided with a heat dissipation cover, and inner walls of the heat dissipation cover respectively connected to the front and back surfaces of the chip body are provided with grooves, and the grooves are filled with heat-conducting glue.

7. The high-performance chip according to claim 6, characterized in that: The heat dissipation cover is made of copper-aluminum alloy.

8. A method for manufacturing a high-performance chip according to any one of claims 1 to 7, characterized in that: The steps include: S1. Prepare a chip body, add a device layer, a bridge portion and an I / O port layer on the substrate in sequence, add a heat dissipation area and a port area surrounding the outer periphery of the heat dissipation area on the I / O port layer, the heat dissipation area corresponds to the main device area on the device layer, the port area corresponds to the auxiliary device area on the device layer, the port area array adds I / O ports, and the bridge portion includes a plurality of bridge circuit layers stacked together; The I / O port near the outer edge of the port area is used as a power port and is connected to a power lead; the I / O port located on the inner side of the power port and close to the power port is used as a ground port and is connected to a ground lead; the I / O port located on the inner side of the ground port is used as a signal port and is distributed close to the corresponding main device and the auxiliary device; Starting from the device layer to the bridge circuit layer adjacent to the I / O port layer, adjacent contacts at the same node of the circuit are connected and then wired to the signal port nearby until all circuit connections are completed; S2, adding the main device to the main device area, adding some auxiliary devices to the auxiliary device area, and the auxiliary device area surrounds the outer periphery of the main device area; S3. When the chip body is packaged, a corresponding heat dissipation cover is installed according to product positioning.

9. The method for manufacturing a high-performance chip according to claim 8, characterized in that: In step S3, before installing the heat dissipation cover, grooves are formed on the inner walls of the heat dissipation cover respectively connected to the front and back surfaces of the chip body, and the grooves are filled with thermal conductive glue.

10. The method for manufacturing a high-performance chip according to claim 9, characterized in that: The thermal conductive adhesive is made of resin mixed with copper powder.

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