Semiconductor device, semiconductor package, and semiconductor packaging method

Abstract

The present invention relates to the field of semiconductor packaging, and provides a semiconductor device, a semiconductor package, and a semiconductor packaging method. The semiconductor device is applied to semiconductor packaging and includes: a plurality of semiconductor chips stacked, wherein the current semiconductor chip is stacked on the lower semiconductor chip; the substrate of the current semiconductor chip has a first surface and a second surface that are oppositely arranged; the first surface is used to provide an attachment surface for the interconnect layer; the second surface is used to abut against the interconnect layer at the top of the lower semiconductor chip. This structure is used to reduce the interlayer gap and the height fluctuation of the layer, thereby reducing the process steps of the filling gap process, ensuring no short circuit after packaging, and ensuring the performance of the device. Compared with the through-silicon via process, there is no need to precisely etch the internal structure of the silicon wafer, reducing the process difficulty of stacking semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a semiconductor device, a semiconductor packaging and a semiconductor packaging method. Background Art

[0002] Semiconductor devices usually use different semiconductor materials, different processes and geometric structures, and have developed a wide variety of devices with different functions and uses. It is often necessary to electrically connect the conductive materials of each layer to realize the interconnection of devices to achieve the required performance. Semiconductor devices are constantly developing in the direction of being smaller, faster and more efficient, which requires continuous innovation and optimization of the manufacturing process of the device. However, in the manufacturing process of semiconductor devices, there are a series of technical problems that need to be solved. In the traditional scheme, the interconnection layer is physically deposited, and silicon through-holes are usually used when interconnecting inter-layer devices across layers. However, this requires control of inter-layer alignment and drilling accuracy. If the accuracy is too low, it is easy to cause device failure, and the use of insulating layers to fill it is easy to block cross-layer conduction, further affecting the performance of the device. Therefore, there is an urgent need for a semiconductor device, semiconductor package and semiconductor packaging method to improve the above problems. Summary of the invention

[0003] An object of the present invention is to provide a semiconductor device, a semiconductor package and a semiconductor packaging method, which are used to reduce layer height fluctuations in a multi-layer chip to ensure the performance of the semiconductor device.

[0004] In the first aspect, the present invention provides a semiconductor device for use inside a semiconductor package, comprising: a plurality of stacked semiconductor chips, wherein the current semiconductor chip is stacked on a lower semiconductor chip; each semiconductor chip has a plurality of interconnection layers, a plurality of insulating layers and a substrate; the interconnection layers are used to provide a first conductive region and a second conductive region; the contours of adjacent etched grooves in N layers of interconnection layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2; the insulating layer is located between adjacent interconnection layers and is used to provide an insulating dielectric; the substrate of the current semiconductor chip has a first surface and a second surface arranged opposite to each other; the first surface is used to provide an attachment surface for the interconnection layer; and the second surface is used to abut the interconnection layer on the top of the lower semiconductor chip.

[0005] Optionally, the interconnection layer in each semiconductor chip is set to M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N layers of the interconnection layer do not intersect each other in the stacking direction.

[0006] Optionally, when M is greater than N, contours of the etched grooves in the interconnection layer within the N layers intersect with contours of the etched grooves in the interconnection layer outside the N layers.

[0007] Optionally, the interconnect layer in each semiconductor chip has opposite first and second edges, and the etching grooves in adjacent two interconnect layers are respectively close to the first edge and the second edge, so that the first regions and the second regions in adjacent interconnect layers overlap alternately.

[0008] In a second aspect, the present invention provides a semiconductor package, including: the semiconductor device according to any one of the first aspects, and: a first conductive sealing end for connecting the first regions of the interconnect layers in each semiconductor chip; a second conductive sealing end for connecting the second regions in the interconnect layers in each semiconductor chip; the first conductive sealing end and the second conductive sealing end are isolated from each other.

[0009] In a third aspect, the present invention provides a semiconductor packaging method for forming the semiconductor device according to any one of the first aspects, including: S1, providing a substrate and forming an interconnect region at a part where conductor leads are required; S2, performing an etching process on the non-interconnect regions on the surface that do not require conductor leads, so that the non-interconnect regions are blocked by etching grooves into a first region and a second region; S3, forming an insulating layer on the surface of the interconnect layer; forming an interconnect layer on the upper surface of the insulating layer; S4, after repeating S2-S3 several times, performing S2 once again to form a semiconductor chip; the outlines of the adjacent etching grooves in the N-layer interconnect layer do not intersect in the stacking direction, where N is a positive integer greater than 2; S5, repeating S1-S4 for L times, where L is a positive integer greater than 1; stacking the L-layer semiconductor chips to form a semiconductor device.

[0010] Optionally, the semiconductor chip is thinned, and the L-layer thinned semiconductor chips are stacked to form a semiconductor device.

[0011] Optionally, the edges of the stacked interconnect layers are cut or polished so that the first regions and the second regions of the interconnect layers in the semiconductor chip are exposed.

[0012] Optionally, a first conductive sealing end for connecting the first regions in each interconnect layer is formed, and a second conductive sealing end for connecting the second regions in each interconnect layer is formed.

[0013] Optionally, the interconnect layer and the insulating layer are respectively formed by at least one of atomic layer deposition or chemical vapor deposition processes; the first conductive sealing end and the second conductive sealing end are formed by an electroplating process.

[0014] The beneficial effects of the present invention are as follows: The semiconductor device is applied to semiconductor packaging and includes a plurality of semiconductor chips stacked. Among them, the current semiconductor chip is stacked on the lower semiconductor chip; the substrate of the current semiconductor chip has a first surface and a second surface arranged opposite to each other; the first surface is used to provide an attachment surface for the interconnect layer; the second surface is used to abut against the interconnect layer at the top of the lower semiconductor chip. This structure is used to reduce the interlayer gap and layer height fluctuation, thereby reducing the process steps of the filling gap process, ensuring no short circuit after packaging, and ensuring the performance of the device. Compared with the through-silicon via process, there is no need to precisely etch the internal structure of the silicon wafer, reducing the process difficulty of semiconductor device stacking. Description of the Drawings

[0015] Figure 1 Schematic diagram of a semiconductor device provided by the present invention;

[0016] Figure 2 Schematic diagram of the structure of a semiconductor package provided by the present invention;

[0017] Figure 3 Schematic diagram of the process flow of a semiconductor packaging method provided by the present invention;

[0018] Figure 4 Schematic diagram of the structure of an odd-numbered first interconnect layer formed on a substrate provided by the present invention;

[0019] Figure 5 Schematic diagram of the structure of an odd-numbered first interconnect layer etching groove formed in the odd-numbered first interconnect layer provided by the present invention;

[0020] Figure 6 Schematic diagram of the structure of a first insulating layer formed on the odd-numbered first interconnect layer provided by the present invention;

[0021] Figure 7 Schematic diagram of the structure of an odd-numbered second interconnect layer formed on the first insulating layer provided by the present invention;

[0022] Figure 8 Schematic diagram of the structure of an odd-numbered second interconnect layer etching groove formed in the odd-numbered second interconnect layer provided by the present invention;

[0023] Figure 9 Schematic diagram of the structure of a second insulating layer formed on the odd-numbered second interconnect layer provided by the present invention;

[0024] Figure 10 Schematic diagram of the structure of a semiconductor package provided with a conductive sealing end provided by the present invention.

[0025] Explanation of the reference numerals in the drawings:

[0026] 1. Substrate; 6. Chip unit;

[0027] 21. First interconnection layer for odd digits; 22. First interconnection layer for even digits; 31. Second interconnection layer for odd digits; 32. Second interconnection layer for even digits; 41. First insulating layer; 42. Second insulating layer; 43. Third insulating layer; 51. First conductive sealing end; 52. Second conductive sealing end;

[0028] 201. Etching groove for the first interconnection layer of odd digits; 202. Etching groove for the first interconnection layer of even digits; 211. High potential region of the first interconnection layer of odd digits; 212. Low potential region of the first interconnection layer of odd digits; 221. High potential region of the first interconnection layer of even digits; 222. Low potential region of the first interconnection layer of even digits;

[0029] 301. Etching groove for the second interconnection layer of odd digits; 302. Etching groove for the second interconnection layer of even digits; 311. High potential region of the second interconnection layer of odd digits; 312. Low potential region of the second interconnection layer of odd digits; 321. High potential region of the second interconnection layer of even digits; 322. Low potential region of the second interconnection layer of even digits. Detailed implementation mode

[0030] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should have the ordinary meaning understood by those of ordinary skill in the art in the field to which the present invention belongs. The words such as "including" used herein mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects.

[0031] Currently, through-silicon via technology is usually adopted in the prior art to achieve 3D packaging. However, for the existing etching processes of vias, including laser etching and deep reactive ion etching, high-precision processes are required to achieve the preparation of microholes with high aspect ratio structures, and high-precision etching equipment is needed. These advanced equipment are usually expensive, increasing the cost of mass production and being unfavorable for the popularization of high-integration packaging.

[0032] Regarding the problems existing in the prior art, such as Figure 1As shown in the figure, the first embodiment of the present invention provides a semiconductor device, which is applied inside a semiconductor package and includes: a plurality of semiconductor chips stacked, wherein the current semiconductor chip is stacked on the lower semiconductor chip; each semiconductor chip has a plurality of interconnect layers, a plurality of insulating layers, and a substrate; the interconnect layers are used to provide a first conductive region and a second conductive region; the contours of adjacent etching grooves in the N interconnect layers do not intersect in the stacking direction, where N is a positive integer greater than 2; the insulating layers are located between adjacent interconnect layers and are used to provide insulating dielectrics; the substrate of the current semiconductor chip has a first surface and a second surface arranged opposite to each other; the first surface is used to provide an attachment surface for the interconnect layers; the second surface is used to abut against the interconnect layer at the top of the lower semiconductor chip. In this embodiment, since the contours of adjacent etching grooves in the N interconnect layers do not intersect in the stacking direction, the height difference accumulation of the etching grooves in the multi-layer interconnect layers is avoided, the actual effective conductive area can be increased, the electric field between the interconnect layers can be kept uniform, the local electric field strength can be prevented from being too high, thereby reducing the leakage current, improving the insulation performance of the insulating layer, avoiding breakdown, and being beneficial to improving the performance of the semiconductor device.

[0033] In some other specific embodiments, the stacking direction of the N interconnect layers is along the vertical direction Z, and the extending directions of the substrate 1, the interconnect layers, and the insulating layers are along the horizontal plane. The etching grooves are configured to gradually penetrate into the interconnect layers along the vertical direction Z until they contact the substrate 1 or the insulating layer. The stacking structure of this embodiment can disperse stress, reduce the pressure on the single-chip structure, and improve the mechanical stability of the semiconductor device.

[0034] In still some other specific embodiments, the substrate 1 in each semiconductor chip is made of materials such as silicon, silicon oxide, zirconium oxide, hafnium oxide, germanium, silicon nitride, aluminum oxide, or gallium oxide. The interconnect layers are provided as conductive materials. The insulating layers are provided as insulating materials. The insulating layers are also used to fill the etching grooves in the interconnect layers below them, so that the first region and the second region are separated by the insulating materials.

[0035] In some embodiments, the interconnect layers are provided as M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etching grooves in the N interconnect layers do not intersect in the stacking direction.

[0036] In some specific embodiments, M = N = 4. An odd-numbered first interconnect layer 21 is connected to the attachment surface provided by the substrate 1. A first insulating layer 41 is connected to the odd-numbered first interconnect layer 21. An odd-numbered second interconnect layer 31 is connected to the first insulating layer 41. A second insulating layer 42 is connected to the odd-numbered second interconnect layer 31. An even-numbered first interconnect layer 22 is connected to the second insulating layer 42. A third insulating layer 43 is connected to the even-numbered first interconnect layer 22. An even-numbered second interconnect layer 32 is connected to the third insulating layer 43. In this embodiment, by setting the etching grooves in the N interconnect layers not to intersect in the Z direction, the accumulation of the height difference of the etching grooves is avoided, and the step difference can be fundamentally eliminated. The actual effective conductive area of the chip is increased, the electric field between the interconnect layers is kept uniform, the local electric field strength is prevented from being too high, thereby reducing the leakage current, improving the insulation performance of the insulating layer, avoiding breakdown, and being beneficial to improving the performance of semiconductor devices.

[0037] In some examples, the odd-numbered first interconnect layer 21 is provided with an odd-numbered first interconnect layer etching groove 201 near the opposite direction of X, and the even-numbered first interconnect layer 22 is provided with an even-numbered first interconnect layer etching groove 202 near the opposite direction of X. The odd-numbered first interconnect layer etching groove 201 and the even-numbered first interconnect layer etching groove 202 are adjacent etching grooves, and their profiles in the Z direction do not intersect.

[0038] In some other examples, the odd-numbered second interconnect layer 31 is provided with an odd-numbered second interconnect layer etching groove 301 near the X direction, and the even-numbered second interconnect layer 32 is provided with an even-numbered second interconnect layer etching groove 302 near the X direction. The odd-numbered second interconnect layer etching groove 301 and the even-numbered second interconnect layer etching groove 302 are adjacent etching grooves, and their profiles in the Z direction do not intersect.

[0039] It should be noted that the Micro-displacement Fine Trench Patterning (MDFTP) is adopted to define the positions of the etching grooves of adjacent interconnect layers. It can achieve a positioning accuracy of sub-micron or even nano-scale, which is beneficial to improving the integration degree of integrated circuits.

[0040] In some embodiments, when M is greater than N, the profiles of the etching grooves in the interconnect layers within N layers and the interconnect layers outside N layers partially intersect.

[0041] In some specific embodiments, M = 20, N = 10. Twenty interconnection layers and twenty insulating layers are stacked on the substrate 1 along the Z direction. The profiles of the etching grooves in the interconnection layer located at the first layer intersect with the profiles of the etching grooves in the interconnection layer located at the 401st layer in the Z direction; the profiles of the etching grooves in the interconnection layer located at the second layer intersect with the profiles of the etching grooves in the interconnection layer located at the 402nd layer in the Z direction; the profiles of the etching grooves in the interconnection layer located at the tenth layer intersect with the profiles of the etching grooves in the interconnection layer located at the twentieth layer in the Z direction. In this embodiment, by reusing the positions of the etching grooves after every N interconnection layers, the local accumulation of the height difference of the etching grooves can be minimized as much as possible, enabling the semiconductor device to reach a higher number of layers to meet the design of large-capacity semiconductor packaging. On the other hand, in this embodiment, by increasing the number of interconnection layers to M layers, the effective conductive area can be further increased, thereby improving the overall working efficiency of the semiconductor device.

[0042] In some embodiments, the interconnection layers in each semiconductor chip have opposite first and second edges, and the etching grooves in adjacent two interconnection layers are respectively close to the first edge and the second edge, so that the first regions and the second regions in adjacent interconnection layers overlap alternately.

[0043] In some specific embodiments, the first edge is in the negative X direction, and the second edge is in the X direction. In some examples, the low-potential regions 212 of the odd-numbered first interconnection layers, the high-potential regions 311 of the odd-numbered second interconnection layers, the low-potential regions 222 of the even-numbered first interconnection layers, and the high-potential regions 321 of the even-numbered second interconnection layers overlap alternately from bottom to top. In some other specific embodiments, the first edge is in the X direction, and the second edge is in the negative X direction. In this embodiment, by making the etching grooves in adjacent two interconnection layers respectively close to the first edge and the second edge, the space can be better utilized, the effective conductive area can be further increased, and thus the working efficiency can be improved.

[0044] In some embodiments, the semiconductor device includes a chip unit 6, and the chip unit 6 is located at the central position of the semiconductor device. The etching grooves 201 of the odd-numbered first interconnection layers are in the negative X direction of the chip unit 6; the etching grooves 301 of the odd-numbered second interconnection layers are in the X direction of the chip unit 6.

[0045] In some specific embodiments, the chip unit 6 is configured as a memory chip unit. The memory chip unit includes a static random access memory (SRAM), a dynamic random access memory (DRAM), or other types of non-volatile memories.

[0046] In some other specific embodiments, the chip unit 6 is set as a logic chip unit. The logic chip unit includes an Arithmetic Logic Unit (ALU), a microprocessor core, a Digital Signal Processor (DSP), or an Application-Specific Integrated Circuit (ASIC) for executing specific algorithms.

[0047] As Figure 2 shown, the second embodiment provides a semiconductor package, including: the internal semiconductor device of the semiconductor device in any one of the above embodiments, and: a first conductive sealing end 51 for connecting a first region of the interconnect layer in each semiconductor chip; a second conductive sealing end 52 for connecting a second region of the interconnect layer in each semiconductor chip; the first conductive sealing end 51 and the second conductive sealing end 52 are not connected to each other.

[0048] In some specific embodiments, the first conductive sealing end 51 is used to connect a high-potential terminal, and the second conductive sealing end 52 is used to connect a low-potential terminal. When there is a potential difference between the high-potential terminal and the low-potential terminal, an electric field is formed between the first region and the second region. In some other specific embodiments, the first conductive sealing end 51 is used to connect a low-potential terminal, and the second conductive sealing end 52 is used to connect a high-potential terminal. It should be noted that in this embodiment, by setting the non-connected first conductive sealing end 51 and the second conductive sealing end 52, the adjacent interconnect layers are paralleled, which is beneficial to increasing the area of the terminals. Thanks to the parallel connection of multiple interconnect layers and the effective use of space, the integration degree of the semiconductor device can be improved.

[0049] In some examples, the number of interconnect layers is even, and charges are stored through alternating insulating layers and interconnect layers. In some other examples, the number of interconnect layers is odd, and the topmost interconnect layer is not connected to the first conductive sealing end 51 and the second conductive sealing end 52, and is used for providing shielding. This design can reduce electromagnetic interference between the semiconductor device and other components, especially in high-frequency applications. The shielding effect of the topmost interconnect layer helps to maintain the stable performance of the semiconductor device and reduce electromagnetic interference to the outside.

[0050] As Figure 3As shown in the figure, the third embodiment provides a semiconductor packaging method for forming an internal semiconductor device of the semiconductor device described in any one of the above embodiments, including: S1, providing a substrate 1 and forming an interconnect layer in the part where conductor leads are required; S2, performing an etching process on the non-interconnect area on the surface that does not require conductor leads, so that the non-interconnect area is blocked by etching grooves into a first area and a second area; S3, forming an insulating layer on the surface of the interconnect layer; forming an interconnect layer on the upper surface of the insulating layer; S4, after repeating S2 - S3 several times, performing S2 one more time to form a semiconductor chip; the contours of adjacent etching grooves in the N-layer interconnect layer do not intersect in the stacking direction, where N is a positive integer greater than 2; S5, repeating S1 - S4 L times, where L is a positive integer greater than 1; stacking the L-layer semiconductor chips to form a semiconductor device.

[0051] It should be noted that the interconnect layer and the insulating layer are respectively formed by at least one of the processes of Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). In this embodiment, by repeatedly executing steps S2 and S3, a new layer is deposited on the basis of the previous layer c and the insulating layer each time, realizing the layer-by-layer alternating accumulation of the multi-layer interconnect layer and the insulating layer structure. This process demonstrates a high degree of repeatability and control precision, supporting the large-scale industrial production of complex multi-layer structures.

[0052] In some embodiments, S5 further includes: thinning the semiconductor chips, and stacking the L-layer thinned semiconductor chips to form a semiconductor device. It should be noted that in this embodiment, by stacking the semiconductor chips, the local differences in layer height are reset, avoiding the reduction of the effective conductive area caused by excessive layer height fluctuations, improving the uniformity of the electric field between interconnect layers, being beneficial to reducing leakage current, improving the insulation performance of the insulating layer, avoiding the risk of breakdown, and ensuring the performance of the semiconductor device group.

[0053] More specifically, when thinning the bottom surface of the substrate of each semiconductor chip, a thinning process is performed on the second surface of the substrate to thin the substrate to 80 - 100 microns. The thinning process is mechanical grinding, chemical mechanical polishing or etching. In this embodiment, by thinning the substrate in the semiconductor chip, the volume ratio of the substrate in the semiconductor device group is reduced as much as possible, so that more interconnect layers can be accommodated in the limited on-chip space.

[0054] As Figure 4 shown, in the first example, a reactive ion etching process is used to pattern-etch 5 silicon substrates 1 with a size of 2 cm * 2 cm. S1 includes: depositing 20 nanometers of titanium nitride (TiN) on the silicon wafer surface by atomic layer deposition process as the first interconnect layer 21 at odd positions.

[0055] As Figure 5 shown, when S2 is executed for the first time, it also includes: etching the first odd-bit interconnect layer 21 at the first edge in the opposite direction of X to form an etching groove 201 for the first odd-bit interconnect layer, and dividing the first odd-bit interconnect layer 21 into a high-potential region 211 and a low-potential region 212 of the first odd-bit interconnect layer.

[0056] As Figure 6 shown, when S3 is executed for the first time, it also includes: S31, depositing 10 nm of hafnium zirconium oxide (HfZrO) antiferroelectric material as the first insulating layer 41 on the surface of the first odd-bit interconnect layer 21 using atomic layer deposition. As Figure 7 shown, depositing 40 nm of titanium nitride as the second odd-bit interconnect layer 31 on the first insulating layer 41 using atomic layer deposition.

[0057] As Figure 8 shown, when S2 is executed for the second time, it also includes: S41, etching the second odd-bit interconnect layer 31 at the second edge in the X direction to form an etching groove 301 for the second odd-bit interconnect layer, and dividing the second odd-bit interconnect layer 31 into a high-potential region 311 and a low-potential region 312 of the second odd-bit interconnect layer.

[0058] As Figure 9 shown, when S3 is executed for the second time, it also includes: S42, depositing 10 nm of silicon oxide as the second insulating layer 42 on the surface of the second odd-bit interconnect layer 31 using chemical vapor deposition. Depositing 20 nm of titanium nitride as the first even-bit interconnect layer 22 on the second insulating layer 42 using atomic layer deposition.

[0059] When S2 is executed for the third time, it also includes: S43, etching the first even-bit interconnect layer 22 at the first edge in the X direction to form an etching groove 202 for the first even-bit interconnect layer, and dividing the first even-bit interconnect layer 22 into a high-potential region 221 and a low-potential region 222 of the first even-bit interconnect layer.

[0060] When S3 is executed for the third time, it also includes: S44, depositing 10 nm of hafnium zirconium oxide (HfZrO) antiferroelectric material as the third insulating layer 43 on the surface of the first even-bit interconnect layer 22 using atomic layer deposition. Depositing 50 nm of titanium nitride as the second even-bit interconnect layer 32 on the third insulating layer 43 using atomic layer deposition.

[0061] When S2 is executed for the fourth time, it also includes: S45, etching the second even-bit interconnect layer 32 at the second edge in the X direction to form an etching groove 302 for the second even-bit interconnect layer, and dividing the second even-bit interconnect layer 32 into a high-potential region 321 and a low-potential region 322 of the second even-bit interconnect layer.

[0062] When performing S3 for the fourth time, it also includes: S46, depositing 10 nm of silicon oxide on the surface of the second interconnection layer 32 at even positions by chemical vapor deposition process as the fourth insulating layer.

[0063] It should be noted that when performing S2 for the last time on the current substrate, it also includes: etching the interconnection layer on the surface layer to form an etched groove of the surface layer interconnection layer, and dividing the interconnection layer on the surface layer into a surface layer high potential region and a surface layer low potential region.

[0064] Taking the fourth insulating layer as the substrate 1, the above S1 - S46 are repeatedly executed 10 times to form the semiconductor chip in the first example. The 5 semiconductor chips are thinned until 80 microns, and finally a liquid metal slurry is prepared on the substrate to stack the 5 semiconductor chips to form the semiconductor device.

[0065] In this example, by adopting a combination of atomic layer deposition and chemical vapor deposition, the thickness and quality of the insulating layer (such as zirconia, hafnium oxide) are precisely controlled, ensuring the effective utilization of high - dielectric - constant materials, and thus improving the energy density and efficiency of the semiconductor device. Selecting titanium nitride as the material of the interconnection layer, due to its excellent electrical conductivity and thermal stability, combined with high - dielectric - constant materials, significantly improves the high - frequency performance and thermal stability of the device, meeting the requirements of high - performance electronic devices.

[0066] In the second example, 20 silicon substrates 1 with a size of 1 cm * 1 cm are patterned and etched by reactive ion etching process. 400 nm of tungsten metal is deposited on the silicon wafer surface by atomic layer deposition process as the first interconnection layer 21 at odd positions.

[0067] As Figure 5 shown, when performing S2 for the first time, it also includes: etching the first interconnection layer 21 at odd positions at the first edge in the opposite direction of X to form an etched groove 201 of the first interconnection layer at odd positions, and dividing the first interconnection layer 21 at odd positions into a high potential region 211 of the first interconnection layer at odd positions and a low potential region 212 of the first interconnection layer at odd positions.

[0068] As Figure 6 shown, when performing S3 for the first time, it also includes: S31, depositing 20 nm of silicon oxide on the surface of the first interconnection layer 21 at odd positions by chemical vapor deposition process as the first insulating layer 41. As Figure 7 shown, 200 nm of tungsten metal is deposited on the first insulating layer 41 by chemical vapor deposition process as the second interconnection layer 31 at odd positions.

[0069] As Figure 8As shown, when S2 is executed for the second time, it further includes: S41, etching the odd-numbered second interconnect layer 31 at the second edge in the X direction to form an odd-numbered second interconnect layer etching groove 301, and dividing the odd-numbered second interconnect layer 31 into an odd-numbered second interconnect layer high potential region 311 and an odd-numbered second interconnect layer low potential region 312.

[0070] As Figure 9 shown, when S3 is executed for the second time, it further includes: S42, depositing 10 nm of silicon oxide on the surface of the odd-numbered second interconnect layer 31 using chemical vapor deposition as the second insulating layer 42. Depositing 400 nm of tungsten metal on the second insulating layer 42 as the even-numbered first interconnect layer 22.

[0071] When S2 is executed for the third time, it further includes: S43, etching the even-numbered first interconnect layer 22 at the first edge in the X direction to form an even-numbered first interconnect layer etching groove 202, and dividing the even-numbered first interconnect layer 22 into an even-numbered first interconnect layer high potential region 221 and an even-numbered first interconnect layer low potential region 222.

[0072] When S3 is executed for the third time, it further includes: S44, depositing 20 nm of silicon oxide on the surface of the even-numbered first interconnect layer 22 using chemical vapor deposition as the third insulating layer 43. Depositing 200 nm of tungsten metal on the third insulating layer 43 using chemical vapor deposition as the even-numbered second interconnect layer 32.

[0073] When S2 is executed for the fourth time, it further includes: S45, etching the even-numbered second interconnect layer 32 at the second edge in the X direction to form an even-numbered second interconnect layer etching groove 302, and dividing the even-numbered second interconnect layer 32 into an even-numbered second interconnect layer high potential region 321 and an even-numbered second interconnect layer low potential region 322.

[0074] When S3 is executed for the fourth time, it further includes: S46, depositing 10 nm of silicon oxide on the surface of the even-numbered second interconnect layer 32 using chemical vapor deposition as the fourth insulating layer.

[0075] Taking the fourth insulating layer as the substrate 1, the above S1 - S46 are repeatedly executed 15 times to form the semiconductor chip in the second example. Thinning the substrates of 20 such semiconductor chips until 100 microns, and finally spin-coating inorganic glue on the substrates to stack and fix 20 such semiconductor chips to form the semiconductor device.

[0076] Compared with other metals and alloys, tungsten metal has higher electrical conductivity and better corrosion resistance, which not only enhances the electrical conductivity of the interconnect layer but also may improve the overall stability and service life of the device. For the first time, chemical vapor deposition process is used in S3 to deposit 20 nm silicon oxide as the first insulating layer 41, and the change of the thickness of the subsequent insulating layers (such as 100 nm silicon oxide of the second insulating layer 42) can adjust different dielectric materials and thicknesses to optimize the chip integration and leakage current, so as to achieve the goal of higher integration or lower leakage.

[0077] In some embodiments, S4 further includes S45, cutting or grinding the edges of the stacked interconnect layers to expose the first region and the second region of the interconnect layers.

[0078] In some specific embodiments, first cut the edges of the stacked interconnect layers and then grind the edges so that a flat cut surface is exposed at the first edge on the opposite side of the X direction of the first region of the interconnect layer, and at the same time, a flat cut surface is exposed at the second edge on the X direction side of the second region of the interconnect layer. In this embodiment, by cutting and subsequent grinding of the edges of the stacked interconnect layers, it is ensured that the edges of the first region and the second region present flat cut surfaces on the opposite side of the X direction and the X direction side. This treatment method improves the edge neatness of the interconnect layer structure, reduces the risk of electric field concentration or short circuit caused by rough edges, and improves the reliability and electrical performance of the device.

[0079] As Figure 10 shown, in some embodiments, it further includes S5, forming a first conductive end portion 51 for connecting the first regions in each interconnect layer, and forming a second conductive end portion 52 for connecting the second regions in each interconnect layer.

[0080] It should be noted that the filling materials in the prior art need to have good fluidity and wettability, as well as appropriate process conditions. During the filling process, it is necessary to achieve filling with both high efficiency and low cost, while ensuring that there are no voids inside the metal core and no delamination or cracking occurs at the interface with the barrier layer. Depositing a high-quality metal seed layer on the sidewall of the through-silicon via is a difficult task, which directly affects the filling effect and the overall reliability of the through-silicon via. As the aperture decreases and the aspect ratio increases, the difficulty further intensifies.

[0081] In some comparative examples, the capping can be achieved by electroplating copper. However, electroplating copper is more difficult, and it is necessary to ensure that the growth rates at the top, middle, and bottom of the hole are consistent, which requires both a high-quality seed layer, a long growth time, and complex process conditions, and is easily contaminated.

[0082] In some specific embodiments of the present application, the first conductive sealing end portion 51 and the second conductive sealing end portion 52 are formed by electroplating using graphite paste or silver paste. In this embodiment, the conductive sealing end portions formed by electroplating using graphite paste or silver paste can significantly enhance the conductivity of the electrical connection between the interconnection layers, ensure efficient current transmission, reduce resistance loss, which is particularly crucial for improving the overall electrical performance of semiconductor devices. Both graphite and silver materials have good electrical conductivity and stability, and the formed sealing end portions can effectively resist the influence of environmental factors on the electrical connection part, increasing the long-term stability and durability of the device. Using the electroplating process to deposit and form the conductive sealing end portions can precisely control the thickness and uniformity of the deposited layer, is suitable for mass production, can simplify the manufacturing process of the conductive sealing end portions, improve production efficiency and reduce costs.

[0083] The liquid metal paste or inorganic glue in the above embodiments is used to bond adjacent semiconductor chips after solidification. In some examples, the liquid metal paste is defined as an interconnection layer participating in connecting the first conductive sealing end portion 51 or the second conductive sealing end portion 52. This example makes full use of the insulating characteristics of the substrate and the conductive characteristics of the liquid metal, increases the effective conductive area, and further improves the working efficiency of the semiconductor package.

[0084] The process flow of the prior art is relatively complex, involving multiple process steps, including via etching, insulating layer deposition, seed layer deposition, and electroplating filling. These steps need to be closely coordinated, and any mistake in any step may lead to the failure of the entire product. However, in the present application, by using graphite paste or silver paste for electroplating to form the conductive sealing end portions, not only the process flow is simplified, the production cost is reduced, but also the reliability and electrical performance of semiconductor devices are significantly improved.

[0085] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes fall within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A semiconductor device, used in a semiconductor package, characterized in that: include: A plurality of semiconductor chips arranged in a stack, wherein a current semiconductor chip is stacked on a lower semiconductor chip; Each semiconductor chip has N interconnection layers, a plurality of insulating layers and a substrate, where N is a positive integer greater than 2; The interconnection layer is used to provide a first conductive region and a second conductive region; the first region and the second region are separated by an etched groove; Along the stacking direction, the N interconnection layers include a first interconnection layer for odd bits, a first interconnection layer for even bits, a second interconnection layer for odd bits, and a second interconnection layer for even bits; the interconnection layer in each semiconductor chip has a first edge and a second edge opposite to each other; The odd-numbered first interconnection layer is provided with an odd-numbered first interconnection layer etching groove, and the even-numbered first interconnection layer is provided with an even-numbered first interconnection layer etching groove; the profiles of the odd-numbered first interconnection layer etching groove and the even-numbered first interconnection layer etching groove in the stacking direction do not intersect each other; The odd-numbered second interconnection layer is provided with an odd-numbered second interconnection layer etching groove, and the even-numbered second interconnection layer is provided with an even-numbered second interconnection layer etching groove; the contours of the odd-numbered second interconnection layer etching groove and the even-numbered second interconnection layer etching groove in the stacking direction do not intersect each other; The odd-numbered first interconnection layer etching grooves and the even-numbered first interconnection layer etching grooves are close to the first edge, and the odd-numbered second interconnection layer etching grooves and the even-numbered second interconnection layer etching grooves are close to the second edge; The insulating layer is located between adjacent interconnect layers and is used to provide an insulating dielectric; The substrate of the current semiconductor chip has a first surface and a second surface arranged opposite to each other; the first surface is used to provide an attachment surface for an interconnection layer; and the second surface is used to abut against the interconnection layer on the top of the lower semiconductor chip.

2. The semiconductor device according to claim 1, wherein: The interconnection layer in each semiconductor chip is set to M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N layers of the interconnection layer do not intersect each other in the stacking direction.

3. The semiconductor device according to claim 2, characterized in that When M is greater than N, the contours of the etched grooves in the interconnection layer within the N layer intersect with the contours of the etched grooves in the interconnection layer outside the N layer.

4. A semiconductor package, characterized in that: include: The semiconductor device according to any one of claims 1 to 3, and: A first conductive sealing end portion, used to connect to a first region of an interconnect layer in each semiconductor chip; The second conductive sealing end portion is used to connect the second region in the interconnection layer in each semiconductor chip; the first conductive sealing end portion and the second conductive sealing end portion are isolated from each other.

5. A semiconductor packaging method for forming the semiconductor device according to any one of claims 1 to 3, characterized in that: include: S1, providing a substrate, and forming an interconnection region at a portion where a conductor needs to be led out; S2, performing an etching process on a non-interconnected area on the surface where no conductor is required to be led out, so that the non-interconnected area is blocked by the etching groove into a first area and a second area; S3, forming an insulating layer on the surface of the interconnection layer; forming an interconnection layer on the upper surface of the insulating layer; S4, after repeating S2-S3 for several times, S2 is performed again to form a semiconductor chip; the contours of the odd-numbered first interconnection layer etching grooves and the even-numbered first interconnection layer etching grooves in the N layers of interconnection layers do not intersect each other in the stacking direction, and the contours of the odd-numbered second interconnection layer etching grooves and the even-numbered second interconnection layer etching grooves in the stacking direction do not intersect each other, and N is a positive integer greater than 2; S5, repeat S1-S4 L times, where L is a positive integer greater than 1; stack L layers of the semiconductor chips to form a semiconductor device.

6. The semiconductor packaging method according to claim 5, characterized in that: S5 also includes: thinning the semiconductor chips, and stacking L layers of thinned semiconductor chips to form a semiconductor device.

7. The semiconductor packaging method according to claim 5, characterized in that: S4 further includes: cutting or grinding the edges of the stacked interconnection layers to expose the first region and the second region of the interconnection layers in the semiconductor chip.

8. The semiconductor packaging method according to claim 7, characterized in that: Also includes: A first conductive sealing end portion is formed for connecting the first region in each interconnection layer, and a second conductive sealing end portion is formed for connecting the second region in each interconnection layer.

9. The semiconductor packaging method according to claim 8, characterized in that: The interconnection layer and the insulating layer are respectively formed by at least one of atomic layer deposition and chemical vapor deposition processes; the first conductive sealing end portion and the second conductive sealing end portion are formed by an electroplating process.

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