Driver chip, driver system and laser for semiconductor laser

Abstract

The present invention relates to the field of semiconductor laser technology, and in particular to a driver chip, a driver system and a laser for a semiconductor laser. The driver chip includes a package body, on which an EN pin, a RST_N pin, an SCL pin, an SDA pin, a VFB pin, an I_LIMIT pin, an NTC pin, a PD+ pin, a PGND pin, a PH pin, a VIN pin, a BOOT pin, a VOUT pin, a VDD pin and a GND pin are provided; the package body includes: a power processing module for processing an input power signal, and the VIN pin, the BOOT pin, the PH pin, the VOUT pin and the VDD pin are all connected to the power processing module; a signal processing module for transmitting and storing data, and the SCL pin, the SDA pin, the NTC pin, the PGND pin and the GND pin are all connected to the signal processing module; an APC module for controlling the laser current and power to be constant, and the VFB pin, the PD+ pin and the I_LIMIT pin are all connected to the APC module; automatic power adjustment can be achieved according to the characteristics of the semiconductor laser, and the power adjustment flexibility is high.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to a driving chip, a driving system and a laser for a semiconductor laser. Background Art

[0002] Semiconductor lasers use semiconductor materials as working materials, can emit lasers of specific wavelengths and powers, and have the advantages of small size and long life. In recent years, with the increasing maturity of semiconductor technology, semiconductor lasers have become one of the mainstream laser light sources and are widely used in consumer electronics, medical beauty, automotive aviation and other fields.

[0003] Since semiconductor lasers are very sensitive to operating temperature and have obvious light decay, constant current driving methods are generally used in applications where light output power and service life are not required. However, in applications where relatively high requirements are required, APC (automatic optical power control) circuits are often used for driving. By detecting the direction and degree of deviation of the actual optical power from the set value, the driving current is dynamically corrected to make it work in constant power mode, thereby stabilizing the light output power. However, existing driving systems for semiconductor lasers can only perform fixed constant power driving, and cannot automatically adjust and match the constant power parameters according to the characteristics of semiconductor lasers. Summary of the invention

[0004] The technical problem to be solved by the present invention is: in order to solve the technical problem that the existing driving system for semiconductor lasers cannot automatically adjust and match the parameters of constant power according to the characteristics of the semiconductor lasers, the present invention provides a driving system for semiconductor lasers, which can realize automatic power adjustment according to the characteristics of each semiconductor laser, thereby greatly improving the flexibility of semiconductor laser power adjustment.

[0005] A driver chip for a semiconductor laser, the driver chip comprising a package body, the package body being provided with an EN pin, a RST_N pin, a SCL pin, a SDA pin, a VFB pin, an I_LIMIT pin, an NTC pin, a PD+ pin, a PGND pin, a PH pin, a VIN pin, a BOOT pin, a VOUT pin, a VDD pin and a GND pin;

[0006] The package includes:

[0007] A power processing module, used for processing an input power signal, wherein the VIN pin, the BOOT pin, the PH pin, the VOUT pin and the VDD pin are all connected to the power processing module;

[0008] A signal processing module, connected to the power processing module, for transmitting and storing data, wherein the SCL pin, SDA pin, NTC pin, PGND pin and GND pin are all connected to the signal processing module;

[0009] APC module, the power processing module and the signal processing module are both connected to the APC module, the APC module is used to control the laser current and power to be constant, the VFB pin, the PD+ pin, and the I_LIMIT pin are all connected to the APC module;

[0010] The APC module includes an adjustable resistor RP1, a first MOS tube Q4, an operational amplifier OPA1, and a first comparator CMP1 and a second comparator CMP2;

[0011] The adjustable resistor RP1 realizes a resistance configuration of 0.75K-67.3K through the logic configuration of the signal processing module, and performs trans-impedance amplification on the photocurrent at the laser PD end. The product of the photocurrent reflected by the laser PD end and the set resistance value of the adjustable resistor network is used to obtain the reverse input terminal voltage of the operational amplifier OPA1. A constant reference voltage is input to the positive input terminal of the operational amplifier OPA1, and the first MOS tube Q4 is controlled by negative feedback regulation at the output terminal of the operational amplifier OPA1, so as to control the laser current and power to be constant. The first comparator CMP1 and the second comparator CMP2 are configured for power abnormality detection.

[0012] Further, specifically, the positive input terminal of the second comparator CMP2 is connected to the reference terminal VREF3, the negative input terminal and the output terminal of the second comparator CMP2 are both connected to the power processing module, the negative input terminal of the second comparator CMP2 is connected to the source of the first MOS tube Q4, and the source of the MOS is connected to the VFB pin;

[0013] The positive input terminal of the first comparator is connected to the signal processing module, the negative input terminal of the first comparator is connected to the drain of the first MOS transistor Q4, and the output terminal of the first comparator is connected to the gate of the first MOS transistor Q4 through a diode;

[0014] The positive input terminal of the operational amplifier is connected to the signal processing module, the negative input terminal of the operational amplifier is connected to the PD+ pin, and the output terminal of the operational amplifier is connected to the gate of the MOS tube;

[0015] The variable end of the adjustable resistor RP1 is connected to the signal processing module, and the fixed end of the adjustable resistor RP1 is connected to the PD+ pin;

[0016] The drain of the first MOS tube Q4 is also connected to the I_LIMIT pin.

[0017] Further, specifically, the signal processing module includes an IIC interface unit, a control logic unit, an oscillator, a temperature detection unit and a signal conversion unit;

[0018] The IIC interface unit, the oscillator, the temperature detection unit and the signal conversion unit are all connected to the control logic unit;

[0019] The IIC interface unit is also connected to the SCL pin and the SDA pin respectively;

[0020] The temperature detection unit is also connected to the NTC pin;

[0021] The signal conversion unit includes a first digital-to-analog converter DAC1 and a second digital-to-analog converter DAC2 , wherein the first digital-to-analog converter is connected to the first comparator CMP1 , and the second digital-to-analog converter is connected to the operational amplifier OPA1 .

[0022] Further, specifically, the power processing module includes a DC-DC power processing module, an LDO voltage stabilizing unit, a BUCK bootstrap unit, a second MOS tube Q1, a third comparator CMP3, a high-side driving circuit and a low-side driving circuit;

[0023] The DC-DC power processing module, the LDO voltage stabilizing unit and the source of the second MOS tube Q1 are all connected to the VIN pin;

[0024] The DC-DC power supply processing module, the high-side drive circuit, the low-side drive circuit and the APC module are all connected to the BUCK bootstrap unit;

[0025] The BUCK bootstrap unit is also connected to the VOUT pin;

[0026] The high-side driving circuit is connected to the BOOT pin, and a connection node between the high-side driving circuit and the low-side driving circuit is connected to the PH pin.

[0027] Further, specifically, the high-side driving circuit includes a high-side driver and a third MOS tube Q2, the BUCK bootstrap unit, the gate of the third MOS tube and the BOOT pin are all connected to the high-side driver, and the source of the third MOS tube is connected to the VIN pin.

[0028] Further, specifically, the low-side drive circuit includes a low-side driver and a fourth MOS tube Q3, the BUCK bootstrap unit and the gate of the fourth MOS tube Q3 are both connected to the low-side driver, the source of the fourth MOS tube Q3 is connected to the drain of the third MOS tube Q2, the connected node is connected to the PH pin, the drain of the fourth MOS tube Q3 is connected to the common ground terminal, and the common ground terminal is connected to the GND pin.

[0029] Further, specifically, the pin EN is connected to the pin VDD terminal through a first pull-up resistor, and the RST_N is connected to the pin VIN terminal through a second pull-up resistor.

[0030] A driving system for a semiconductor laser, comprising:

[0031] Semiconductor lasers;

[0032] and a driver chip for a semiconductor laser as described above;

[0033] The pin VFB is connected to the LD end of the semiconductor laser, and the pin PD+ is connected to the PD end of the semiconductor laser.

[0034] Further, specifically, the pin VIN is connected to a power input terminal;

[0035] A charging capacitor C2 is connected between the BOOT pin and the PH pin, the PH pin is also connected to one end of the inductor L2, the other end of the inductor is connected to one end of the capacitor C3, and after the connection, it is also connected to the VOUT pin, and the other end of the capacitor C3 is connected to the common ground terminal;

[0036] The I_LIMIT pin is connected to the resistor R1;

[0037] The NTC pin is connected to a thermistor.

[0038] A semiconductor laser, wherein the semiconductor laser adopts the driving chip for semiconductor laser according to any one of claims 1 to 7.

[0039] The beneficial effect of the present invention is that the driver chip for semiconductor lasers of the present invention can realize constant power output of the laser with maximum efficiency according to the characteristics of the LD of each semiconductor laser by maintaining constant power, and integrates multiple protection functions, which can meet the EN60825 laser safety specification, greatly improve the flexibility of LD power adjustment, and make the LD performance fully explored. Compared with the fixed constant power drive in the prior art, the internal structure of the chip is simple, and the customized design work is reduced. In addition, it is ensured that the optimal adjustment parameters are configured under the constant power of each LD, which greatly improves the reliability of LD application; the parameter configuration of the driver chip is also realized through the integrated signal processing module, and the signal processing module can also store the working parameters of the laser. In addition, the temperature of the driver chip is monitored and compensated in real time, and the working stability of the driver chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0041] Figure 1 It is a schematic diagram of the structure of the driver chip according to the first embodiment of the present invention.

[0042] Figure 2 It is a schematic diagram of the aged or mutated high voltage power abnormal protection waveform according to the first embodiment of the present invention.

[0043] Figure 3 It is a schematic diagram of abnormal power protection waveform when the negative electrode of the laser LD end is short-circuited to GND according to the first embodiment of the present invention.

[0044] Figure 4 This is a power-on timing diagram of the first embodiment of the present invention.

[0045] Figure 5 This is a power-off timing diagram of the first embodiment of the present invention.

[0046] Figure 6 This is a schematic diagram of 5V overvoltage detection according to the first embodiment of the present invention.

[0047] Figure 7 It is a schematic diagram of the transmission frame format for continuously writing N data bytes by the IIC according to the first embodiment of the present invention.

[0048] Figure 8 It is a waveform timing diagram of the IIC write register of the first embodiment of the present invention.

[0049] Fig. 9 It is a schematic diagram of the transmission frame format for continuously reading out N data bytes by the IIC according to the first embodiment of the present invention.

[0050] Fig.10 It is a schematic diagram of the adjustable resistor network structure of the first embodiment of the present invention.

[0051] Fig.11 This is a schematic diagram of the pins of the driver chip according to the first embodiment of the present invention.

[0052] Fig.12 It is a schematic diagram of the structure of the driving system of the second embodiment of the present invention.

[0053] Fig.13 It is a schematic diagram of the interior of a temperature detection unit according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0054] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0055] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0056] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] Example 1

[0058] The present application embodiment provides a driver chip for a semiconductor laser, such as Figure 1-11 As shown, the driver chip includes a package body, and the package body is provided with an EN pin, a RST_N pin, a SCL pin, a SDA pin, a VFB pin, an I_LIMIT pin, an NTC pin, a PD+ pin, a PGND pin, a PH pin, a VIN pin, a BOOT pin, a VOUT pin, a VDD pin and a GND pin;

[0059] The package includes:

[0060] A power processing module is used to process the input power signal. The VIN pin, BOOT pin, PH pin, VOUT pin and VDD pin are all connected to the power processing module.

[0061] The signal processing module is connected to the power processing module to transmit and store data. The SCL pin, SDA pin, NTC pin, PGND pin and GND pin are all connected to the signal processing module.

[0062] APC module, power processing module and signal processing module are all connected to the APC module. The APC module is used to control the laser current and power to be constant. The VFB pin, PD+ pin, and I_LIMIT pin are all connected to the APC module.

[0063] Among them, the APC module includes an adjustable resistor RP1, a first MOS tube Q4, an operational amplifier OPA1, and a first comparator CMP1 and a second comparator CMP2; the adjustable resistor RP1 realizes a resistance configuration of 0.75K-67.3K through the logic configuration of the signal processing module, and performs transimpedance amplification on the photocurrent at the laser PD end. The product of the reflected photocurrent at the laser PD end and the set resistance value of the adjustable resistor network is used to obtain the reverse input terminal voltage of the operational amplifier OPA1. A constant reference voltage is input to the positive input terminal of the operational amplifier OPA1, and the first MOS tube Q4 is controlled by negative feedback regulation at the output terminal of the operational amplifier OPA1, so as to control the laser current and power to be constant. The first comparator CMP1 and the second comparator CMP2 are configured for power anomaly detection.

[0064] Further, the positive input terminal of the second comparator CMP2 is connected to the reference terminal VREF3, the negative input terminal and the output terminal of the second comparator CMP2 are both connected to the power processing module, the negative input terminal of the second comparator CMP2 is connected to the source of the first MOS tube Q4, and the source of the MOS is connected to the VFB pin; the positive input terminal of the first comparator is connected to the signal processing module, the negative input terminal of the first comparator is connected to the drain of the first MOS tube Q4, and the output terminal of the first comparator is connected to the gate of the first MOS tube Q4 through a diode; the positive input terminal of the operational amplifier is connected to the signal processing module, the negative input terminal of the operational amplifier is connected to the PD+ pin, and the output terminal of the operational amplifier is connected to the gate of the MOS tube; the variable end of the adjustable resistor RP1 is connected to the signal processing module, and the fixed end of the adjustable resistor RP1 is connected to the PD+ pin; the drain of the first MOS tube Q4 is also connected to the I_LIMIT pin.

[0065] It should be noted that abnormal laser power includes the sudden increase in the current of the DCDC output-LD-MOS and the short circuit of the negative electrode of the laser LD end to GND due to laser aging or sudden high voltage.

[0066] When the current of DCDC output-LD-MOS suddenly increases due to laser aging or sudden high voltage, the first comparator CMP1 compares with the fixed reference VREF2 and flips, quickly pulling down the gate voltage of the first MOS tube Q4 to reduce power. When the power is reduced below the preset threshold, the first comparator CMP1 flips, stops pulling down the threshold of the first MOS tube Q4, and the current rises. Figure 2 As shown, the normal current at the laser LD end is about 100mA, and the preset threshold of the first comparator CMP1 is 150mA. If the current at the laser LD end suddenly increases and exceeds 150mA, the first comparator CMP1 will flip, so that the gate output of the first MOS tube Q4 is clamped at a limit value, which means that the current at the laser LD end is always limited to the vicinity of the preset threshold value until the LD current decreases to less than the current limiting threshold, and the output of the first comparator CMP1 returns to normal.

[0067] When the negative electrode of the laser LD terminal is short-circuited to GND, in order to meet the IEC 60825 safety standard, when the negative electrode of the laser LD terminal is short-circuited, the laser cannot continue to output high power. Therefore, the second comparator CMP2 is used for short-circuit monitoring. When the negative electrode of the laser LD terminal is grounded, the power processing module enters the hiccup mode. The second comparator CMP2 will shut down the voltage output of the power processing module at the moment it detects a short circuit, and will restart the power processing module after a few milliseconds. If the short circuit is still there, the power processing module will continue to be shut down for a few milliseconds. Figure 3 As shown in the figure, VREFSS is the internal reference of the chip (0.3V). When the chip detects that the pin VFB (pin VFB is connected to the negative terminal of the laser LD) is shorted to the ground, the hiccup mode is started, that is, the DCDC loop and the APC circuit are turned off, which lasts for about 8ms. When the timing is over, try to restart. If it is detected that the pin VFB is still in a short-circuit state, the power processing module and the APC module will continue to be turned off for about 8ms. This cycle is repeated until it is detected that the pin VFB is out of the short-circuit state, that is, it is restarted and the driver chip works normally.

[0068] In this embodiment, the power processing module includes a DC-DC power processing module, an LDO voltage stabilizing unit, a BUCK bootstrap unit, a second MOS tube Q1, a third comparator CMP3, a high-side drive circuit and a low-side drive circuit; the DC-DC power processing module, the LDO voltage stabilizing unit and the source of the second MOS tube Q1 are all connected to the VIN pin; the DC-DC power processing module, the high-side drive circuit, the low-side drive circuit and the APC module are all connected to the BUCK bootstrap unit; the BUCK bootstrap unit is also connected to the VOUT pin; the high-side drive circuit is connected to the BOOT pin, and the connection node of the high-side drive circuit and the low-side drive circuit is connected to the PH pin.

[0069] The DC-DC power processing module is used to convert the input power signal. The DC-DC is a synchronous rectifier dual N-type power tube buck regulator with adaptive on-time control. The input voltage range is 6V to 10V, and it can provide efficient and stable voltage output in a wide range of load applications. It can also implement a variety of protection circuits, such as load overcurrent protection, input undervoltage protection, VDD overvoltage protection, and output short circuit protection.

[0070] The BUCK bootstrap unit is to realize that in the synchronous driving of the high-side drive circuit and the low-side drive circuit, for the N-type high-voltage power MOSFET, the high-side power tube can be driven to achieve a more efficient output of the converted power signal. In the present embodiment, the high-side drive circuit includes a high-side driver and a third MOS tube Q2, the BUCK bootstrap unit, the gate of the third MOS tube and the BOOT pin are all connected to the high-side driver, and the source of the third MOS tube is connected to the VIN pin. The low-side drive circuit includes a low-side driver and a fourth MOS tube Q3, the BUCK bootstrap unit and the gate of the fourth MOS tube Q3 are all connected to the low-side driver, the source of the fourth MOS tube Q3 is connected to the drain of the third MOS tube Q2, the connected node is connected to the PH pin, the drain of the fourth MOS tube Q3 is connected to the common ground terminal, and the common ground terminal is connected to the GND pin. The third MOS tube Q2 and the fourth MOS tube Q3 are both N-type high-voltage power MOSFETs.

[0071] In order to facilitate signal modulation, the power processing module needs to be powered on quickly in tens of microseconds and start the laser LD end. The power-on speed of the DC-DC power processing module is limited due to inductance. The chip in the DC-DC power processing module integrates LDO, which can be powered on quickly and switch to the DC-DC power processing module for power supply after a period of time to ensure output efficiency. See the power-on timing for details. Figure 4As described above, after VIN is pulled high, LDO quickly charges the energy storage capacitor, and starts the signal processing module and APC module at the same time, so that the laser is controlled. After 20us, the output quickly rises to near the target value. After 80us, the LDO is turned off, and the power supply is taken over by the DC-DC power supply processing module, and the VFB pin voltage is pulled up to 300mV to achieve fast power-on of the APC module.

[0072] In order to ensure normal power-off and not damage the laser, the chip in the DC-DC power processing module integrates an undervoltage protection circuit, see Figure 5 As shown in the figure, when VIN drops and is lower than about 4.5V, the undervoltage comparator VINUVLO inside the chip will flip, triggering the shutdown of the APC module, and pulling down the gate voltage of the first MOS tube Q4 to shut it down, and then shutting down the DC-DC power supply processing module, temperature detection unit, control logic unit, and IIC interface unit through ENOFF. Since the APC module is shut down first and then the DCDC is shut down, the power-down laser will not burn out due to the APC circuit out of control, which improves the stability of the driver chip.

[0073] The reference voltages of the chips in the DC-DC power processing module are obtained by dividing the 5V voltage. In order to meet the safety test and ensure the normal response of the laser, see Figure 6 As shown, when the VDD pin level is forced to be pulled high, the chip will be forced to shut down, the laser will stop laser output, and VDD (5V) overvoltage detection will be realized, further improving the stability of the driver chip.

[0074] In this embodiment, the LDO voltage stabilizing unit is used to convert the input power supply signal into a 5V voltage output for powering the signal processing module.

[0075] In this embodiment, the signal processing module includes an IIC interface unit, a control logic unit, an oscillator, a temperature detection unit and a signal conversion unit; the IIC interface unit, the oscillator, the temperature detection unit and the signal conversion unit are all connected to the control logic unit; the IIC interface unit is also connected to the SCL pin and the SDA pin respectively; the temperature detection unit is also connected to the NTC pin; the signal conversion unit includes a first digital-to-analog converter DAC1 and a second digital-to-analog converter DAC2, the first digital-to-analog converter is connected to the first comparator CMP1, and the second digital-to-analog converter is connected to the operational amplifier OPA1.

[0076] The communication interface integrated in the IIC interface unit is a standard two-wire IIC interface, which is mainly used for reading and writing data between the driver chip and the outside world. The maximum communication rate supported is 200Kbps, which is used for reading and writing registers. Furthermore, the external debugging device is connected to the IIC interface unit through the SCL pin and the SDA pin. The device address of the external debugging device (slave) is strobed and controlled by the address signal of the analog end. This address can be modified through ECO, and the default value is 1100111. In order to ensure the effectiveness of signal transmission, the SCL pin and the SDA pin need to be connected to a 4.7kΩ pull-up resistor in actual use.

[0077] Furthermore, the waveform timing of IIC writing register is as follows Figure 8 As shown, a complete IIC write register transfer includes the following steps:

[0078] S11, when the host detects that the bus is in the "idle state" (that is, the SDA and SCL lines are both high), it sends a start signal "S" to start a communication transmission;

[0079] S12, the host then sends a command byte. This byte consists of a 7-bit slave device address and a 1-bit read / write control bit R / W (R / W = 0 during write transmission);

[0080] S13, after receiving the command byte, the corresponding slave device feeds back an acknowledgement signal ACK (ACK=0) to the host;

[0081] S14, after receiving the response signal from the slave, the host starts to send the register address byte data ADDR0;

[0082] S15 slave returns an ACK signal after receiving the address data;

[0083] S16, after receiving the response signal from the slave, the host starts to send the first byte of data DATA0;

[0084] S17, after receiving the data, the slave returns an ACK signal;

[0085] S18, the host sends the next data byte after receiving the response signal;

[0086] S19, when the host sends the last data byte and receives the ACK response signal from the slave, it ends the communication and releases the bus by sending a stop signal P to the slave. The slave exits the communication with the host after receiving the signal P. It should be noted that the host establishes a communication relationship with the corresponding slave by sending the slave address, and the other slaves connected to the bus exit the communication with the host because their addresses do not match their own. After each byte sent by the host, it needs to understand the reception status of the slave through the ACK response signal of the slave. If the response is wrong, the host should resend the data to ensure the effective transmission of signals between the host and the slave.

[0087] The IIC interface unit supports auto-increment read and write operations. The transmission frame format for IIC to continuously write N registers is shown in Figure 7 As shown, data byte 0 represents the data written to the register corresponding to address byte ADDR0, and when N>1, data byte i represents the data written to register ADDR0+i. The gray blocks in the figure represent the signals sent by the host to the slave, and the white blocks represent the signals sent by the slave to the host.

[0088] Referring to the waveform timing of the IIC write register shown in the figure, a complete IIC read register transfer operation includes a write transfer and a read transfer, including the following steps:

[0089] S21, after the host sends the start signal S, it then sends the command byte, at this time the read / write control bit R / W in the command byte is 0;

[0090] S22, after receiving the command byte, the slave feeds back an acknowledgement signal ACK (ACK=0) to the host;

[0091] S23, after receiving the response signal from the slave, the host starts to send the address byte data ADDR0 of the register to be read;

[0092] S24, after receiving the address data, the slave returns an ACK signal. After receiving the ACK signal, the host resends a start signal S and a command word for a read operation (R / W=1).

[0093] S25, the slave receives the command and returns an ACK signal, and at the same time sends the data in the internal register address ADDR0 to the host. After receiving the data, the host feeds back an ACK signal to the slave;

[0094] S26, after receiving the response signal, the slave sends the data in the next self-incrementing address ADDR1 to the host;

[0095] S27, after receiving the data, the host returns a non-acknowledgement signal NACK (ACK=1) to the slave;

[0096] S28, after receiving the non-response signal from the host, the slave stops transmitting data and releases the bus;

[0097] S29, the host sends a stop signal P to release the bus and end the communication.

[0098] The transmission frame format of IIC reading N registers is as follows Fig. 9 As shown, data byte 0 represents the data read from the register corresponding to address byte ADDR0, and when N>1, data byte i represents the data read from register ADDR0+i. The gray blocks in the figure represent the signals sent by the host to the slave, and the white blocks represent the signals sent by the slave to the host.

[0099] In this embodiment, the control logic unit is used to carry out data transfer and programming of the MTP and Fuse in the chip;

[0100] The processing chip of the control logic unit has a built-in MTP memory (EEPROM with a capacity of 32×8 bits), and the main stored data includes the configuration bytes of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, the temperature range compensation bytes of the adjustable resistor RP1, the temperature compensation range threshold bytes, and the analog reserved high and low level bytes. After power-on reset, the processing chip waits for a 10ms delay, automatically executes the MTP reading logic, quickly reads the corresponding data from the MTP storage, and transmits the configuration bytes of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2; at the same time, the temperature range compensation bytes and the temperature compensation range threshold bytes are sent to the temperature detection unit.

[0101] The processing chip of the control logic unit also includes a fuse unit, which mainly stores data including the coarse adjustment and fine adjustment bytes of the adjustable resistor. Under default conditions, the 12 fuses are not blown, and the level output to the digital end is 0. <11> Corresponding to the coarse adjustment byte REG_CON1[7] of the adjustable resistor, Fuse<10:5> corresponds to the coarse adjustment byte REG_CON1[5:0] of the adjustable resistor, and Fuse<4:0> corresponds to the fine adjustment byte REG_CON0[4:0] of the adjustable resistor. After power-on reset, the processing chip immediately reads the data byte in the fuse Fuse. The coarse adjustment and fine adjustment byte data of the adjustable resistor network are XOR-ed with the initial value ANA_TRIM (default all 0, TRIM is available) of the analog input, and immediately sent to the decoder to select and configure the adjustable resistor network.

[0102] In this embodiment, since the default values ​​of the first digital-to-analog converter DAC1, the second digital-to-analog converter DAC2, and the adjustable resistor RP1 may not meet the actual requirements, corresponding configuration can be performed through the IIC interface unit. During configuration, the TRIM_EN register is first set to switch the processing chip to TRIM mode, and then the configuration results of the DAC and resistor of the processing chip will be responded to in real time. The configuration of DAC and resistor includes the configuration of the first digital-to-analog converter DAC1, the second digital-to-analog converter DAC2, and the adjustable resistor RP1.

[0103] In TRIM mode, adjust the register until it meets the requirements, and then the current DAC and resistor configuration parameters can be written to the corresponding MTP interval or Fuse. MTP is burned by setting the register TRIM_PGM (this register automatically resets) through the IIC interface unit. After waiting for 400ms, the processing chip is soft reset or powered on again, and then the processing chip control logic automatically reads the adjusted value from the MTP storage. In TRIM mode, the Fuse is burned by setting the register TRIM_FUSE (this register automatically resets) through the IIC interface unit. The blowing time of a fuse requires at least 50ms, so you need to wait at least 50ms after each setting of the register TRIM_FUSE. A total of 12 IIC instructions need to be sent, and the circuit will burn 12 fuses in turn. After all the fuses are burned, reset or power on the processing chip again, and then the processing chip control logic automatically reads the adjusted value from the Fuse to adjust the adjustable resistor.

[0104] Further, such as Fig.10 As shown, the adjustable resistor network can adjust the power of the circuit output, and the network mainly includes three control bytes.

[0105] Coarse adjustment byte Con_1: TRIM control is performed by register REG_CON1. ​​The initial value is determined by the XOR of the Fuse unit and ANA_TRIM data. The default value is 0x00. The highest bit Con_1[7] indicates shifting. The low bit Con_1[5:0] controls 64 switches. Each switch changes 1K ohm resistance.

[0106] Fine adjustment byte Con_0: TRIM control is performed by register REG_CON0, the initial value is determined by the XOR of Fuse and ANA_TRIM data, and the default value is 0x00. The low bit Con_0[4:0] controls 32 switches, each switch changes 50 ohm resistance;

[0107] Temperature compensation byte Con_2: TRIM control is performed by register REG_CON2_Tx (x=0~4), the initial value is determined by MTP data, and the default value is 0x00. Temperature compensation is divided into 5 sections, which are set by temperature sampling, and the compensation amount requires experimental parameters. Each temperature range corresponds to a temperature compensation byte Con_2, and each compensation byte Con_2 contains 32 gears, and the resistance change of each gear is 2K ohms. For example, the temperature detection unit detects the temperature change and changes the value of the resistor network, so as to balance the output power in different temperature ranges. The temperature compensation function is controlled by the register TEMPER_EN. The temperature compensation is not turned on by default in the processing chip. The register can be configured through the IIC interface unit and burned into the MTP to realize the automatic turning on of the temperature compensation function after the processing chip is powered on.

[0108] In this embodiment, when the register ENCRYPT is enabled through the IIC interface unit, the processing chip will turn on the encryption function. The processing chip will automatically write the current values ​​of each register including the register ENCRYPT into the MTP memory. In encryption mode, the processing chip disables the read and write instructions of the IIC interface unit to addresses 00h to 16h (the write instruction is invalid, and the data returned in the read instruction is all 0), and retains the MTP erase instruction corresponding to address 17h to implement register storage value encryption. After reset or power-on again, the encryption function will be automatically turned on. When the register MTP_ERASE is enabled through the IIC interface unit, the processing chip will erase the MTP memory, and the MTP memory will be completely erased to 0. The chip will turn off the encryption function and restore the read and write instructions of the IIC interface unit to all addresses. After reset or power-on again, the chip automatically turns off the encryption function.

[0109] In this embodiment, the clock of the control logic unit is provided by an oscillator, and the clock frequency is 2 MHz.

[0110] In this embodiment, the pin EN is connected to the pin VDD through a first pull-up resistor, and the pin RST_N is connected to the pin VIN through a second pull-up resistor.

[0111] Example 2

[0112] A drive system for a semiconductor laser, such as Fig.12 As shown, it includes: a semiconductor laser and a driving chip for the semiconductor laser as above; a pin VFB is connected to the LD end of the semiconductor laser, and a pin PD+ is connected to the PD end of the semiconductor laser.

[0113] In this embodiment, the pin VIN is connected to the power input terminal; the charging capacitor C2 is connected between the BOOT pin and the PH pin, the PH pin is also connected to one end of the inductor L2, the other end of the inductor is connected to one end of the capacitor C3, and after the connection, it is also connected to the VOUT pin, and the other end of the capacitor C3 is connected to the common ground terminal; the I_LIMIT pin is connected to the resistor R1, and the NTC pin is connected to the thermistor.

[0114] Among them, resistor R1 is a current limiting resistor, and the temperature change is reflected by the ratio of NTC and fixed value resistor, see Fig.13 As shown, the temperature detection unit consists of four comparators, each of which can set an independent threshold value to divide the temperature into five intervals. The initial value of the temperature interval threshold is determined by the data stored in the MTP memory, and the TRIM setting is controlled by registers REG_TH_T0~REG_TH_T4. After the main control logic completes the transfer of MTP data, the temperature interval compensation byte and the temperature compensation interval threshold byte data of the adjustable resistor are sent to the temperature detection unit, and the temperature detection and compensation logic is started after waiting for 1ms. According to the output of the four comparators and the corresponding relationship between the temperature intervals, the temperature detection compensation module obtains the current temperature interval Tn, and decodes the preset adjustable resistor compensation byte REG_CON2_Tn in the interval and gives it to the temperature compensation selection branch of the adjustable resistor network.

[0115] Example 3

[0116] A semiconductor laser adopts the above driving chip for semiconductor laser.

[0117] In summary, the driver chip, the drive system and the semiconductor laser of the present invention for semiconductor lasers can achieve constant power output of the laser with maximum efficiency according to the characteristics of the LD of each semiconductor laser by maintaining constant power, and integrate multiple protection functions, which can meet the EN60825 laser safety specification, greatly improve the flexibility of LD power adjustment, and make the LD performance fully explored. Compared with the fixed constant power drive in the prior art, the internal structure of the chip is simple, and the customized design work is reduced. In addition, it is ensured that the optimal adjustment parameters are configured under the constant power of each LD, which greatly improves the reliability of LD application; the parameter configuration of the driver chip is also realized through the integrated signal processing module, and the signal processing module can also store the working parameters of the laser. In addition, the temperature of the driver chip is monitored and compensated in real time to improve the working stability of the driver chip.

[0118] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A driver chip for a semiconductor laser, characterized in that: The driver chip includes a package body, and the package body is provided with an EN pin, a RST_N pin, a SCL pin, a SDA pin, a VFB pin, an I_LIMIT pin, an NTC pin, a PD+ pin, a PGND pin, a PH pin, a VIN pin, a BOOT pin, a VOUT pin, a VDD pin and a GND pin; The package includes: A power processing module, used for processing an input power signal, wherein the VIN pin, the BOOT pin, the PH pin, the VOUT pin and the VDD pin are all connected to the power processing module; A signal processing module, connected to the power processing module, for transmitting and storing data, wherein the SCL pin, SDA pin, NTC pin, PGND pin and GND pin are all connected to the signal processing module; APC module, the power processing module and the signal processing module are both connected to the APC module, the APC module is used to control the laser current and power to be constant, the VFB pin, the PD+ pin, and the I_LIMIT pin are all connected to the APC module; The APC module includes an adjustable resistor RP1, a first MOS tube Q4, an operational amplifier OPA1, and a first comparator CMP1 and a second comparator CMP2; The adjustable resistor RP1 realizes a resistance configuration of 0.75K-67.3K through the logic configuration of the signal processing module, and performs trans-impedance amplification on the photocurrent at the laser PD end. The product of the photocurrent reflected by the laser PD end and the set resistance value of the adjustable resistor network is used to obtain the reverse input terminal voltage of the operational amplifier OPA1. A constant reference voltage is input to the positive input terminal of the operational amplifier OPA1, and the first MOS tube Q4 is controlled by negative feedback regulation at the output terminal of the operational amplifier OPA1, so as to control the laser current and power to be constant. The first comparator CMP1 and the second comparator CMP2 are configured for power abnormality detection.

2. The driver chip for a semiconductor laser as claimed in claim 1, characterized in that: The positive input terminal of the second comparator CMP2 is connected to the reference terminal VREF3, the negative input terminal and the output terminal of the second comparator CMP2 are both connected to the power processing module, the negative input terminal of the second comparator CMP2 is connected to the source of the first MOS tube Q4, and the source of the MOS is connected to the VFB pin; The positive input terminal of the first comparator is connected to the signal processing module, the negative input terminal of the first comparator is connected to the drain of the first MOS transistor Q4, and the output terminal of the first comparator is connected to the gate of the first MOS transistor Q4 through a diode; The positive input terminal of the operational amplifier is connected to the signal processing module, the negative input terminal of the operational amplifier is connected to the PD+ pin, and the output terminal of the operational amplifier is connected to the gate of the MOS tube; The variable end of the adjustable resistor RP1 is connected to the signal processing module, and the fixed end of the adjustable resistor RP1 is connected to the PD+ pin; The drain of the first MOS tube Q4 is also connected to the I_LIMIT pin.

3. The driver chip for a semiconductor laser as claimed in claim 1, characterized in that: The signal processing module includes an IIC interface unit, a control logic unit, an oscillator, a temperature detection unit and a signal conversion unit; The IIC interface unit, the oscillator, the temperature detection unit and the signal conversion unit are all connected to the control logic unit; The IIC interface unit is also connected to the SCL pin and the SDA pin respectively; The temperature detection unit is also connected to the NTC pin; The signal conversion unit includes a first digital-to-analog converter DAC1 and a second digital-to-analog converter DAC2 , wherein the first digital-to-analog converter is connected to the first comparator CMP1 , and the second digital-to-analog converter is connected to the operational amplifier OPA1 .

4. The driver chip for a semiconductor laser as claimed in claim 1, characterized in that: The power processing module includes a DC-DC power processing module, an LDO voltage stabilization unit, a BUCK bootstrap unit, a second MOS tube Q1, a third comparator CMP3, a high-side drive circuit and a low-side drive circuit; The DC-DC power processing module, the LDO voltage stabilizing unit and the source of the second MOS tube Q1 are all connected to the VIN pin; The DC-DC power supply processing module, the high-side drive circuit, the low-side drive circuit and the APC module are all connected to the BUCK bootstrap unit; The BUCK bootstrap unit is also connected to the VOUT pin; The high-side driving circuit is connected to the BOOT pin, and a connection node between the high-side driving circuit and the low-side driving circuit is connected to the PH pin.

5. The driving chip for a semiconductor laser as claimed in claim 4, characterized in that: The high-side driving circuit includes a high-side driver and a third MOS tube Q2, the BUCK bootstrap unit, the gate of the third MOS tube and the BOOT pin are all connected to the high-side driver, and the source of the third MOS tube is connected to the VIN pin.

6. The driving chip for a semiconductor laser as claimed in claim 5, characterized in that: The low-side driving circuit includes a low-side driver and a fourth MOS tube Q3, the BUCK bootstrap unit and the gate of the fourth MOS tube Q3 are both connected to the low-side driver, the source of the fourth MOS tube Q3 is connected to the drain of the third MOS tube Q2, the connected node is connected to the PH pin, the drain of the fourth MOS tube Q3 is connected to the common ground terminal, and the common ground terminal is connected to the GND pin.

7. The driving chip for a semiconductor laser as claimed in claim 1, characterized in that: The pin EN is connected to the pin VDD through a first pull-up resistor, and the RST_N is connected to the pin VIN through a second pull-up resistor.

8. A driving system for a semiconductor laser, characterized in that: include: Semiconductor lasers; And a driver chip for a semiconductor laser according to any one of claims 1 to 7; The pin VFB is connected to the LD end of the semiconductor laser, and the pin PD+ is connected to the PD end of the semiconductor laser.

9. A driving system for a semiconductor laser as claimed in claim 8, characterized in that: The pin VIN is connected to the power input terminal; A charging capacitor C2 is connected between the BOOT pin and the PH pin, the PH pin is also connected to one end of the inductor L2, the other end of the inductor is connected to one end of the capacitor C3, and after the connection, it is also connected to the VOUT pin, and the other end of the capacitor C3 is connected to the common ground; The I_LIMIT pin is connected to the resistor R1; The NTC pin is connected to a thermistor.

10. A semiconductor laser, characterized in that: The semiconductor laser uses the driver chip for a semiconductor laser according to any one of claims 1 to 7.

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