A low ripple overcurrent protection circuit

Abstract

The present invention relates to the field of integrated circuit technology, and provides an overcurrent protection circuit with low ripple protection, comprising: a power supply, a bias circuit, a comparator circuit, a Schmitt circuit, and a driver circuit; the power supply is electrically connected to the bias circuit, the comparator circuit, the Schmitt circuit, and the driver circuit, respectively; the input end of the bias circuit is connected to the power supply, the output end of the bias circuit is connected to the input end of the comparator circuit, and is used to provide a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmitt circuit, the output end of the Schmitt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to a load. The overcurrent protection circuit with low ripple protection of the present invention avoids false triggering of overcurrent protection, improves the overcurrent protection function of the CMOS circuit, and further improves user experience and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an overcurrent protection circuit capable of preventing low ripple. Background Art

[0002] With the continuous advancement of science and technology and the popularization of electronic products, power semiconductor chips play a vital role in the electronics industry. The acceptable overcurrent short-circuit time of commonly used power semiconductors is extremely short, only within microseconds or nanoseconds. If the power semiconductor chip cannot disconnect the power supply in time within the acceptable overcurrent short-circuit time, it will cause damage to the power semiconductor chip.

[0003] Driven by the rapid evolution of large-scale integrated circuits (SMICs), portable electronic products are rapidly proliferating and entering people's lives at an astonishing rate. Overcurrent protection is crucial in power management chips. While the basic circuitry of overcurrent protection circuits was relatively simple in the past, practical applications can be susceptible to ripple issues, leading to false triggering.

[0004] However, when using electronic devices, especially outdoors, the power management chip mentioned above is subject to many influencing factors, such as false triggering of overcurrent protection, which makes the chip's overcurrent protection unable to resist the bottom ripple function, affecting the product user experience and poor reliability. Summary of the Invention

[0005] The present invention provides an overcurrent protection circuit with low ripple protection, aiming to solve the problems of poor reliability and poor user experience of existing semiconductor chips.

[0006] An embodiment of the present invention provides an overcurrent protection circuit with low ripple protection, comprising: a power supply, a bias circuit, a comparator circuit, a Schmitt circuit, and a driver circuit; the power supply is electrically connected to the bias circuit, the comparator circuit, the Schmitt circuit, and the driver circuit, respectively;

[0007] The input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is connected to the input end of the comparator circuit, for providing a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmitt circuit, the output end of the Schmitt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to a load;

[0008] The Schmitt circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor and a second resistor;

[0009] The source of the first PMOS transistor is connected to the power supply, the gate of the first PMOS transistor is respectively connected to the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor and serves as the input end of the Schmitt circuit, the drain of the first PMOS transistor is respectively connected to the source of the second PMOS transistor and the source of the third PMOS transistor, the drain of the third PMOS transistor is connected to the first end of the first resistor, and the second end of the first resistor is grounded; the drain of the second PMOS transistor is respectively connected to the drain of the first NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor;

[0010] The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the source of the third NMOS transistor respectively, and the source of the second NMOS transistor is grounded; the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor, the drain of the third NMOS transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded;

[0011] The source of the fourth PMOS tube is connected to the power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the Schmitt circuit; the source of the fourth NMOS tube is grounded.

[0012] Preferably, the bias circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third resistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor;

[0013] The source of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor, and is also connected to the power supply; the gate of the fifth PMOS transistor is connected to the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor and the drain of the sixth PMOS transistor;

[0014] The drain of the fifth PMOS transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the gate of the eighth PMOS transistor and the drain of the seventh NMOS transistor respectively; the drain of the eighth PMOS transistor is connected to the source of the seventh NMOS transistor and is grounded; the source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor and the drain of the fifth NMOS transistor respectively; the source of the fifth NMOS transistor is grounded;

[0015] The gate of the fifth NMOS tube is connected to the gate of the seventh NMOS tube and the gate of the sixth NMOS tube respectively; the drain of the sixth NMOS tube is connected to the gate of the sixth NMOS tube and the drain of the seventh PMOS tube respectively; the source of the sixth NMOS tube is grounded.

[0016] Preferably, the comparator circuit includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a fourth resistor, a fifth resistor, a first diode, a seventh NMOS transistor, and an eighth NMOS transistor;

[0017] The source of the ninth PMOS transistor and the source of the twelfth PMOS transistor are connected and connected to the power supply; the gate of the ninth PMOS transistor and the gate of the twelfth PMOS transistor are used to receive the bias voltage output by the bias circuit; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor respectively;

[0018] The gate of the tenth PMOS transistor is connected to the bias voltage of the bias circuit; the drain of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is respectively connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor, and the source of the seventh NMOS transistor is grounded;

[0019] The gate of the eleventh PMOS transistor is connected to the first end of the fourth resistor and the first end of the fifth resistor respectively, and the second end of the fourth resistor is connected to the drain of the twelfth PMOS transistor; the drain of the twelfth PMOS transistor is also connected to the cathode of the first diode, and the anode of the first diode is grounded;

[0020] The second end of the fifth resistor is grounded; the drain of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor and serves as the output end of the comparator circuit;

[0021] The source of the eighth NMOS transistor is grounded.

[0022] Preferably, the driver circuit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor;

[0023] The source of the thirteenth PMOS transistor is connected to the power supply, and the drain of the thirteenth PMOS transistor is respectively connected to the source of the fourteenth PMOS transistor, the source of the fifteenth PMOS transistor, and the source of the sixteenth PMOS transistor; the gate of the thirteenth PMOS transistor is connected to the gate of the fourteenth PMOS transistor, and the drain of the fourteenth PMOS transistor is respectively connected to the gate of the fifteenth PMOS transistor, the drain of the ninth NMOS transistor, and the gate of the tenth NMOS transistor; the gate of the ninth NMOS transistor serves as the input end of the driver circuit, and the source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor and the source of the eleventh NMOS transistor and is grounded;

[0024] The drain of the fifteenth PMOS tube is respectively connected to the drain of the tenth NMOS tube, the gate of the sixteenth PMOS tube and the gate of the eleventh NMOS tube; the drain of the sixteenth PMOS tube is connected to the drain of the eleventh NMOS tube and serves as the output end of the driver circuit.

[0025] Compared with the prior art, the beneficial effect of the present invention lies in that the power supply is electrically connected to the bias circuit, the comparator circuit, the Schmitt circuit and the driver circuit respectively; the input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is connected to the input end of the comparator circuit to provide a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmitt circuit, the output end of the Schmitt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to the load; by electrically connecting the bias circuit, the comparator circuit, the Schmitt circuit and the driver circuit in sequence, the current output by the comparator circuit is processed by the Schmitt circuit, so as to avoid false triggering of overcurrent protection, improve the overcurrent protection function of the CMOS circuit, and further improve user experience and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0027] Figure 1 1 is a circuit diagram of an overcurrent protection circuit for low ripple protection provided by an embodiment of the present invention;

[0028] Figure 2 is a circuit diagram of a bias circuit provided in an embodiment of the present invention;

[0029] Figure 3 is a circuit diagram of a comparator circuit provided by an embodiment of the present invention;

[0030] Figure 4 is a circuit diagram of a Schmitt circuit and a driver circuit provided by an embodiment of the present invention;

[0031] Figure 5 Schematic diagram of overcurrent protection effect of falsely triggered overcurrent voltage provided by an embodiment of the present invention;

[0032] Figure 6 Schematic diagram of the effect of the overcurrent protection voltage provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] Combined with attachment Figures 1-6 As shown, an embodiment of the present invention provides an overcurrent protection circuit with low ripple protection, including: a power supply VDD, a bias circuit 1, a comparator circuit 2, a Schmitt circuit 3 and a driver circuit 4; the power supply VDD is electrically connected to the bias circuit 1, the comparator circuit 2, the Schmitt circuit 3 and the driver circuit 4 respectively.

[0035] The input end of the bias circuit 1 is connected to the power supply VDD, and the output end of the bias circuit 1 is connected to the input end of the comparator circuit 2, for providing a bias voltage for the comparator circuit 2; the output end of the comparator circuit 2 is connected to the input end of the Schmitt circuit 3, the output end of the Schmitt circuit 3 is connected to the input end of the driver circuit 4, and the output end of the driver circuit 4 is connected to a load; by electrically connecting the power supply VDD to the bias circuit 1, the comparator circuit 2, the Schmitt circuit 3 and the driver circuit 4 respectively; the input end of the bias circuit 1 is connected to the power supply VDD, The output end of the bias circuit 1 is connected to the input end of the comparator circuit 2 to provide a bias voltage for the comparator circuit 2; the output end of the comparator circuit is connected to the input end of the Schmitt circuit 3, the output end of the Schmitt circuit 3 is connected to the input end of the driver circuit 4, and the output end of the driver circuit 4 is connected to the load; through the bias circuit 1, comparator circuit 2, Schmitt circuit 3 and driver circuit 4 electrically connected in sequence, the current output by the comparator circuit 2 is processed by the Schmitt circuit 3 to avoid false triggering of the overcurrent protection, improve the overcurrent protection function of the CMOS circuit, and further improve the user experience and reliability.

[0036] Specifically, the Schmitt circuit 3 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first resistor R1, and a second resistor R2. The source of the first PMOS transistor M1 is connected to the power supply VDD, the gate of the first PMOS transistor M1 is respectively connected to the gate of the second PMOS transistor M2, the gate of the first NMOS transistor N1, and the gate of the second NMOS transistor N2, and serves as the input end of the Schmitt circuit 3. The drain of the first PMOS transistor M1 is respectively connected to the source of the second PMOS transistor M2 and the source of the third PMOS transistor M3. The drain of the third PMOS transistor M3 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded. The drain of the second PMOS transistor M2 is respectively connected to the drain of the first NMOS transistor N1, the gate of the fourth PMOS transistor M4, and the gate of the fourth NMOS transistor N4.

[0037] The source of the first NMOS transistor N1 is respectively connected to the drain of the second NMOS transistor N2 and the source of the third NMOS transistor N3, and the source of the second NMOS transistor N2 is grounded; the gate of the third NMOS transistor N3 is connected to the gate of the third PMOS transistor M3, the drain of the third NMOS transistor N3 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0038] The source of the fourth PMOS transistor M4 is connected to the power supply VDD, the drain of the fourth PMOS transistor M4 is connected to the drain of the fourth NMOS transistor N4 and serves as the output end of the Schmitt circuit 3; the source of the fourth NMOS transistor N4 is grounded.

[0039] Specifically, in order to prevent the output signal from being affected by noise and other signal clutter;

[0040] VTH+ is mainly affected by the width-to-length ratio of the NMOS tube;

[0041] VTH- is mainly affected by the width-to-length ratio of the PMOS tube;

[0042] The effect of the MOS tube width-to-length ratio on the threshold voltage gradually decreases as the ratio increases;

[0043] The change in the width-to-length ratio of the fourth PMOS transistor M4 and the first NMOS transistor N1 has minimal effect on the threshold voltage, which remains essentially unchanged. Increasing the width-to-length ratio of the first NMOS transistor N1 slightly increases the positive threshold voltage; increasing the width-to-length ratio of the fourth PMOS transistor M4 slightly decreases the negative threshold voltage. M4 and N1 act as the turning point for the positive-to-negative threshold voltage reversal (similar to the effect of a switch).

[0044] In the six-transistor Schmitt circuit 3, the negative threshold voltage is mainly affected by M1 / M3, and the positive threshold voltage is mainly affected by N2 / N3.

[0045] To increase / decrease the threshold voltage:

[0046] By increasing / decreasing the width-to-length ratio of the first PMOS tube M1 or decreasing / increasing the width-to-length ratio of the third PMOS tube M3;

[0047] If the width-to-length ratios of the first PMOS transistor M1 and the third PMOS transistor M3 are changed at the same time, the increase / decrease range of the width-to-length ratio of the first PMOS transistor M1 must be greater than / less than the decrease / increase range of the width-to-length ratio of the third PMOS transistor M3.

[0048] To increase / decrease the positive threshold voltage while keeping the negative threshold voltage unchanged:

[0049] By increasing / decreasing the width-to-length ratio of the third NMOS tube N3;

[0050] On the premise that the positive threshold voltage rises / falls and the negative threshold voltage remains unchanged, the width-to-length ratio of the third PMOS transistor M3 is increased / decreased until the negative threshold voltage falls / rises to the initial value.

[0051] To decrease / increase the negative threshold voltage while keeping the positive threshold voltage unchanged:

[0052] Increase / decrease the width-to-length ratio of the third PMOS tube M3;

[0053] Under the above premise, the width-to-length ratio of the third NMOS transistor N3 is increased / decreased until the forward threshold voltage rises / falls to the initial value.

[0054] In this embodiment, the bias circuit 1 includes a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a third resistor R3, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;

[0055] The source of the fifth PMOS transistor M5 is connected to the source of the sixth PMOS transistor M6 and the source of the seventh PMOS transistor M7, respectively, and is connected to the power supply VDD; the gate of the fifth PMOS transistor M5 is connected to the gate of the fifth PMOS transistor M5, and the gate of the sixth PMOS transistor M6 is connected to the gate of the seventh PMOS transistor M7 and the drain of the sixth PMOS transistor M6, respectively;

[0056] The drain of the fifth PMOS transistor M5 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the gate of the eighth PMOS transistor M8 and the drain of the seventh NMOS transistor N7 respectively; the drain of the eighth PMOS transistor M8 is connected to the source of the seventh NMOS transistor N7 and is grounded; the source of the eighth PMOS transistor M8 is connected to the drain of the sixth PMOS transistor M6 and the drain of the fifth NMOS transistor N5 respectively; the source of the fifth NMOS transistor N5 is grounded;

[0057] The gate of the fifth NMOS transistor N5 is connected to the gate of the seventh NMOS transistor N7 and the gate of the sixth NMOS transistor N6 respectively; the drain of the sixth NMOS transistor N6 is connected to the gate of the sixth NMOS transistor N6 and the drain of the seventh PMOS transistor M7 respectively; the source of the sixth NMOS transistor N6 is grounded.

[0058] Specifically, the bias voltage VB output by the bias circuit 1 is generated by a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7; a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a third resistor R3. The fifth PMOS transistor M5 and the third resistor R3 act as a branch voltage divider, while the sixth PMOS transistor M6 and the seventh PMOS transistor M7 form a current mirror. The fifth NMOS transistor N5 and the sixth NMOS transistor N6 also form a current mirror.

[0059] The sixth PMOS transistor M6 and the sixth NMOS transistor N6 are diode-connected, and when they are turned on, they are in saturation state. As shown in the formula Vds>Vgs-Vth(1);

[0060] Vds drain-source voltage, vgs gate-source voltage, vth threshold voltage.

[0061]

[0062] I is the drain-source current, μn is the electron mobility, which reflects the speed at which electrons move in the semiconductor. Cox is the capacitance of the gate oxide layer. W is the channel width. L is the channel length.

[0063] VGS is the voltage between the gate and the source. Vth is the threshold voltage of the MOS tube.

[0064] Since the sixth PMOS transistor M6 and the seventh PMOS transistor M7, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are current mirrors, the current between them is the width-to-length ratio.

[0065]

[0066] IDS2, IDS3 is the drain-source current, and W / L is the width-to-length ratio of mos2 and mos3.

[0067] The seventh PMOS transistor M7 and the fifth NMOS transistor N5 are in the linear region;

[0068]

[0069] I is the drain-source current, μn is the electron mobility, which reflects the speed at which electrons move in the semiconductor.

[0070] Cox is the capacitance of the gate oxide. W is the width of the channel. L is the length of the channel.

[0071] VGS is the voltage between the gate and the source. Vth is the threshold voltage of the MOS tube, λ is the channel length modulation parameter, and VDS is the voltage from the drain to the source.

[0072] Adjust I by aspect ratio DS2 =I DS3 , that is, the currents in each branch are equal. The bias voltage VB can be adjusted by adjusting the width-to-length ratio of the sixth NMOS transistor N6 and the seventh PMOS transistor M7.

[0073] The sixth NMOS transistor N6 is in saturation state. Due to the stable current, the width-to-length ratio is increased, and V GS The gate voltage of the sixth NMOS transistor N6 decreases. The fifth NMOS transistor N5 is in the linear region, the current is equal, and the width-to-length ratio does not change. The fifth NMOS transistor N5 and the sixth NMOS transistor N6 are interconnected with the common gate. As the V GS N5 decreases, V DS As N5 increases, the voltage of VB increases.

[0074] The seventh PMOS tube M7 is a linear region, which increases the width-to-length ratio, V DS M7 increases, V GS As the gate voltage of N7 increases, the fifth NMOS tube N5 is in the linear region, the current is equal, and the width-to-length ratio does not change. The fifth NMOS tube N5 and the sixth NMOS tube N6 are interconnected with the common gate. As the V GS N5 increases, V DS As N5 decreases, VB both increases and decreases.

[0075] In this embodiment, the comparator circuit 2 includes a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a fourth resistor R4, a fifth resistor R5, a first diode D1, a seventh NMOS transistor N7, and an eighth NMOS transistor N8.

[0076] The source of the ninth PMOS transistor M9 and the source of the twelfth PMOS transistor M12 are connected to the power supply VDD; the gate of the ninth PMOS transistor M9 and the gate of the twelfth PMOS transistor M12 are used to receive the bias voltage output by the bias circuit 1; the drain of the ninth PMOS transistor M9 is connected to the source of the tenth PMOS transistor M10 and the source of the eleventh PMOS transistor M11, respectively.

[0077] The gate of the tenth PMOS transistor M10 is connected to the bias voltage of the bias circuit 1; the drain of the tenth PMOS transistor M10 is connected to the drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7 is respectively connected to the drain of the seventh NMOS transistor N7 and the gate of the eighth NMOS transistor N8, and the source of the seventh NMOS transistor N7 is grounded.

[0078] The gate of the eleventh PMOS transistor M11 is respectively connected to the first end of the fourth resistor R4 and the first end of the fifth resistor R5, and the second end of the fourth resistor R4 is connected to the drain of the twelfth PMOS transistor M12; the drain of the twelfth PMOS transistor M12 is also connected to the cathode of the first diode D1, and the anode of the first diode D1 is grounded.

[0079] The second end of the fifth resistor R5 is grounded; the drain of the eleventh PMOS transistor M11 is connected to the drain of the eighth NMOS transistor N8 and serves as the output end of the comparator circuit 2; the source of the eighth NMOS transistor N8 is grounded.

[0080] Specifically, the twelfth PMOS transistor M12, the fourth resistor R4, the fifth resistor R5, and the first diode D1 form a sampling circuit. The parallel circuit divides the voltage, and the D1 voltage regulator diode stabilizes the fixed voltage. By adjusting the size of the fourth resistor R4 and the fifth resistor R5, different sampling voltages can be output.

[0081] The value of the bias voltage VB is just enough to conduct, and the thirteenth PMOS tube M13 and the fourteenth PMOS tube M14 make Vout1 output a low voltage and operate normally, and Vout2 is high level, and the signal is given to the next circuit module.

[0082] VA is the input port for external signals. When an overcurrent signal is input, it flows through the resistor to form a high-voltage signal, which is fed to the comparator composed of the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, the seventh NMOS transistor N7, and the eighth NMOS transistor N8.

[0083] In the comparator, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are set to have the same width-to-length ratio, and I DS N4=I DSN5, the currents in the two branches are equal.

[0084] M10 V G M10 changes from small to large, and a linear region appears. GS M10 becomes larger, pushing V DS M10 decreases, the gate voltages of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 decrease, and V DS N8 increases the output high level.

[0085] The voltage flows through the Schmitt circuit, which reduces ripple. The high level is output to the sixth NMOS transistor N6, which turns on and pulls down the voltage of the thirteenth and fourth PMOS transistors M14, causing Vout1 to output a high voltage, shutting down the operation, and Vout2 to be low, sending the signal to the next circuit module.

[0086] In this embodiment, the driver circuit 4 includes a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11;

[0087] The source of the thirteenth PMOS transistor is connected to the power supply VDD, and the drain of the thirteenth PMOS transistor M13 is respectively connected to the source of the fourteenth PMOS transistor M14, the source of the fifteenth PMOS transistor M15, and the source of the sixteenth PMOS transistor M16; the gate of the thirteenth PMOS transistor M13 is connected to the gate of the fourteenth PMOS transistor M14, and the drain of the fourteenth PMOS transistor M14 is respectively connected to the gate of the fifteenth PMOS transistor M15, the drain of the ninth NMOS transistor N9, and the gate of the tenth NMOS transistor N10; the gate of the ninth NMOS transistor N9 serves as the input end of the driver circuit 4, and the source of the ninth NMOS transistor N9 is connected to the source of the tenth NMOS transistor N10 and the source of the eleventh NMOS transistor N11, and is grounded;

[0088] The drain of the fifteenth PMOS transistor M15 is respectively connected to the drain of the tenth NMOS transistor N10, the gate of the sixteenth PMOS transistor M16, and the gate of the eleventh NMOS transistor N11; the drain of the sixteenth PMOS transistor M16 is connected to the drain of the eleventh NMOS transistor N11 and serves as the output end of the driver circuit 4.

[0089] Specifically, the fifteenth PMOS transistor M15, the sixteenth PMOS transistor M16, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11 form a driver that enhances signal driving capability and improves signal integrity, while also providing both in-phase and inverting functions. First, signal enhancement enables more efficient signal transmission to subsequent circuits, preventing signal weakening during transmission due to factors such as attenuation and loading. Second, signal integrity improvement reduces signal distortion and aberration, ensuring signal quality.

[0090] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, article, or device comprising the element.

[0091] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A low ripple overcurrent protection circuit, characterized in that: include: Power supply, bias circuit, comparator circuit, Schmitt circuit and driver circuit; The power supply is electrically connected to the bias circuit, the comparator circuit, the Schmitt circuit and the driver circuit respectively; The input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is connected to the input end of the comparator circuit, for providing a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmitt circuit, the output end of the Schmitt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to a load; The Schmitt circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor and a second resistor; The source of the first PMOS transistor is connected to the power supply, the gate of the first PMOS transistor is respectively connected to the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor and serves as the input end of the Schmitt circuit, the drain of the first PMOS transistor is respectively connected to the source of the second PMOS transistor and the source of the third PMOS transistor, the drain of the third PMOS transistor is connected to the first end of the first resistor, and the second end of the first resistor is grounded; the drain of the second PMOS transistor is respectively connected to the drain of the first NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor; The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the source of the third NMOS transistor respectively, and the source of the second NMOS transistor is grounded; the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor, the drain of the third NMOS transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The source of the fourth PMOS tube is connected to the power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the Schmitt circuit; the source of the fourth NMOS tube is grounded.

2. The low ripple overcurrent protection circuit according to claim 1, wherein: The bias circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third resistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor; The source of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor, and is also connected to the power supply; the gate of the fifth PMOS transistor is connected to the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor and the drain of the sixth PMOS transistor; The drain of the fifth PMOS transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the gate of the eighth PMOS transistor and the drain of the seventh NMOS transistor respectively; the drain of the eighth PMOS transistor is connected to the source of the seventh NMOS transistor and is grounded; the source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor and the drain of the fifth NMOS transistor respectively; the source of the fifth NMOS transistor is grounded; The gate of the fifth NMOS tube is connected to the gate of the seventh NMOS tube and the gate of the sixth NMOS tube respectively; the drain of the sixth NMOS tube is connected to the gate of the sixth NMOS tube and the drain of the seventh PMOS tube respectively; the source of the sixth NMOS tube is grounded.

3. The low ripple overcurrent protection circuit according to claim 1, wherein: The comparator circuit includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a fourth resistor, a fifth resistor, a first diode, a seventh NMOS transistor, and an eighth NMOS transistor; The source of the ninth PMOS transistor and the source of the twelfth PMOS transistor are connected and connected to the power supply; the gate of the ninth PMOS transistor and the gate of the twelfth PMOS transistor are used to receive the bias voltage output by the bias circuit; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor respectively; The gate of the tenth PMOS transistor is connected to the bias voltage of the bias circuit; the drain of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is respectively connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor, and the source of the seventh NMOS transistor is grounded; The gate of the eleventh PMOS transistor is connected to the first end of the fourth resistor and the first end of the fifth resistor respectively, and the second end of the fourth resistor is connected to the drain of the twelfth PMOS transistor; the drain of the twelfth PMOS transistor is also connected to the cathode of the first diode, and the anode of the first diode is grounded; The second end of the fifth resistor is grounded; the drain of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor and serves as the output end of the comparator circuit; The source of the eighth NMOS transistor is grounded.

4. The low ripple overcurrent protection circuit according to claim 1, wherein: The driver circuit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor; The source of the thirteenth PMOS transistor is connected to the power supply, and the drain of the thirteenth PMOS transistor is respectively connected to the source of the fourteenth PMOS transistor, the source of the fifteenth PMOS transistor, and the source of the sixteenth PMOS transistor; the gate of the thirteenth PMOS transistor is connected to the gate of the fourteenth PMOS transistor, and the drain of the fourteenth PMOS transistor is respectively connected to the gate of the fifteenth PMOS transistor, the drain of the ninth NMOS transistor, and the gate of the tenth NMOS transistor; the gate of the ninth NMOS transistor serves as the input end of the driver circuit, and the source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor and the source of the eleventh NMOS transistor and is grounded; The drain of the fifteenth PMOS tube is respectively connected to the drain of the tenth NMOS tube, the gate of the sixteenth PMOS tube and the gate of the eleventh NMOS tube; the drain of the sixteenth PMOS tube is connected to the drain of the eleventh NMOS tube and serves as the output end of the driver circuit.

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