Current-limiting protection circuit, current-limiting protection method and electronic equipment

Abstract

The embodiment of the invention provides a current-limiting protection circuit, a current-limiting protection method and electronic equipment, and relates to the technical field of electronics, and the current-limiting protection circuit comprises the steps that a sampling module samples the output current of a first power sub-module and the output current of a second power sub-module, and an overcurrent protection module generates a current-limiting indication signal when any output current is larger than a preset current range; the current-limiting module generates a first current-limiting control signal and a second current-limiting control signal which are different according to the current-limiting indication signal, and transmits the first current-limiting control signal and the second current-limiting control signal to the first logic sub-module and the second logic sub-module respectively; and the pulse width modulation signals in the first logic sub-module and the second logic sub-module are adjusted at the same time, so that the output current of the first power sub-module and the second power sub-module is kept in a preset current range, an overcurrent protection mechanism is started in time, and a device is protected from being damaged.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a current limiting protection circuit, a current limiting protection method and an electronic device. Background Art

[0002] Class D power amplifier, also known as switching amplifier, has the main function of converting the input analog audio signal or PCM (pulse code modulation) digital information into PWM (pulse width modulation) or PDM (pulse density modulation) pulse signals, and then using the PWM or PDM pulse signals to control the on / off of high-power switching devices to restore the amplified analog signal.

[0003] In the related art, a class D power amplifier is generally provided with an overcurrent protection circuit, which is provided with a sampling resistor in the class D power amplifier. The sampling resistor is sampled to obtain a sampling voltage. When the sampling voltage reaches the reference voltage, a control signal is generated, and the driving unit in the class D power amplifier is controlled to be turned off based on the control signal to reduce the voltage and prevent device damage. However, in the process of obtaining the sampling voltage, comparing the sampling voltage and the reference voltage, generating a control signal, and then controlling the output MOSFET to be turned off based on the control signal, there is a signal delay, which causes the overcurrent protection mechanism to be untimely started and damage the device. And because the sampling resistor is easily affected by factors such as temperature, humidity, air pressure, and process angle, the obtained sampling voltage may be inaccurate, and then the overcurrent protection mechanism may be triggered by mistake, resulting in audio interruption, poor robustness of the audio system, and poor user experience.

[0004] Therefore, it is now urgent to redesign a current limiting protection circuit, a current limiting protection method and an electronic device, and overcome the above-mentioned defects. Summary of the invention

[0005] The embodiments of the present application provide a current limiting protection circuit, a current limiting protection method and an electronic device, which are used to timely start an overcurrent protection mechanism to protect devices from damage.

[0006] In a first aspect, an embodiment of the present application provides a current limiting protection circuit, comprising: a sampling module, an overcurrent protection module, a current limiting module, a logic module, and a power module connected in sequence;

[0007] The logic module includes a first logic submodule and a second logic submodule, wherein the current limiting module is connected to the first logic submodule and the second logic submodule respectively; the power module includes a first power submodule and a second power submodule, wherein the first logic submodule is connected to the first power submodule, the second logic submodule is connected to the second power submodule, and the first power submodule and the second power submodule are respectively connected to the sampling module;

[0008] When at least one of the first output current and the second output current respectively received by the sampling module from the first power sub-module and the second power sub-module exceeds a preset current, the overcurrent protection module generates a current limiting indication signal, and the current limiting module jointly adjusts the pulse width modulation signal input to the first logic sub-module and the second logic sub-module according to the current limiting indication signal with the first logic sub-module and the second logic sub-module, so that the output current of the first power sub-module and the second power sub-module remains within the preset current range.

[0009] Optionally, the current limiting module includes a first current limiting submodule and a second current limiting submodule;

[0010] The first positive output terminal of the first current limiting submodule is connected to the first logic submodule, and the first negative output terminal is connected to the second logic submodule;

[0011] The second positive output terminal of the second current limiting submodule is connected to the second logic submodule, and the second negative output terminal is connected to the first logic submodule.

[0012] Optionally, the first current limiting submodule includes a first OR gate, a first inverter and a first trigger connected in sequence; the second current limiting submodule includes a second OR gate, a second inverter and a second trigger connected in sequence;

[0013] The control end of the first trigger is used to receive a clock signal, the first positive output end is used to output the first current limiting control signal in a trigger state, and the first negative output end is used to output the second current limiting control signal in a trigger state;

[0014] The control end of the second trigger is used to receive a clock signal, the second positive output end is used to output the second current limiting control signal in a triggered state, and the second negative output end is used to output the first current limiting control signal in a triggered state.

[0015] Optionally, the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, the first logic submodule includes a first AND gate and a first OR gate; the second logic submodule includes a second AND gate and a second OR gate;

[0016] The current limiting input terminal of the first AND gate is connected to the first positive output terminal of the first trigger, the signal input terminal receives the first pulse width modulation signal, and the output terminal is connected to the signal input terminal of the first OR gate;

[0017] The current limiting input terminal of the first OR gate is connected to the second negative output terminal of the second trigger, and the output terminal is connected to the first power sub-module;

[0018] The current limiting input terminal of the second AND gate is connected to the second positive output terminal of the second trigger, the signal input terminal receives the second pulse width modulation signal, and the output terminal is connected to the signal input terminal of the second OR gate;

[0019] The current limiting input terminal of the second OR gate is connected to the first negative output terminal of the first trigger, and the output terminal is connected to the second power sub-module.

[0020] Optionally, the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal.

[0021] Under the triggering of the current limiting indication signal:

[0022] The first current limiting submodule adjusts the first pulse width modulation signal in the first logic submodule through the first current limiting control signal in a first time period, so that the first output current drops within the preset current range; and adjusts the second pulse width modulation signal in the second logic submodule through the second current limiting control signal, so that the second output current rises within the preset current range;

[0023] Or the second current limiting submodule adjusts the second pulse width modulation signal in the second logic submodule through the second current limiting control signal in the second time period, so that the second output current drops to within the preset current range, and adjusts the first pulse width modulation signal in the first logic submodule through the first current limiting control signal, so that the first output current rises to within the preset current range; the first time period and the second time period correspond to different intervals in the pulse width modulation signal cycle.

[0024] Optionally, the current limiting module is used to simultaneously adjust the duty cycle of the pulse width modulation signal in the first logic submodule and the second logic submodule so that the output current of the first power submodule and the second power submodule remains within the preset current range.

[0025] Optionally, a filtering module is provided between the overcurrent protection module and the current limiting module, and the filtering module is used to filter the current limiting indication signal.

[0026] Optionally, the filtering module includes an input inverter, a resistor, a Schmitt trigger, an intermediate inverter and an output inverter connected in sequence, and a grounding branch is branched between the resistor and the Schmitt trigger. A transmission gate and a capacitor connected in series are arranged on the grounding branch, and the capacitor is grounded.

[0027] In a second aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes a current limiting protection circuit as described in any one of the first aspects.

[0028] In a third aspect, an embodiment of the present application provides a current limiting protection method, the method comprising:

[0029] Sampling a first output current of a first power submodule and a second output current of a second power submodule, and generating a current limiting indication signal when at least one of the first output current and the second output current exceeds a preset current range;

[0030] A first current limiting control signal and a second current limiting control signal are generated in response to the current limiting indication signal, and the first current limiting control signal is transmitted to the first logic submodule, and the second current limiting control signal is transmitted to the second logic submodule, so as to simultaneously adjust the pulse width modulation signals in the first logic submodule and the second logic submodule, so that the output currents of the first power submodule and the second power submodule are maintained within the preset current range.

[0031] Optionally, the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, the first pulse width modulation signal and the second pulse width modulation signal are obtained according to a differential signal, and the simultaneously adjusting the pulse width modulation signals in the first logic submodule and the second logic submodule includes:

[0032] In a first time period, the first pulse width modulation signal is processed in response to the first current limiting control signal so that the first output current drops within the preset current range; the second pulse width modulation signal is processed in response to the second current limiting control signal so that the second output current rises within the preset current range;

[0033] In a second time period, the first pulse width modulation signal is processed in response to the first current limiting control signal so that the first output current rises to within the preset current range; the second pulse width modulation signal is processed in response to the second current limiting control signal so that the second output current drops to within the preset current range, and the first time period and the second time period correspond to different intervals in the pulse width modulation signal cycle.

[0034] Optionally, the simultaneously adjusting the pulse width modulation signals in the first logic submodule and the second logic submodule so that the output currents of the first power submodule and the second power submodule remain within the preset current range includes:

[0035] The duty ratios of the pulse width modulation signals in the first logic submodule and the second logic submodule are adjusted simultaneously, so that the output currents of the first power submodule and the second power submodule are maintained within the preset current range.

[0036] Optionally, before generating the first current limiting control signal and the second current limiting control signal in response to the current limiting indication signal, the current limiting indication signal is filtered.

[0037] The beneficial effects of this application are as follows:

[0038] An embodiment of the present application provides a current limiting protection circuit, which includes a sampling module, an overcurrent protection module, a current limiting module, a logic module including a first logic submodule and a second logic submodule, and a power module including a first power submodule and a second power submodule. The sampling module samples the first output current of the first power submodule and the second output current of the second power submodule. When at least one of the first output current and the second output current exceeds a preset current range, the overcurrent protection module generates a current limiting indication signal. The current limiting module generates a first current limiting control signal and a second current limiting control signal based on the current limiting indication signal, and performs current limiting control on the pulse width modulation signals of the first logic submodule and the second logic submodule respectively and simultaneously. In this way, the two output currents can be quickly regulated within the preset current range. Compared with the prior art, a sampling resistor is set in the device, the sampling resistor is sampled, resulting in a control signal delay, and then overcurrent protection is performed based on the control signal, which is easy to damage the device. In this application, the output currents of the two power submodules are sampled respectively, and the output currents of the two logic subcircuits are controlled at the same time, so as to quickly reduce the output current and reliably protect the device from damage.

[0039] Other features and other advantages of the present application will be described in the subsequent description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of a block diagram of an overcurrent protection system for a conventional class D audio power amplifier provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of the structure of a current limiting protection circuit provided in an embodiment of the present application;

[0043] Figure 3A schematic diagram of the structure of a first power submodule and a second power submodule provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the structure of an overcurrent protection module provided in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of the structure of a current limiting module provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the structure of another current limiting module provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of a differential signal provided in an embodiment of the present application;

[0048] Figure 8 A schematic diagram of the structure of a first current limiting submodule provided in an embodiment of the present application;

[0049] Fig. 9 A schematic diagram of the structure of a second current limiting submodule provided in an embodiment of the present application;

[0050] Fig.10 A schematic diagram of an analog signal of overcurrent-current limiting corresponding to a first pulse width modulation signal and a second pulse width modulation signal provided in an embodiment of the present application;

[0051] Fig.11 A schematic diagram of an analog signal of overcurrent-current limiting corresponding to a first pulse width modulation signal and a second pulse width modulation signal provided in an embodiment of the present application;

[0052] Fig.12 A schematic diagram of a clock signal and a differential signal with the same signal period provided in an embodiment of the present application;

[0053] Fig.13 A schematic diagram of signal transmission of a first logic submodule provided in an embodiment of the present application;

[0054] Fig.14 A schematic diagram of signal transmission of a second logic submodule provided in an embodiment of the present application;

[0055] Fig.15 A pulse width modulation signal and its analog signal schematic diagram provided in an embodiment of the present application;

[0056] Fig.16 A schematic diagram of the structure of a current limiting protection circuit provided in an embodiment of the present application;

[0057] Fig.17 A structural schematic diagram of a filtering module provided in an embodiment of the present application;

[0058] Fig.18 A schematic diagram of the structure of a CBC system including a current limiting protection circuit provided in an embodiment of the present application;

[0059] Fig.19 A schematic diagram of a waveform of a relevant signal under normal circumstances provided in an embodiment of the present application;

[0060] Fig. 20 A waveform diagram of a related signal provided in an embodiment of the present application under abnormal conditions in the first half cycle of a first pulse width modulation signal;

[0061] Fig.21 A waveform diagram of a related signal provided in an embodiment of the present application under abnormal conditions in the second half cycle of a first pulse width modulation signal;

[0062] Fig. 22 A schematic diagram of a simulated signal waveform under a short circuit condition provided in an embodiment of the present application;

[0063] Fig.23 A waveform diagram of a related signal provided in an embodiment of the present application under an abnormal condition of a short circuit;

[0064] Fig.24 A schematic diagram of a hardware structure of an electronic device to which an embodiment of the present application is applied;

[0065] Fig.25 A schematic diagram of a structure of connecting an electronic device and an external device using an embodiment of the present application;

[0066] Fig.26 The present invention is a flowchart of an overcurrent protection method according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily.

[0068] It should be noted that in the description of the present application, "at least one" refers to one or more, wherein a plurality refers to two or more. In view of this, in the embodiments of the present invention, "a plurality" may also be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0069] It should be pointed out that in the embodiments of the present application, "connection" can be understood as electrical connection and / or signal connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as A and B connection, or A and C direct connection, C and B direct connection, and A and B are connected through C. In some scenarios, "connection" can also be understood as coupling, such as electromagnetic coupling between two inductors. In short, the connection between A and B enables the transmission of electrical energy between A and B.

[0070] To facilitate understanding of the technical solutions provided in the embodiments of the present application, some key terms used in the embodiments of the present application are explained here:

[0071] Cycle-By-Cycle (CBC) current limiting function is often used to limit the output current of the inverter circuit to prevent the inverter circuit from outputting overcurrent during loading and thus damaging the hardware circuit.

[0072] Pulse width modulation (PWM) is an analog control method that modulates the bias of the transistor base or MOS tube gate according to the change of the corresponding load to achieve the change of the transistor or MOS tube conduction time, thereby achieving the change of the output of the switching regulated power supply. This method can keep the output voltage of the power supply constant when the working conditions change. It is a very effective technology for controlling analog circuits using digital signals from microprocessors. This technology can be used to obtain pulse width modulation signals.

[0073] Analog signals refer to information expressed by continuously changing physical quantities, such as temperature, humidity, pressure, length, current, voltage, etc. We usually call analog signals continuous signals, which can have infinite different values ​​within a certain time range. Digital signals refer to signals that are discrete and discontinuous in value.

[0074] Differential transmission is a signal transmission technology. Different from the traditional method of one signal line and one ground line, differential transmission transmits signals on both lines. The two signals have the same amplitude and opposite phase. The signal transmitted on these two lines is a differential signal. The signal receiving end compares the difference between the two voltages to determine the logical state sent by the sending end. On the circuit board, the differential traces must be two lines of equal length, equal width, close proximity, and on the same layer.

[0075] Clock signals are the basis of sequential logic. They are used to determine when the state in a logic unit is updated. They are semaphores with a fixed period and are independent of operation. Clock signals have a fixed clock frequency, which is the inverse of the clock period. In electronics, especially synchronous digital circuits, clock signals are a special type of signal that oscillates between high and low states. The signal is used like a metronome to coordinate the actions of digital circuits. Digital clock signals are basically square wave voltages.

[0076] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, MOS) can be referred to as MOSFET or metal-oxide-semiconductor field-effect transistor. MOS transistors are divided into P-type MOS tubes and N-type MOS tubes. The integrated circuit composed of MOS tubes is called MOS integrated circuit, the circuit composed of NMOS is NMOS integrated circuit, the circuit composed of PMOS tubes is PMOS integrated circuit, and the complementary MOS circuit composed of NMOS and PMOS tubes is CMOS circuit.

[0077] PMOS (positive channel Metal Oxide Semiconductor) refers to a MOS tube with an n-type substrate and a p-channel, which relies on the flow of holes to transport current. Its alias is positive MOS.

[0078] NMOS (N-Metal-Oxide-Semiconductor) is a MOS tube with N-type metal-oxide-semiconductor, p-type substrate, n-channel, and relies on the flow of electrons to transport current. Transistors with this structure are called NMOS transistors.

[0079] AND gate, also known as "AND circuit", logical "product", and logical "AND" circuit. It is a basic logic gate circuit that performs "AND" operation. It has multiple input terminals and one output terminal. When all inputs are high level (logic 1) at the same time, the output is high level, otherwise the output is low level (logic 0).

[0080] OR gate, also known as OR circuit, logic and circuit. If an event occurs as long as one of several conditions is met, this relationship is called an "OR" logic relationship. A circuit with an "OR" logic relationship is called an OR gate. The OR gate has multiple input terminals and one output terminal. As long as one of the inputs is at a high level (logic "1"), the output is high (logic "1"); only when all the inputs are at a low level (logic "0"), the output is low (logic "0").

[0081] The inverter can reverse the phase of the input signal by 180 degrees. This circuit is used in analog circuits, such as audio amplifiers, clock oscillators, etc. Inverters are often used in electronic circuit design. The CMOS inverter circuit consists of two enhancement MOS field effect transistors. The typical TTL NAND gate circuit consists of an input stage, an intermediate stage, and an output stage.

[0082] A flip flop is an electronic circuit with two stable states that can be used to store binary data. The stored data can be changed by applying different inputs.

[0083] The Schmitt trigger has two stable states, but unlike general triggers, the Schmitt trigger uses a potential trigger mode, and its state is maintained by the input signal potential; for input signals with two different change directions, negative decreasing and positive increasing, the Schmitt trigger has different threshold voltages. In electronics, the Schmitt trigger is a comparator circuit containing positive feedback. For a standard Schmitt trigger, when the input voltage is higher than the positive threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output does not change, that is, the threshold voltage corresponding to the output flipping from a high potential to a low potential, or from a low potential to a high potential is different. The output will only change when the input voltage changes enough, so this component is named a trigger. This dual threshold action is called hysteresis, indicating that the Schmitt trigger has memory. In essence, the Schmitt trigger is a bistable multivibrator.

[0084] The half-bridge circuit includes two power switching devices connected in series. The power switching devices may be MOS, IGBT, etc., and may also include a driving unit for driving the power switching devices.

[0085] The following is a brief introduction to the design concept of the embodiment of the present application:

[0086] In traditional Class D audio amplifier systems, the output power tube generally adopts P / N MOS architecture or dual NMOS architecture. Considering the efficiency and load capacity of the chip, if the output stage adopts P / N MOS architecture, the size of PMOS needs to be very large, which has a greater impact on the area. Therefore, many Class D audio amplifiers use dual NMOS architecture, such as Figure 1 As shown, it is a block diagram of an overcurrent protection system of a traditional Class D audio amplifier provided in an embodiment of the present application; wherein, what is shown is a dual N-architecture half-bridge power output stage. M1 is an upper power tube (NMOS), M3 is a lower power tube (NMOS), M2 is an upper sampling tube, and M4 is a lower sampling tube. Wherein M1 and M3 are alternately turned on and cannot be connected in series. When the current flowing through M1 or M3 reaches the set overcurrent protection threshold, M2 or M4 will sample the current of the power tube to the overcurrent protection circuit (OCP), and after relevant signal processing (usually compared with the reference current), an overcurrent indication signal (OC indication signal) is generated, which will be sent to the protection logic circuit of the chip, and the protection logic circuit controls the gate drive circuit to turn off the power tube, so that the power amplifier stops working.

[0087] During the overcurrent protection process, several situations may cause overcurrent: First, abnormal components in the circuit cause a sudden increase in current, triggering OC and interrupting the audio. Second, when the load is small and the amplifier outputs a large signal, OC may be triggered, causing the audio to be interrupted. Third, in some special scenarios, such as when the output loads are short-circuited, or when the output is short-circuited to the power supply or ground, a large instantaneous current will be caused, triggering OC and interrupting the audio. In these cases, if the OC does not respond in time, the device may burn out. In addition, the traditional Class D amplifier overcurrent protection system usually does not have an anti-mistouch function, which will cause the amplifier to stop working immediately when a short-term OC occurs, greatly affecting the user experience.

[0088] In view of this, a current limiting protection circuit provided in an embodiment of the present application includes: a sampling module, an overcurrent protection module, a current limiting module, a logic module, and a power module connected in sequence; the sampling module samples the output current of the first power submodule and the second power submodule in the power module, and the overcurrent protection module determines that when any output current exceeds a preset current range, the current limiting module combines with the first logic submodule in the logic module to limit the first output current based on the first current limiting control signal, and combines with the second logic submodule in the logic module to limit the second output current based on the second current limiting control signal. The current limiting module also periodically restores the pulse width modulation signal based on the clock period of the clock signal. Figure 2 In the embodiment shown, the first power submodule and the second power submodule are power submodules of a class D audio power amplifier system. The preset current range is defined by a current threshold, that is, within the preset current range, the current value of any output current does not exceed the current threshold.

[0089] The following briefly introduces the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In the specific implementation process, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.

[0090] The solution provided in the embodiments of the present application can be applied to most application scenarios of overcurrent protection circuits. For example, the overcurrent protection circuit provided in the embodiments of the present application can be applied to the reading and writing systems, audio and video playback systems, as well as power drivers, household appliances, industrial electronic equipment, etc. of electronic devices such as mobile phones, computers, readers, smart wearable devices and servers, and are not listed one by one here.

[0091] The current limiting protection circuit provided by the exemplary embodiment of the present application is described below in combination with the application scenarios described above and with reference to the accompanying drawings. It should be noted that the above application scenarios are only shown to facilitate understanding of the spirit and principles of the present application, and the implementation methods of the present application are not limited in this regard.

[0092] like Figure 2 , which is a schematic diagram of the structure of the current limiting protection circuit provided in an embodiment of the present application, including: a sampling module, an overcurrent protection module, a current limiting module, a logic module, and a power module connected in sequence;

[0093] The logic module includes a first logic submodule and a second logic submodule, wherein the current limiting module is connected to the first logic submodule and the second logic submodule respectively; the power module includes a first power submodule and a second power submodule, wherein the first logic submodule is connected to the first power submodule, the second logic submodule is connected to the second power submodule, and the first power submodule and the second power submodule are connected to the sampling module respectively;

[0094] When at least one of the first output current and the second output current respectively received by the sampling module from the first power submodule and the second power submodule exceeds a preset current range, the overcurrent protection module generates a current limiting indication signal, and the current limiting module jointly adjusts the pulse width modulation signal input to the first logic submodule and the second logic submodule according to the current limiting indication signal together with the first logic submodule and the second logic submodule, so that the output current of the first power submodule and the second power submodule remains within the preset current range.

[0095] In one embodiment, the current limiting module also receives a clock signal, and the clock signal has a corresponding clock cycle. If the current limiting module detects a preset clock edge entering the clock signal, it stops generating the first current limiting control signal and the second current limiting control signal until the overcurrent protection module generates a current limiting indication signal again. In other words, the sampling module continuously samples the first output current of the first power submodule and the second output current of the second power submodule, and when the overcurrent protection circuit detects that the first output current and / or the second output current exceeds the preset current range, the overcurrent protection module instructs the current limiting module to perform overcurrent-current limiting. In the process of overcurrent-current limiting based on the current limiting indication signal of the overcurrent protection module, when entering the next clock cycle of the clock signal, the current limiting module "attempts" to restore the pulse width modulation signal to ensure the normal drive of the pulse width modulation signal, but if the current limiting indication signal is still received, the overcurrent-current limiting is performed again quickly to ensure that the circuit is not damaged. In this way, the audio will be restored in time after the overcurrent ends. Since short-term overcurrent may usually be only at the millisecond level, it is difficult for users to detect, so it will not affect user applications, and improve user experience.

[0096] In one embodiment, the pulse width modulation signal may be a processed audio signal, and the specific setting of the pulse width modulation signal is not limited herein.

[0097] In one embodiment, if the pulse width modulation signal is an analog signal or is obtained based on an analog signal, the preset current range can be determined based on the current in different directions in the analog signal, for example, the current value from the positive end of the load to the negative end of the load is I, and the current value from the negative end of the load to the positive end of the load is -I, then the preset current range can be (I, -I); if it is a pulse width modulation signal, then the preset current range can also be (I1, I2), where I1 and I2 can both be greater than 0, or I1 can be greater than 0, and I2 can be less than 0. There is no specific restriction on the boundary values ​​(I1, I2) of the interval of the preset current range, and it can be set as needed. The preset current range can be selected from multiple current ranges, and can be selected through circuit control, program control, or manual control. There is no specific restriction on the determination of the preset current range.

[0098] In one embodiment, if Figure 3 As shown, it is a schematic diagram of the structure of a first power submodule and a second power submodule provided in an embodiment of the present application. The first power submodule and the second power submodule may respectively include a driving module and a power amplifier module. A capacitor element may be provided in the driving module to store charge to drive the power amplifier module. One or more resistor elements may also be provided to control the current in the submodule, etc. The specific settings of the first power submodule and the second power submodule are not limited here and can be set as needed.

[0099] In one embodiment, if Figure 4 As shown, it is a structural schematic diagram of an overcurrent protection module provided by an embodiment of the present application. A current detection circuit, a current comparison circuit, and a current amplification circuit can be set in the overcurrent protection module; the current detection circuit can be set to sample the first output current and the second output current respectively by mutual inductance, and then based on the preset current range in the current comparison circuit, the first output current and the second output current obtained by sampling are compared respectively. If any output current exceeds the preset current range, a current limiting indication signal is generated. Before the comparison, the first output current and the second output current can also be amplified by the current amplification circuit. It should be noted that the current detection circuit, the current comparison circuit, and the current amplification circuit are all relatively mature technologies. In this application, circuits with corresponding functions can be sampled for implementation. The specific settings of the sampling module are not limited here, and can be selected as needed.

[0100] In one embodiment, if Figure 5 As shown, it is a structural schematic diagram of a current limiting module provided in an embodiment of the present application. A signal conversion circuit can be set in the current limiting module, and multiple comparators can be set in the signal conversion circuit. Then, in a possible implementation, after the overcurrent protection module determines that the first output current and / or the second output current exceeds the preset current range, the overcurrent protection module generates a current greater than a fixed current value as a current limiting indication signal through an amplification circuit. Then, the current limiting module can receive the current limiting indication signal through multiple comparators, and compare and determine that the current value of the current limiting indication signal is greater than the fixed current value in the comparator, and respectively generate a first current limiting control signal and a second current limiting control signal to control the power of the pulse width modulation signal in the first logic submodule and the second logic submodule. If both the first output current and the second output current do not exceed the preset current range, the current limiting indication signal may not be generated.

[0101] In one embodiment, the first power sub-module and the second power sub-module may also be the positive sub-module and the negative sub-module at both ends of the load corresponding to electronic devices such as a power driver and a power converter, respectively. Accordingly, the overcurrent protection circuit can perform overcurrent protection on the pulse width modulation signal at both ends of the load.

[0102] The above-mentioned current limiting protection circuit generates a current limiting indication signal when any one of the sampled first output current and the second output current exceeds the preset current range, generates different first current limiting control signals and second current limiting control signals based on the current limiting indication signal, and performs current limiting control on the pulse width modulation signals in the first logic submodule and the second logic submodule respectively and simultaneously, so as to quickly reduce the output current of the first power submodule and the second power submodule, that is, reduce the output current in the circuit, reduce the load current, and protect the device from damage. The current limiting module can also restore the pulse width modulation signal when the next clock cycle arrives when the overcurrent protection occurs in the current clock cycle, and the output current in the circuit is reduced in the current clock cycle. After the short-term overcurrent-current limiting (if the pulse width modulation signal is an audio-related signal), the audio output can be quickly restored without affecting the user application. If the current limiting module still receives the current limiting indication signal when the next clock cycle arrives, the first current limiting control signal and the second current limiting control signal are still generated to reduce the output current, that is, the current limiting protection may be triggered twice and the pulse width modulation signal may be restored once in two adjacent clock cycles. In this way, the quality of the pulse width modulation signal and the circuit safety can be taken into account.

[0103] Based on the above Figure 2-5 In the circuit structure diagram, the embodiment of the present application provides a current limiting module, which includes a first current limiting sub-module and a second current limiting sub-module;

[0104] The first positive output terminal of the first current limiting submodule is connected to the first logic submodule, and the first negative output terminal is connected to the second logic submodule;

[0105] The second positive output terminal of the second current limiting submodule is connected to the second logic submodule, and the second negative output terminal is connected to the first logic submodule.

[0106] In one embodiment, the first current limiting submodule is used to generate the first current limiting control signal and the second current limiting control signal in response to the current limiting indication signal in a first time period; the second current limiting submodule is used to generate the first current limiting control signal and the second current limiting control signal in response to the current limiting indication signal in a second time period different from the first time period. T1 (first time period) + T2 (second time period) = T 主周期 (Pulse Width Modulation Signal Cycle), the time periods T1 and T2 can be equal or different and can be set as needed. That is to say, the first time period and the second time period correspond to different intervals in the main signal cycle.

[0107] In one embodiment, the present application embodiment provides a structural diagram of a current limiting module, such as Figure 6As shown, the pulse width modulation signal is obtained based on the differential signal, and the two sub-signals of the differential signal are transmitted through two paths, that is, the first pulse width modulation signal transmitted by the first logic submodule and the first power submodule, and the second pulse width modulation signal transmitted by the second logic submodule and the second power submodule are respectively two sub-signals of the differential signal. T1 is the first half cycle of the pulse width modulation signal, and T2 is the second half cycle of the pulse width modulation signal; the first current limiting submodule is used to generate different first current limiting control signals and second current limiting control signals according to the current limiting indication signal when the first pulse width modulation signal is in the first half cycle, and transmit the first current limiting control signal to the first logic submodule through the first positive output terminal, and transmit the second current limiting control signal to the second logic submodule through the first negative output terminal; the second current limiting submodule is used to generate different first current limiting control signals and second current limiting control signals according to the current limiting indication signal when the first pulse width modulation signal is in the second half cycle, and transmit the first current limiting control signal to the first logic submodule through the second negative output terminal, and transmit the second current limiting control signal to the second logic submodule through the second positive output terminal. As shown Figure 7 As shown, a differential signal is provided in an embodiment of the present application. It can be seen that the sub-signal amplitudes of the upper and lower differential signals are equal and the phases are opposite. It should be noted that the differential signal shown here is only used to clearly illustrate the technical solution in the present application and does not limit the specific implementation of the solution in the present application. It is understandable that in each specific implementation of the present application, the differential signal and its related data involved, when the various embodiments of the present application are applied to specific products or technologies, need to obtain relevant licenses or consents, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0108] Based on the above Figure 6 The structural diagram of the current limiting module shown in the figure, a first current limiting submodule and a second current limiting submodule provided in the embodiment of the present application, such as Figure 8 As shown, the first current limiting submodule includes a first OR gate, a first inverter and a first trigger connected in sequence; Fig. 9 As shown, the second current limiting submodule includes a second OR gate, a second inverter and a second trigger connected in sequence;

[0109] The control end of the first trigger is used to receive a clock signal, the first positive output end is used to output a first current limiting control signal in a triggered state, and the first negative output end is used to output a second current limiting control signal in a triggered state;

[0110] The control end of the second trigger is used to receive a clock signal, the second positive output end is used to output a second current limiting control signal in a triggered state, and the second negative output end is used to output a first current limiting control signal in a triggered state.

[0111] In one embodiment, the first positive output terminal of the first current limiting submodule is the first positive output terminal of the first trigger, the first negative output terminal of the first current limiting submodule is the first negative output terminal of the first trigger, the second positive output terminal of the second current limiting submodule is the second positive output terminal of the second trigger, and the second negative output terminal of the second current limiting submodule is the second negative output terminal of the second trigger.

[0112] In one embodiment, the current limiting indication signal is a high-level signal; the first OR gate is used to output a high-level signal to the first inverter according to the current limiting indication signal, and can also be used to report a trigger signal (high-level signal) to the monitoring module; the first inverter is used to perform level conversion on the received high-level signal, and output the obtained low-level signal to the first trigger; the first trigger is used to enter the trigger state from the reset state based on the trigger of the received low-level signal, output the first current limiting control signal through the first positive output terminal, and output the second current limiting control signal through the first negative output terminal. The control terminal of the first trigger receives a clock signal, and enters the reset state from the trigger state when a preset clock edge of the clock signal is detected. Wherein, when the first trigger is in the trigger state, the first positive output terminal outputs a low-level signal, and the first negative output terminal outputs a high-level signal. In the reset state, the first positive output terminal outputs a high-level signal, and the first negative output terminal outputs a low-level signal. Then based on Figure 8The structural diagram of the first current limiting submodule shown in the figure, CBC_UP_A and / or CBC_DN_B are current limiting indication signals of high level signals, CBC_UP_A is determined according to whether the first output current exceeds the preset current range, if so, CBC_UP_A is a high level signal, otherwise it is a low level signal; CBC_DN_B is determined according to whether the second output current exceeds the preset current range, if so, CBC_DN_B is a high level signal, otherwise it is a low level signal. OR4 is the first OR gate, INV1 is the first inverter, D1 is the first trigger, CLK_CBC is the clock signal, TEH is a normally high signal, in the reset state, the first positive output terminal Q outputs a high level signal, and the first negative output terminal QN outputs a low level signal. The first trigger D1 is triggered by a low-level signal. When the first current limiting submodule receives the current limiting indication signal (CBC_UP_A and / or CBC_DN_B are high-level signals), a CBC_A high-level signal is obtained based on the first OR gate OR4, and the high-level signal CBC_A is transmitted to the first inverter INV1. CBC_A is also reported to the monitoring module. When the CBC_A obtained by the monitoring module is a high-level signal-trigger signal, it can be recorded that the current limiting protection is triggered. The first inverter converts the high-level signal into a low-level signal, triggering the first trigger D1, so that the first trigger D1 enters the trigger state, and the first positive output terminal Q outputs a low-level signal VOP_DN_ENN-the first current limiting control signal, and the first negative output terminal QN outputs a high-level signal VON_UP_EN-the second current limiting control signal. When receiving the high-level signal transmitted by INV1, or when the control end detects the preset clock edge of the clock signal, it enters the reset state, the first positive output terminal Q outputs a high-level signal, and the first negative output terminal QN outputs a low-level signal.

[0113] In one embodiment, the current limiting indication signal is a high-level signal; the second OR gate is used to output a high-level signal to the second inverter according to the current limiting indication signal, and can also be used to report the trigger signal (high-level signal) to the monitoring module; the second inverter is used to perform level conversion on the received high-level signal, and output the obtained low-level signal to the second trigger; the second trigger is used to enter the trigger state from the reset state based on the trigger of the received low-level signal, output the second current limiting control signal through the second positive output terminal, and output the first current limiting control signal through the second negative output terminal; the control terminal of the second trigger receives the clock signal, and enters the reset state from the trigger state when the preset clock edge of the clock signal is detected. Wherein, when the second trigger is in the triggered state, the second positive output terminal outputs a low-level signal, and the second negative output terminal outputs a high-level signal; in the reset state, the second positive output terminal outputs a high-level signal, and the second negative output terminal outputs a low-level signal. Then based on Fig. 9The structural diagram of the second current limiting submodule shown in the figure, CBC_UP_B and / or CBC_DN_A are current limiting indication signals of high level signals, CBC_DN_A is determined according to whether the first output current exceeds the preset current range, if so, CBC_DN_A is a high level signal, otherwise it is a low level signal; CBC_UP_B is determined according to whether the second output current exceeds the preset current range, if so, CBC_UP_B is a high level signal, otherwise it is a low level signal. OR5 is the second OR gate, INV2 is the second inverter, D2 is the second trigger, CLK_CBC is the clock signal, TEH is a normally high signal, in the reset state, the second positive output terminal Q outputs a high level signal, and the second negative output terminal QN outputs a low level signal. The first trigger D2 is triggered by a low-level signal. When the second current limiting submodule receives the current limiting indication signal (CBC_UP_B and / or CBC_DN_A are high-level signals), a CBC_B high-level signal is obtained based on the second OR gate OR5, and the high-level signal CBC_B is transmitted to the second inverter INV2. CBC_B is also reported to the monitoring module. When the CBC_B obtained by the monitoring module is a high-level signal-trigger signal, it can be recorded that the current limiting protection is triggered. The second inverter converts the high-level signal into a low-level signal, triggering the second trigger D2, entering the trigger state, and making the second positive output terminal Q output a low-level signal VON_DN_ENN-the second current limiting control signal, and the second negative output terminal QN outputs a high-level signal VOP_UP_EN-the first current limiting control signal. When receiving a high-level signal, it enters the reset state, the second positive output terminal Q outputs a high-level signal, and the second negative output terminal QN outputs a low-level signal.

[0114] In one embodiment, if Figure 8 , 9 As shown, the output end of the first OR gate OR4 and the output end of the second OR gate OR5 can be connected to the OR gate OR1 at the same time, then the first OR gate OR4 reports CBC_A to the OR gate OR1, and the second OR gate OR5 reports CBC_B to the OR gate OR1. If the first current limiting submodule is in the current limiting trigger state, CBC_A is a high level signal, otherwise it is a low level signal. If the second current limiting submodule is in the current limiting trigger state, CBC_B is a high level signal, otherwise it is a low level signal. If there is a high level signal in CBC_A and CBC_B, the OR gate OR1 can report the trigger state to the monitoring module, and the monitoring module can obtain that the current limiting protection circuit is in the current limiting state at this time.

[0115] In one embodiment, the first current limiting submodule can be configured to include a first OR gate, a first NOT gate, and a first trigger connected in sequence; the first OR gate outputs a high-level signal to the first NOT gate according to the current limiting indication signal; the first NOT gate performs level conversion on the received high-level signal and outputs the obtained low-level signal to the first trigger, so that the first trigger enters the trigger state from the reset state. The second current limiting submodule can be configured to include a second OR gate, a second NOT gate, and a second trigger connected in sequence; the second OR gate outputs a high-level signal to the second NOT gate according to the current limiting indication signal; the second NOT gate performs level conversion on the received high-level signal and outputs the obtained low-level signal to the second trigger, so that the second trigger enters the trigger state from the reset state. It can be seen that those skilled in the art can easily transform the circuit based on the idea of ​​the overcurrent protection circuit in the present application, and therefore, the circuit structure included in the idea of ​​the overcurrent protection circuit in the present application should be protected.

[0116] In one embodiment, based on the above Figure 8 and Fig. 9 The first current limiting submodule and the second current limiting submodule in the overcurrent protection module can generate a current limiting indication signal based on the first output current and / or the second output current respectively; specifically, the current limiting indication signal generated by the overcurrent protection module based on the first output current exceeding the preset current range - the first current limiting indication signal, and / or the current limiting indication signal generated based on the second output current exceeding the preset current range - the second current limiting indication signal; wherein the D trigger -D1 is a rising edge trigger, and in the reset state, the input terminal D is connected to the normally high level signal TEH, the corresponding first positive output terminal Q outputs a high level signal, the first negative output terminal QN outputs a low level signal, and the trigger clock signal It is the CBC logic control clock CLK_CBC, which is triggered based on a low level signal. When it enters the triggered state, the first positive output terminal Q outputs a low level signal, and the first negative output terminal QN outputs a high level signal; the D flip-flop -D2 is a rising edge trigger. In the reset state, the input terminal D is connected to the normally high level signal TEH, and the corresponding second positive output terminal Q outputs a high level signal, and the second negative output terminal QN outputs a low level signal. The trigger clock signal is the CBC logic control clock CLK_CBC, which is triggered based on a low level signal. When it enters the triggered state, the second positive output terminal Q outputs a low level signal, and the second negative output terminal QN outputs a high level signal.

[0117] In one embodiment, the sampling module includes 4 sampling tubes (the connection method can refer to Fig.18The four sampling tubes of the sampling module are connected to the overcurrent protection module to transmit the first output current and the second output current to the overcurrent protection module, and the overcurrent protection module is respectively connected to the first current limiting submodule and the second current limiting submodule.

[0118] Then, in the first time period, if the first output current of the first power submodule exceeds the preset current range, the overcurrent protection module generates a first current limiting indication signal (CBC_UP_A) and sends it to the first current limiting submodule, and / or, if the second output current of the second power submodule exceeds the preset current range, the overcurrent protection module generates a second current limiting indication signal (CBC_DN_B) and sends it to the first current limiting submodule;

[0119] In the second time period, if the first output current of the first power submodule exceeds the preset current range, the overcurrent protection module generates a first current limiting indication signal (CBC_UP_B) and sends it to the second current limiting submodule, and / or, if the second output current of the second power submodule exceeds the preset current range, the overcurrent protection module generates a second current limiting indication signal (CBC_DN_A) and sends it to the second current limiting submodule. Here, the first current limiting indication signal and the second current limiting indication signal in the first time period and the second time period can be collectively referred to as current limiting indication signals.

[0120] Based on the above, the first trigger and the second trigger work as follows:

[0121] Assume that in the first time period - the first half cycle of the first pulse width modulation signal: any output current of the first output current and the second output current exceeds the preset current range, then the first current limiting indication signal corresponding to the first power submodule and the second current limiting indication signal corresponding to the second power submodule are obtained. The first current limiting indication signal and the second current limiting indication signal are high level signals after passing through OR4, and low level signals after passing through INV1. The low level signal is used as the trigger signal of the D trigger D1, and the low level signal is valid. Based on the triggering of the low level signal caused by the first current limiting indication signal and the second current limiting indication signal, D1 enters the trigger state, and the first positive output terminal Q outputs the first current limiting control signal that pulls the VOP terminal (positive terminal of the load) of the first power submodule to a low level, which is valid at a low level, and the first negative output terminal QN outputs the second current limiting control signal that pulls the VON terminal (negative terminal of the load) of the second power submodule to a high level, which is valid at a high level. Based on the first current limiting control signal and the second current limiting control signal, the output current of the first pulse width modulation signal and the second pulse width modulation signal in the first half cycle of the first pulse width modulation signal is limited to within the preset current range, such as Fig.10 , which is a schematic diagram of an analog signal of overcurrent-current limiting corresponding to a first pulse width modulation signal and a second pulse width modulation signal provided in an embodiment of the present application, wherein: Fig.10 (a) is a schematic diagram of a limited analog signal corresponding to the first pulse width modulation signal, Fig.10 (b) is a schematic diagram of a limited analog signal corresponding to the second pulse width modulation signal.

[0122] Assume that in the second time period - the second half cycle of the first pulse width modulation signal: Similarly, if any of the first output current and the second output current exceeds the preset current range, the first current limiting indication signal corresponding to the first power submodule and the second current limiting indication signal corresponding to the second power submodule are obtained. The first current limiting indication signal and the second current limiting indication signal are high level signals after passing through OR5, and then low level signals after passing through INV2. The low level signal causes D2 to enter a trigger state, and the second positive output terminal Q outputs the second current limiting control signal that pulls the VON terminal (negative terminal of the load) of the second power submodule to a low level, which is valid at a low level, and the second negative output terminal QN outputs the first current limiting control signal that pulls the VOP terminal (positive terminal of the load) of the first power submodule to a high level, which is valid at a high level. Based on the first current limiting control signal and the second current limiting control signal, the output current of the first pulse width modulation signal and the second pulse width modulation signal in the second half cycle of the first pulse width modulation signal is limited within the preset current range, such as Fig.11 , which is a schematic diagram of an analog signal of overcurrent-current limiting corresponding to a first pulse width modulation signal and a second pulse width modulation signal provided in an embodiment of the present application, wherein: Fig.11 (a) is a schematic diagram of a limited analog signal corresponding to the first pulse width modulation signal, Fig.11(b) is a schematic diagram of a limited analog signal corresponding to the second pulse width modulation signal.

[0123] When the D flip-flops D1 and D2 detect a rising edge, they enter a reset state until a current limiting indication signal is received again.

[0124] In one embodiment, if the first trigger detects a preset clock edge of the clock signal, it enters a reset state from a trigger state; if the second trigger detects a preset clock edge of the clock signal, it enters a reset state from a trigger state, the preset clock edge is the upper edge or the lower edge of the clock signal, the clock period of the clock signal and the signal period of the pulse width modulation signal (if the pulse width modulation signal is a periodic signal) meet the set period condition, and the set period condition is used to characterize the period ratio relationship between the clock period and the signal period. For example, the set period condition is that the period ratio relationship between the clock period of the clock signal and the signal period of the pulse width modulation signal is 1.5. For example, the clock period T clk / Signal period T 调制 =1.5; or the period condition is set such that the period ratio of the clock period of the clock signal to the signal period of the pulse width modulation signal is 1, that is, the clock period T clk Equal to the signal period T 调制 ; or set the period condition to be 0.5, where the period ratio of the clock period of the clock signal to the signal period of the pulse width modulation signal is 0.5, such as the clock period T clk / Signal period T 调制 =0.5. That is, the period ratio relationship between the clock period and the signal period can be set as required, and is not specifically limited here.

[0125] In one embodiment, if T clk =T 调制 , then correspondingly, in each cycle, the sampling module and the overcurrent protection module will sample and detect the output current of the first power submodule and the second power submodule. When the output current exceeds the preset current range, the overcurrent protection module generates a current limiting indication signal and transmits it to the current limiting module. The current limiting module generates the first current limiting control signal and the second current limiting control signal based on the current limiting indication signal within the clock cycle of the current clock signal, and if it enters the next clock cycle of the clock signal, it stops generating the first current limiting control signal and the second current limiting control signal until the overcurrent protection module generates the current limiting indication signal again. In this way, the detection cycle is consistent with the pulse width modulation signal cycle, which can further ensure the integrity of the information carried by the pulse width modulation signal.

[0126] In one embodiment, the clock signal may be Figure 8 and Fig. 9 The clock signal CLK_CBC in.

[0127] In one embodiment, if the pulse width modulation signal is obtained based on the differential signal, such as Fig.12 As shown, a clock signal and a differential signal with the same signal period are provided in an embodiment of the present application.

[0128] Based on the above Figures 2 to 12 In the circuit and related embodiments shown in , the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, the first logic submodule includes a first AND gate and a first OR gate; the second logic submodule includes a second AND gate and a second OR gate;

[0129] The current limiting input terminal of the first AND gate is connected to the first positive output terminal of the first trigger, the signal input terminal receives the first pulse width modulation signal, and the output terminal is connected to the signal input terminal of the first OR gate;

[0130] The current limiting input terminal of the first OR gate is connected to the second negative output terminal of the second trigger, and the output terminal is connected to the first power submodule;

[0131] The current limiting input terminal of the second AND gate is connected to the second positive output terminal of the second trigger, the signal input terminal receives the second pulse width modulation signal, and the output terminal is connected to the signal input terminal of the second OR gate;

[0132] The current limiting input terminal of the second OR gate is connected to the first negative output terminal of the first trigger, and the output terminal is connected to the second power submodule. In one embodiment, the first time period is the first half cycle of the first pulse width modulation signal, and the second time period is the second half cycle of the first pulse width modulation signal; when the first pulse width modulation signal is in the first half cycle:

[0133] A first AND gate, used for performing AND logic processing on a first pulse width modulation signal received by the signal input terminal and a first current limiting control signal received by the current limiting input terminal from the first positive output terminal, to obtain a first intermediate branch signal;

[0134] a first OR gate, used for performing OR logic processing on the first intermediate divided signal received by the signal input terminal and the low level signal received by the current limiting input terminal from the second negative output terminal, and transmitting the obtained low level signal to the first power submodule through the output terminal, so as to drive the output current of the first power submodule to drop to a preset current range based on the low level signal;

[0135] A second AND gate is used for performing AND logic processing on the second pulse width modulation signal received by the signal input terminal and the high level signal received by the current limiting input terminal from the second positive output terminal to obtain a second intermediate divided signal;

[0136] a second OR gate, used for performing OR logic processing on the second intermediate divided signal received by the signal input terminal and the second current limiting control signal received by the current limiting input terminal from the first negative output terminal, and transmitting the obtained high level signal to the second power submodule through the output terminal, so as to drive the output current of the second power submodule to rise to a preset current range based on the obtained high level signal;

[0137] and when the first pulse width modulation signal is in the second half cycle;

[0138] A first AND gate is used for performing AND logic processing on the first pulse width modulation signal received by the signal input terminal and the high level signal received by the current limiting input terminal from the first positive output terminal to obtain a third intermediate signal;

[0139] a first OR gate, configured to perform OR logic processing on the third intermediate branch signal received by the signal input terminal and the first current limiting control signal received by the current limiting input terminal from the second negative output terminal, and transmit the obtained high-level signal to the first power submodule through the output terminal, so as to drive the output current of the first power submodule to rise to a preset current range based on the obtained high-level signal;

[0140] A second AND gate is used for performing AND logic processing on the second pulse width modulation signal received by the signal input terminal and the second current limiting control signal received by the current limiting input terminal from the second positive output terminal to obtain a fourth intermediate branch signal;

[0141] The second OR gate is used to perform OR logic processing on the fourth intermediate branch signal received by the signal input terminal and the low level signal received by the current limiting input terminal from the first negative output terminal, and transmit the obtained low level signal to the second power sub-module through the output terminal to drive the output current of the second power sub-module to drop to a preset current range based on the obtained low level signal.

[0142] In a Fig.13 In the illustrated embodiment, the pulse width modulation signal (including the first pulse width modulation signal and the second pulse width modulation signal) is a pulse width modulation signal, and the first logic submodule includes a first AND gate AND1 and a first OR gate OR2. The first AND gate AND1 receives the first pulse width modulation signal based on the signal input terminal, and performs AND logic processing on the high level signal or low level signal received from the first positive output terminal of the first trigger at the current limiting input terminal, and transmits the obtained intermediate sub-signal to the first OR gate OR2 through the output terminal. The first OR gate OR2 performs OR logic processing on the intermediate sub-signal received at the signal input terminal, and the high level signal or low level signal received from the second negative output terminal of the second trigger at the current limiting input terminal. And as Fig.14As shown, it is a structural schematic diagram of a second logic submodule provided in an embodiment of the present application, the second logic submodule includes a second AND gate AND2 and a second OR gate OR3, the second AND gate AND2 receives the second pulse width modulation signal based on the signal input terminal, and performs AND logic processing on the high level signal or low level signal received from the second positive output terminal of the second trigger at the current limiting input terminal, and transmits the obtained intermediate divided signal to the second OR gate OR3 through the output terminal, and the second OR gate OR3 performs OR logic processing on the intermediate divided signal received at the signal input terminal, and the high level signal or low level signal output from the first negative output terminal of the first trigger at the current limiting input terminal.

[0143] Based on the above Figure 2-14 The circuit and related embodiments shown in , the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal,

[0144] Under the triggering of the current limiting indication signal:

[0145] The first current limiting submodule adjusts the first pulse width modulation signal in the first logic submodule through the first current limiting control signal in the first time period, so that the first output current drops to within the preset current range; and adjusts the second pulse width modulation signal in the second logic submodule through the second current limiting control signal, so that the second output current rises to within the preset current range;

[0146] Or the second current limiting submodule adjusts the second pulse width modulation signal in the second logic submodule through the second current limiting control signal in the second time period, so that the second output current drops to within the preset current range, and adjusts the first pulse width modulation signal in the first logic submodule through the first current limiting control signal, so that the first output current rises to within the preset current range; the first time period and the second time period correspond to different intervals in the pulse width modulation signal cycle.

[0147] In one embodiment, if the pulse width modulation signal is obtained by a differential signal, the first time period is the first half cycle of the pulse width modulation signal, and the second time period is the second half cycle of the pulse width modulation signal, the current limiting processing process of the first logic submodule and the second logic submodule includes:

[0148] When the first pulse width modulation signal is in the first half cycle:

[0149] The first AND gate AND1 performs AND logic processing based on the first pulse width modulation signal and the first current limiting control signal (VOP_DN_ENN which is a low level signal) output from the first positive output terminal of the first trigger, and transmits the obtained first intermediate divided signal to the first OR gate OR2. The first OR gate OR2 performs AND logic processing based on the received first intermediate divided signal and the low level signal output from the second negative output terminal of the second trigger, and obtains a low level signal. Then, based on the low level signal, the output current of the first power submodule is driven to drop to a preset current range. At the same time, the second AND gate AND2 performs AND logic processing based on the second pulse width modulation signal and the first negative output terminal of the second trigger. The high-level signal output from the second positive output terminal is processed with an AND logic, and the obtained second intermediate divided signal is transmitted to the second OR gate OR3. The second OR gate OR3 performs an AND logic processing based on the received second intermediate divided signal and the second current limiting control signal (high-level signal - VON_UP_EN) output from the first negative output terminal of the first trigger to obtain a high-level signal. Subsequently, based on the high-level signal, the output current of the second power sub-module is driven to rise to within the preset current range. Then, the output current of the first power sub-module and the second power sub-module becomes smaller, and accordingly, the load current of the load connected to the first power sub-module and the second power sub-module becomes smaller.

[0150] When the first PWM signal is in the second half cycle:

[0151] The first AND gate AND1 performs AND logic processing based on the first pulse width modulation signal and the high level signal output from the first positive output terminal of the first trigger, and transmits the obtained third intermediate divided signal to the first OR gate OR2. The first OR gate OR2 performs AND logic processing based on the received third intermediate divided signal and the first current limiting control signal (VOP_DN_ENN which is a high level signal) output from the second negative output terminal to obtain a high level signal. Subsequently, based on the second intermediate divided signal which is a high level signal, the output current of the first power submodule is driven to rise to a preset current range. The second AND gate AND2 performs AND logic processing based on the second pulse width modulation signal and the second positive output terminal of the second trigger. The second current limiting control signal (low level signal -VON_DN_ENN) output from the output end is processed with AND logic, and the obtained fourth intermediate sub-signal is transmitted to the second OR gate OR3. Then, the second OR gate OR3 performs AND logic processing based on the received fourth intermediate sub-signal and the low level signal output from the first negative output end to obtain a low level signal. Subsequently, based on the fourth intermediate sub-signal which is a low level signal, the output current of the second power sub-module is driven to drop to a preset current range, and at the same time, the output current of the first power sub-module is increased. Then, the output current of the first power sub-module and the second power sub-module becomes smaller, that is, the load current of the load connected to the two outputs becomes smaller.

[0152] Based on the above Figure 2-15Any of the circuits shown in and its related embodiments, an embodiment of the present application provides a current limiting module, which is used to simultaneously adjust the duty cycle of the pulse width modulation signal in the first logic sub-module and the second logic sub-module, so that the output current of the first power sub-module and the second power sub-module is maintained within a preset current range.

[0153] In one embodiment, if Fig.15 As shown, a pulse width modulation signal and its analog signal provided by an embodiment of the present application, wherein: Fig.15 (a) may be a differential signal of a first pulse width modulation signal of a first logic submodule and its corresponding analog signal, Fig.15 (b) may be a differential signal of the second pulse width modulation signal of the second logic submodule and its corresponding analog signal, and the analog signal may be an analog signal representing physical information such as temperature, humidity, pressure, length, current, voltage, etc. It should be noted that the pulse width modulation signal and the analog signal are only an example used by the present application to clearly illustrate the present solution. In implementation, the amplitude, period, frequency of the waveform, and the influence of the environment on the waveform may all produce different analog signals and pulse width modulation signals, which are not limited here.

[0154] Based on the above Figure 2-15 Any circuit and related embodiments in Fig.16 As shown, an overcurrent protection circuit is provided for an embodiment of the present application, and a filtering module is arranged between the overcurrent protection module and the current limiting module, and the filtering module is used to filter the current limiting indication signal.

[0155] In one embodiment, the filtering module may include an RC circuit (full name: resistor-capacitance circuit), which may be an RC series circuit or an RC parallel circuit.

[0156] Based on the above Fig.16 The circuit in this application embodiment provides a filtering module, such as Fig.17 As shown, the filtering module includes an input inverter INV3, a resistor R1, a Schmitt trigger SMT1, an intermediate inverter INV4 and an output inverter INV5 connected in sequence, a grounding branch is branched between the resistor R1 and the Schmitt trigger SMT1, and a transmission gate TG1 and a capacitor C1 are provided in series on the grounding branch, and the capacitor C1 is grounded.

[0157] In one embodiment, the current limiting indication signal can be a pulse signal with a certain pulse width. In order to prevent the overcurrent protection from being triggered by mistake, the pulse signal needs to be filtered out of interference signals. The pulse width that can be filtered out by the filter module is controlled by a 2-bit register. By configuring CBC_DEGLITCH_SEL<1:0> to enable different transmission gate TG1 switches, different sizes of capacitors C1 are switched to achieve different signal delay times, thereby achieving the purpose of selecting different pulse filtering widths and increasing the flexibility of filtering.

[0158] The current limiting indication signal is inverted by the input inverter INV3, and passes through a filtering network composed of a resistor R1, a transmission gate TG1 and a capacitor C1. Based on the switched capacitor of a certain size, the high-frequency part of the current limiting indication signal is brought to ground to eliminate the interference signal in the current limiting indication signal, and then enters the Schmitt trigger SMT1. The Schmitt trigger SMT1 has a hysteresis function, which can prevent the logic from being incorrectly flipped due to signal jitter, and then prevent the overcurrent protection from being falsely triggered. If the pulse width modulation signal is obtained based on the audio, it can prevent the audio from stopping suddenly and improve the robustness of the audio playback. Then, the signal passing through the Schmitt trigger SMT1 passes through the intermediate inverter INV4 and the output initiator INV5 and reaches the output OUT end and is sent to the current limiting module.

[0159] Based on the above Figure 2-17 In any circuit and related embodiments, the sampling module includes a first sampling half-bridge circuit and a second sampling half-bridge circuit; the first power submodule includes a first driving module and a first power half-bridge circuit, and the second power submodule includes a second driving module and a second power half-bridge circuit;

[0160] The first driving module is connected to the first power half-bridge circuit, and is used to drive the first power half-bridge circuit to amplify the first pulse width modulation signal;

[0161] The first sampling half-bridge circuit is connected to the first power half-bridge circuit and is used to sample a first output current of the first power half-bridge circuit;

[0162] The second driving module is connected to the second power half-bridge circuit, and is used to drive the second power half-bridge circuit to perform signal amplification processing on the second pulse width modulation signal;

[0163] The second sampling half-bridge circuit is connected to the second power half-bridge circuit and is used for sampling a second output current of the second power half-bridge circuit.

[0164] In one embodiment, the first power half-bridge circuit is formed by two transistors connected in series, and the second power half-bridge circuit is formed by two transistors connected in series, and the first pulse width modulation signal and the second pulse width modulation signal can be amplified respectively.

[0165] In one embodiment, in order to reduce the impact of the environment on the sampled output current, the first sampling half-bridge circuit and the second sampling half-bridge circuit can also be designed to be composed of two series-connected transistors to improve the accuracy of the sampled output current.

[0166] In one embodiment, if Fig.18 As shown, a schematic diagram of the structure of a CBC (cycle-by-cycle current limiting protection) system including a current limiting protection circuit provided in an embodiment of the present application is provided, which mainly includes: a first logic submodule (including AND1 and OR2), a second logic submodule (including AND2 and OR3), a first power submodule (including a first drive module (gate drive module), a first power half-bridge circuit), a second power submodule (including a second drive module (gate drive module), a second power half-bridge circuit), a sampling module (including a first sampling half-bridge circuit (including 2 sampling tubes: M2A, M4A) and a second sampling half-bridge circuit (including 2 sampling tubes: M2B, M4B)), an OC overcurrent protection module, a filtering module (pulse filtering module), a current limiting module (CBC current limiting module_A and CBC current limiting module_B), and the current limiting module may also include OR1, which is used to report the overcurrent and current limiting situation of the corresponding monitoring module when generating the first current limiting control signal and the second current limiting control signal, such as the corresponding monitoring module may be a log module.

[0167] The main signal names in the system design block diagram of this application are explained as follows:

[0168] CBC system, an overcurrent-current limiting system using the above-mentioned current limiting protection circuits;

[0169] VOP: load positive end, corresponding to end A;

[0170] VON: negative end of load, corresponding to terminal B;

[0171] PWMA / B: pulse width modulation signal output by CLASS_D at the A / B terminal, that is, PWMA is the first pulse width modulation signal, and PWMB is the second pulse width modulation signal;

[0172] PWMOA / B: PWMA / B signal is sent to the A / B end gate drive module as a pulse width modulation signal after logic processing;

[0173] CBC_UP / DN_A: Current limiting indication signal when the upper N-tube / lower N-tube current at the A end reaches the CBC current limiting value (the interval boundary of the preset current range), and the high level is valid;

[0174] CBC_UP / DN_B: Current limiting indication signal when the upper N-tube / lower N-tube current at the B terminal reaches the CBC current limiting value (the interval boundary of the preset current range), and the high level is valid;

[0175] CLK_CBC: CBC logic control clock (clock signal);

[0176] VOP_DN_ENN: CBC current limiting control signal (the first half cycle of the first pulse width modulation signal is the first current limiting control signal): indicates that this signal pulls the VOP signal low, and the low level is valid;

[0177] VOP_UP_EN: CBC current limiting control signal (the first current limiting control signal in the second half cycle of the first pulse width modulation signal): indicates that this signal pulls the VOP signal high, and the high level is valid;

[0178] VON_DN_ENN: CBC current limiting control signal (the first half cycle of the first pulse width modulation signal is the second current limiting control signal): indicates that this signal pulls the VON signal low, and the low level is valid;

[0179] VON_UP_EN: CBC current limiting control signal (the first half cycle of the first pulse width modulation signal is the second current limiting control signal): indicates that this signal pulls the VON signal high, and the high level is valid;

[0180] CBC_A / B: CBC trigger signal output by the CBC current limiting module at both ends of A and B;

[0181] CBC_S: CBC trigger indication signal, high level is valid;

[0182] The CBC triggering process is as follows:

[0183] OC determines whether there is overcurrent by sampling the output current sampled by the sampling module. The current limiting indication signal output by OC is divided into two groups. Among them, in the first half cycle of the first pulse width modulation signal, CBC_UP_A and CBC_DN_B are a group of current limiting indication signals, which means that the upper N-tube of the A end and / or the lower N-tube of the B end triggers CBC. At this time, the current flows from VOP to VON; in the second half cycle of the first pulse width modulation signal, CBC_UP_B and CBC_DN_A are a group of current limiting indication signals, which means that the upper N-tube of the B end and / or the lower N-tube of the A end triggers CBC. At this time, the current flows from VON to VOP. Note: the above two situations cannot occur at the same time.

[0184] Next, the high and low levels of each signal in the CBC system when the overcurrent limit is not triggered are analyzed:

[0185] first step:

[0186] After receiving the output current reported by the sampling tubes of the first sampling half-bridge circuit and the second sampling half-bridge circuit, the OC makes a comparison based on the preset current range. The first output current and the second output current do not exceed the preset current range. Therefore, under normal circumstances, each output is as follows:

[0187] CBC_UP_A (low level, expressed as 0), CBC_DN_B (low level, expressed as 0) --

[0188] >DEGLITCH-->OR4

CBC_UP_A(0), CBC_DN_B(0)

[0189] CBC_DN_A (low level, expressed as 0), CBC_UP_B (low level, expressed as 0) --

[0190] >DEGLITCH-->OR5

CBC_DN_A(0),CBC_UP_B(0)

[0191] -->OR1

CBC_A(0), CBC_B(0)

[0192] Step 2:

[0193] CBC_A(0)-->INV1-->1-->D1(high level is invalid, not triggered)=VOP_DN_ENN(1), VON_UP_EN(0);

[0194] CBC_B(0)-->INV2-->1-->D2(high level is invalid, not triggered)=VON_DN_ENN(1), VOP_UP_EN(0);

[0195] Step 3:

[0196] AND1

VOP_DN_ENN(1), PWMA(0.1)=(0.1)

(0.1), VOP_UP_EN(0)=(0.1)

[0197] AND2

VON_DN_ENN(1),PWMB(0.1)=(0.1)

(0.1)VON_UP_EN(0)=(0.1)

[0198] like Fig.19 As shown, it is a waveform diagram of the above-mentioned related signals provided in an embodiment of the present application under normal circumstances, wherein the CBC_LIMIT signal is a signal after CBC_UP_A and CBC_DN_B are subjected to logical OR and NOT, and this signal is a control signal for the CBC current limiting module to enter a reset state or a trigger state, and is enabled at a low level.

[0199] Based on the above, four situations in which overcurrent limiting protection is triggered are given here. The first situation is that the input signal is too large or the first power submodule or the second power submodule is affected by factors such as the environment or devices, and the output current exceeds the preset current range:

[0200] In the first half cycle of the first pulse width modulation signal, the current flows from VOP to VON:

[0201] first step:

[0202] After receiving the output current reported by the sampling tubes of the first sampling half-bridge circuit and the second sampling half-bridge circuit, the OC makes a comparison based on the preset current range. If the first output current and / or the second output current exceeds the preset current range, each output is as follows:

[0203] CBC_UP_A(0), CBC_DN_B(1), or CBC_UP_A(1), CBC_DN_B(0), or CBC_UP_A(1), CBC_DN_B(1)-->DEGLITCH-->OR4=CBC_A(1);

[0204] CBC_DN_A (low level, expressed as 0), CBC_UP_B (low level, expressed as 0)-->DEGLITCH-->OR5=CBC_B(0);

[0205] -->OR1

CBC_A(1), CBC_B(0)

[0206] Step 2:

[0207] CBC_A(1)-->INV1-->0-->D1(Low level valid, trigger)=VOP_DN_ENN(0), VON_UP_EN(1);

[0208] CBC_B(0)-->INV2-->1-->D2(high level is invalid, not triggered)=VON_DN_ENN(1), VOP_UP_EN(0);

[0209] Step 3:

[0210] AND1

VOP_DN_ENN(0), PWMA(0.1)=(0)

(0), VOP_UP_EN(0)=(0)

[0211] AND2

VON_DN_ENN(1), PWMB(0.1)=(0.1)

(0.1), VON_UP_EN(1)=(1)

[0212] like Fig. 20 As shown, it is a schematic diagram of the waveform of the above-mentioned related signals provided in an embodiment of the present application under abnormal conditions in the first half cycle of the first pulse width modulation signal (taking CBC_UP_A(1) and CBC_DN_B(1) as examples).

[0213] In the second half cycle of the first pulse width modulation signal, the current flows from VON to VOP:

[0214] first step:

[0215] After receiving the output current reported by the sampling tubes of the first sampling half-bridge circuit and the second sampling half-bridge circuit, the OC makes a comparison based on the preset current range. If the first output current and / or the second output current exceeds the preset current range, each output is as follows:

[0216] CBC_UP_A(0), CBC_DN_B(0)-->DEGLITCH-->OR4=CBC_A(0);

[0217] CBC_DN_A(0), CBC_UP_B(1), or CBC_DN_A(1), CBC_UP_B(0), or CBC_DN_A(1), CBC_UP_B(1)-->DEGLITCH-->OR5=CBC_B(1);

[0218] -->OR1

CBC_A(0), CBC_B(1)

[0219] Step 2:

[0220] CBC_A(0)-->INV1-->1-->D1(high level is invalid, not triggered)=VOP_DN_ENN(1), VON_UP_EN(0);

[0221] CBC_B(1)-->INV2-->0-->D2(Low level valid, trigger)=VON_DN_ENN(0), VOP_UP_EN(1);

[0222] Step 3:

[0223] AND1

VOP_DN_ENN(1), PWMA(0.1)=(0.1)

(0.1), VOP_UP_EN(1)=(0.1)

[0224] AND2

VON_DN_ENN(0), PWMB(0.1)=(0)

(0), VON_UP_EN(0)=(0)

[0225] like Fig.21 As shown, it is a schematic diagram of the waveforms of the above-mentioned related signals provided in an embodiment of the present application under abnormal conditions in the second half cycle of the first pulse width modulation signal (taking CBC_DN_A(1) and CBC_UP_B(1) as examples).

[0226] When the positive terminal (PAD-VOP) or negative terminal (VON) of the load is short-circuited to the power supply or ground, I MAX =P VDD / R DSON , R DSON is the on-resistance of the power tube (here, it is assumed that the impedances of the two power tubes in series (the two power tubes in series of the first power half-bridge circuit and the two power tubes in series of the second power half-bridge circuit) are equal), or, when the positive end of the load (PAD-VOP) or the negative end of the load (VON) is short-circuited to each other, I MAX =P VDD / 2*R DSON ,like Fig. 22 As shown, it is a schematic diagram of a short-circuit analog signal waveform provided by an embodiment of the present application. Correspondingly, the analysis is as follows:

[0227] CBC_UP_A(1), CBC_DN_B(0)-->DEGLITCH-->OR4=CBC_A(1)

[0228] CBC_DN_A(0), CBC_UP_B(0)-->DEGLITCH-->OR5=CBC_B(0)

[0229] -->OR1

CBC_A(1), CBC_B(0)

[0230] Step 2:

[0231] CBC_A(1)-->INV1-->0-->D1(Low level valid, trigger)=VOP_DN_ENN(0), VON_UP_EN(1);

[0232] CBC_B(0)-->INV2-->1-->D2(high level is invalid, not triggered)=VON_DN_ENN(1), VOP_UP_EN(0);

[0233] Step 3:

[0234] AND1

VOP_DN_ENN(0), PWMA(0.1)=(0)

(0), VOP_UP_EN(0)=(0)

[0235] AND2

VON_DN_ENN(1), PWMB(0.1)=(0.1)

(0.1), VON_UP_EN(1)=(1)

[0236] like Fig.23 , which is a schematic diagram of waveforms of the above-mentioned related signals provided in an embodiment of the present application under abnormal conditions of short circuit.

[0237] Based on the above Figure 2-6 , Figure 8 , Fig. 9 , Fig.13 , Fig.14 , Figure 16-18 A current limiting protection circuit, an embodiment of the present application provides an electronic device, in which any current limiting protection circuit as described above can be set.

[0238] A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is as follows: Fig.24 As shown, the electronic device may be a terminal device or a server device. The electronic device may include: a processor 2401, for example, a CPU, a network interface 2404, a user interface 2403, a memory 2405, and a communication bus 2402. Among them, the communication bus 2402 is used to realize the connection and communication between these components. The user interface 2403 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the optional user interface 2403 may also include a standard wired interface and a wireless interface. The network interface 2404 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 2405 may be a high-speed RAM memory, or a stable memory (non-volatile memory), for example, a disk memory. The memory 2405 may optionally be a storage device independent of the aforementioned processor 2401, which may include an operating system, a network communication module, a user interface module, a software program module, etc.

[0239] Those skilled in the art will understand that Fig.24The device structure shown in the figure does not constitute a limitation on the device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. The chips in each component can be adaptively adopted as described in the present application. Figure 2-6 , Figure 8 , Fig. 9 , Fig.13 , Fig.14 , Figure 16-18 Current limiting protection circuit.

[0240] Based on the above Fig.24 An electronic device in the present application provides a structural diagram of an electronic device connected to an external device, such as Fig.25 As shown, the electronic device is connected to each external device and the set external device of the set interface based on a bus.

[0241] Based on the same concept as the above-mentioned current limiting protection circuits and related embodiments, and electronic devices, such as Fig.26 As shown, the present application embodiment provides a flow chart of a current limiting protection method, including:

[0242] Step 2601: sampling a first output current of a first power submodule and a second output current of a second power submodule, and generating a current limiting indication signal when at least one of the first output current and the second output current exceeds a preset current range;

[0243] Step 2602: Generate a first current limiting control signal and a second current limiting control signal in response to the current limiting indication signal, and transmit the first current limiting control signal to the first logic submodule, and transmit the second current limiting control signal to the second logic submodule, so as to simultaneously adjust the pulse width modulation signals in the first logic submodule and the second logic submodule, so that the output currents of the first power submodule and the second power submodule are maintained within a preset current range.

[0244] Based on the above Fig.26 In the current limiting protection method flow shown in the figure, the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, and the first pulse width modulation signal and the second pulse width modulation signal are obtained according to the differential signal. Then, in step 2602, the pulse width modulation signals in the first logic submodule and the second logic submodule are adjusted simultaneously, including:

[0245] In a first time period, the first pulse width modulation signal is processed in response to the first current limiting control signal so that the first output current drops within the current range; the second pulse width modulation signal is processed in response to the second current limiting control signal so that the second output current rises within the current range;

[0246] In the second time period, the first pulse width modulation signal is processed in response to the first current limiting control signal so that the first output current rises within the current range; the second pulse width modulation signal is processed in response to the second current limiting control signal so that the second output current drops within the current range.

[0247] Based on the above Fig.26 In the current limiting protection method flow shown, the pulse width modulation signal is a pulse width modulation signal, then in step 2602, the pulse width modulation signals in the first logic submodule and the second logic submodule are adjusted simultaneously so that the output currents of the first power submodule and the second power submodule are kept within the current range, including:

[0248] The duty ratios of the pulse width modulation signals in the first logic submodule and the second logic submodule are adjusted simultaneously, so that the output currents of the first power submodule and the second power submodule are maintained within a preset current range.

[0249] Based on the above Fig.26 The current limiting protection method process shown in the figure, then after step 2602, in response to the clock signal, stop generating the first current limiting control signal and the second current limiting control signal, and then, step 2601 can also be executed. Then, in a possible implementation manner, there is a situation where steps 2601 and 2602 are executed cyclically, and the step of stopping generating the control signal in response to the clock signal is performed here.

[0250] Based on the above Fig.26 In the overcurrent protection method flow shown, in step 2602, before generating the first current limiting control signal and the second current limiting control signal in response to the current limiting indication signal, the current limiting indication signal is filtered.

Claims

1. A current limiting protection circuit, characterized in that: include: The sampling module, overcurrent protection module, current limiting module, logic module and power module are connected in sequence; The logic module includes a first logic submodule and a second logic submodule, wherein the current limiting module is connected to the first logic submodule and the second logic submodule respectively; The power module includes a first power submodule and a second power submodule, wherein the first logic submodule is connected to the first power submodule, the second logic submodule is connected to the second power submodule, and the first power submodule and the second power submodule are respectively connected to the sampling module; When at least one of the first output current and the second output current respectively received by the sampling module from the first power sub-module and the second power sub-module exceeds a preset current range, the overcurrent protection module generates a current limiting indication signal, and the current limiting module jointly adjusts the pulse width modulation signal input to the first logic sub-module and the second logic sub-module according to the current limiting indication signal with the first logic sub-module and the second logic sub-module, so that the output current of the first power sub-module and the second power sub-module remains within the preset current range.

2. The current limiting protection circuit according to claim 1, characterized in that: The current limiting module includes a first current limiting submodule and a second current limiting submodule; The first positive output terminal of the first current limiting submodule is connected to the first logic submodule, and the first negative output terminal is connected to the second logic submodule; The second positive output terminal of the second current limiting submodule is connected to the second logic submodule, and the second negative output terminal is connected to the first logic submodule.

3. The current limiting protection circuit according to claim 2, characterized in that: The first current limiting submodule comprises a first OR gate, a first inverter and a first trigger connected in sequence; the second current limiting submodule comprises a second OR gate, a second inverter and a second trigger connected in sequence; The control end of the first trigger is used to receive a clock signal, the first positive output end is used to output the first current limiting control signal in a triggered state, and the first negative output end is used to output the second current limiting control signal in a triggered state; The control end of the second trigger is used to receive a clock signal, the second positive output end is used to output the second current limiting control signal in a triggered state, and the second negative output end is used to output the first current limiting control signal in a triggered state.

4. The current limiting protection circuit according to claim 3, characterized in that: The pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, the first logic submodule includes a first AND gate and a first OR gate; the second logic submodule includes a second AND gate and a second OR gate; The current limiting input terminal of the first AND gate is connected to the first positive output terminal of the first trigger, the signal input terminal receives the first pulse width modulation signal, and the output terminal is connected to the signal input terminal of the first OR gate; The current limiting input terminal of the first OR gate is connected to the second negative output terminal of the second trigger, and the output terminal is connected to the first power sub-module; The current limiting input terminal of the second AND gate is connected to the second positive output terminal of the second trigger, the signal input terminal receives the second pulse width modulation signal, and the output terminal is connected to the signal input terminal of the second OR gate; The current limiting input terminal of the second OR gate is connected to the first negative output terminal of the first trigger, and the output terminal is connected to the second power sub-module.

5. The current limiting protection circuit according to claim 2, characterized in that: The pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal. Under the triggering of the current limiting indication signal: The first current limiting submodule adjusts the first pulse width modulation signal in the first logic submodule through the first current limiting control signal in a first time period, so that the first output current drops within the preset current range; and adjusts the second pulse width modulation signal in the second logic submodule through the second current limiting control signal, so that the second output current rises within the preset current range; or the second current limiting submodule adjusts the second pulse width modulation signal in the second logic submodule through the second current limiting control signal in the second time period so that the second output current drops within the preset current range; and adjusts the first pulse width modulation signal in the first logic submodule through the first current limiting control signal so that the first output current rises within the preset current range; The first time period and the second time period correspond to different intervals in a pulse width modulation signal cycle.

6. The current limiting protection circuit as claimed in claim 1, characterized in that: The current limiting module is used to simultaneously adjust the duty cycle of the pulse width modulation signal in the first logic submodule and the second logic submodule, so that the output current of the first power submodule and the second power submodule is maintained within the preset current range.

7. The current limiting protection circuit as claimed in claim 1, characterized in that: A filtering module is provided between the overcurrent protection module and the current limiting module, and the filtering module is used to filter the current limiting indication signal.

8. The current limiting protection circuit according to claim 7, characterized in that: The filtering module comprises an input inverter, a resistor, a Schmitt trigger, an intermediate inverter and an output inverter connected in sequence, a grounding branch is branched between the resistor and the Schmitt trigger, a transmission gate and a capacitor connected in series are arranged on the grounding branch, and the capacitor is grounded.

9. An electronic device, characterized in that: The electronic device comprises the current limiting protection circuit as claimed in any one of claims 1 to 8.

10. A current limiting protection method, characterized in that: The method comprises: Sampling a first output current of a first power submodule and a second output current of a second power submodule, and generating a current limiting indication signal when at least one of the first output current and the second output current exceeds a preset current range; A first current limiting control signal and a second current limiting control signal are generated in response to the current limiting indication signal, and the first current limiting control signal is transmitted to the first logic submodule, and the second current limiting control signal is transmitted to the second logic submodule, so as to simultaneously adjust the pulse width modulation signals in the first logic submodule and the second logic submodule, so that the output currents of the first power submodule and the second power submodule are maintained within the preset current range.

11. The current limiting protection method according to claim 10, characterized in that: The pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are obtained according to a differential signal, and the simultaneously adjusting the pulse width modulation signals in the first logic submodule and the second logic submodule includes: In a first time period, the first pulse width modulation signal is processed in response to the first current limiting control signal so that the first output current drops within the preset current range; the second pulse width modulation signal is processed in response to the second current limiting control signal so that the second output current rises within the preset current range; In a second time period, the first pulse width modulation signal is processed in response to the first current limiting control signal so that the first output current rises within the preset current range; the second pulse width modulation signal is processed in response to the second current limiting control signal so that the second output current falls within the preset current range; The first time period and the second time period correspond to different intervals in a pulse width modulation signal cycle.

12. The current limiting protection method according to claim 10 or 11, characterized in that: The simultaneously adjusting the pulse width modulation signals in the first logic submodule and the second logic submodule so that the output currents of the first power submodule and the second power submodule are maintained within the preset current range includes: The duty ratios of the pulse width modulation signals in the first logic submodule and the second logic submodule are adjusted simultaneously, so that the output currents of the first power submodule and the second power submodule are maintained within the preset current range.

13. The current limiting protection method according to claim 10, characterized in that: Before generating the first current limiting control signal and the second current limiting control signal in response to the current limiting indication signal, filtering is performed on the current limiting indication signal.

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