Method implemented in a phase controller of a multi-phase switching converter

Abstract

The phase controller of a multi-phase switching converter provided according to one aspect of the present disclosure provides corresponding phase control signals to multiple power stages, which work together to provide a stable supply voltage from an input voltage. The phase controller activates a group of power stages (power stage set) and keeps the remaining power stages in an inactive state. The first power stage in the group of activated power stages operates as the main stage. When it is necessary to support the current load current, the phase controller changes this group of power stages. When implementing this change, if the number of stages in the power stage set is greater than or equal to the threshold number, the phase controller selects other power stages except the first power stage from the changed power stage set as the main stage.

Description

[0001] Priority declaration

[0002] This patent application is related to and claims priority from co-pending provisional Indian patent application number 202441001829, filed on January 10, 2024, entitled “Power Stage Pressure Equalization in a Multi-Phase Buck Converter by Randomizing Phase Distribution”; its attorney docket number is AURA-355-INPR, the entire contents of which are incorporated herein to the extent not inconsistent with the description herein. Technical Field

[0003] Embodiments of the present disclosure generally relate to a multi-phase switching converter, and more particularly to a method performed in a phase controller of a multi-phase switching converter, a phase controller of a multi-phase switching converter, and a multi-phase switching converter. Background Art

[0004] A switching converter is a component that converts an input alternating current (AC) or direct current (DC) voltage of a certain magnitude into an output DC voltage of a desired magnitude by using and operating a switching element, which is well known in the relevant art. A switching converter can be used, for example, as a stand-alone power supply or as a voltage regulation module in devices such as laptop computers and mobile phones.

[0005] Switching converters usually use multiple power stages that together generate the required DC voltage. During the corresponding operation period, the power stage used is called the active stage. Each active power stage generates a corresponding portion of the required load current in the corresponding phase of the phase sequence, so this switching converter is called a multi-phase switching converter.

[0006] The power stages are controlled by the phase controller via corresponding phase control signals. The phase controller controls the addition and removal / removal of power stages based on factors such as load current requirements, which means that the set of active stages changes as power stages are added / removed.

[0007] The phase controller can operate one of the power stages as a "master" for a given duration, which means that the master is always included in the set of active stages even if there are additions and / or deletions of power stages during the given duration. Thus, the master remains active for the entire (given) duration, regardless of the load current.

[0008] It is generally recognized that there is a need to modify the primary stage in a multi-phase switching converter. Aspects of the present disclosure relate to modifying the primary stage in a multi-phase switching converter. Summary of the invention

[0009] The phase controller of a multi-phase switching converter provided according to one aspect of the present disclosure provides corresponding phase control signals to multiple power stages, which work together to provide a stable supply voltage from an input voltage. The phase controller activates a group of power stages (power stage set) and keeps the remaining power stages in an inactive state. The first power stage in the group of activated power stages operates as the main stage. When it is necessary to support the current load current, the phase controller changes this group of power stages. When implementing this change, if the number of stages in the power stage set is greater than or equal to the threshold number, the phase controller selects other power stages except the first power stage from the changed power stage set as the main stage.

[0010] It will be appreciated that changing the master stage can reduce stress on a single power stage that would otherwise continue to operate as the master stage. It will also be appreciated that when the number of active stages exceeds a threshold number, selecting the previously active stage as the new master stage can prevent transients in the stable supply voltage.

[0011] According to another aspect, the phase controller includes a phase activator and a main phase selector. The phase activator receives information including the current load current demand and generates an active phase signal. The active phase signal indicates a set of power stages that are driven to an activated state to support the load current demand. The main phase selector receives the active phase signal and generates a main phase signal. The main phase signal indicates the power stage in the power stage set to be operated as the main stage. When it is necessary to support the current load current, the phase activator changes the power stage set. If the number of stages is greater than or equal to the threshold number, the main phase selector selects a power stage other than the first power stage as the main stage in the changed power stage set.

[0012] According to another aspect of the present disclosure, a phase controller includes a main control signal generator module. The main control signal generator module receives a stable supply voltage and a reference voltage of a desired amplitude and generates a common control signal. The common control signal has a periodic transition generated based on the amplitude difference between the reference voltage and the stable supply voltage. A phase distributor of the phase controller receives the common control signal and generates a corresponding phase control signal synchronized with the transition of the common control signal.

[0013] According to another aspect of the present disclosure, a multiphase switching converter includes a plurality of tracks, each track corresponding to an operable main stage. In one embodiment, the threshold number is equal to the total number of power stages, so that the main stage corresponding to the first track is changed only when all power stages assigned to the first track work as a changed power stage set, wherein the first track provides a stable supply voltage.

[0014] In one embodiment, the master phase selector selects the master stage in a round-robin order among the power stages in the changed set of power stages.

[0015] Several aspects of the present disclosure will be described below by way of example. However, those skilled in the relevant art will recognize that the present disclosure may be implemented even if one or more specific details are missing or other methods, components, materials, etc. are used. In other cases, well-known constructions, materials, or operations are not shown in detail to avoid obscuring the features of the present disclosure. In addition, the described features / aspects may be practiced in a variety of combinations, but for brevity, only some of these combinations are described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Example embodiments of the present disclosure will be described with reference to the accompanying drawings, which are briefly described below.

[0017] Figure 1 A block diagram of an example system is shown in which aspects of the present disclosure may be implemented.

[0018] Figure 2 is a block diagram showing in detail the multi-phase switching converter in the embodiment of the present disclosure.

[0019] Figure 3 is a flow chart illustrating how a phase controller operates to change the primary phase of a multi-phase switching converter according to one aspect of the present disclosure.

[0020] Figure 4 It is a block diagram showing the implementation of the phase controller in one embodiment of the present disclosure.

[0021] Figure 5 This is a block diagram showing the implementation of a phase distributor in a phase controller in one embodiment of the present disclosure.

[0022] Figure 6 It is a block diagram showing the implementation of the loop unit in one embodiment of the present disclosure.

[0023] Figure 7 is a timing diagram (not drawn to scale) illustrating phase management and primary level changes in one embodiment of the present disclosure.

[0024] Fig. 8A and Figure 8B A table showing the main level changes in two example scenarios in one embodiment of the present disclosure.

[0025] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0026] 1. Example system

[0027] Figure 1 1 shows a block diagram of an example system in which aspects of the present disclosure may be implemented. The illustrated system 100 includes a power supply 110, a central processing unit (CPU) 120, a storage device 130, a network interface 140, and peripheral devices 150. In one embodiment, the system 100 corresponds to a computer (desktop, laptop, etc.), although in other embodiments, the system 100 may represent other types of systems. It is understood that the system 100 may include more than one computer. Figure 1 More or fewer modules as shown.

[0028] CPU 120 generally represents a processor or a system on a chip (SoC), and as shown, it receives a pair of supply voltages (Va and Vb) from power supply 110 via paths 112A and 112B, respectively. As an example, Va may be at a lower voltage than Vb and may be used to power the core portion of the CPU, which may include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb may be used to power the rest of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals to power supply 110 (all of which are considered to be included in path 121) that indicate a number of requirements, including its power requirements. Examples of such signals may be those that specify a particular operating mode (in terms of power consumption), such as PS1, PS2, PS3, etc., which refer to "power saving states for improved efficiency."

[0029] Storage device 130 represents a type of memory that can include both volatile and non-volatile memory. For example, in a personal computer, the storage device can include magnetic memory (hard disk) as well as solid-state memory (RAM, flash memory, etc.). Storage device 130 is shown as receiving a supply voltage on path 113 for powering various circuits and modules therein.

[0030] The network interface 140 is used to implement two-way communication between the system 100 and a computer network (usually the Internet). The network interface 140 implements the use of specific physical layer and data link layer standards (such as Ethernet or Wi-Fi). TM ) for communication. Network interface 140 may also include a network protocol stack to allow communication with other computers within the same local area network (LAN) and large-scale network communication through routable protocols such as the Internet Protocol (IP). Network interface 140 receives power from path 114 to power internal circuits and modules. Network interface 140 receives data from external systems and sends data to CPU 120 via path 141 and path 124, respectively.

[0031] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power on path 115 and communicates with external devices via path 151 .

[0032] The power supply 110 obtains power from one or more power sources (e.g., a battery) on the path 101 and is used to provide the required supply voltage on the paths 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 is designed to internally include one or more multi-phase DC-DC converters for generating the supply voltage. The power supply 110 responds to the signal from the CPU 120 received on the path 121 to control the multi-phase converter to reduce / increase the current output according to a specific signal (e.g., PS1, PS2, and PS3).

[0033] In this embodiment, the power supply 110 is a voltage regulation module (VRM), sometimes also referred to as a processor power module (PPM), which includes one or more step-down switching (Buck) converters for generating multiple lower voltages from a higher voltage power supply. However, in other embodiments, other types of DC-DC converters, such as boost converters, buck-boost converters, hysteretic converters, etc., can also be used instead of buck converters. With the help of VRM, multiple devices / ICs requiring different supply voltages can be installed on the same platform, such as a computer motherboard of a personal computer (PC). Therefore, the following will describe the following. Figure 2 The VRM shown is implemented as a multi-phase switching converter.

[0034] 2. Multiphase switching converter

[0035] Figure 2 is a block diagram showing in detail the power supply 110 ( Figure 1 (in) details. Figure 1 The power supply 110 in the figure is implemented as a multi-phase switching converter that generates two regulated power supplies (power rails) Va (240) and Vb (250), and as shown in the figure, it includes a phase controller 210, smart power stages (power stages) (SPS) SPSA-1 (220-1) to SPSA-6 (220-6), SPSB-1 ​​(230-1) to SPSB-10 (230-10), inductors 225A-1 to 225A-6, 227B-1 to 227B-10, output capacitors 226A-1 to 226A-6, 228B-1 to 228B-10, and bootstrap capacitors 224A-1 to 224A-6, 224B-1 to 224B-10.

[0036] In this example, the power source Va (240) is generated by a 6-phase buck converter (with six smart power stages, numbered 220-1 to 220-6), while the power source Vb (250) is generated by a 10-phase buck converter (with ten smart power stages, numbered 230-1 to 230-10). Nodes / paths 240 and 250 correspond to Figure 1 Paths 112A and 112B in FIG. ... Figure 2 Not shown are the other power circuits that generate the power supplies on paths 113, 114, and 115. Thus, in the exemplary embodiment, the total number of power stages in multiphase switching converter 110 is 16, of which six SPS are "assigned" to rail Va (240) and ten SPS are assigned to rail Vb (250).

[0037] Each bootstrap capacitor associated with an SPS in the figure is connected between the SW and BOOT nodes of the corresponding SPS. Thus, the bootstrap capacitor 224A-1 is shown as being connected between the switch nodes SWA-1 (221) and BOOTA-1 (215-1). Although the bootstrap capacitors are shown as being connected external to each SPS, in alternative embodiments, the bootstrap capacitors may also be located internal to the SPS.

[0038] Depending on the context, power levels 220-1 to 220-6 may be collectively or individually referred to by the digital identifier 220, as may be clear from the context. In addition, signals / nodes 211-1 to 211-6, 213-1 to 213-6, 221-1 to 221-6 may be collectively or individually referred to by the digital identifiers 211, 213, and 221, as may be clear from the context. Similar conventions are followed for other blocks / components / signals in the present disclosure. Since power levels function in corresponding phases, the terms "power level" and "phase" may be used interchangeably in the present disclosure, as may be clear from the context.

[0039] Each power stage can be implemented as a high-side switch, a low-side switch, a gate drive circuit for the two switches, and other circuits. Examples of other circuits include, but are not limited to, temperature monitoring circuits, inductor current detection (or simulation) circuits, etc., to provide information such as the temperature of the SPS / power stage, the magnitude of the inductor current, etc. to the phase controller 210. Each SPS receives a power supply as an input, which is connected to the high-side switch. In Figure 2, the power supply is numbered 201 and has a voltage Vin. In one embodiment, the value of Vin is 21 volts (V), while the voltage values ​​of Va and Vb are 3.3V and 1.8V, respectively. As shown, each SPS receives a voltage Vcc on path 202. In one embodiment, the voltage of Vcc is 3.3V and is provided by phase controller 210.

[0040] Each SPS communicates with the phase controller 210 via corresponding PWM, CS and TMP signals. Thus, SPSA-1 is shown connected to the phase controller 210 via signals / paths PWMA-1 (211), CSA-1 (213-1) and TMPA (214). SPSA-6 communicates with the phase controller 210 via signals PWMA-6, CSA-6 and TMPA (214). Similarly, SPSB-1 ​​is shown connected to the phase controller 210 via signals / paths PWMB-1 (216-1), CSB-1 (218-1) and TMPB (219). SPSB-10 communicates with the phase controller 210 via signals PWMB-10, CSB-10 and TMPB (219). The other SPSs have similar connections to the phase controller 210.

[0041] The TMP signal is the output of the SPS to the phase controller 210, which provides information about the internal temperature of the SPS. The phase controller 210 can process the TMP signal (or the information contained therein) to adjust the current provided by the phase, or to shut down the VRM. The TMP outputs of each phase of the converter are connected together, and a single input is connected to the phase controller 210.

[0042] The CS signal (current sense) is the input of the phase controller 210, which comes from the SPS and contains information indicating the magnitude of the inductor current of the phase. The information can be in the form of current, voltage, value, etc.

[0043] The PWM signal is an input to the SPS, which comes from the phase controller 210 and can be regarded as a "phase control signal" that controls the operation (ON and OFF states) of the power switches in the SPS of the corresponding phase. In one embodiment of the present disclosure, the PWM signal is a pulse width modulation (PWM) signal. Therefore, in this embodiment, the PWM signal is a fixed frequency, variable duty cycle signal. The duty cycle of the PWM signal is set by the phase controller 210 to generate the required supply voltage and / or control / change the current provided by the phase. For example, the duty cycle of PWMA-1 (211-1) will be set based on the amplitude of Va (240) and the current provided by SPSA-1 (220-1). However, in general, the PWM signal may have other characteristics, depending on the specific implementation details of the power supply 110.

[0044] For example, in another embodiment, the phase controller 210 can use a constant on-time control technique to generate Va. Therefore, in such an embodiment, the PWM signal is a variable frequency, fixed pulse width (constant on-time) signal (such as a pulse frequency modulated signal, although the abbreviation PWM is still used to refer to such a signal for ease of reference). The frequency of the signal is generally proportional to the desired regulated voltage (Va) and the load current. In another embodiment, the PWM signal can switch between a constant on-time variable frequency signal and a fixed frequency pulse width modulated signal based on the load current demand, the expected efficiency of the power supply 110, and other relevant factors, which will be apparent to those skilled in the relevant art.

[0045] One cycle / cycle of the signal PWM consists of two intervals: in the first interval, only the high-side (HS) switch of the SPS is switched to ON; in the second interval, only the low-side (LS) switch of the SPS is switched to ON. The PWM signal (or more commonly, the drive signal derived from the PWM signal) controls the opening and closing of the high-side switch and the low-side switch of the SPS. It is well known in the relevant art that the PWM signals of each SPS of the same multi-phase voltage regulator are interleaved / interleaved, that is, delayed in phase with each other, so that usually no two high-side switches in the converter (i.e., each SPS) are turned on at the same time. Reasons for adopting this technique include, for example, ensuring that the peak instantaneous current extracted from Vin is always relatively low, improving efficiency, reducing fluctuations in output voltage, etc.

[0046] When the SPS detects a logic low on the PWM signal, the low-side switch is turned on; when a logic high is detected on the PWM signal, the high-side switch is turned on. When a high-impedance (hi-Z) state (usually a mid-rail voltage between power and ground) is detected on the signal PWM, the SPS turns off its high-side and low-side switches. Therefore, the SPS is considered "active" when the corresponding PWM signal switches between high and low states, thereby contributing to the output voltage and current; and the SPS is considered "inactive" when the corresponding PWM signal is in a high-impedance state (i.e., a mid-rail voltage between a logic high and a logic low). In the inactive state, the power stage does not contribute to the load current.

[0047] The phase controller 210 controls the operation of the power stage through the above signals to provide various functions including regulation functions so that the corresponding power stage set can generate stable voltages Va and Vb. Therefore, Va and Vb are regarded as inputs to the phase controller 210 to enable one or more feedback loops within the phase controller 210 to regulate Va and Vb. The phase controller 210 also receives inductor current information (the current flowing through each inductor) from each SPS to implement various operations, such as current mode control for voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS on the same track (e.g., track Va) so that the current of each SPS is substantially equal in magnitude. For the sake of brevity, various other operations that the phase controller 210 may also perform are not mentioned here.

[0048] The phase controller 210 is also used to control the power stage to reduce / increase the current output according to the load demand. In addition, the phase controller 210 can also receive a signal (PS1, PS2, etc. as described above) from the CPU 120 indicating the desired power state in which the CPU will run from time to time. In response, the phase controller 210 can activate / deactivate one or more power stages 220 according to the power state and load current. The phase controller 210 staggers the PWM signals of the active stages (or delays turning on the high-side switch).

[0049] The phase controller 210 may be designed to implement automatic phase management (APM). Thus, the number of particular phases activated by the phase controller 210 may vary depending on a variety of factors, such as the magnitude of the load current drawn from the rail (e.g., Va240). In general, the smaller the load current, the fewer phases are activated, and vice versa. For example, the phase controller 210 may store (in internal memory) predetermined load current thresholds to determine the number of active phases. These thresholds are designed to meet a given load current requirement with substantially equal phase output currents within the maximum current range that each individual phase can provide.

[0050] For example, for a moderate load current drawn from rail Va (240), the phase controller 210 may activate three power stages to generate Va (240) and keep the other three power stages in an "inactive" mode. When the load current increases from a previous value and exceeds a predetermined threshold, the phase controller 210 may activate all six power stages assigned to rail Va (240). However, when the load current decreases from a previous value and falls below another preset threshold, the phase controller 210 may deactivate (lower or reduce) two of the three previously active power stages, thereby keeping only one power stage active while keeping the other five power stages in an inactive mode. For example, assuming that the designed maximum current of each power stage is 10 amperes (A), the phase controller 210 may use only 1 power stage when the load current is 0-10A, use 2 power stages when the load current is 10-20A, and so on.

[0051] Therefore, changes in Vin (201) / Va (240) / load current etc. may cause changes in the number of active and inactive power stages, which is called a "phase change event". Therefore, within the interval defined by two consecutive phase change events, the number of active power stages (and inactive phases) remains unchanged.

[0052] Referring to the previous example, for a medium load current, assume that the set of active power stages consists of the following power stages:

[0053] [SPSA-1(220-1) to SPSA-3(220-3)].

[0054] When the load current demand increases, all six SPSs are activated, resulting in the following set of active power stages:

[0055] [SPSA-1(220-1) to SPSA-6(220-6)].

[0056] When the load current demand is moderate again, and the three active stages are removed, the set of active power stages is:

[0057] [SPSA-1(220-1) to SPSA-3(220-3)].

[0058] When the load current demand drops further (the load current drawn from Rail A (Va240) is very low) and only one power stage is needed to meet the load current demand, only SPS-1 (220-1) remains activated and the remaining SPSs (SPS-2 (220-2) to SPS-6 (220-6)) are deactivated.

[0059] When the load current demand is moderate again, and two power stages are added, the set of active stages includes:

[0060] [SPSA-1(220-1) to SPSA-3(220-3)].

[0061] It can be observed that among the power stages in the active stage set, the phase controller 210 operates a certain power stage / phase (here SPS-1 (220-1)) as a "master stage", which remains active regardless of the load current value extracted from the track Va (240). Therefore, considering the long continuous operation period when the load current varies between the lowest level (only one power stage is required to be active) and the highest level (all power stages assigned to the track are required to be active), it can be understood that SPSA-1 (220-1) is active during the entire operation period. It can also be noted that in the above example, the active duration of SPSA-2 (220-2) and SPSA-3 (220-3) is longer than the active duration of SPS-4 (220-4) to SPS-6 (220-6). Therefore, the power stages SPSA-1 (220-1) to SPSA-6 (220-6) assigned to track Va (240) are not uniformly stressed because they are active for different periods of time, with SPSA-1 (220-1) being most stressed. This in turn may result in a shorter lifespan for SPSA-1 (220-1) compared to the other power stages.

[0062] Therefore, it is generally recognized that over time, the primary stage needs to be adjusted to balance pressure between different power stages.A phase controller 210 implemented according to aspects of the present disclosure varies the primary stage, as described below by way of example.

[0063] 3. Flowchart

[0064] Figure 3 is a flow chart showing how a phase controller of a multi-phase switching converter according to one aspect of the present disclosure changes the primary stage. Figure 1 and Figure 2 The system / multi-phase switching converter in the present invention is described for illustration only. However, many functions can also be implemented in other systems and / or other environments without departing from the scope and spirit of several aspects of the present disclosure, and technicians in the relevant fields will understand this by reading the disclosure provided herein.

[0065] In addition, those skilled in the relevant art will appreciate that, depending on the specific circumstances, the execution order of some or all steps may be different from that shown below. Various aspects of the present disclosure cover a variety of such implementations. The flowchart begins with step 301, in which the control flow immediately goes to step 310.

[0066] In step 310, the phase controller 210 activates a group of power stages while keeping the remaining power stages (assigned to the corresponding rails) inactive to support the required load current. The phase controller 210 operates one of the active power stages as a master stage.

[0067] In step 320, the phase controller 210 checks whether the set of active power stages needs to be changed to support the current load current. It is understood that not all changes in the load current require a corresponding change in the number of active stages. For example, the phase controller 210 may activate a certain number of power stages for a corresponding load current range.

[0068] If a change is required (value is "yes"), control flow will pass to step 330. If no such change is required (value is "no"), phase controller 210 will continue to check whether such a change is required and the set of active power levels has not changed.

[0069] In step 330, the phase controller 210 activates and / or deactivates additional stages / phases to support the current load current. Specifically, if the current load current is greater than a predetermined threshold, the phase controller 210 activates additional power stages; if the current load current is less than another predetermined threshold, the phase controller 210 deactivates one or more previously active power stages. The phase controller 210 continues to include the main stage in the (changed) set of active power stages.

[0070] In step 340, the phase controller 210 checks whether the number of active levels is greater than or equal to the threshold number. If the number of active levels is greater than or equal to the threshold number (the value is "yes"), the control flow goes to step 350. If the number of active levels is less than the threshold number (the value is "no"), the control flow goes to step 320, in which the phase controller 210 continues to check whether the active level set needs to be modified.

[0071] In step 350 , the phase controller 210 changes the master stage in the active stage. In other words, the new master stage is selected as one of the stages in the active stage set, which can avoid transient changes in the output. Then, control goes to step 320 .

[0072] Although the change of step 350 is shown as taking effect when the condition of step 340 is met, in another embodiment described below, the change takes effect only after a threshold duration has passed since the last major level change. In other words, the major level will change when both conditions (the threshold duration has passed since the last major level change and step 340) are met.

[0073] Therefore, the phase controller of the present disclosure is used to change the primary stage in a multi-phase switching converter. Next, implementation details of the phase controller that performs such a change in one embodiment of the present invention will be provided.

[0074] 4. Phase controller

[0075] Figure 4 4 is a block diagram showing the implementation details of the phase controller in one embodiment of the present disclosure. The phase controller 210 is shown to include a control block 410, a PWM generator 415, a phase manager 420 and a phase distributor 430. The phase manager 420 is shown to include a phase activator 425 and a main phase selector 445. For ease of understanding and clear presentation, Figure 4 Also shown are power stages 220-1 to 220-6 and corresponding inductors and capacitors. For ease of understanding, Figure 4 Only the six-phase converter including power stages SPSA-1 (220-1) to SPSA-6 (220-6) is shown, which together generate the voltage Va (240) and the corresponding parts of the phase controller 210 required to generate the voltage Va (240).

[0076] Furthermore, this article specifically points out that Figure 4 Only components relevant to understanding the present disclosure are shown. It is understood that the phase controller 210 may include more Figure 4 More or fewer modules as shown. For example, there may be more blocks 410, 415, 420 and 430 (and appropriate inputs thereto) to implement the corresponding functions of the track Vb (250). In addition, for illustrative purposes only, the phase controller 210 is described and shown as using current mode control technology. However, it must be clear that the phase controller 210 can use other types of control technology. The internal modules of the phase controller 210 can be powered by a power supply not shown in the figure.

[0077] Vref represents the desired target voltage to be provided at the node Va (240). Therefore, Vref represents a stable reference DC voltage, which is generated in a known manner inside the phase controller 210. The control block 410 receives the reference voltage Vref (401), the output voltage Va (240) (or obtains a portion of the voltage of Va using a voltage divider network) and generates a voltage Vc (411), which represents the difference between the voltage Vref (401) and Va (240), which constitutes an input to the PWM generator 415. The control block 410 may include components such as an error amplifier, a PID controller, etc., which are well known in the relevant art. The control block 410 can be implemented in a known manner.

[0078] PWM generator 415 generates signal PWM-CLK (417) according to signal Vc (411). PWM-CLK (417) may be a series of pulses (e.g., with variable pulse width), and its frequency may be fixed in steady-state operation of multi-phase switching converter 110 (e.g., when Vin, Va and load current are substantially constant). However, in transient processes, such as a step change in supply voltage Vin (201) or a load change, the frequency of PWM-CLK (417) may change in a short period of time, which is well known in the relevant art.

[0079] The signal PWM-CLK (417) provides a clock for components (such as flip-flops) within the phase distributor 430, which will be described in detail below. As described above, the period (or frequency) and pulse width of the signal PWM-CLK (417) depend on the feedback signal (e.g., the sensed inductor current, the instantaneous amplitude of the output voltage Va, etc.), which is well known in the relevant art. Therefore, modules / components 410 and 415 can be collectively regarded as a "common control signal generator module" whose design purpose is to generate the "common control signal" PWM-CLK (417) to ensure that the voltage Va (240) remains at the desired amplitude indicated by Vref (401). The PWM generator 415 may include components such as a sawtooth waveform generator, a comparator, etc. for generating the signal PWM-CLK (417) ( Figure 4 PWM generator 415 may be implemented in a known manner.

[0080] The phase activator 425 receives the assigned phase signal on path 421, the master phase signal on path 447, receives inputs representing load current requirements, sensed inductor currents of each power stage, overshoot / undershoot of voltage Va (240), etc. on path 422, and generates an "active phase" signal on path 427. The phase activator 425 controls the increase or decrease of the phase (and thus the power stage) based on the values ​​received on path 422. Therefore, the phase activator 425 determines the number of phases that need to be activated and / or deactivated to meet the load current demand for a given duration.

[0081] In one embodiment, each of the allocated phase signal (421), active phase signal (427), and master phase signal (447) is n bits wide, where "n" is the total number of phases in the multi-phase switching converter 110. Therefore, each bit of the allocated phase signal (421), active phase signal (427), and master phase signal (447) corresponds to a power level. The allocated phase signal (421) indicates the phase assigned to a particular track, while the active phase signal (427) indicates the specific phase of the phases assigned to the track that is activated to support the track load current demand for a given duration. The master phase signal (447) represents the power level that operates as the master level for the duration.

[0082] In the illustrative embodiment, the phase activator 425 activates the phases sequentially (from the least significant bit (LSB) to the most significant bit (MSB)) starting from the master level index in the master phase signal (447), and taking into account the rotation of the index, which will be explained in further detail below. For example, among the six phases (SPSA-1, 220-1 to SPSA-6, 220-6) assigned to track Va (240), assuming that the phase activator 425 determines that three phases need to be activated to support the load current, and the master level is SPSA-2 (220-2), the active phases will be SPSA-2 (220-2) to SPS-4 (220-4). For example, the phase activator 425 can be implemented by using a state machine, but other techniques can also be used, which will be clear to those skilled in the art by reading the disclosure provided herein.

[0083] The master phase selector (445) receives the allocated phase signal on the path 421, the active phase signal on the path 427, the threshold time signal on the path 422, and the threshold number signal on the path 444, and generates a master phase signal on the path 447. The master phase selector (445) is used to change the master level in the active level to an active level other than the current master level when a specific condition is met. In one embodiment, the condition is as follows:

[0084] Condition-1: When the number of active stages (indicated by the number of indices with a value of "1" in the active phase signal 427) is greater than or equal to a certain value (indicated by the value in the threshold number signal (444)).

[0085] Condition-2: When Condition-1 lasts for more than a certain period of time (indicated by the value in the threshold time signal (442)).

[0086] In one embodiment, the threshold number (444) is equal to the number of phases assigned to the track, and the master phase selector (445) switches the master stage to the next higher index (from LSB to MSB direction) in the active phase signal 427 (or switches to the leftmost active phase index in the case of flipping). In other words, the process of changing / selecting the master stage is performed in a round-robin order. The master phase selector (445) may include logic blocks such as a state machine and / or a synchronization counter to implement the above functions. When the phase controller 210 is powered on, the first LSB index with a logic value of "1" in the assigned phase signal (421) can be selected as the default master stage.

[0087] Therefore, in Figure 2 In an exemplary embodiment of (wherein the multiphase switching converter 110 includes 6 phases assigned to track Va (240) and 10 phases assigned to track Vb (250)), n=16. Therefore, each power level / phase is indexed in the n-bit assigned phase signal (421). Therefore, in the assigned phase signal (421), the active phase signal (427) and the main phase signal (447), with index 0 as the least significant bit (LSB) and index 15 as the most significant bit (MSB), SPSA-1 (220-1) to SPSA-6 (220-6) can be indexed at positions 0 to 5, respectively, and SPSB-1 ​​(230-1) to SPSB-10 (230-10) can be indexed at positions 6 to 15, respectively. In the index of the assigned phase signal (421), a logical '1' indicates that the corresponding phase is available for track Va (240), while a logical '0' in the index indicates that it is not available. Similar conventions are followed for the active phase signal (427) and the main phase signal (447). It is understood that at a given time, for a certain track, only one index in the main phase signal (447) will have a logic value of "1", representing the main level of the track. The designer / user can assign phases to tracks (in a corresponding manner) during design, and such assignment information can be stored in a non-volatile memory (not shown) of the multi-phase switching converter 110.

[0088] Phase distributor 430 (PD430) receives the PWM-CLK signal on path 417, receives the active phase signal on path 427, and generates PWMA signals 211-1 to 211-6. PD430 asserts the corresponding signal 211 in response to each pulse of the PWM-CLK signal (417). In one embodiment, PD430 is used to generate PWM signals (211) for the currently active power stages in a rotating sequence. Therefore, for example, if power stages SPS-1 (220-1) to SPS-5 (220-5) are active for a certain duration and SPS-6 (220-6) is inactive for the duration, PD430 asserts signals 211-1 to 211-5 in a rotating sequence in response to corresponding pulses of PWM-CLK (417) while maintaining signal 211-6 in a hi-Z state. In an alternative embodiment employing a constant on-time control technique, the phase divider 430 may generate intermediate output pulses that are provided to corresponding T-ON generators to generate corresponding fixed width PWM signals 211 .

[0089] The description continues with an example of a phase distributor implemented within the phase controller 210 in one embodiment of the present disclosure.

[0090] 5. Phase distributor

[0091] Figure 5 The implementation details of the phase controller in one embodiment of the present disclosure are shown. The phase distributor 430 is shown to include loop units 520-1 to 520-6. It is worth noting that Figure 5 The implementation of the phase distributor 430 shown in FIG. 4 is for illustration only. It will be appreciated that alternative implementations of the phase controller 430 may include Figure 5 More or fewer modules as shown.

[0092] Each loop unit 520 corresponds to a corresponding power stage 220 ( Figure 5 ). Therefore, Figure 5 Six loop units 520-1 to 520-6 are shown in FIG. 5 , each loop unit corresponding to a corresponding SPS, such as Figure 2 An example embodiment of a six-phase buck converter generating voltage Va (240) is shown in FIG. Loop unit 520 is shown receiving a PWM-CLK signal on path 417, the bit value of which corresponds to the index of the corresponding power level in the active phase signal (427), and receiving an input signal i-from-prev-flop (signal from the previous flip-flop) on path 518, and is shown generating a signal o-to-next-flop (signal to the next flip-flop) on path 523, and generating a PWMA signal on path 211.

[0093] The loop unit 520 includes a circuit (hereinafter referred to as Figure 6 Detailed description) is provided for checking whether the corresponding power stage is in an active state (based on the signal received on path 427) and switching the PWM signal of the corresponding power stage according to the input signal i-from-prev-flop received on path 518 and the PWM-CLK received on path 417. In one embodiment, when a logic high level is received on path 518, loop unit 520 generates a logic high level on path 523 at the next rising edge of PWM-CLK (417), otherwise a logic low level is generated. Figure 5 As can be seen in the figure, loop units 520-1 to 520-6 are connected in a ring manner, so that the input signal (518) of each loop unit 520 corresponds to the output signal 523 of the previous loop unit, and the first loop unit (520-1) receives the output signal (o-to-next-flop, 523-6) of the last loop unit (520-6). It should be noted that in the present disclosure, the loop unit immediately adjacent to the right side of the "current" loop unit (i.e., the loop unit currently referred to) is called the "next" loop unit, and the loop unit immediately adjacent to the left side of the current loop unit is called the "previous" loop unit. Therefore, loop unit 520-2 is the previous loop unit of loop unit 520-3, and loop unit 520-4 is the next loop unit of loop unit 520-3. Loop unit 520-1 is the leftmost loop unit, and loop unit 520-6 is the rightmost loop unit.

[0094] The following describes the implementation details of the loop unit in the embodiment of the present disclosure.

[0095] 6. Loop unit

[0096] Figure 6 is a block diagram showing the implementation details of the loop unit in the embodiment of the present disclosure. Figure 6 The loop unit 520-1 is shown in detail. The loop unit 520-1 is shown to include an AND gate 610, a MUX 630, and a D flip-flop 620. Other loop units can also be implemented similarly to the loop unit 520-1. In addition, it is specifically pointed out herein that Figure 6 Only components relevant to understanding the present disclosure are shown. It is understood that the loop unit 520 may include more Figure 6 More or fewer modules as shown.

[0097] AND gate 610 receives the active phase signal (427) [0], the signal i-from-prev-flop on path 518-1, and generates an AND output on path 611. Therefore, when the active phase signal (427) [0] and the i-from-prev-flop signal are both logic high, the AND gate generates a logic high.

[0098] Flip-flop 620 receives the output of AND gate 610 on path 611 at its D input and produces an output (Q) on path 211. Flip-flop 620 is clocked by signal PWM-CLK (417). In one embodiment, flip-flop 620 is implemented as a positive edge trigger with active low PR (preset) and CLR (clear) inputs ( Figure 6 Although in the exemplary embodiment, the Q output of the flip-flop 620 is shown as being provided to each SPS (220) as the signal PWM (211), in an alternative embodiment, an AND gate (417) that performs an AND operation on the Q output and the signal PWM-CLK (417) is provided. Figure 6 The output of the control circuit (not shown) can be provided as a PWM signal (211).

[0099] MUX 630 receives the Q output of flip-flop 620 on path 211-1, receives signal i-from-prev-flop on path 518-1, and forwards one of signals 211-1 and 518-1 as output (MUX output / o-to-next-flop) on path 523-1 according to the logic value of the active phase signal (427) [0]. In one embodiment, when the active phase signal (427) [0] is at a logic high level, Q output 211-1 is selected as the MUX output on path 523-1; and when the active phase signal (427) [0] is at a logic low level, signal i-from-prev-flop (518-1) is selected as the MUX output on path 523-1. In other words, when the SPS corresponding to loop unit 520 is inactive, the input signal (518) indicating the active state of the previous loop unit will be forwarded on path 523.

[0100] Thus, loop cells 520-1 to 520-6 are used to shift the logic high level of the Q output of the flip-flop (thereby activating different phases (SPSA-1220-1 to SPSA-6220-6)) in a rotating sequence. During each low-to-high transition of the signal PWM-CLK (417), the position of the active flip-flop (620) in the loop cell 520 of the phase distributor 430 is advanced one position to the right, or rolled back to the leftmost flip-flop. Thus, at any time, there is one (and only one) active flip-flop (Q output is logic high).

[0101] The first active flip-flop in the toggle sequence (the logic high level starts shifting from here in the toggle sequence) corresponds to the leftmost active phase (indicated by the corresponding index in the active phase signal 427), which also represents the main stage. After a phase change event occurs, the preset (PR) input of the flip-flop 620 corresponding to the leftmost active phase in the loop unit 520 is set, and the clear (CLR) inputs of the other flip-flops are set to logic low levels accordingly.

[0102] The following describes the manner in which phase management is performed in one embodiment of the present disclosure.

[0103] 7. Phase Management

[0104] Figure 7 is a timing diagram (not drawn to scale) illustrating phase management and primary level changes of track Va (240) in an embodiment of the present disclosure. Figure 7 An example waveform of a load current (Iload) (710) extracted from the rail voltage Va (240) is shown, along with an active phase signal (427) [0] ... [3] and a main phase signal (447) [0] ... [1]. It is worth noting that Figure 7 Only waveforms relevant to understanding the present disclosure are shown. By reading the disclosure herein, those skilled in the art will be able to understand the logic states of other waveforms. Voltages VL and VH represent the voltage values ​​of a logic low level and a logic high level, respectively. In one embodiment, voltage VL is equal to 0V, and VH is equal to 3.3V.

[0105] To simplify the explanation, Figure 7 In the example diagram, it is assumed that the multi-phase switching converter 110 includes only four SPSs (SPSA-1 (220-1) to SPSA-4 (220-4) ( Figure 2 )), and all four phases are assigned to track Va (240). Therefore, n=4. The assigned phase signal (421) is

[1111] , where the LSB index position (i.e., 0) corresponds to SPSA-1 (220-1) and the MSB index position (i.e., 3) corresponds to SPSA-4 (220-4). In the illustrative embodiment, the threshold number (444) is equal to 4.

[0106] Before time t710, assume that the load current demand is 30 amperes (A). According to the load current demand (indicated by the value on path 422), the phase activator 425 has activated two power stages - SPSA-1 (220-1) and SPSA-2 (220-2). Therefore, before t710:

[0107] The active set consists of SPSA-1 (220-1) and SPSA-2 (220-2).

[0108] The inactive level set consists of SPSA-3 (220-3) and SPSA-4 (220-4).

[0109] The active phase signal (427) is:

[0011] .

[0110] In addition, before t710, it is assumed that SPSA-1 (220-1) operates as the master stage. Therefore, the master phase signal (447) is:

[0001] . Therefore, Figure 7 In, before t710:

[0111] Active phase (427) [0] and active phase (427) [1] are displayed as logic high, active phase (427) [2] and active phase (427) [3] are displayed as logic low, main phase (447) [0] is displayed as logic high, and main phase (447) [1] is displayed as logic low. Main phase (447) [2] and main phase (447) [3] ( Figure 7 ) is also at a logic low level.

[0112] At time t710, it is assumed that the signal received by the phase controller 210 from the CPU 120 indicates that the load current demand is 60A. Although for ease of explanation, Figure 7 The change of the load current in FIG. 4 is shown as a step change, but it should be understood by those skilled in the art that such a change actually occurs within a non-zero time interval, which is obvious to those skilled in the art.

[0113] Phase activator 425 determines that the active power stage set needs to be changed to support the current load current (ie, 60A), such as Figure 3 As described in step 320 of the flowchart of . Therefore, the phase activator 425 activates the phases in order (from LSB to MSB) starting from the main level index in the main phase signal (447), here SPSA-1 (220-1). Therefore, in addition to activating SPSA-1 (220-1) and SPSA-2 (220-2), the phase activator 425 also activates SPSA-3 (220-3). Therefore, starting from t710:

[0114] The active level set consists of SPSA-1 (220-1) to SPSA-3 (220-3).

[0115] The inactive set consists of SPSA-4 (220-4),

[0116] The active phase signal (427) is:

[0111] ,

[0117] Active Phase (427) [0] and Active Phase (427) [1] continue to be at a logic high level,

[0118] The active phase (427) [2] transitions from a logic low level to a logic high level, and

[0119] The active phase (427) [3] continues to be at a logic low level.

[0120] The master phase selector (445) checks whether the number of active phases is greater than or equal to the threshold number (444), as described in step 340 of the flowchart. Since the condition is not met, the master phase selector (445) does not change the master stage. Therefore, starting from t710:

[0121] The main phase signal (447) continues to be

[0001] ,

[0122] The main phase (447)[0] continues to be at a logic high level, and

[0123] The main phase (447)[1] continues to be at a logic low level.

[0124] At time t713, the signal received by phase controller 210 from CPU 120 indicates that the load current demand is 50 A. However, phase activator 425 determines that no change is required to the activation level set of the current load current. Therefore, at time t713, the waveforms of signals 427 and 447 do not change.

[0125] At time t719, the signal received by the phase controller 210 from the CPU 120 indicates that the load current demand is 80A. The phase activator 425 determines that all phases assigned to the track need to be activated to meet the load current demand. Therefore, in addition to activating SPSA-1 (220-1) to SPSA-3 (220-3), the phase activator 425 also activates SPSA-4 (220-4). Therefore, starting from t719:

[0126] The active level set consists of SPSA-1 (220-1) to SPSA-4 (220-4).

[0127] There are no inactive power stages.

[0128] The active phase signal (427) is:

[1111] ,

[0129] The active phase (427) [0…2] continues to be at a logic high level, and

[0130] The active phase (427) [3] transitions from a logic low level to a logic high level.

[0131] The master phase selector (445) checks whether the number of active phases is greater than or equal to the threshold number (444). Since the above condition 1 is satisfied, the master phase selector (445) waits for a period of time indicated by the threshold time (442) before changing the master level. Assume that the duration of the time interval t719 to t723 is equal to the threshold time (442). Therefore, at time t723, the above condition 2 is satisfied, and the master phase selector (445) switches the master level to the next higher index (from LSB to MSB direction), that is, changes the master level from SPSA-1 (220-1) to SPSA-2 (220-2). Therefore, starting from t723:

[0132] The main phase signal (447) is

[0010] ,

[0133] The main phase (447)[0] transitions from a logic high level to a logic low level, and

[0134] The main phase (447)[1] transitions from a logic low level to a logic high level.

[0135] Although in the exemplary embodiment, the main phase selector (445) is shown as waiting for the threshold time (442) before changing the main level, it will be appreciated that in alternative embodiments, the main phase selector (445) may change the main level at time t719 (when the phase change event occurs) without waiting for any threshold time.

[0136] At time t726, the load current demand of CPU 120 drops to 40 amps. Phase activator 425 determines that fewer phases (e.g., 2 phases) are sufficient to support the current load current. Therefore, phase activator 425 activates the phases in sequence (from LSB to MSB) starting from the main level index in the main phase signal (447), which is SPSA-2 (220-2) in this case. Therefore, phase activator 425 keeps SPSA-2 (220-2) and SPSA-3 (220-3) in the active state and removes SPSA-1 (220-1) and SPSA-4 (220-4) from the active level set. Therefore, starting from t726:

[0137] The active set consists of SPSA-2 (220-2) and SPSA-3 (220-3).

[0138] The inactive level set consists of SPSA-1 (220-1) and SPSA-4 (220-4).

[0139] The active phase signal (427) is:

[0110] ,

[0140] Active Phase (427)[0] and Active Phase (427)[3] transition from a logic high level to a logic low level, and

[0141] Active phase (427)[1] and active phase (427)[2] continue to be in a logic high state.

[0142] After the active phase (427) changes, the main phase selector (445) checks whether the number of active phases is greater than or equal to the threshold number (444). Since the condition is not met, the main phase selector (445) does not change the main level. Therefore, starting from t726:

[0143] The main phase signal (447) continues to be

[0010] ,

[0144] The main phase (447)[0] continues to be at a logic low level, and

[0145] The main phase (447)[1] continues to be at a logic high level.

[0146] At time t729, the load current demand of CPU 120 further drops to 20A. Phase activator 425 determines that a single phase is sufficient to support the current load current. Therefore, phase activator 425 activates the phases in sequence (from LSB to MSB) starting from the main level index in the main phase signal (447), which is SPSA-2 (220-2) in this case. Therefore, phase activator 425 keeps SPSA-2 (220-2) in the active state and removes the previously active phase SPSA-3 (220-3) from the active level set. Therefore, starting from t729:

[0147] The active set consists of SPSA-2 (220-2),

[0148] The inactive level set consists of SPSA-1 (220-1), SPSA-3 (220-3) and SPSA-4 (220-4).

[0149] The active phase signal (427) is:

[0010] ,

[0150] Active Phase (427) [0] and Active Phase (427) [3] continue to be at a logic low level,

[0151] The active phase (427)[1] continues to be at a logic high level, and

[0152] The active phase (427) [2] transitions from a logic high level to a logic low level.

[0153] It can be understood that the previous master stage (SPSA-1, 220-1) has been removed from the active stage set, thereby relieving the pressure on the power stage. If the master stage continues to be SPSA-1 (220-1), then regardless of how the load current changes, the phase will be included in the active power stage set, which may result in a shortened working life of the power stage.

[0154] After the active phase (427) changes, the main phase selector (445) checks whether the number of active phases is greater than or equal to the threshold number (444). Since the condition is not met, the main phase selector (445) does not change the main level. Therefore, starting from t729:

[0155] The main phase signal (447) continues to be

[0010] ,

[0156] The main phase (447)[0] continues to be at a logic low level, and

[0157] The main phase (447)[1] continues to be at a logic high level.

[0158] Although the exemplary embodiment shows the threshold number (444) as the total number (maximum number) of phases assigned to the track, various aspects of the present disclosure may also be well applied when the threshold number (444) is a non-zero number less than the maximum number of assigned phases. It can be appreciated that changing the main stage when the number of active power stages exceeds the threshold number can prevent transient changes in the output voltage Va (240) compared to changing the main stage when there is only one active power stage. In other words, changing the main stage when only one power stage is active will require deactivating the currently active power stage and activating the newly selected main stage, resulting in a transient change in the output voltage Va (240). In addition, according to aspects of the present disclosure, the change of the main stage is only a change of the internal signal / register, so this change will not be reflected in the output current / voltage.

[0159] Furthermore, although for simplicity, the exemplary embodiment describes selecting the primary stage in a rotational order, aspects of the present disclosure are also applicable to using other techniques in selecting the primary stage (e.g., randomly changing the primary stage, or based on parameters such as current sensed from the power stage, active duration of the power stage, etc.). This will be apparent to those skilled in the art by reading the disclosure herein.

[0160] The description continues to illustrate two example scenarios of changing the main phase in a 16-phase multi-phase switching converter.

[0161] 8. Example scene of changing the main level

[0162] Fig. 8A and Figure 8BTables showing the main level changes in two example scenarios are shown. Specifically, tables 800 and 820 are each shown to contain 4 rows ( Fig. 8A Lines 811-814 in , and Figure 8B 831-834 in FIG. 801 ). Columns 801 / 821, 803 / 823, and 804 / 824 represent the values ​​of the allocated phase signal (421), the main phase signal (447), and the active phase signal (427), respectively. Columns 802 / 822 show the number of phases required to support the load current demand (given by Figure 4 425 in the phase activator).

[0163] exist Fig. 8A and Figure 8B In the exemplary embodiment of , it is assumed that the example track is assigned 6 phases, whose index positions are 2-7 (as indicated by the logical "1" in rows 811-814 / 831-834, columns 801 / 821). It is also assumed that the threshold number (444) ( Fig. 8A and Figure 8B not shown) is equal to 6.

[0164] Row 811 shows that the current master (column 803) is at index position 2 and the desired phase number is 3. Therefore, starting from index 2, the phase activator 425 counts to 3, so that the active phase (427) at index position 2-4 (column 804) has a logic "1".

[0165] Row 812 shows that the load current demand has increased from the previous value and the number of phases required is 6. Therefore, starting from index 2, the phase activator 425 counts to 6, so that the active phases (427) at index positions 2-7 have a logic "1". It can be seen that the main phase (447) has not changed. Assume that this condition (the number of active phases (427) is greater than or equal to the threshold number (444)) lasts for a threshold time (442). Therefore, as shown in row 813, the main stage is shifted to index position 3. It is worth noting that from row 812 to row 813, the active phase (427) has not changed.

[0166] Row 814 shows that the load current demand has decreased from the previous value and the number of phases required has decreased from 6 to 3. Now, the phase activator 425 starts counting from index 3 (the new primary index) to 3, so that the active phase (427) has a logic "1" in index position 3-5.

[0167] Continue to change the main level in the above rotation order. After a period of time, the signal value is as follows Figure 8B As shown in row 831 of , where the main level index is 7 (the last index with a logical "1" in the allocation phase (421)).

[0168] Row 832 shows that the load current demand has increased from the previous value, and the number of phases required is 6. Therefore, starting at index 7, the phase activator 425 counts to 6. However, since index 7 represents the index of the last phase assigned to the track, the phase activator 425 rolls back and starts counting from index 2, so that the active phase (427) has a logic "1" in index position 2-7.

[0169] Assume that this condition (the number of active phases (427) is greater than or equal to the threshold number (444)) persists for a threshold time (442). Therefore, the master phase selector (445) decides to change the master level to the next higher index. However, since index 7 (of the current master level) represents the index of the last assigned phase, the master phase selector (445) rolls back and sets the master level at index position 2, as shown in row 833. It is noteworthy that the active phase (427) has not changed from row 832 to row 833.

[0170] Row 834 shows that the load current demand has decreased from the previous value and the number of phases required has decreased from 6 to 3. Now, the phase activator 425 counts from index 2 (the new primary index) to 3, so that the active phase (427) has a logic "1" in index position 2-4.

[0171] Thus, various aspects of the present disclosure are used to change the primary stage in a multi-phase switching converter.

[0172] 9. Conclusion

[0173] The "one embodiment", "an embodiment" or similar expressions mentioned in this specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment", "in an embodiment" and similar expressions appearing in this specification may, but not necessarily, refer to the same embodiment.

[0174] exist Figure 1 , Figure 2 , Figure 4 , Figure 5 and Figure 6 In the illustrations, while terminals / nodes are shown as being directly connected (i.e., “connected to”) various other terminals, it should be appreciated that there may be other components in the path (as applicable to the particular circumstances) and therefore, these connections may be viewed as being “electrically coupled” to the same connection terminal.

[0175] It should be understood that the specific types of transistors mentioned above (e.g., NMOS, PMOS, etc.) are used only as examples. However, by reading the disclosure provided herein, those skilled in the relevant art will understand other embodiments using different configurations and transistors. For example, an NMOS transistor can be replaced by a PMOS (P-type metal oxide semiconductor) transistor, while swapping the connections of the power terminal and the ground terminal.

[0176] Therefore, in this application, the power supply and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of the transistor (which provide a current path when the transistor is turned on and an open circuit when the transistor is turned off) are referred to as current terminals, and the gate (base) terminal is referred to as the control terminal.

[0177] Although various embodiments of the present disclosure have been described above, it should be understood that these embodiments are presented only as examples and not limitations. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above embodiments, but should only be defined according to the following claims and their equivalents.

Claims

1. A method implemented in a phase controller of a multi-phase switching converter, the phase controller being used to provide corresponding phase control signals to a plurality of power stages, the plurality of power stages working together to provide a stable supply voltage from an input voltage, characterized in that: The method comprises: activating a group of power stages (a power stage set) of the plurality of power stages and maintaining the remaining power stages of the plurality of power stages in an inactive state, wherein a first power stage of the power stage set operates as a master stage; When it is necessary to support the current load current, changing the power level set; If the number of levels in the power level set is greater than or equal to a threshold number, a power level other than the first power level is selected from the changed power level set as a main level.

2. The method according to claim 1, characterized in that The multiphase switching converter comprises a plurality of rails, and wherein a corresponding primary stage is available for each of the plurality of rails, Wherein, the threshold number is equal to the total number of power levels in the multiple power levels, so that the main level corresponding to the first track among the multiple tracks will be changed only when all power levels assigned to the first track work as the changed power level set, wherein the first track provides a stable supply voltage.

3. The method according to claim 1, characterized in that When the number of levels in the changed power level set is greater than or equal to the threshold number and lasts for a threshold time, the main level is changed.

4. The method according to claim 1, characterized in that The master stage is selected in a round-robin order among the power stages in the changed set of power stages.

5. The method according to claim 4, characterized in that The master level is indicated by a first signal comprising a first plurality of bits, wherein each bit represents a respective index in the first signal and corresponds to a respective power level in the plurality of power levels, The index median value of the first signal being 1 indicates that the corresponding power level is the main level.

6. The method according to claim 5, characterized in that The set of active power levels is indicated by a second signal comprising a second plurality of bits, wherein each bit represents a respective index in the second signal and corresponds to a respective power level in the plurality of power levels, Wherein, a median value of the index of the second signal being 1 indicates that the corresponding power level is in an active state, and a median value of the index of the second signal being 0 indicates that the corresponding power level is in an inactive state, wherein the index of each power level of the plurality of power levels in the second signal is the same as the index in the first signal, Wherein, the method comprises: A required number of power stages are activated in sequence, taking the index corresponding to the main stage in the first signal as the starting index.

7. A phase controller for a multi-phase switching converter, the phase controller being used to provide corresponding phase control signals to a plurality of power stages, the plurality of power stages working together to provide a stable supply voltage from an input voltage, characterized in that: The phase controller comprises: a main control signal generator module coupled to receive the stable supply voltage and a reference voltage of a desired amplitude and generate a common control signal, wherein a switching period of the common control signal is generated based on an amplitude difference between the reference voltage and the stable supply voltage; a phase distributor for receiving the common control signal and generating the corresponding phase control signal synchronized with the conversion of the common control signal; a phase activator for receiving information including a present load current and generating an active phase signal, wherein the active phase signal indicates a set of power stages to be driven into an active state to support the present load current; and a master phase selector for receiving the active phase signal and generating a master phase signal, wherein the master phase signal indicates the power stage in the set of power stages operating as a master stage, wherein when it is necessary to support the current load current, the phase activator changes the power level set, If the number of levels is greater than or equal to a threshold number, the main phase selector selects a power level other than the first power level from the changed power level set as the main level.

8. The phase controller according to claim 7, characterized in that: The multiphase switching converter comprises a plurality of rails, and wherein a corresponding primary stage is available for each of the plurality of rails, Wherein, the threshold number is equal to the total number of power levels in the multiple power levels, so that the main level corresponding to the first track will be changed only when all power levels assigned to the first track work as the changed power level set, wherein the first track provides a stable supply voltage.

9. The phase controller according to claim 7, characterized in that: When the number of levels in the changed power level set is greater than or equal to the threshold number and lasts for a threshold time, the main phase selector changes the main level.

10. The phase controller according to claim 7, characterized in that: The master phase selector selects the master stage in a round-robin order among the power stages in the changed set of power stages.

11. The phase controller according to claim 10, characterized in that: The main phase signal comprises a first plurality of bits, wherein each bit represents a respective index in the main phase signal and corresponds to a respective power level in the plurality of power levels, The median value of the index of the main phase signal being 1 indicates that the corresponding power level is the main level.

12. The phase controller according to claim 11, characterized in that: the active phase signal comprises a second plurality of bits, wherein each bit represents a respective index in the active phase signal and corresponds to a respective power level in the plurality of power levels, Wherein, the median value of the index of the active phase signal is 1, indicating that the corresponding power level is activated, and the median value of the index of the active phase signal is 0, indicating that the corresponding power level is deactivated. The phase activator uses the index corresponding to the main stage in the main phase signal as the starting index to activate the required number of power stages in sequence. The index of each power level of the plurality of power levels in the active phase signal is the same as the index in the main phase signal.

13. The phase controller according to claim 12, characterized in that: The phase distributor comprises: a plurality of loop cells, wherein each loop cell corresponds to a respective power stage of the plurality of power stages, wherein each loop cell of the plurality of loop cells is coupled to receive an input trigger signal and a respective bit of the active phase signal and to generate an output trigger signal, The plurality of loop units are connected in a ring manner, so that an input trigger signal of each loop unit corresponds to an output trigger signal of a previous loop unit, wherein each loop unit comprises a trigger which is clock-controlled by the common control signal.

14. A multiphase switching converter for providing a stable supply voltage from an input voltage, characterized in that The multi-phase switching converter comprises: a plurality of power stages, wherein each power stage receives a respective phase control signal and connects the input voltage to a respective inductor when the respective phase control signal is in a first state; and disconnects the input voltage from the respective inductor when the respective phase control signal is in a second state; A phase controller, configured to generate the phase control signal, wherein the phase controller comprises: a common control signal generator module coupled to receive the stable supply voltage and a reference voltage of a desired amplitude and generate a common control signal, wherein a switching period of the common control signal is generated based on an amplitude difference between the reference voltage and the stable supply voltage; a phase distributor for receiving the common control signal and generating the corresponding phase control signal synchronized with the conversion of the common control signal; a phase activator for receiving information including a present load current and generating an active phase signal, wherein the active phase signal indicates a set of power stages to be driven into an active state to support the present load current; and a master phase selector for receiving the active phase signal and generating a master phase signal, wherein the master phase signal indicates the power stage in the first set of power stages operating as a master stage, wherein when it is necessary to support the current load current, the phase activator changes the power level set, If the number of levels is greater than or equal to a threshold number, the main phase selector selects a power level other than the first power level from the changed power level set as the main level.

15. The multi-phase switching converter according to claim 14, characterized in that: The multiphase switching converter comprises a plurality of rails, and wherein a corresponding primary stage is available for each of the plurality of rails, Wherein, the threshold number is equal to the total number of power levels in the multiple power levels, so that the main level corresponding to the first track will be changed only when all power levels assigned to the first track work as the changed power level set, wherein the first track provides a stable supply voltage.

16. The multi-phase switching converter according to claim 14, characterized in that: When the number of levels in the changed power level set is greater than or equal to the threshold number and lasts for a threshold time, the main phase selector changes the main level.

17. The multi-phase switching converter according to claim 14, characterized in that: The master phase selector selects the master stage in a round-robin order among the power stages in the changed set of power stages.

18. The multi-phase switching converter according to claim 17, characterized in that: The main phase signal comprises a first plurality of bits, wherein each bit represents a respective index in the main phase signal and corresponds to a respective power level in the plurality of power levels, The median value of the index of the main phase signal being 1 indicates that the corresponding power level is the main level.

19. The multi-phase switching converter according to claim 18, characterized in that: the active phase signal comprises a second plurality of bits, wherein each bit represents a respective index in the active phase signal and corresponds to a respective power level in the plurality of power levels, Wherein, the median value of the index of the active phase signal is 1, indicating that the corresponding power level is activated, and the median value of the index of the active phase signal is 0, indicating that the corresponding power level is deactivated. wherein the index of each power level of the plurality of power levels in the main phase signal is the same as the index in the active phase signal, The phase activator uses the index corresponding to the main stage in the main phase signal as the starting index and activates the required number of power stages in sequence.

20. The multi-phase switching converter according to claim 19, characterized in that: The phase distributor comprises: a plurality of loop cells, wherein each loop cell corresponds to a respective power stage of the plurality of power stages, wherein each loop cell of the plurality of loop cells is coupled to receive an input trigger signal and a respective bit of the active phase signal and to generate an output trigger signal, The plurality of loop units are connected in a ring manner, so that an input trigger signal of each loop unit corresponds to an output trigger signal of a previous loop unit, wherein each loop unit comprises a trigger which is clock-controlled by the common control signal.

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