A circuit for improving power factor

Abstract

The present invention provides a circuit for improving power factor. A PF compensation circuit is constructed by using discrete resistors, capacitors, electronic switches and voltage regulator elements. The low-voltage on and high-voltage off working mode can effectively avoid surge failure and compatibility problems of integrated chips.

Description

Technical Field

[0001] The present invention relates to the technical field of lighting fixture driving circuits, and in particular to a circuit for improving power factor. Background Art

[0002] Currently, high-voltage linear integrated chips in the lighting field on the market are divided into two categories: those with PF (power factor) compensation and those without PF compensation. The latter requires an additional PF compensation circuit, which is almost entirely implemented using an additional integrated chip. This method has limitations such as poor surge resistance and possible compatibility with the main circuit.

[0003] Therefore, it is necessary to provide a circuit for improving the power factor to solve the above technical problems. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a circuit for improving the power factor. The PF compensation circuit is constructed using discrete components. Its low-voltage turn-on and high-voltage turn-off working mode can effectively avoid surge failure and compatibility problems of integrated chips.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a circuit for improving power factor, including a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first voltage regulator ZD1, a first electronic switch Q1, and a second electronic switch Q2;

[0006] One end of the first resistor R1, the second resistor R2 and the third resistor R3 is a pulsating direct current connection terminal and an input end of a load circuit, the other end of the first resistor R1 is connected to the cathode of the first voltage regulator tube ZD1, the anode of the first voltage regulator tube ZD1 is grounded through the first capacitor C1, and the anode of the first voltage regulator tube ZD1 is connected to the first pin of the first electronic switch Q1, the other end of the second resistor R2 is connected to the second pin of the first electronic switch Q1 and the first pin of the second electronic switch Q2, the other end of the third resistor R3 is connected to the second pin of the second electronic switch Q2, and the third pins of the first electronic switch Q1 and the second electronic switch Q2 are grounded;

[0007] When the voltage at the pulsating DC terminal is less than the threshold voltage, the first electronic switch Q1 is turned off, the second electronic switch Q2 is turned on, and current flows through the third resistor R3;

[0008] When the voltage at the pulsating direct current terminal is greater than or equal to the threshold voltage, the first electronic switch Q1 is turned on, the second electronic switch Q2 is turned off, and no current flows through the third resistor R3.

[0009] In one embodiment, the circuit for improving the power factor further includes a second voltage regulator tube DZ2, which is connected in series between the anode of the first voltage regulator tube ZD1 and the first pin of the first electronic switch Q1.

[0010] In one embodiment, the circuit for improving the power factor further includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0011] The third resistor R3 and the fifth resistor R5 connected in parallel, and the fourth resistor R4 and the sixth resistor R6 connected in parallel, are connected in series between the pulsating direct current terminal and the second pin of the second electronic switch Q2.

[0012] In one embodiment, the first electronic switch Q1 and the second electronic switch Q2 are NPN transistors, the first pin is the base, the second pin is the collector, and the third pin is the emitter.

[0013] In one embodiment, the first electronic switch Q1 and the second electronic switch Q2 are N-channel enhancement mode MOS transistors, the first pin is a gate, the second pin is a drain, and the third pin is a source.

[0014] The beneficial effects of the present invention are:

[0015] Use discrete components to build a PF compensation circuit to effectively avoid surge failure and integrated chip compatibility issues;

[0016] Furthermore, by using the on-voltage of the voltage regulator tube and the first electronic switch to set the threshold voltage, and by virtue of the working mode of the second electronic switch being turned on at low voltage and turned off at high voltage, surge failure can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a circuit structure schematic diagram of a first preferred embodiment of a circuit for improving power factor of the present invention;

[0018] Figure 2 It is a circuit structure diagram of a second preferred embodiment of a circuit for improving power factor of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0020] The circuit for improving the power factor of the present invention adopts a first electronic switch Q1 and a second electronic switch Q2 with three pins, and utilizes the principle that the low-voltage first electronic switch Q1 is turned off and the second electronic switch Q2 is turned on; the high-voltage first electronic switch Q1 is turned on and the second electronic switch Q2 is turned off, thereby effectively avoiding surge failure and compatibility problems of integrated chips.

[0021] Example 1

[0022] In this embodiment, the first electronic switch Q1 adopts a first NPN transistor Q1, and the second electronic switch Q2 adopts a second NPN transistor Q2.

[0023] See also Figure 1 As shown, in Embodiment 1, the circuit 100 for improving the power factor includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first voltage regulator ZD1, a first NPN transistor Q1, and a second NPN transistor Q2;

[0024] Among them, the high-voltage output end of the rectifier module BD, that is, the pulsating direct current connection terminal is connected to one end of the first resistor R1, the second resistor R2 and the third resistor R3, the other end of the first resistor R1 is connected to the cathode of the first voltage regulator ZD1, the anode of the first voltage regulator ZD1 is grounded through the first capacitor C1, and the anode of the first voltage regulator ZD1 is connected to the first pin of the first NPN transistor Q1, the other end of the second resistor R2 is connected to the second pin of the first NPN transistor Q1 and the first pin of the second NPN transistor Q2, the other end of the third resistor R3 is connected to the second pin of the second NPN transistor Q2, and the third pins of the first NPN transistor Q1 and the second NPN transistor Q2 are grounded.

[0025] In this embodiment, the threshold voltage is set by the first voltage regulator ZD1 and the first NPN transistor Q1. The AC voltage forms a pulsating DC voltage after passing through the rectifier module BD. In each cycle:

[0026] ① When the pulsating DC voltage is less than the threshold voltage, the first NPN transistor Q1 is turned off, the second NPN transistor Q2 is turned on, and a current flows through the third resistor R3, and the current has the same amplitude and phase as the voltage;

[0027] ② When the pulsating DC voltage is greater than or equal to the threshold voltage, the first NPN transistor Q1 is turned on, the second NPN transistor Q2 is turned off, and no current passes through the third resistor R3.

[0028] The conduction time of the second NPN transistor Q2 , ie, the degree of PF compensation, can be adjusted by adjusting the threshold voltage.

[0029] When the surge voltage enters, it belongs to the second situation. Although the first NPN transistor Q1 is turned on, its series resistor is usually selected to be greater than 100KΩ. The surge voltage cannot damage the first NPN transistor Q1, and the second NPN transistor Q2 is in the off state and will not be affected by the surge voltage.

[0030] Since this solution has the characteristics of small size, flexible layout, convenient adjustment, sensitive action, low cost and no EMI (electromagnetic interference), it can be used with all integrated chips without PF compensation function.

[0031] In this embodiment, further Figure 1As shown, a varistor MOV is connected between the two input ends of the rectifier module BD, one input end of the rectifier module BD is connected to the mains live wire terminal AC-L through a current limiting resistor RL, and the other input end of the rectifier module BD is connected to the mains neutral wire terminal AC-N, so as to protect the circuit when abnormal mains current or voltage occurs.

[0032] Example 2

[0033] See also Figure 2 As shown, in the second embodiment, the circuit for improving the power factor is different from the first embodiment in that, in the second embodiment of the present invention, the circuit 100 for improving the power factor further includes a second voltage regulator tube DZ2, and the second voltage regulator tube DZ2 is connected in series between the anode of the first voltage regulator tube ZD1 and the first pin of the first NPN transistor Q1; the PF improvement circuit module further includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0034] The third resistor R3 and the fifth resistor R5 connected in parallel, and the fourth resistor R4 and the sixth resistor R6 connected in parallel, are connected in series between the high-voltage output end of the rectifier module BD and the second pin of the second NPN transistor Q2.

[0035] Of course, in other embodiments of the present invention, multiple resistors at various positions of the circuit can be used in series or in parallel, multiple voltage regulator diodes can be used in series, and multiple capacitors can be used in parallel, all of which are within the protection scope of the present invention.

[0036] Furthermore, of course, in the embodiments of the present invention, two N-channel enhancement MOS transistors may be used to replace the first NPN transistor Q1 and the second NPN transistor Q2 to achieve the functions of the first NPN transistor Q1 and the second NPN transistor Q2 in the first and second embodiments of the present invention. Of course, in the circuit where the N-channel enhancement MOS transistor is used to replace the NPN transistor, the gate replaces the base, the drain replaces the collector, and the source replaces the emitter.

[0037] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A circuit for improving power factor, characterized in that: It includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first voltage regulator tube ZD1, a first electronic switch Q1, and a second electronic switch Q2; One end of the first resistor R1, the second resistor R2 and the third resistor R3 is a pulsating direct current connection terminal and an input end of a load circuit, the other end of the first resistor R1 is connected to the cathode of the first voltage regulator tube ZD1, the anode of the first voltage regulator tube ZD1 is grounded through the first capacitor C1, and the anode of the first voltage regulator tube ZD1 is connected to the first pin of the first electronic switch Q1, the other end of the second resistor R2 is connected to the second pin of the first electronic switch Q1 and the first pin of the second electronic switch Q2, the other end of the third resistor R3 is connected to the second pin of the second electronic switch Q2, and the third pins of the first electronic switch Q1 and the second electronic switch Q2 are grounded; When the voltage at the pulsating DC terminal is less than the threshold voltage, the first electronic switch Q1 is turned off, the second electronic switch Q2 is turned on, and current flows through the third resistor R3; When the voltage at the pulsating direct current terminal is greater than or equal to the threshold voltage, the first electronic switch Q1 is turned on, the second electronic switch Q2 is turned off, and no current flows through the third resistor R3.

2. The circuit for improving power factor according to claim 1, characterized in that: The circuit for improving the power factor further includes a second voltage regulator tube DZ2, which is connected in series between the anode of the first voltage regulator tube ZD1 and the first pin of the first electronic switch Q1.

3. The circuit for improving power factor according to claim 2, characterized in that: The circuit for improving the power factor further includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; The third resistor R3 and the fifth resistor R5 connected in parallel, and the fourth resistor R4 and the sixth resistor R6 connected in parallel, are connected in series between the pulsating direct current terminal and the second pin of the second electronic switch Q2.

4. The circuit for improving power factor according to claim 3, characterized in that: The first electronic switch Q1 and the second electronic switch Q2 are NPN transistors, the first pin is the base, the second pin is the collector, and the third pin is the emitter.

5. The circuit for improving power factor according to claim 1, characterized in that: The first electronic switch Q1 and the second electronic switch Q2 are N-channel enhancement type MOS transistors, the first pin is a gate, the second pin is a drain, and the third pin is a source.

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