Method of controlling non-inverting buck-boost DC-DC converter and corresponding converter

Abstract

The invention relates to a method for controlling a non-inverting buck-boost DC-DC converter and a corresponding converter. A non-inverting buck-boost DC-DC converter operating in a ripple-hysteresis-current-mode-control includes: a control signal closing a first state of a first high side switch and a second low side switch; the control signal closes a second state of the first high-side switch and the second high-side switch; the control signal closes a third state of the first low side switch and the second high side switch; and a fourth state in which the control signal closes the first low-side switch and the second low-side switch. A peak voltage and a valley voltage of the control signal are detected. The transition between the first, second, third, and fourth states depends on peak voltage detection, valley voltage detection, expiration of a variable first time interval after entering the second state, and expiration of a fixed second time interval after entering the third state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000020445, filed on October 3, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present specification relates to a method for controlling a non-inverting buck-boost DC-DC converter, the non-inverting buck-boost DC-DC converter comprising a first input half-bridge coupled to one end of an induction coil and a second output half-bridge coupled to the other end of the induction coil, the second output half-bridge comprising a high-side switch. The first input half-bridge comprises a first high-side switch coupled between an input node and the end of the induction coil and a first low-side switch coupled between the end of the induction coil and ground. The second input half-bridge comprises a second high-side switch coupled between an output node and the other end of the induction coil and a second low-side switch coupled between the one end of the induction coil and ground. The control method comprises performing ripple-hysteresis-current mode control on the DC-DC converter by providing a control voltage as an error between a feedback signal from the output of the converter and a reference signal, the reference signal being a control signal applied to the switch of the converter obtained from the control voltage.

[0004] One or more embodiments may be applied to converters used in AMOLED applications. Background Art

[0005] DC-DC converters are currently used extensively in a variety of applications to generate the appropriate power supply voltage rails required by complex systems to operate and ensure the required performance. Many of these systems pay special attention to both efficiency and performance. In many applications, the converter is required to have great flexibility and multiple operating modes are required.

[0006] The non-inverting buck-boost (NIBB) converter is a switched inductor topology for DC-DC converters that allows the voltage to be proportional to the input voltage (V IN ) to adjust the output voltage (V OUT ).

[0007] For example, Figure 1An exemplary embodiment of a NIBB converter 10 is shown, which includes: an input node IN, to which an input voltage VIN is brought; an inductor L, i.e., an inductive coil, which is coupled to the input node IN at a first inductor terminal LX1 through a first half-bridge HB1, the first half-bridge HB1 including a high-side switch HS1 coupled between the input voltage VIN and the first inductor terminal LX1; and a low-side switch LS1 coupled between the first inductor terminal LX1 and the ground GND. In the same way, the second inductor terminal LX2 is coupled to an output node through a second half-bridge HB2, on which an output voltage VOUT of the NIBB converter 10 is formed, the second half-bridge HB2 including a high-side switch HS2 coupled between the output voltage VOUT and the second inductor terminal LX2, and a low-side switch LS2 coupled between the second inductor terminal LX2 and the ground GND. Therefore, the NIBB converter 10 includes two half-bridges with a total of four switches, and it can be regarded as a cascade of two DC-DC converters, respectively buck and boost, which share a common coil, i.e., the inductor L.

[0008] In consumer applications, miniaturization is very important and requires small external passive components, especially in terms of thickness. High efficiency at input voltage V IN and output voltage V OUT It is mandatory under every condition, especially under high loads where the thermal budget is limited. To meet this need, the DC-DC converter should keep the coil current low, allow reducing the silicon area (i.e., small power switch) and find a suitable inductor.

[0009] In AMOLED applications, the NIBB converter usually provides an input voltage V from 2.2V to 5V. IN The desired regulated output voltage is typically selected from 1.8V to 5.2V and represents the positive display panel voltage rail. The required performance of the converter is challenging and demanding, in fact, any ripple and transients on the positive regulated supply directly translate into display flicker, thus affecting the end user experience and overall display quality. For this reason, the converter is usually required to operate in continuous conduction mode (CCM) as the preferred operating mode.

[0010] Figure 2 Shows reports such as Figure 1 The conversion ratio of the standard NIBB converter shown is M = V OUT / V IN , thereby changing the duty cycle D of the PWM signal that drives the switch in its open and closed states.

[0011] Generally speaking, for any DC-DC converter, the coil current (I COIL) and the output load current (I LOAD ) is a good indicator which also allows to understand how much "work" the DC-DC converter needs and accumulates inside the coil to ensure output regulation: the lower such a ratio the better, meaning less work for the DC-DC converter and increased efficiency.

[0012] Among the different control methods applicable to NIBB converters, a specific current-mode control is now described: ripple-hysteresis-current-mode-control.

[0013] Figure 3A A schematic diagram of a control circuit 50 is shown, which is configured to control a device such as Figure 1 The DC-DC converter shown implements ripple-hysteresis-current mode control, while Figure 3B shows the control voltage v issued by the control circuit 50 c (t) timing diagram.

[0014] like Figure 3A As shown, the control voltage v c (t) is provided by the error amplifier (i.e., compensator, not shown) and then processed to obtain two symmetrically shifted versions: the peak voltage v c_p (t) and valley voltage v c_v (t). In particular, in summation block 51, for a given voltage offset ΔV c The sum is performed to obtain the peak voltage v c_c , while the same voltage is offset by ΔV by the corresponding subtraction block 52 c Subtract to get the valley voltage v c_v . Such a peak voltage v c_p (t) and valley voltage v c_v (t) and the sensing voltage v sense (t) is compared with the sensed voltage, which is the current I flowing in the coil L. COIL Proportional voltage: V sense =GI COIL The two hysteresis comparators 53 and 54 are used to convert the sense voltage v sense Respectively with the peak voltage v c_p (t) and valley voltage v c_v (t) is compared, and the outputs of the comparators 53, 54 are supplied to the set S and reset R inputs of the SR flip-flop 55, which are the main (i.e., active) switch output control action or command c(t) (supplied at the output Q of the SR flip-flop 55) of a general DC-DC converter (e.g., the high side in a buck DC-DC converter, the low side in a boost DC-DC converter). When such a main switch is operated, the coil current I COILIncrease and sense voltage V sense Also increases, when Vsense = V c_p (peak control voltage), the output Q (i.e., control action c(t)) is reset, turning off the main switch of the DC-DC converter. The coil current decreases, and the sense voltage V sense Also decreases; when Vsense=V c_v (i.e., valley control voltage) When the control action c(t) is set again, the main switch of the DC-DC converter 10 is turned on and a new switching cycle begins. Basically, the controller regulates the average coil current, and in fact, in the steady state, the control voltage v provided by the error amplifier c (t) is a scaled version of the average coil current (with the coil current I COIL and the sensing voltage V SENSE The scaling factor between them is given by the scaling factor G).

[0015] The advantages of this control algorithm are the inherent current limiting, the need for a simple compensator consisting of a Type II network rather than a more complex Type III network, and a fast reaction to any transients due to the inherent nonlinear response. c The coil ripple current is fixed (ΔI COIL =2ΔV c / G), and the DC-DC converter operates at a corresponding switching frequency. For this reason, the converter switching frequency depends on the operating conditions V IN 、V OUT , while L is the up / down slope of the coil current and depends mainly on these parameters. Another advantage of this control method is that it does not require any slope compensation ramp, which is necessary in fixed frequency current mode control.

[0016] In a NIBB converter, how the four switches are operated is important for the final DC-DC converter efficiency; different modes have been used and studied.

[0017] The solution is given by a four-phase trapezoidal current. In this case, Figure 4A The NIBB converter 10 shown again in FIG. 1 is operated in a single mode, wherein the coil current I COIL (t) consists of four phases P1, P2, P3, and P4 that follow one another in time t, thus forming a trapezoid, such as Figure 4B The introduction of an additional fourth phase P4 allows managing the minimum on-time of the second low-side switch LS2 and the minimum off-time of the first high-side switch HS1, in fact extending them; in fact, Figure 4CThe table shown in , which shows which switches HS1 , HS2 , LS1 , LS2 are operated according to phases P1 , P2 , P3 , P4 , shows that only a single switch is changed between each phase, thereby allowing each switch to operate two consecutive phases. Figure 4A The current paths on the converter 10 associated with the four phases P1 , P2 , P3 , P4 are shown.

[0018] The additional hold phase P4 is lossy by definition and should be minimized, otherwise it affects efficiency and increases the required coil current. Moreover, always executing with all 4-phases is inefficient and causes many difficulties when the value of the input voltage is much larger than the output voltage. In AMOLED applications, there may be two main problems. First, the required power switches may not be practical not only to meet the efficiency specifications, but also for thermal issues. Second, it is difficult to find a suitable low-profile inductor that supports such high currents (i.e. saturation current as well as rated current) while exhibiting a low DCR, i.e. DC resistance (to meet the efficiency specifications).

[0019] There is a need in the art to assist in addressing the many problems believed to exist in the context as discussed above. Summary of the invention

[0020] One or more embodiments may be directed to a method.

[0021] One or more embodiments may relate to a corresponding converter.

[0022] In an embodiment, the solution described herein relates to a method for controlling a non-inverting buck-boost DC-DC converter, the DC-DC converter comprising a first input half-bridge coupled to one end of an induction coil and a second output half-bridge coupled to the other end of the induction coil, the first input half-bridge comprising a first high-side switch coupled between an input node and the end of the induction coil and a first low-side switch coupled between the end of the induction coil and ground, the second input half-bridge comprising a second high-side switch coupled between an output node and the other end of the induction coil and a second low-side switch coupled between the other end of the induction coil and ground.

[0023] The method includes performing ripple-hysteresis-current mode control on the non-inverting buck-boost DC-DC converter, including providing a control voltage based on an error between a feedback signal from the output of the non-inverting buck-boost DC-DC converter and a reference signal; and performing at least a first comparison and a second comparison of the control voltage with a reference signal, the reference signal being proportional to a current flowing in the coil, and adding and subtracting an offset voltage in corresponding comparison operations, respectively, to obtain a control signal applied to one or more of the switches of the converter to drive their open and closed states.

[0024] The method further includes operating the control between a plurality of operating states, including: a first state, wherein the control signal determines that the first high-side switch and the second low-side switch are closed; a second state, wherein the control signal determines that the first high-side switch and the second high-side switch are closed; a third state, wherein the control signal determines that the first low-side switch and the second high-side switch are closed; and a fourth state, wherein the control signal determines that the first low-side switch and the second low-side switch are closed.

[0025] The method also includes performing at least the first and second comparisons for detecting reaching a peak voltage and a valley voltage, respectively, and the operational control includes: transitioning from the first state to the second state when reaching the peak voltage is detected; transitioning from the second state to the first state when reaching the valley voltage is detected; transitioning from the second state to the third state when a variable first time interval measured from entering the second state is detected to have expired, the length of the variable first time interval varying as a function of a set of detection parameters and decreasing as the input voltage increases, the control voltage being detected as not having reached the valley voltage; transitioning from the third state to the fourth state when reaching the valley voltage is detected and a second time interval having a fixed length measured from entering the third state has not expired; transitioning from the third state to the first state if the second duration expires and the valley voltage is reached; and transitioning from the fourth state to the first state if the second duration expires.

[0026] In an embodiment, said length of the first time interval also decreases as a function of the difference between the input voltage and the output voltage.

[0027] In an embodiment, the converter is configured to: operate in a buck boost mode if the input voltage is close to the output voltage within a determined voltage range; operate in a step up mode if the input voltage is lower than the output voltage and outside the range; and operate in a step down mode if the input voltage is greater than the output voltage and outside the range; and the transitions (passes) between the three operating modes are regulated by selecting the values ​​of the set of detection parameters and the fixed length of the second time interval.

[0028] In an embodiment, the step-up mode includes: in a switching cycle of the control signal, switching from a first state to a second state when the control voltage reaches the peak voltage, and switching from the second state to the first state when the control voltage reaches the valley voltage.

[0029] In an embodiment, the buck-boost mode includes in a switching cycle of a control signal: transitioning from the first state to the second state when the control voltage reaches the peak voltage; transitioning from the second state to the third state when a first determined time length expires, and the control voltage is detected as not having reached the valley voltage; transitioning from the third state to the fourth state when it is detected that the control voltage reaches the valley voltage and a second time interval having a fixed length has not expired; and transitioning from the fourth state to the first state if the second determined time length expires.

[0030] In an embodiment, when the control voltage reaches the peak voltage, the step-down mode includes, in a switching cycle in which the control signal switches from a first state to a second state: switching from the second state to a third state when a first determined time length expires, and the control voltage is detected as not having reached the valley voltage; and switching from the third state to the first state if a second determined time length expires and the valley voltage is reached.

[0031] In an embodiment, the startup process of the converter comprises: providing a fixed frequency startup clock to the converter; at the beginning, placing the converter in a first startup state, in which only the first high-side switch is asserted, which lasts until the coil current reaches a peak value, signaled by asserting a corresponding peak signal, and then performing a transition to a second state, in which the coil discharge is performed at a subsequent rising edge of the startup clock, in particular by asserting only the first low-side switch, entering the first state if the output voltage has not reached a given minimum value, or entering a third state, in which the ripple-hysteresis-current mode control is performed.

[0032] In an embodiment, said operational control comprises said detection of expiration of a variable first time interval measured from entering said second state and detection of expiration of a fixed second time interval measured from entering said third state, said operational control comprising sending of a respective signal starting said measurements.

[0033] The solution also relates to embodiments of a control circuit for a non-inverting buck-boost DC-DC converter configured to perform ripple-hysteresis-current-mode-control.

[0034] In an embodiment, the control circuit includes a circuit configured to compare the control voltage with a sense voltage to detect when it reaches a peak or a valley, assert a corresponding peak flag or a valley flag, and the circuit includes a first circuit configured to detect expiration of the determined length of time proportional to the difference between the input voltage and the output voltage for asserting a corresponding buck timer flag, and a second circuit configured to detect expiration of the second determined length of time for asserting a corresponding minimum timer flag.

[0035] In an embodiment, the circuit configured to compare the control voltage is configured to compare the control voltage in the comparator with a shifted sensing voltage, the shifted sensing voltage being obtained by applying a voltage proportional to the current flowing in the coil to the shift resistor and injecting a fixed current, an upward current proportional to the difference between the output voltage and the input voltage, and a downward current proportional to the inverse of the difference between the output voltage and the input voltage in a node of the shift resistor coupled to the input of the comparator. Specifically, the shifted sensing voltage is applied to the positive input in the first comparator to obtain the peak mark, and the shifted sensing voltage is applied to the negative input in the second comparator to obtain the valley mark.

[0036] In an embodiment, the control circuit includes a timer circuit, which is configured to detect the first time interval, the timer circuit includes a capacitor, the capacitor is charged by a current having a first proportional factor to the input voltage, and in particular, is charged by a current having a second proportional factor to the difference between the input voltage and the output voltage, the voltage drop across the capacitor is compared by a comparator with a reference time voltage to obtain the timer step-down flag value, and the detection parameter group includes the value of the capacitor, the reference time voltage, the first proportional factor, and in particular also includes the second proportional factor.

[0037] In an embodiment, the circuit comprises a timer circuit for detecting the second time interval, the timer circuit comprising a corresponding capacitor charged by a given fixed current, the voltage drop across the capacitor being compared by a comparator with a corresponding time reference voltage to obtain the minimum timer mark value.

[0038] In an embodiment, the circuit is configured to send the respective signal initiating the measurement to a switch enabling the charging of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0040] Figure 1 , 2 , 3A, 3B and 4A to 4C have been described above;

[0041] Figure 5 is a schematic representation of a state diagram illustrating a method;

[0042] Fig. 6A and 6B A circuit diagram of a converter controlled by the method and a switching state table of a converter according to the control method are respectively shown;

[0043] Fig. 7A , 7B 7C respectively show a circuit diagram of a converter controlled by a method in a first control mode, a timing diagram of a coil current in the first control mode, and a state table of switches of the converter in the first control mode;

[0044] Fig. 8A , 8B 8C respectively show a circuit diagram of a converter controlled by a method in a second control mode, a timing diagram of coil current in the second control mode, and a state table of switches of the converter in the second control mode;

[0045] Fig.9A , 9B 9C and 9D respectively show a circuit diagram of a converter controlled by the method in a third control mode, a timing diagram of the coil current in the third control mode, and a state table of switches of the converter in the third control mode;

[0046] Fig.10 A circuit schematic diagram showing a portion of a circuit implementation of a control circuit implementing the method;

[0047] Fig.11 yes Fig.10 An alternative circuit diagram for realizing the method of;

[0048] Fig.12 and Fig.13 A circuit schematic diagram showing an implementation of a timer used by a control circuit implementing the method;

[0049] Fig.14is a circuit diagram of a sensor used in a control circuit implementing the method;

[0050] Fig.15 A state diagram schematically illustrating a start-up process of a converter implementing the method is shown;

[0051] Fig.16 shows a timing diagram illustrating the operation of the converter during the startup procedure; and

[0052] Fig.17 A timing diagram is shown, illustrating the operation of the converter in the transition from the start-up procedure to the control method. DETAILED DESCRIPTION

[0053] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0054] References to "one embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0055] The references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0056] The solution proposed here is based on the observation of the above-mentioned four-phase trapezoidal coil current operation compared to the desired / ideal NIBB converter.

[0057] When the input voltage V IN Much lower than the output voltage V OUT , the coil current becomes huge, which represents a major problem: In this case, ideally, the NIBB converter should be operated as a classic step-up DC-DC, which is usually best, operating only the second half-bridge, i.e. switches HS2, LS2, leaving the first low-side switch LS1 open and the first high-side switch HS1 always on. Then, only at voltage V IN and voltage V OUTWhen approaching, the additional fourth stage is not always needed. In fact, only in this case, the minimum second low-side switch LS2 on-duration and the first low-side switch LS1 on-duration are critical and, if not managed correctly, cause the converter to naturally skip some cycles (first half-bridge or second half-bridge or both), resulting in undesirable higher output voltage ripple. Under all other conditions, this additional stage should ideally be avoided to improve efficiency and reduce coil current. Finally, considering the stringent requirements for fast line transients in AMOLED applications, it is necessary to customize a fast control loop that can maximize the converter bandwidth and exploit nonlinearities to enhance any transient response.

[0058] Figure 5 A state diagram illustrating an embodiment of the proposed method for controlling a non-inverting buck-boost DC-DC converter is shown.

[0059] In each switching cycle of the control signal, e.g., c(t) as described above, their sequence depends on different events, including:

[0060] Detect the given coil current peak value (by controlling the voltage V C defined by the compensator or error amplifier). In this case, for example, Fig.10 The RHCP circuit 60 asserts the peak mark signal PEAK, for example, set to 1;

[0061] Detect the given coil current valley value (by controlling the voltage V C In this case, the valley flag signal VALLEY is asserted, e.g. Fig.10 The RHCP circuit 60 is set to 1;

[0062] When a time corresponding to the first determined duration is reached, a timeout on the first buck timer is detected, (eg, Fig.12 70) asserting the buck timer flag TIMER_BUCK to, for example, 1; and

[0063] When the time corresponding to the second determined duration is reached, a second fixed minimum timer (eg, Fig.13 80) times out, asserts the fixed minimum timer flag signal MIN_TOFF, for example, sets it to 1.

[0064] Figure 6B Shows the corresponding Figure 4B The stages are P1, P2, P3, P4 and their paths. Fig. 6A Shown according to Figure 4BThe control signal c(t) of each of the phase control switches HS1, LS1, HS2, LS2 is in its open and closed state. Of course, the control signal c(t) thus corresponds to four commands, according to Figure 4B The phase controls each switch with one command.

[0065] according to Figure 5 In the state diagram, if the peak flag PEAK=1, a transition T12 from stage or state P1 to stage or state P2 is executed, and if the valley flag VALLEY=1, a reverse transition from stage P2 to stage P1 is executed. If, when in stage P2, the buck timer flag TIMER_BUCK is 1, i.e., asserted, because the associated first determined duration is reached or has expired, a transition T23 to stage P3 is executed. If the valley flag VALLEY=1 and the minimum timer flag MIN_TOFF=1 (i.e., asserted), a transition T31 from stage P3 to stage P1 is executed from stage P3 because the associated second determined duration is reached or has expired. If the valley flag VALLEY=1 and the minimum timer flag MIN_TOFF=0, i.e., the corresponding second timer (e.g., 80) has not timed out, i.e., the second determined time has not expired, a transition T34 from stage P3 to stage P4 is executed. When such a second timer times out, i.e. the minimum timer flag MIN_TOFF=1, a transition T41 from phase P4 to phase P1 is performed. This second determined duration of the fixed minimum timer flag signal MIN_TOFF is therefore selected as the time after the fourth phase P4 is enabled in order to avoid skipping cycles. In particular, the timeout length of the flag MIN_TOFF must be minimized (for efficiency reasons as explained before), but so that in the first position, the first high-side switch: LS1 remains activated (during the cumulative time of phase P3 plus phase P4) for a time longer than its feasible minimum time, and then the second low-side switch LS2 must remain activated (during the cumulative time of phase P4 plus phase P1) for a time longer than its feasible minimum time. Thus, the solution provides that in the state corresponding to phase P3, the first low side switch LS1 is operated, but if the valley flag assertion (i.e., VALLEY=1) arrives too early, which means that the duration of activation of the first low side switch LS1 is lower than its feasible minimum value, the system enters a state or phase P4, in which LS1 is still operated and remains in operation for a duration (the cumulative time in state P3 plus state P4) longer than its feasible minimum value. The same applies to the second low side switch LS2, since it is operated in state P4.

[0066] From another point of view, when the input voltage VIN is close to the output voltage VOUT, both situations when HS1=1=LS2 and HS2=1=LS1 become very short, because there is no need to charge (HS1=1=LS2) and discharge (HS2=1=LS1) the coil a lot, so the "regulation / buffering" state P4 is introduced, but its time length is minimized.

[0067] Furthermore, not only the minimum on-time of the first low-side switch LS1 but also the minimum off-time of the first high-side switch HS1 should be considered. The slowest power switch is the switch that should be considered when setting the time length of the timeout MIN_TOFF (the same applies to LS2 and HS2).

[0068] Therefore, the control signal c(t) is sent from the logic control module 100 to the converter 10, and the logic control module 100 implements Figure 5 The control module 100 (eg, a finite state machine) controls the RHCP control circuit (eg, Fig.10 The circuit 60 in FIG. 60 receives the flags PEAK and VALLEY from the timer circuit (e.g., Fig.12 The circuit 70 shown in FIG. 1 receives the flag TIMER_BUCK and receives the flag TIMER_BUCK from another timer circuit (eg, Fig.13 These modules 100, 60, 70, 80, together with a current sensor (e.g., sensor 90) for detecting the current flowing in the converter 10, may be collectively represented as a circuit for use in accordance with the present disclosure and referenced herein. Figure 5 The control module 100 may also issue a reset signal RST. BU , RST MIN of the control circuits 70, 80 to start the time intervals in the detection circuits 70, 80 when entering the corresponding states (eg, P2 and P3).

[0069] depending on Figure 5 The events and transitions indicated in Fig. 6A The NIBB converter 10 shown in FIG. 1 with the respective paths in the different phases P1, P2, P3, P4 may be operated differently, and in particular, based on Fig. 6A According to the state diagram, three operation modes are possible:

[0070] The first mode of operation of the NIBB converter 10 is a step-up boost mode. In this first mode, the NIBB converter 10 operates as a hysteretic current ripple controlled boost converter, acting only on the second half-bridge HB2 (i.e., switching the second high-side switch HS2 and the low-side switch LS2), while not switching the first half-bridge HB1 (i.e., the low-side switch LS1 remains off and the high-side switch HS1 is fixed on). This corresponds to performing a step-up operation at each switching cycle of the control signal controlling the switch. Figure 5 The performance is maximized, in fact, the DC-DCNIBB converter 10 is regulated with a classic two-phase delta coil current, such as Figure 7B As shown. Figure 5 The state diagram of Figure 5 In the first state in FIG. 1 , the NIBB converter 10 charges the coil L as in a classic step-up DC-DC, and this phase P1 lasts until the coil current I COIL (t) Peak value (peak value PEAK = 1); In the next stage P2, the coil L discharges until the coil current I COIL (t) reaches the valley value (valley flag VALLEY=1), and the NIBB converter 10 starts a new switching cycle with phase P1. It should be noted that in the state corresponding to phase P2, not only the valley coil current I COIL (t), but also monitors the timeout of an adapted analog time detection circuit (or timer) generating a timer flag TIMER_BUCK: this circuit indicates that the second phase P2 has reached the maximum possible time limit and is adapted to (i.e. it depends on (e.g. is proportional to) the difference V between the input and output voltages IN -V OUT This means that if the input voltage V IN As the voltage changes closer to the output voltage value, the first determination time is reduced, thereby timely determining the assertion of the timer flag TIMER_BUCK before the assertion of the valley flag VALLEY. However, in the step-up mode, at V IN Much lower than V OUT In the case of , the coil valley current I is detected before the detection circuit generating the timer flag TIMER_BUCK times out. COIL (t); As mentioned above, this occurs when the input voltage is much lower than the output voltage, below the point where the valley flag VALLEY=1 occurs before the timer flag TIMER_BUCK=1. It is emphasized that the length of the timeout for generating the timer flag TIMER_BUCK is measured from the beginning of the second phase P2;

[0071] The second mode, buck-boost mode: Here, as Figure 8A-8CAs shown, the NIBB converter 10 operates with a 4-phase trapezoidal coil current, and as described above, when the input voltage V IN Close to the output voltage V OUT , the DC-DC converter 10 operates in this mode, i.e., so that the timer flag TIMER_BUCK has enough time to be asserted before reaching the valley value of the control signal. The switching cycle starts from the same phase P1 as in the previous mode; as described above, in this case, in phase P2, the first trigger event is not the valley coil current detection (VALLEY=1) as in the previous mode, but the timeout of the first timer sets the timer flag TIMER_BUCK to 1, which triggers transition T23. The NIBB converter 10 moves to the state corresponding to phase P3, and the coil current I COIL (t) discharges as in a classic buck DC-DC: in other words, it discharges with the steepest possible slope V OUT / L (i.e., fastest discharge) discharge. In phase P3, the coil current I is still monitored. COIL (t), i.e. detecting whether the valley value is reached, as in phase P2, but also monitoring the minimum timer asserting the minimum flag MIN_TOFF. It should be emphasized that the timeout length for generating the timer flag MIN_TOF is measured from the beginning of the second phase P3. In this mode, the first trigger event is the detection of the valley coil current I before the second minimum timer has reached the timeout setting the flag MIN_TOFF to 1. COIL (t) value; this indicates that such phase P3 is short (ie, the coil current discharges at the steepest slope for only a short period of time) and the system moves in state P4, in which the coil current I is maintained COIL Until the aforementioned minimum timer reaches a timeout and the flag MIN_TOFF is asserted. Figure 8B The coil current I in this operating mode is reported in COIL (t), where in phases P2 and P3, the dashed line refers to the input voltage V IN Slightly higher than the output voltage V OUT The solid line refers to the output voltage V OUT Slightly higher than the input voltage V IN The situation that the coil current decreases during phase P2 (= the coil current I in the second phase P2) COIL (t) will be flat); and

[0072] The third mode is the step-down mode. In this mode, the NIBB converter 10 operates using a three-phase coil current operation, such as Figures 9A-9C, and as will be clear, this is the case when the input voltage is much higher than the output voltage. Here, the operation is similar to the previous buck-boost mode, the only difference being that the last and fourth phase, P4, is avoided. In fact, when the state of phase P3 is reached, the minimum timer setting the flag MIN_TOFF is set to the minimum value after the valley current I COIL (t)(Transition T31) is triggered before VALLEY=1 and MIN_TOFF=1, that is, when VALLEY=1 and the time length of the timeout of the flag MIN_TOFF has elapsed, the system moves from phase P3 to phase P1, indicating that the coil discharge with a steep slope is not short, but lasts for a sufficient time to allow proper switching of the first low-side switch LS1 (that is, sufficient on-time).

[0073] In the boost mode (first mode), the NIBB converter 10 acts as a ripple-hysteresis-current controlled DC-DC, while in the other modes (second, buck-boost and third, step-down), the control procedure is no longer a ripple-hysteresis-current mode, but a mixed one. In fact, in the buck-boost mode as well as in the step-down mode, the control voltage no longer controls the actual peak coil current. During the first phase P1, the control voltage V C A given amount of current must be stored in the coil L; it should be emphasized that this corresponds to the coil current I COIL (t) The peak value. In fact, in the second phase P2, the coil current I COIL (t) can still be increased (if V IN >V OUT ) or decrease (if V OUT >V IN ). Ideally, without taking losses into account, in the solution described here, the coil current I COIL The valley value of (t) is always determined by the control voltage V C Fixed, in fact, when detected by the control voltage V C Specified coil current I COIL (t) value, the coil discharge is always completed. Always control the voltage V C Indicates the coil peak and valley currents, and in fact the algebraically increasing voltage offsets are fixed / constant, as they are not controlled by any loop. They are actually tuned according to the input voltage VIN and the output voltage VOUT, but again not controlled by any loop. Now consider the non-idealities and losses, i.e. the fourth stage P4 has losses, and the coil current I COIL (t) does not remain completely flat, but decreases slightly, dissipated by the on-resistance of the first low-side switch LS1 and the second low-side switch LS2.

[0074] The switching period of the control signal c(t) is the period of the control signal c(t) issued by the control module, such as Figure 3A-3B As shown or referenced below Figure 10-11 Repeats itself, specifically repeats its phase pattern, for example two phases P1-P2 in the first mode, four phases P1-P2-P3-P4 in the second mode, three phases P1-P3 in the third mode. In other words, a cycle can generally be defined by the repetition of the first phase P1, which is the phase that is always executed in each cycle of each mode at the beginning.

[0075] Fig.10 A possible implementation of the proposed solution is reported. It shows the control circuit 60 outputting the control voltage v c (t) and its valley mark VALLEY and peak mark PEAK. Fig.12 and Fig.13 A portion of the control circuit 60 is shown which operates as a timer 70, 80, and Fig.14 A current sensor is shown that provides a sense current to the control circuit 60. A voltage buffer may be present between the current sensor and the terminal over which the sense current is provided, thereby forming a sense voltage SENSE as described below P , SENSE N .

[0076] The control circuit 60 includes an error amplifier 62 implemented by an operational transconductance amplifier (OTA) that calculates the error between a feedback signal FB and a reference signal REF. The feedback signal FB is taken, for example, from the converter output, such as the output voltage V OUT or a signal obtained from it by a feedback network, the reference signal REF is used, for example, for the output voltage V OUT The reference voltage is used as the control voltage V by buffer 63. C Provided to a peak detector 64 and a valley detector 65, two comparators are provided to the negative and positive inputs, respectively, so that the offset is added with opposite signs as described below. The error amplifier 62 generating the control voltage is in this example an OTA with a type II compensation network, but in general it can also be an operational amplifier with a compensation network locally closed in the feedback on the feedback signal FB. SENSE represents a low impedance voltage signal provided by a circuit that performs coil current sensing to monitor the coil current I COIL (t) and provides a scaled copy of the voltage, SENSE, with a proportionality factor G. Such a circuit is not shown in the figure, but Fig.14An example of such a circuit, indicated generally at 90, for performing current sensing monitoring is shown in FIG. Based on the low impedance voltage SENSE, two offset voltages are added, of equal magnitude and opposite sign, to obtain a downwardly shifted sense voltage SENSE at the other input of the valley comparator 64. P , and obtain the upward shifted voltage sense SENSE at the other input of the peak comparator 65 V , are the downward and upward displacements ΔV respectively C =R SHIFT (I FIXED +I UP -I DOWN ), where R SHIFT , respectively indicate the shift resistors connected in series between the voltage SENSE and the nodes, the nodes are respectively the positive input of the peak comparator 64 and the negative input of the valley comparator 65, wherein the three currents are added together to form the rising current I UP , falling current I DOWN and fixed current I FIXED , the rising current indication value is proportional to the rising current I of the positive current UP , which passes through the rising resistor R UP For the difference between the output voltage and the input voltage (when the input voltage is higher than the output voltage, the current is clamped to 0), the drop current is the difference between the output voltage and the input voltage (when the output voltage is higher than the input voltage, the current is clamped to 0), and has another proportionality factor, the drop resistance R DN Such currents, upward current, downward current, and fixed current are shown as being generated by current generators 66p, 67p, 68p for the peak branch and current generators 66v, 67v, 68v for the valley branch, respectively. In general, the control voltage V can be obtained directly from the error amplifier 62 C , or as shown, a feed-forward action can be added on top of the voltage provided by the error amplifier, i.e. allowing improved fast out-of-loop compensation for specific transients / events to obtain the control voltage; this is not mandatory and is used to optionally introduce specific feed-forward actions to increase transient performance on specific events. For example, when the input voltage V IN When experiencing a sag, instead of waiting for a slow compensation action from the error amplifier 62, the control voltage is shifted directly upward, allowing the DC-DC converter 10 to suddenly increase its coil current and improve output transients.

[0077] exist Fig.10 , resistors R1 and R2 represent a bias network for the input of amplifier 62, while the series connection of resistor Rc and capacitor Cc coupled between the positive input of buffer 63 (on which voltage VBUFF is developed) and ground operates as a Type II compensation network, e.g., C C =70pF, RC =90kΩ, Between the output of buffer 63 and the input of comparator 64, 65 (64 positive, 65 negative) is a feed-forward resistor RFF. The bias current generator 69 is connected to the feed-forward resistor R FF The input bias current is absorbed by the voltage buffer 63 and the input voltage V IN A proportional variable current is input to the same node by a variable generator 69a.

[0078] The peak current (or better, coil current charge) detected in the peak comparator 64 is the sum of the sensed coil current signal plus its downward shift (ie, offset ΔV C )(or minus its displacement ΔV C ) triggers V when the control voltage is reached C , thereby triggering comparator 64 to indicate PEAK=1 (ie, asserted, e.g., outputting a logic high). In the same manner, when the sensed coil current signal is added with its upward shift (ie, offset ΔV C )(or simply add its displacement ΔV C ) reaches the control voltage V C , the valley current detection in valley comparator 65 triggers, thereby triggering the comparator to indicate VALLEY=1. In a general implementation, a single comparator can be used to detect both events by simply multiplexing its inputs; moreover, the polarity of such an event is not strict, but can be selected according to another rule or form. Fig.10 In the implementation shown, the offset ΔV C has been introduced into the coil current sensing voltage, and the control voltage V C has been directly monitored by the comparators 64, 65. For this reason and for precise reasons, the offset ΔV C It should not be referred to as ΔV C The exact equivalent is ΔV SENSE , this is because they define the ripple coil current ΔI on coil L COIL However, another equivalent and possible implementation would be to generate the control voltage V C The offset ΔV C , get V C_V and V C_P ,like Fig.11 shown.

[0079] It is important to note that the introduction of an offset ΔV C For input voltage V IN and output voltage V OUT dependence to reduce and compensate for the input voltage V IN and output voltage V OUTRipple coil current ΔI COIL , so that the input voltage V IN and output voltage V OUT In many applications, the switching frequency is not imposed and must be constant, but the ripple coil current ΔI COIL Depends on the input voltage V IN and output voltage V OUT Allows for reduced switching frequency expansion.

[0080] If V IN <V OUT :

[0081] If V IN >V OUT :

[0082] Therefore, if the input voltage V IN Lower than the output voltage V OUT , then the ripple coil current ΔI COIL With fixed current I FIXED And the rising current I UP is proportional to the sum (multiplied by the ratio of 2Rshift / G), and if the input voltage V IN Greater than the output voltage V OUT , then the ripple coil current ΔI COIL With fixed current I FIXED And the falling current I DOWN The sum is proportional (multiplied by the ratio of 2Rshift / G).

[0083] The two analog timers discussed, namely, counting the timeout of the adapted analog counter (the timer flag TIMER_BUCK is set to 1) and counting the timeout of the fixed minimum timer (the fixed minimum timer MIN_TOFF is set to 1), can be as described in reference Fig.13 is implemented as described, Fig.13 It refers to the first timer 70 detecting the timeout of the buck timer flag TIMER_BUCK. In this case, the resistor R is connected to the input voltage V IN A variable current proportional to the input of the variable generator 71 is fed into the same node, i.e., at a given step-down timer capacitor C BU Provides an adaptive current V IN / R, thereby generating a voltage ramp with hysteresis on the positive input of comparator 72. When such a voltage ramp equals the step-down reference voltage REF BUWhen such a comparator 72 is triggered, thus signaling a timeout. BU The reset switch 74 is controlled so that the capacitor C BU The next timeout detection starts when the reset switch 74 is deasserted and the reset switch 74 is in the reset signal RST BU When asserted, it couples to capacitor C BU The current generator 73 is coupled to the input of the comparator 72. The current generator 73 is coupled to the step-down timer capacitor C BU Provides current (V IN -V OUT ) / R BU , R BU is the resistance scaling factor.

[0084] refer to Figure 5 state diagram, switch 74 or equivalently reset signal RST BU In the second phase P2 is deasserted, i.e., the capacitor C BU Charging, while in the other phases it is asserted, operation is disabled, meaning that the timer 70 is detected only during the second phase P2.

[0085] Similarly, in order to IN and V OUT To balance the switching frequency over all possible variations, mainly for optimization purposes, the timer 70 is made dependent on the voltage V IN and V OUT (through current generator 73). In particular, always adopt the same input voltage V IN proportional to the current, and when V IN >V OUT , using another (always positive) contribution proportional to the difference between them (when V IN <V OUT This current is clamped to zero).

[0086] Fig.13 A timer 80 is depicted for a minimum fixed timer flag MIN_TOFF. The operating principle is similar to that of the timer 70, but here the current for charging the capacitor is a fixed constant. In this case, the current generator 81 charges the capacitor C at a fixed minimum time. MIN The input current I MIN , thus coupling to the minimum time capacitor C MIN A voltage ramp is generated on the positive input of comparator 82 at the same node as the reference voltage REF. MIN When such a comparator 82 is triggered, thus signaling a timeout. MINThe reset switch 84 is controlled so that the capacitor C MIN When the reset switch 84 is reset by the reset signal RST MIN When deasserted, the next timeout check begins.

[0087] refer to Figure 5 State diagram, timer reset signal RST MIN Asserted during phases P1 and P2 and de-asserted during phases P3 and P4, which means that the timer 80 detects a timeout during phases P3 and possibly P4.

[0088] Thus, the control comprises at least said detection of the expiration of a variable first time interval measured from entering said second state P2 (e.g. a flag TIMER_BUCK) and of the expiration of a variable second time interval measured from entering said third state P3 (e.g. a flag MIN_TOFF), thereby sending a respective reset signal RST starting said measurement. BU , RST MIN .

[0089] Of course, timers may generally be implemented differently, and digital counters may also be employed.

[0090] In the following Table 1, the ideal timing of the various phases is reported for the CCM (Continuous Current Mode) case; given the complexity of the results, only the ideal case without losses is given. Once the ripple coil current (defined as ΔI COIL ) is fixed (by setting the control voltage offset ΔV C The value of the timer (e.g. 70 and 80) and the timeout duration (indicated by the MIN TOFF and TIMER BUCK The switching frequency and duration or length of phases P1, P2, P3 and P4 are defined by the timeout represented by , as shown in Table 1.

[0091]

[0092]

[0093] Table 1

[0094] It is important to emphasize that the boundaries of each operating mode are not fixed but change according to the losses, so for a given input voltage V IN and output voltage V OUT , which depends on the load current. When the load current increases, the DC-DC converter must increase its duty cycle and store more charge in the coil L; in other words, the work of the DC-DC converter 10 increases, and the value of the converter 10 operating in the step-up mode (V IN, V OUT )(That is, if placed on the axis with V IN and V OUT The number of areas on the graph) increases, while the value pairs associated with the step-down mode (V IN , V OUT ) is reduced. Therefore, the behavior of the above converter can be simply summarized as follows. The first phase P1 of the NIBB converter 10 is always executed and used to excite the coil L. During this charging phase, i.e. P1, the input voltage V IN The higher the coil current I COIL The higher the slope, the easier it is for the coil L to store current. The second phase P2 can be a discharge phase (if V IN <V OUT ) or charging phase (if V IN >V OUT ). In the first case, when the input voltage V IN Keep away from output voltage V OUT When the coil current I COIL The slope over time is quite large, so the valley current detection (such as comparator 65) is designed to be triggered before the timeout TIMER_BUCK. It should be emphasized that without the buck timer (such as 70) issuing the buck timer flag TIMER_BUCK, the second phase P2 will never end and V IN >V OUT or V IN =V OUT , because the valley current detection 65 will never be triggered. To this end, a buck timer flag TIMER_BUCK is issued by the buck timer (e.g. 70) to set a limit on the second stage P2. Fig.12 In the embodiment, the timer 70 is analog and the current generator 71 is used to make the timeout duration of the flag TIMER_BUCK depend on the input voltage V IN , thereby allowing the NIBB converter 10 to operate at an input voltage V IN When the input voltage V IN The lower the timer 70, the slower it is, allowing execution in step-up mode. IN As V increases, the timer reaches the timeout detection sooner, while the coil current slope decreases and the valley detection trigger in comparator 65 occurs later. In the second case, if V IN <V OUT However, if their values ​​are close, the coil L discharges slowly and cannot trigger the valley current detection 65. In this second case, the step-down timer 70 is set according to the input voltage V INThis speeds up its timeout detection, also because of the addition of another current contribution. This allows reducing the duration of the second phase P2, thus equalizing the switching frequency; in fact, for high input voltages V IN The coil L has been well charged from the first phase P1 and does not need to store more charge in the second phase P2. In the buck-boost mode BB and the step-down mode SD, the second phase P2 can be identified as a phase in which the current I COIL is converted to the output without actually discharging the coil L too much; on the contrary, phase P3 is needed in both modes to release the coil current and transfer it to the load. In this phase P3, especially in the buck-boost mode, when V IN <V OUT (where the coil current has already started to decrease in phase P2), at a fixed minimum timer (e.g., Fig.13 Before the timeout is indicated by 80 in the figure, the valley detection may be triggered, i.e., VALLEY=1, thereby setting the fixed minimum timer flag MIN_TOFF to 1, which means that the duration of phase P3 is already very limited, potentially resulting in the minimum power switch action time. For this reason, the fixed minimum timer, such as 80, is adjusted, i.e., by setting the current I MIN The value of is set to the minimum value required to allow proper driving of switches LS1 and LS2, as described above. In the event that this fixed minimum timer is not triggered when the valley current detection 65 is triggered, an additional extended phase P4 is added, in which the coil current I is maintained COIL In this way, a timing buffer is added to appropriately accommodate the first low side switch LS1 drive circuit, and phase P1 is started with the second low side switch LS2 already turned on, thereby allowing phase P1 to be unconstrained by the second low side switch LS2 drive circuit (and therefore its operating time).

[0095] As already mentioned, the timeout signaled by the flag TIMER_BUCK is chosen, in particular the added offset ΔV C , with an input voltage V IN and output voltage V OUT The switching frequency F is balanced over the entire range SW In step-up mode, the switching frequency F SW Naturally higher than the other modes, since there are only two phases. In the same way, the slowest switching frequency F SW is associated with a buck-boost mode with four phases. From an ideal point of view, this is exactly the desired behavior. In fact, in step-boost mode, due to the large step-up ratio, the effort required of the DC-DC converter 10 is high, so the converter 10 must operate faster, i.e. with a higher switching frequency FSW , to provide as much current as possible (switching frequency F SW The higher the better). On the contrary, when the input voltage V IN Close to the output voltage V OUT , the effort required of the converter 10 approaches zero, since ideally it should keep “passing” even if V IN =V OUT There is no switching (ie, the lower the switching frequency, the better).

[0096] Therefore, based on the above, the solution described herein relates to a method for controlling a non-inverting buck-boost DC-DC converter 10, the DC-DC converter comprising: Figure 1 A first input half-bridge HB1 and a second output half-bridge HB2 are depicted.

[0097] The method includes performing ripple-hysteresis-current mode control on the non-inverting buck-boost DC-DC converter 10, including providing a control voltage (e.g., V) based on an error between a feedback signal (e.g., FB) at the output node OUT of the non-inverting buck-boost DC-DC converter 10 and a reference signal (e.g., REF). C (t));

[0098] Execute the control voltage (V C (t)) and a reference signal (e.g., Fig.11 SENSE or Fig.10 At least a first comparison (e.g., comparator 53 or 64) and a second comparison (e.g., comparator 54 or 65) of SENSEP, SENSEV in the reference signal with the current (e.g., I COIL ), the offset voltages are added and subtracted in corresponding comparison operations, respectively, to obtain control signals (e.g., c(t)) applied to one or more of the switches HS1, LS1, HS2, LS2 of such converter 10 to drive their open and closed states, Fig.11 In the case of C is applied to the control voltage V C (t), while Fig.10 In the C =R SHIFT (I FIXED +I UP -I DOWN ), which is used to shift the voltage SENSE up or down to obtain the voltage SENSE P 、SENSE V, obtaining a control signal, such as c(t), applied to one or more of the switches HS1, LS1, HS2, LS2 of the converter 10 to drive their open and closed states;

[0099] Wherein, the method includes operating control in multiple states (e.g., operating P1, P2, P3, P4), including:

[0100] A first state P1, in which the control signal c(t) determines that the first high-side switch HS1 and the second low-side switch LS2 are closed;

[0101] A second state P2, wherein the control signal c(t) determines that the first high-side switch HS1 and the second high-side switch HS2 are closed;

[0102] a third state P3, wherein the control signal c(t) determines that the first low-side switch LS1 and the second high-side switch HS2 are closed; and

[0103] The fourth state P4, wherein the control signal c(t) determines that the first low-side switch LS1 and the second low-side switch LS2 are closed. Of course, in each state, the other switches (not indicated) of the converter 10 are preferably open, as shown by the current path in the figure.

[0104] The method includes performing at least the first comparison (e.g., 53 or 64) and the second comparison (e.g., 54 or 65) to detect a peak voltage reaching an assertion flag PEAK and a valley voltage asserting a flag VALLEY, respectively;

[0105] When it is detected that the peak voltage is reached (for example, PEAK=1), the first state P1 is switched to the second state P2 (for example, switching T12);

[0106] When it is detected that the valley voltage (eg, VALLEY=1) is reached, the second state P2 is converted (eg, transition T21 ) to the first state P1 ;

[0107] Upon detection of expiry of a variable first time interval, for example transition T23 from the second state P2 to the third state P3, the variable first time interval in particular asserts a flag TIMER_BUCK, the length of which is used as a set of detection parameters (eg Fig.12 In the circuit 70, R, C BU , R BU ) and varies with the input voltage V IN decreases as the injection into capacitor C BU One of the currents in the INThe interval is measured from the time when the control enters the second state P2 (i.e., the second stage begins). If the control voltage V C (t) when it is detected that the valley voltage has not been reached (ie, VALLEY=0), the flag TIMER_BUCK is asserted, and a transition T23 occurs;

[0108] When the control voltage V C (t) reaches the valley voltage (e.g., VALLEY=1) and has a second time interval of a fixed length (specifically, Fig.13 The current I shown in MIN MIN_TOFF=0), transitioning from the third state P3 to the fourth state P4 (e.g., transition T34), the interval being measured from when control enters the third state P3 (i.e., the start of the third phase); and

[0109] If the second time interval expires, ie the flag MIN_TOFF=1, a transition is made from the fourth state P4 to the first state ( P1 ), for example a transition T41 .

[0110] In addition, the length of the first time interval can also be used as the input voltage V IN and output voltage V OUT The difference between the two functions decreases as Fig.12 As shown, the parameter R BU Proportional.

[0111] It should be emphasized that the reset switches of timers 70, 74 and timers 80, 84 are controlled by the corresponding control signals RST BU and RST MIN Control, RST BU and RST MIN The control module 100 itself may issue a signal to the timers 70, 80 and deassert, i.e., disconnect, during the corresponding phases P2 and P3, so that the timers 70 and 80 measure their corresponding timeouts. Therefore, the control module 100 may issue a set of control signals including the signal c(t) to the switches of the converter 10 as a whole, and these signals control the reset switches of the timers 70, 80, i.e., control the detection of the start of the corresponding interval from the start of the phases P2, P3.

[0112] As shown in the figure, due to the above conversion, the converter 10 is configured as follows: if the input voltage V IN Within the specified voltage range, it is close to the output voltage V OUT , it operates in buck-boost mode; if the input voltage V IN Lower than the output voltage V OUT Outside the range, it operates in step-up mode; and if the input voltage VIN Greater than the output voltage V OUT Outside the range, it operates in step-down mode; the transition between the three operation modes is adjusted by selecting the length of the detection parameter group and the value of the fixed length of the second time interval. IN Close to the output voltage V OUT The range in which it operates as a buck-boost depends on how the values ​​of the components and parameters of, for example, circuits 70 and 80 are selected, which settings determine when the mode changes.

[0113] Now, another embodiment having a startup method is described.

[0114] In a general DC-DC converter with ripple-hysteresis-current mode control (RHCMC), the instantaneous coil current is required in each stage of the DC-DC conversion in order to faithfully detect the peak and valley values ​​of the coil current. Typically, in each stage, the coil current information is obtained by monitoring the current flowing in the actual power switch enabled in the particular stage by means of a current sensing circuit. Then, the signal v is obtained by summing all the different contributions provided by the different current sensors in each stage. sense (t) (i.e., combining the coil current information during each phase).

[0115] Similar to Figure 1 Taking the NIBBDC-DC in FIG. 1 as an example, depending on its operation, a valley value of the coil current may occur when the first low-side switch LS1 and the second high-side switch HS2 are operated together and when the first high-side switch HS1 and the second high-side switch HS2 are operated together. The second high-side switch HS2 is the only power switch that is always operated during any coil discharge phase; therefore, sensing the current flowing in the second high-side switch HS2 always allows obtaining the instantaneous coil current, thereby obtaining the sensing voltage v sense (t) for valley current detection. This is the most convenient option to obtain the instantaneous coil current with only a single current sensor during coil discharge. This is very relevant considering that the current sensing circuit is a complex circuit that is also very demanding in terms of area and quiescent current.

[0116] Fig.14 Depicts a typical current sensor circuit indicated at 90 based on the replica MOS (or replica MOS) concept (also referred to as a "sense FET based current sensor"), which is applied to the high side power MOS of a boost converter, or in particular to a Figure 1The current sensor 90 utilizes an amplifier 91 and a replica MOS 92, which is a scaled version of a power MOS, such as HS2 (i.e., the replica MOS is M times smaller than the power MOS, i.e., its W / L ratio is M times smaller than the W / L ratio of the power MOS HS2). The amplifier 91 is coupled to a terminal of the switch HS2 coupled to the output terminal through its positive input terminal having a signal, i.e., an output voltage V is formed thereon. OUT The terminal OUT of the power MOS 92 is coupled to the negative input terminal thereof, while its negative input terminal is coupled to the same electrode of the replica MOS 92. The other electrode of the replica MOS 92 is coupled to the second inductor terminal LX2, such as the switch HS2. Through the negative feedback loop, the amplifier 91 keeps the drain-source voltage of the replica MOS 92 equal to the drain-source voltage of the power MOS HS2; therefore, since these MOSFET transistors operate at the same gate voltage, the sense current I flowing in the replica MOS 92 SENSE is the power MOSHS2 current (i.e., coil current I COIL ) is a scaled version of: I COIL =M·I SENSE The output of amplifier 91 controls the opening of MOS switch 93, which allows the sense current to be transmitted to a node with a sense voltage VSENSE, which in this example is located across a sense resistor Rsns having the other end coupled to ground. Amplifier 91 has one power supply terminal also coupled to an output node OUT, forming an output voltage V OUT , and the other power supply terminal is grounded. The sensing voltage VSENSE is specifically sent as an input to the buffer 95, and the buffer 95 outputs a voltage signal SENSE, which can correspond to Fig.11 (or Fig.10 ) in the same voltage signal SENSE.

[0117] The flag signals VALLEY, PEAK, BUCK_TIMER and MIN_OFF are sent to the logic module, such as Fig. 6A The logic control module 100 in Figure 5 The state diagram shown sets the converter 10 in phases P1, P2, P3, P4, i.e. operates its switches. Thus, in particular, the logic module can be implemented by a finite state machine, although other logic implementations including, for example, logic gates and / or flip-flops are also possible, or can be implemented by a correspondingly programmed microprocessor.

[0118] When the DC-DC starts, V OUT= 0 and needs to be charged to reach the desired regulation set point. The startup phase must be carefully managed to limit the inrush current and is usually achieved by slowly ramping up the set point reference (e.g. Fig.10 This phase is performed using the signal REF in the output capacitor to slowly charge the bulky output capacitor and reach the final set point (soft start). Unfortunately, at startup, the current sensor 90 does not work because V OUT = 0 (e.g., the amplifier does not have any power supply). In practice, this means that the sensed voltage v sense (t) is unavailable for a significant portion of the startup phase (i.e., until V OUT reaches the minimum value to ensure the correct operation of the current sensor circuit), and no information about the coil current I COIL In this context, any DC-DC converter utilizing a control scheme that requires valley coil current information is impaired and unable to perform startup, remaining stagnant.

[0119] Typically, converter performance must be guaranteed for all possible start-up conditions and variations, mainly due to: operating conditions and parameters (i.e., V IN , V OUT , L, C, parasitics, application scenarios, etc.); PVT changes; other reasons occurring after final testing, packaging, and assembly (i.e. aging, soldering, etc.).

[0120] To avoid the startup problem, another embodiment is proposed herein that temporarily utilizes a fixed frequency clock (i.e., a common timing signal) and initially operates the DC-DC converter 10 in asynchronous mode (i.e., without performing synchronous rectification). This is done until the output voltage V OUT high enough to ensure that the high-side current sensing circuit (connected to V OUT ), the high-side current sensing circuit is responsible for reliably providing coil current information during the coil discharge phase.

[0121] Fig.15 A state diagram schematically illustrating the start-up process of the NIBB converter 10 is shown. At the start (transition TS0), the converter 10 enters a first start-up phase or state ST1. A fixed frequency clock is represented by CLK. The rising edge of the clock CLK signal indicates the start of the coil charging phase, so here the first high-side switch HS1 is asserted, i.e. closed. This first start-up phase or state ST1 lasts until the peak coil current is detected (the current sensor on the first high-side switch HS1 is always available and reliable because it is connected to the input voltage V IN The event is signaled by the rising edge of the signal PEAK, which is generated by monitoring the sense signal SENSE and V C_PEAK comparator provides that the V C _PEAK corresponds to Figure 3A or Fig.11 The signal V C_P , the signal is shifted by a given voltage ΔV C The control voltage V provided by the error amplifier 62 C Add together to obtain, as reference Fig.10 discussed. Only the rising edge of the signal PEAK is relevant and carries information that allows the transition TS12 to the state ST2. The transition TS12 to the second state ST2 occurs at the falling edge of the clock CLK. Thus, the system moves from state ST1 to state ST2 if one of the following conditions occurs: a rising edge of the flag PEAK (i.e., PEAK becomes 1), or a falling edge of the clock CLK (i.e., the clock CLK becomes 0).

[0122] In the next phase ST2, the coil discharge is performed. Here, only the first low-side switch LS1 is asserted, i.e. turned on or closed, while the power switches HS2, LS2 in the second half-bridge are not asserted: the coil L is discharged by means of the diode conduction of the second high-side switch HS2. It is emphasized that asserting the first low-side switch LS1 is not strictly mandatory, because by means of the diode conduction of the switches LS1 and HS2, the coil current I COIL will still be discharged, but for better performance it is recommended to also assert the first low side switch LS1. The next switching cycle starts with the following clock rising edge (TS21 or TS23), which means that the coil discharge duration in phase ST2 is therefore limited by the clock.

[0123] This behavior continues until the output voltage V OUT The minimum value that allows the current sensor on switch HS2 to operate correctly is reached. Specifically, this event is signaled by a comparator circuit (not shown in the figure), the output of which is labeled COMP_1V7), which monitors the output voltage V relative to a given value (e.g., 1.7V in this example). OUT From this moment on, the DC-DC converter 10 enters state ST3 (transition T23), where it typically operates as a ripple-hysteresis-current mode control (RHCMC) converter with full coil current information available. Specifically, the NIBB converter 10 may be configured according to Figure 5 The ramp-up phase continues in normal mode and at the end of the setpoint ramp-up the clock can be turned off as it is no longer used.

[0124] Fig.16A timing diagram is shown which illustrates the NIBB DC-DC operation during the startup phase, showing the voltages on nodes LX1 and LX2, the coil current I COIL , sensing signal SENSE, peak control signal V C _P, fixed clock CLK, HS1 and LS1 status. Time t norm1 Indicates when the peak flag PEAK is asserted, i.e., the rising edge, thereby triggering the transition T12 from state 1 to state 2.

[0125] Fig.17 shows a timing diagram, which shows the voltage on LX1 and LX2, the coil current I COIL , comparator output COMP_1V7, fixed clock CLK, HS1 and LS1 states, HS2 and LS2 states, and V as a function of time OUT To illustrate that at time t norm2 The startup phase transition (TS23) between asynchronous mode and normal RHCMC operation.

[0126] Fig.16 and 17 The waveforms in V IN =5V and a clock frequency of 1.5MHz. The signal SENSE is provided by the current sensor on HS1 and can be used only to detect the coil peak current (i.e. it determines the HS1_ON duration). A blanking time (masking time tMSK) is typically used to allow proper settling of the current sensor output and obtain a reliable signal (not strictly mandatory).

[0127] It is important to note that the maximum coil charging phase can be limited using a clock signal CLK with an unbalanced duty cycle (e.g., 75% duty cycle clock → 75% maximum DC-DC duty cycle); to do this, Fig.15 The transition from ST1 to ST2 includes the falling edge of the clock CLK in the logical OR; for simplicity, the convention adopted here is to start the switching cycle at the rising edge of the clock CLK, but the switching cycle can also be obtained by inverting the rising edge of the clock; and if necessary, the DC-DC converter automatically operates in DCM mode and also skips some cycles.

[0128] So, in conclusion, Figure 15-17 A solution for handling the startup phase of a RHCMC converter is presented. The converter 10 performs startup in closed loop without losing regulation and remains within specification (eg, no inrush current) regardless of PVT variations, operating conditions, or external component variations (ie, the system automatically adapts).

[0129] This implementation does not require any additional voltage sources / rails nor any additional circuitry, but simply utilizes what is already available. Note that in power management ICs, the clock signal is often used for other different purposes, so the clock CLK can be obtained there. The same comparator used for steady-state protection purposes (e.g. undervoltage protection, short-circuit protection) can easily be utilized to monitor the output voltage V during the startup phase. OUT , thereby reusing (eg, multiplexing) circuits that are already on the chip.

[0130] It should be emphasized that reference Figure 15-17 The described solution can be applied to reference Figure 1-Figure 14 A NIBB converter is described, however it is applicable to any other DC-DC converter, boost, NIBB or other topology affected by similar problems in the start-up phase.

[0131] Therefore, the solution also relates to a method according to any of the preceding claims, wherein it comprises, for example, a start-up procedure of the NIBB converter 10, the start-up procedure comprising:

[0132] Providing a fixed frequency start clock CLK to the converter 10;

[0133] At the beginning, transition TS0 places the converter (eg, 10) in a first start-up state ST1, in which only the first high-side switch HS1 is asserted, which lasts until the coil current I COIL The peak value is reached, which is signaled by asserting a corresponding peak signal (e.g., flag PEAK=1), and then a transition is performed, e.g., from TS12 to a second state ST2, wherein the coil discharge is performed at a subsequent rising edge of the start clock CLK, in particular by asserting only the first low-side switch LS1, and then if the output voltage V OUT If the given minimum value has not been reached, the first state TS21 is entered, or the third state of executing the ripple-hysteresis current mode control is entered.

[0134] As described above, the startup process may be applied to NIBB converter 10 or other converters.

[0135] Therefore, from the above description, the advantages of the solution are clear.

[0136] The solution described here allows the NIBB converter to operate at all input voltages V IN and output voltage V OUT High efficiency in all conditions, especially in the critical area V IN < <V OUT This solution keeps the coil current low under all conditions, thus satisfying V IN < <V OUTThe optimal limit in the critical area.

[0137] Basically, this solution identifies the converter operating in non-inverting buck-boost mode without limiting the output current capability (when V IN <<V OUT (also true).

[0138] The converter allows minimizing the silicon area due to smaller power MOSFETs. At the same time, the DC-DC converter according to the solution described herein facilitates the development of small external passive components with relaxed electrical specifications, which is critical in consumer applications.

[0139] The proposed solution can always operate in forced CCM without skipping to minimize output voltage fluctuations. Moreover, in a more generalized implementation and to optimize light load operation, discontinuous conduction mode (DCM) can be easily implemented and managed: for example, a standard zero current detector comparator can be employed to avoid the coil current to reverse and become negative (in this case, the DC-DC converter automatically performs in pulse frequency mode).

[0140] Furthermore, the solution described here allows to obtain a high performance, free running non-inverting buck-boost DC-DC converter with excellent transient response and high bandwidth allowing to suppress fast line transients, which is critical, for example, in AMOLED applications.

[0141] The solution proposed in the embodiments also properly manages the startup phase so that it does not affect the normal DC-DC operation and the seamless transition is smooth. In fact, the converter design and the control loop are not affected by the solution described here, as the normal operation remains unchanged. In particular, the need to monitor the valley coil current during the initial startup phase is bypassed and no additional valley current sensor is required, nor is there a need to change its design / architecture.

[0142] The solution regarding the startup process can benefit any generic DC-DC topology and is not limited to ripple-hysteretic-current mode control (RHCMC) converters, but is applicable to any control scheme that relies on current sensor information that is not available during startup. Moreover, the proposed algorithm can be directly embedded inside the DC-DC controller / digital core (i.e., written, synthesized and verified HDL code) with minimal area contribution. The impact on the efficiency / quiescent consumption of the entire DC-DC is zero, since the clock is then gated and the steady-state operation is not affected.

[0143] The proposed solution remains fully integrated on chip and does not require any additional pads / balls nor additional off-chip components. The described solution does not require any additional process masks or specific devices and enhances the converter performance without sacrificing other specifications or requiring any fine tuning.

[0144] The details and embodiments may vary even significantly with respect to what is described merely by way of example, without violating the essential principles and without departing from the scope of protection.

[0145] The claims are an integral part of the technical disclosure of the embodiments provided herein.

[0146] The scope of protection is defined by the appended claims.

Claims

1. A method for controlling a non-inverting buck-boost DC-DC converter, the non-inverting buck-boost DC-DC converter comprising: A first input half-bridge coupled to one end of an induction coil and a second output half-bridge coupled to the other end of the induction coil, the first input half-bridge comprising a first high-side switch coupled between an input node and the end of the induction coil and a first low-side switch coupled between the end of the induction coil and ground, the second input half-bridge comprising a second high-side switch coupled between an output node and the other end of the induction coil and a second low-side switch coupled between the other end of the induction coil and ground, the method comprising: providing a control voltage based on an error between a feedback signal from the output of the non-inverting buck-boost DC-DC converter and a reference signal; performing a first comparison of the control voltage plus an offset voltage with a reference signal, the reference signal being proportional to the current flowing in the coil, the first comparison detecting the control voltage reaching a peak voltage; performing a second comparison of the control voltage minus the offset voltage with a reference signal, the reference signal being proportional to the current flowing in the coil, the second comparison detecting the control voltage reaching a valley voltage; generating a control signal applied to the switch of the non-inverting buck-boost DC-DC converter according to a result of the first comparison and a result of the second comparison to drive the switch to open and close; Controlling operation of the non-inverting buck-boost DC-DC converter using ripple-hysteresis-current-mode-control in a plurality of operating states, the plurality of operating states comprising: a first state, in which the control signal causes the first high-side switch and the second low-side switch to be closed; a second state, in which the control signal causes the first high-side switch and the second high-side switch to be closed; a third state in which the control signal causes the first low-side switch and the second high-side switch to close; and a fourth state, in which the control signal causes the first low-side switch and the second low-side switch to be closed; The controls include: When the control voltage is detected to reach the peak voltage, switching from the first state to the second state; When the control voltage is detected to reach the valley voltage, switching from the second state to the first state; transitioning from the second state to the third state upon detecting expiration of a first time interval measured from entering the second state, the first time interval having a length that varies as a function of a set of detection parameters and that decreases as the input voltage increases, the control voltage being detected as not having reached the valley voltage; transitioning from the third state to the fourth state when the control voltage is detected to have reached the valley voltage and a second time interval having a fixed length measured from entering the third state has not expired; transitioning from the third state to the first state when the second time interval expires and the control voltage is detected to have reached the valley voltage; and The fourth state is transitioned to the first state when the second time interval expires. 2 . The method of claim 1 , wherein the length of the first time interval further decreases as a function of a difference between the input voltage and the output voltage.

3. The method according to claim 1, further comprising: operating the non-inverting buck-boost DC-DC converter in a buck-boost mode when the input voltage is within a determined voltage range of the output voltage; When the input voltage is lower than the output voltage outside the determined voltage range, operating the non-inverting buck-boost DC-DC converter in a step-up mode; as well as When the input voltage is greater than the output voltage and is outside the range, the non-inverting buck-boost DC-DC converter is operated in a step-down mode.

4. The method of claim 3, further comprising regulating transitions between the buck-boost mode, the step-boost mode, and the step-down mode by selecting values ​​of the set of detection parameters and the fixed length of the second time interval.

5. The method according to claim 3, wherein the step-up voltage mode comprises: In a switching cycle of the control signal, when the control voltage reaches the peak voltage, the control signal switches from the first state to the second state; and when the control voltage reaches the valley voltage, the control signal switches from the second state to the first state.

6. The method according to claim 3, wherein when the control voltage reaches the peak voltage, the buck-boost mode comprises, in a switching period in which the control signal switches from the first state to the second state: transitioning from the second state to the third state when the first time interval expires and the control voltage is detected as not having reached the valley voltage; transitioning from the third state to the fourth state when the control voltage is detected to have reached the valley voltage and the second time interval has not expired; as well as If the second time interval expires, a transition is made from the fourth state to the first state.

7. The method of claim 3, wherein the step-down mode comprises, when the control voltage reaches the peak voltage, in a switching cycle of the control signal transitioning from the first state to the second state: transitioning from the second state to the third state when a first time interval expires and the control voltage is detected as not having reached the valley voltage; and If the second time interval expires and the valley voltage is reached, a transition is made from the third state to the first state.

8. The method according to claim 1, further comprising executing a startup procedure of the non-inverting buck-boost DC-DC converter, the startup procedure comprising: Providing a fixed frequency start-up clock to the non-inverting buck-boost DC-DC converter; causing the converter to enter a first startup state in which only the first high-side switch is closed, the first startup state lasting until the coil current reaches a peak value; A transition to a second start state is then performed, during which the coil is discharged; as well as Then: a) if the output voltage does not reach a given minimum value, switching to the first start state at a subsequent start clock rising edge, or b) switching to a third start state in which the ripple-hysteresis-current mode control is performed.

9. The method of claim 1, wherein the operation control comprises sending a corresponding signal for measuring expiration of the first time interval starting from entering the second state and expiration of the second time interval measured from entering the third state. 10 . A control circuit for a non-inverting buck-boost DC-DC converter, configured to perform the ripple-hysteresis-current-mode-control according to claim 1 .

11. The control circuit according to claim 10, wherein the control circuit comprises: a circuit configured to compare the control voltage with a sense voltage to detect reaching a peak value and asserting a corresponding peak flag, and to detect reaching a valley value and asserting a valley flag; a first timing circuit configured to detect expiration of a determined length of time proportional to a difference between the input voltage and the output voltage and assert a corresponding buck timer flag; as well as A second timing circuit is configured to detect expiration of the second time interval of asserting the corresponding minimum timer flag.

12. The control circuit of claim 11 , wherein the circuit configured to compare the control voltage comprises: a comparator that compares the control voltage with a shift sensing voltage obtained by applying a voltage proportional to a current flowing in the coil to a shift resistor coupled to an input of the comparator; a circuit configured to inject a fixed current into a node of the shift resistor, a rising current proportional to a difference between the output voltage and the input voltage, and a falling current proportional to an inverse of the difference between the output voltage and the input voltage; Wherein the sense voltage is applied to the positive input of the comparator to generate the peak flag, and the sense voltage is applied to the negative input of the comparator to generate the valley flag.

13. The control circuit of claim 11 , wherein the control circuit comprises a timer circuit configured to detect the first time interval, the timer circuit comprising: a capacitor charged by one of: a) a current proportional to the input voltage with a first proportionality factor, or b) a current proportional to a difference between the input voltage and the output voltage with a second proportionality factor; as well as A comparator is configured to compare the voltage drop on the capacitor with a reference voltage drop time voltage to obtain the timer voltage drop flag value.

14. The control circuit of claim 13, wherein the set of detection parameters comprises: The value of the capacitor, the reference step-down time voltage, the first proportionality factor, and the second proportionality factor.

15. The control circuit of claim 14, configured to send the corresponding signal initiating the measurement to a switch enabling the charging of the capacitor.

16. The control circuit of claim 11, wherein the control circuit comprises a timer circuit configured to detect the second time interval, the timer circuit comprising: A capacitor charged by a given fixed current; as well as A comparator is configured to compare the voltage drop on the capacitor with a minimum time reference voltage to obtain the minimum timer flag value.

17. The control circuit of claim 16, configured to send the corresponding signal initiating the measurement to a switch enabling the charging of the capacitor.

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