Self-adaptive continuous time linear equalizer and control method

Abstract

The invention provides a self-adaptive continuous time linear equalizer and a control method, and the self-adaptive continuous time linear equalizer comprises a signal adjustment module which is provided with an adjustable resistor and an adjustable capacitor; the signal conditioning module is configured to: receive a data signal; performing high-frequency gain processing on the data signal according to the gain coefficient; the eye pattern calculation module is configured to obtain eye height data and eye width data according to the data signal; the adaptive module is configured to obtain a balance coefficient according to the eye height data and the eye width data; the equalization coefficient is a resistance adjusting value of the adjustable resistor and a capacitance adjusting value of the adjustable capacitor; controlling the signal adjusting module to operate according to the equalization coefficient; and when the signal adjusting module operates according to the equalization coefficient, the data signal achieves the target equalization effect, so that the problems that the signal equalization processing process of the existing linear equalizer is relatively long, and the quality of the processed signal is not at the maximum value are solved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to an adaptive continuous-time linear equalizer and a control method thereof. Background Art

[0002] With the continuous evolution of communication technology, the interactive demand for massive data is increasing day by day, which increases the demand for high bandwidth and high-speed data transmission. Serializer or deserializer circuits play a vital role in data transmission. However, during the data transmission process, channel non-ideal factors such as loss, inter-symbol crosstalk and reflection can cause the data at the sender to be distorted when it reaches the receiver.

[0003] In order to improve the transmission quality of the detection data signal, the serializer or deserializer circuit receiving end usually uses a continuous time linear equalizer to compensate for the high frequency components of the signal. The continuous time linear equalizer has the advantages of simple structure and low power consumption, and can effectively compensate for the high frequency components of the signal.

[0004] However, the current continuous-time linear equalizer cannot perform targeted high-frequency gain compensation on the detection data signal according to the detection data, resulting in a long signal equalization process of the continuous-time linear equalizer and the quality of the processed signal is not at the maximum value. Summary of the invention

[0005] The present application provides an adaptive continuous-time linear equalizer and a control method to solve the technical problems that the signal equalization processing process of the existing linear equalizer is long and the quality of the processed signal is not at a maximum value.

[0006] The first aspect of the present application provides an adaptive continuous-time linear equalizer, comprising:

[0007] A signal conditioning module, wherein the signal conditioning module is configured with an adjustable resistor and an adjustable capacitor; the signal conditioning module is configured as follows:

[0008] receiving the data signal;

[0009] According to the gain coefficient, high-frequency gain processing is performed on the data signal; the gain coefficient is the amplification ratio of the data signal by the signal adjustment module;

[0010] An eye diagram calculation module, wherein the eye diagram calculation module is configured to:

[0011] Obtaining eye height data and eye width data according to the data signal;

[0012] An adaptive module, wherein the adaptive module is configured to:

[0013] According to the eye height data and the eye width data, an equalization coefficient is obtained; the equalization coefficient is a resistance adjustment value of the adjustable resistor and a capacitance adjustment value of the adjustable capacitor;

[0014] Adjusting the gain coefficient to the equalization coefficient, and controlling the signal adjustment module to operate according to the equalization coefficient;

[0015] When the signal adjustment module operates according to the equalization coefficient, the data signal achieves a target equalization effect.

[0016] In some embodiments, the eye diagram calculation module includes:

[0017] A phase interpolator, the phase interpolator being configured to:

[0018] Obtaining eye width data according to the data signal;

[0019] A digital-to-analog converter, the digital-to-analog converter being configured to:

[0020] Eye height data is obtained according to the data signal.

[0021] In some embodiments, the eye diagram to be tested includes: an eye detection area and an eye non-detection area;

[0022] The eye diagram calculation module also includes:

[0023] A judging unit, wherein the judging unit is configured to:

[0024] Acquiring an image scanning area of ​​the phase interpolator or the digital-to-analog converter;

[0025] If the image scanning area is an eye detection area, generating a first control signal;

[0026] If the image scanning area is an eye non-detection area, generating a second control signal;

[0027] A control unit, the control unit being configured to:

[0028] According to the first control signal, controlling the phase interpolator or the digital-to-analog converter to scan the eye diagram to be measured with a first preset step size;

[0029] According to the second control signal, the phase interpolator or the digital-to-analog converter is controlled to scan the eye diagram to be measured with a second preset step length; the second preset step length is greater than the first preset step length.

[0030] In some embodiments, the adaptive module is configured with a capacitance adjustment unit, and the capacitance adjustment unit is configured to perform a capacitance adjustment operation; the capacitance adjustment operation is configured to:

[0031] The capacitance value of the adjustable capacitor is reduced according to a preset value to obtain a capacitance adjustment value;

[0032] Acquiring eye height data and eye width data under the capacitance adjustment value;

[0033] Calculating a real-time value of the sum of the eye height data and the eye width data;

[0034] Determine whether the total real-time value is greater than the total reference value, and if not, obtain a target capacitance value based on the capacitance adjustment value;

[0035] If so, the capacitance adjustment operation is repeatedly performed until the target capacitance value is obtained.

[0036] In some embodiments, the adaptive module is configured with a resistance adjustment unit, and the resistance adjustment unit is configured to perform a resistance adjustment operation: the resistance adjustment operation is configured as follows:

[0037] Increasing the resistance value of the adjustable resistor according to a preset value to obtain a resistance adjustment value;

[0038] Obtaining eye height data and eye width data under the resistance adjustment value;

[0039] Calculating a real-time value of the sum of the eye height data and the eye width data;

[0040] Determine whether the total real-time value is greater than the total reference value, and if not, obtain a target resistance value based on the resistance adjustment value;

[0041] If yes, the resistance adjustment operation is repeatedly performed until the target resistance value is obtained;

[0042] The adaptive module is further configured as:

[0043] Based on the target capacitance value and the target resistance value, a balancing coefficient is obtained.

[0044] In some embodiments, the sum reference value is determined by the following steps:

[0045] Acquiring eye height data and eye width data under a set environment; the set environment is configured such that the adjustable resistance is a minimum value and the adjustable capacitance is a maximum value;

[0046] A total reference value of the eye height data and the eye width data is calculated.

[0047] In some embodiments, the signal conditioning module is configured with a TAS circuit;

[0048] The adjustable resistor and the adjustable capacitor are configured in the TAS circuit.

[0049] In some embodiments, the TAS circuit is configured with a high-pass circuit and a low-pass circuit;

[0050] The low-pass circuit is an RC low-pass filter.

[0051] In some embodiments, the signal conditioning module is further configured with a TIS circuit, the TIS circuit being electrically connected to the TAS circuit;

[0052] The TIS circuit is configured with a first inverter and a second inverter, and the first inverter and the second inverter are respectively connected to the TAS circuit.

[0053] A second aspect of the present application provides a control method for an adaptive continuous time linear equalizer, which is applied to an adaptive continuous time linear equalizer as described in any one of the first aspects above, comprising:

[0054] receiving a data signal;

[0055] According to the gain coefficient, high-frequency gain processing is performed on the data signal; the gain coefficient is the amplification ratio of the data signal;

[0056] Obtaining eye height data and eye width data according to the data signal;

[0057] According to the eye height data and the eye width data, an equalization coefficient is obtained; the equalization coefficient is a resistance adjustment value of the adjustable resistor and a capacitance adjustment value of the adjustable capacitor;

[0058] The gain coefficient is adjusted to the equalization coefficient, and the signal adjustment module is controlled to operate according to the equalization coefficient; the signal adjustment module is configured with the adjustable resistor and the adjustable capacitor;

[0059] When the signal adjustment module operates according to the equalization coefficient, the data signal achieves a target equalization effect.

[0060] The present application provides an adaptive continuous time linear equalizer and a control method, the adaptive continuous time linear equalizer comprising: a signal adjustment module, the signal adjustment module is configured with an adjustable resistor and an adjustable capacitor; the signal adjustment module is configured to: receive the data signal; perform high frequency gain processing on the data signal according to a gain coefficient; the gain coefficient is the amplification ratio of the data signal by the signal adjustment module; an eye diagram calculation module, the eye diagram calculation module is configured to: obtain eye height data and eye width data according to the data signal; an adaptive module, the adaptive module is configured to: obtain an equalization coefficient according to the eye height data and the eye width data; the equalization coefficient is the resistance adjustment value of the adjustable resistor and the capacitance adjustment value of the adjustable capacitor; the gain coefficient is adjusted to the equalization coefficient, and the signal adjustment module is controlled to operate according to the equalization coefficient; wherein, when the signal adjustment module operates according to the equalization coefficient, the data signal achieves a target equalization effect, so that the linear equalizer can reduce the signal equalization processing time, and the quality of the processed signal is at a maximum value. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0062] Figure 1 Schematic diagram of the structure of the adaptive continuous time linear equalizer in this application;

[0063] Figure 2 This is a schematic diagram of the structure of the eye diagram calculation module in this application;

[0064] Figure 3 is a flow chart of the adaptive logic in this application;

[0065] Figure 4 This is a schematic diagram of the structure of the signal conditioning module in this application;

[0066] Figure 5 A normalized frequency response curve of a continuous time linear equalizer when the resistance value of the adjustment resistor is changed in the present application;

[0067] Figure 6 A normalized frequency response curve of a continuous time linear equalizer when the capacitance value of the adjustment capacitor is changed in the present application;

[0068] Figure 7 A schematic diagram of eye height data sampling in this application;

[0069] Figure 8 A schematic diagram of eye width data sampling in this application;

[0070] Fig. 9 It is a structural diagram of an adaptive continuous-time linear equalizer based on a spectrum equalization method in this application;

[0071] Fig.10 It is a schematic diagram of the structure of an adaptive continuous-time linear equalizer based on asynchronous sampling histogram in this application;

[0072] Fig.11 It is a structural schematic diagram of an adaptive continuous-time linear equalizer based on a random sigma tracking eye diagram detector in this application;

[0073] Fig.12 It is a structural diagram of a conventional current mode logic type continuous time linear equalizer in this application;

[0074] Fig.13 This is a schematic diagram of the structure of the TAS-TIS with active inductance as load in this application;

[0075] Fig.14 It is a schematic diagram of the structure of the programmable dual-channel continuous-time linear equalizer in this application;

[0076] Fig.15 This is a schematic diagram of the structure of the continuous time linear equalizer of the TAS-TIS structure in this application.

[0077] Description of reference numerals:

[0078] 1- signal conditioning module; 2- eye diagram calculation module; 21- phase interpolator; 22- digital-to-analog converter; 23- judgment unit; 24- control unit; 3- adaptive module. DETAILED DESCRIPTION

[0079] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0080] Since in some technologies, the process of signal equalization processing by a linear equalizer is long, and the quality of the processed signal is not at the maximum value, in order to solve this technical problem, the present application provides an adaptive continuous-time linear equalizer and a control method, and the adaptive continuous-time linear equalizer and the control method are described below:

[0081] With the continuous evolution of communication technology, the interactive demand for massive data is increasing day by day, and the demand for high bandwidth and high-speed data transmission has also increased. SerDes (Serializer / De-serializer) circuits play a vital role in chip-to-chip, board-to-board, and system-to-system interconnection transmission. However, during the data transmission process, channel non-ideal factors such as loss, inter-symbol crosstalk, and reflection can cause the data at the transmitter to be distorted when it reaches the receiver. In order to improve the quality of data transmission, the SerDes receiver usually uses a continuous time linear equalizer circuit. The continuous time linear equalizer circuit has the advantages of simple structure and low power consumption, and can effectively compensate for the high-frequency components of the signal.

[0082] However, for high-speed SerDes circuits, the current continuous time linear equalizer still has the following problems:

[0083] like Fig. 9 As shown, it is an adaptive continuous-time linear equalizer based on spectrum equalization method.

[0084] Since manually configuring the equalization parameters of the continuous time linear equalizer is cumbersome and inflexible, adaptive continuous time linear equalizer is used to achieve parameter adaptive equalization. In the spectrum equalization method, adaptive equalization is achieved by comparing the high-frequency and low-frequency components of the signal power and generating a feedback signal until the power spectrum is balanced. However, the accuracy of this solution is easily affected by process variations, and the capacitors in the filter and feedback loop occupy a large silicon area.

[0085] like Fig.10 As shown, an adaptive continuous-time linear equalizer based on asynchronous sampling histogram is shown.

[0086] In the adaptive equalization method based on asynchronous sampling histogram, the optimal value is obtained by traversing histograms of different equalization degrees. However, there are disadvantages such as long equalization process and slow algorithm convergence.

[0087] like Fig.11 As shown, an adaptive continuous-time linear equalizer based on random sigma tracking eye diagram detector is shown.

[0088] In the adaptive equalization method based on random sigma tracking eye diagram detector, the enhancement gain of the continuous-time linear equalizer is scanned to find the optimal enhancement gain of the continuous-time linear equalizer that maximizes the eye opening area. There is also a trade-off between adaptation time and accuracy.

[0089] like Fig.12 As shown, it is a traditional CML (Current Mode Logic) type continuous time linear equalizer.

[0090] The traditional CML type continuous time linear equalizer constructs a feedback loop by introducing resistors and capacitors at the source of the input tube. The coupling of resistors and capacitors forms a degenerate structure, which provides a high-pass path for the input signal to compensate for the high-frequency loss of the channel. The transfer function shows that the continuous time linear equalizer has one zero point and two poles, limited single-stage high-frequency compensation capability, a small adjustment range, and bandwidth is limited by the load capacitance. With the continuous increase in data transmission rate, it is difficult to meet the expected requirements.

[0091] like Fig.13 As shown, it is a TAS-TIS structure with active inductance as load.

[0092] In the TAS-TIS structure with active inductors as loads, the continuous time linear equalizer uses the TAS-TIS structure and active inductors to expand the bandwidth. However, the disadvantage is that for the adaptive system, the mid- and low-frequency gain is not adjustable and the adjustment range is small.

[0093] like Fig.14 As shown, it is a programmable dual-channel continuous-time linear equalizer.

[0094] In the programmable two-way continuous time linear equalizer, the mid- and low-frequency gains are adjustable and the adjustment range is large. However, the disadvantage is that the adaptive continuous time linear equalizer requires an additional comparator load compared to the manual control continuous time linear equalizer. For the adaptive system, compared with the TAS-TIS structure, the latter stage load limits the bandwidth.

[0095] like Fig.15 As shown, it is a continuous time linear equalizer with TAS-TIS structure.

[0096] In the TAS-TIS CTLE structure, the mid- and low-frequency gain is adjustable with a wide adjustment range. The continuous time linear equalizer topology of the TAS-TIS structure has a low output impedance and expands the bandwidth. However, the disadvantage is that the high-pass circuit and the low-pass circuit are composed of two differential pairs respectively. Although the high-frequency gain is improved, it also leads to increased power consumption. In addition, the multi-stage superposition and the zero-pole environment are complex, which is not as convenient to adjust as a single stage.

[0097] Depend on Figure 1 It can be seen that the first aspect of the present application provides an adaptive continuous time linear equalizer, which is applied to an eye diagram detector, and the eye diagram detector is used to obtain a data signal; comprising:

[0098] A signal conditioning module 1, wherein the signal conditioning module 1 is configured with an adjustable resistor and an adjustable capacitor; the signal conditioning module 1 is configured to: receive the data signal; the data signal is input through a channel, and the adaptive continuous time linear equalizer is used to convert an unbalanced signal into a balanced signal, so the unbalanced signal input into the adaptive continuous time linear equalizer will be input into the signal conditioning module 1 and converted into a balanced signal through the adaptive continuous time linear equalizer.

[0099] According to the gain coefficient, the data signal is subjected to high-frequency gain processing; the gain coefficient is the amplification ratio of the data signal by the signal adjustment module 1; the eye diagram calculation module 2, the eye diagram calculation module 2 is configured to: obtain eye height data and eye width data according to the data signal; the adaptive module 3, the adaptive module 3 is configured to: obtain the equalization coefficient according to the eye height data and the eye width data; the equalization coefficient is the resistance adjustment value of the adjustable resistor and the capacitance adjustment value of the adjustable capacitor; the gain coefficient is adjusted to the equalization coefficient, and the signal adjustment module 1 is controlled to operate according to the equalization coefficient; wherein, when the signal adjustment module 1 operates according to the equalization coefficient, the data signal achieves the target equalization effect. wherein, when the data signal achieves the target equalization effect, the frequency response curve of the data signal tends to be flat within the Nyquist frequency. wherein, the Nyquist frequency is the minimum sampling frequency that needs to be defined to prevent aliasing of the data signal.

[0100] In view of the problems of the current adaptive continuous time linear equalizer, such as large area, long equalization process, slow algorithm convergence, etc., the present application provides an adaptive continuous time linear equalizer, the structure of which is as follows: Figure 1 As shown. The main circuit includes a signal conditioning module 1, an eye diagram calculation module 2 and an adaptive module 3. The eye diagram calculation module 2 detects the eye height and eye width of the signal output by the signal conditioning module 1, and then the adaptive module 3 switches the state of the corresponding switch in the signal conditioning module 1 according to the sum of the eye height and the eye width, so as to change the value of the resistor and capacitor in the circuit of the signal conditioning module 1, thereby changing the high-frequency gain of the circuit of the signal conditioning module 1, and realizing the balanced configuration of different channels to improve the system bit error rate. The present application is implemented by a digital algorithm, and the balance between time and accuracy is broken by the application of non-uniform scanning of the eye diagram calculation module 2.

[0101] like Figure 2 As shown, it is a structural schematic diagram of the eye diagram calculation module 2.

[0102] In this embodiment, the eye diagram calculation module 2 includes: a phase interpolator 21, and the phase interpolator 21 is configured to: obtain eye width data according to the eye diagram to be measured; the phase interpolator 21 is used to obtain the eye width data of the eye diagram to be measured according to the data signal. The specific detection process is as follows Figure 8 shown.

[0103] The digital-to-analog converter 22 is configured to obtain eye height data according to the data signal. The digital-to-analog converter 22 is used to obtain the eye height data of the eye diagram to be tested according to the data signal. The specific detection process is as follows: Figure 7 shown.

[0104] In this embodiment, the eye diagram to be tested includes: an eye detection area and an eye non-detection area; Figure 7 and Figure 8 As shown, the eye detection area is the black part in the figure, and the eye non-detection area is the white part in the figure; the eye detection area is the eye diagram part used to detect eye height data and eye width data, and the eye non-detection area is the part that is unnecessary for the eye diagram part to detect eye height data and eye width data.

[0105] The eye diagram calculation module 2 also includes: a judgment unit 23, the judgment unit 23 is configured to: obtain the image scanning area of ​​the phase interpolator 21 or the digital-to-analog converter 22; if the image scanning area is an eye detection area, generate a first control signal; if the image scanning area is an eye non-detection area, generate a second control signal; a control unit 24, the control unit 24 is configured to: according to the first control signal, control the phase interpolator 21 or the digital-to-analog converter 22 to scan the eye diagram to be tested with a first preset step size; according to the second control signal, control the phase interpolator 21 or the digital-to-analog converter 22 to scan the eye diagram to be tested with a second preset step size; the second preset step size is greater than the first preset step size. Figure 7 and Figure 8 The figure shows a schematic diagram of a first preset step length and a second preset step length.

[0106] It can be understood that when acquiring eye diagram data, the eye detection area needs to be carefully detected and scanned in detail, while the eye non-detection area does not need to be scanned as carefully as the eye detection area. Instead, the scanning process should be completed as quickly as possible to improve the scanning efficiency of the eye image; therefore, for the eye detection area, the eye diagram to be tested is scanned with a first preset step size, and for the eye non-detection area, the eye diagram to be tested is scanned with a second preset step size, and the second preset step size is much larger than the first preset step size.

[0107] Exemplarily, the eye diagram calculation module 2 with more information and higher precision, namely the EOM (eye-opening monitor), is slow and has a large hardware overhead, which hinders the rapid convergence of the adaptive equalizer or clock recovery. In order to break the trade-off between eye diagram accuracy and measurement time, the eye diagram calculation module 2 provided in the present application uses a non-uniform scanning algorithm to increase the scanning speed by adopting a larger step size in the non-detection area of ​​the eye. First, the eye width is scanned with a PI (phase interpolator). When scanning the transition area (i.e., the first control signal PDF = 1) (PDF, probability density function), the scanning step size is minimized to 1 to maintain accuracy. In the data center area where no signal conversion occurs (i.e., the second control signal PDF = 0), a larger step size is used to speed up the scanning process. After determining the eye width, a DAC (Digital-to-Analog Converter) is used at the horizontal center of the eye to scan in the eyelid area (i.e., PDF = 1) with a step size of 1, and a larger step size is applied in the center of the eye diagram (i.e., PDF = 0) to quickly obtain the eye height. The eye diagram calculation module 2 controls the scanning step of the DAC and PI and calculates the eye width data and the eye height data.

[0108] like Figure 3 The figure shows the adaptive logic flow chart of the adaptive module 3.

[0109] In this embodiment, the adaptive module 3 is configured with a capacitance adjustment unit, and the capacitance adjustment unit is configured to perform a capacitance adjustment operation; the capacitance adjustment operation is configured as follows: reducing the capacitance value C_CODE of the adjustable capacitor according to a preset value to obtain a capacitance adjustment value C_CODE-1; obtaining the eye height data EH and the eye width data EW under the capacitance adjustment value; calculating the total real-time value EWH_TEMP=EH+EW of the eye height data and the eye width data; judging whether the total real-time value is greater than the total reference value EWH, if not, obtaining the target capacitance value based on the capacitance adjustment value; if so, repeatedly performing the capacitance adjustment operation until the target capacitance value is obtained.

[0110] In this embodiment, the adaptive module 3 is configured with a resistance adjustment unit, and the resistance adjustment unit is configured to perform a resistance adjustment operation: the resistance adjustment operation is configured to: increase the resistance value R_CODE of the adjustable resistor according to a preset value to obtain a resistance adjustment value R_CODE+1; obtain the eye height data EH and the eye width data EW under the resistance adjustment value; calculate the sum real-time value EWH_TEMP of the eye height data and the eye width data = EH+EW; determine whether the sum real-time value is greater than the sum reference value EWH, if not, obtain the target resistance value based on the resistance adjustment value; if yes, repeat the resistance adjustment operation until the target resistance value is obtained; the adaptive module 3 is also configured to: obtain an equalization coefficient based on the target capacitance value and the target resistance value. The equalization coefficient is the target capacitance value and the target resistance value. By adjusting the resistance value and capacitance value of the adjustable resistor and the adjustable capacitor in the signal adjustment module 1 to the target resistance value and the target capacitance value, the data signal can be equalized.

[0111] In this embodiment, the sum reference value is determined by the following steps: obtaining eye height data and eye width data under a set environment; the set environment is configured so that the adjustable resistor is at a minimum value and the adjustable capacitor is at a maximum value; calculating the sum reference value EWH=EH+EW of the eye height data and the eye width data. The eye height data and the eye width data are the eye height data and the eye width data collected by the eye diagram calculation module 2 when the adjustable resistor is at a minimum value and the adjustable capacitor is at a maximum value. The adaptive module 3 uses an adder to obtain the sum of the eye height and the eye width, and stores it in a register. The maximum value is obtained by comparing the eye opening degrees of the adaptive continuous time linear equalizers with different configurations to determine the optimal equalization coefficient. In order to reduce the time for determining the equalization coefficient, under high loss, the equalization coefficient is adjusted from the configuration with high high-frequency gain, that is, the adaptive module 3 is adjusted from the configuration with the adjustable resistor at a minimum value and the adjustable capacitor at a maximum value.

[0112] Exemplarily, when in use, the signal conditioning module 1 receives the differential input signal through the differential input terminal, and the adaptive module 3 can complete the configuration of the corresponding equalization coefficient, so as to obtain the optimal high-frequency gain of the transmission signal, so that the frequency response curve of the transmission signal tends to be flat within the Nyquist frequency, so as to serve as the input of DFE or DEMUX.

[0113] like Figure 4 As shown, it is a circuit diagram of the signal conditioning module 1 in this application.

[0114] In this embodiment, the signal conditioning module 1 is configured with a TAS circuit; the adjustable resistor and the adjustable capacitor are configured in the TAS circuit. The TAS circuit is configured with a high-pass circuit and a low-pass circuit; the low-pass circuit is an RC low-pass filter. The signal conditioning module 1 is also configured with a TIS circuit, which is electrically connected to the TAS circuit; the TIS circuit is configured with a first inverter and a second inverter, and the first inverter and the second inverter are respectively connected to the TAS circuit.

[0115] Exemplarily, compared with the current circuit structure of the signal conditioning module 1, the signal conditioning module 1 in the present application uses a TAS-TIS structure with a lower output impedance, and the structure can expand the bandwidth to allow data at a higher rate to pass through. At the same time, due to the use of a two-way structure in TAS, the input signal can be more finely balanced at low and high frequencies, and the adjustment range is large. Moreover, the power consumption of the present application is lower than that of the current circuit structure of the signal conditioning module 1 at the same bandwidth, with fewer adjustment variables, faster convergence speed, and convenient adaptive adjustment. In addition, the additional load added by the eye diagram calculation module 2 to the signal conditioning module 1, namely a comparator, will not cause serious bandwidth impact on the signal conditioning module 1 of the TAS-TIS structure.

[0116] This application requires the use of a high-low frequency adjustable, and high-bandwidth adaptive continuous time linear equalizer under the additional load brought by the eye diagram calculation module 2. Therefore, a signal conditioning module 1 with a high-low frequency adjustable TAS-TIS structure is adopted. The architecture consists of two parts, a TAS circuit and a TIS circuit, such as Figure 4 As shown. In the TAS circuit, the idea of ​​subtracting the high-pass branch from the low-pass branch to increase the high-frequency gain is adopted. A dual-path structure is used. In addition to the current single zero point and dual-pole structure for high-frequency equalization, an additional RC low-pass filter is added to subtract from the main path to generate a new pair of zero poles to provide low-frequency equalization. Both equalization capabilities can be configured. Finally, the two signals are superimposed in the form of current as the input signal of the next-level TIS circuit. The size of the resistor and capacitor can be adjusted by connecting multiple transistors in parallel and controlling the gate level. The TIS circuit adopts a transimpedance amplifier structure based on an inverter. Unlike the current amplifier structure, the two inverters provided in the TIS circuit in this application are powered separately to improve the overall gain.

[0117] Exemplarily, in response to the problems of large area, PVT sensitivity, long equalization process, slow algorithm convergence, etc. in existing adaptive continuous time linear equalizers, the present application provides an adaptive continuous time linear equalizer, which detects the degree of eye opening through an on-chip eye diagram detector to accurately and quickly evaluate the signal quality. The signal adjustment module circuit provided by the present application realizes an adaptive continuous time linear equalizer with high and low frequency adjustable high bandwidth, using the TAS-TIS topology, which has a low output impedance and expands the bandwidth. At the same time, in the TAS part, the medium and low frequency gain is adjustable and has a large adjustment range. The overall circuit has low power consumption and few adjustment variables, fast convergence speed, and convenient adaptive adjustment.

[0118] Figure 5 and Figure 6 They are the frequency responses of the adaptive continuous-time linear equalizer under the changed configuration. Frequency response is used to describe the difference in the processing capability of an instrument for signals of different frequencies. Frequency response refers to the curve of amplitude gain changing with frequency. By changing the capacitance value or resistance value of the adjustable capacitor or the adjustable resistor, the signal variation amplitude of the linear equalizer tends to be stable within the Nyquist frequency, that is, the signal equalization achieved by the adaptive continuous-time linear equalizer provided by the present application is more stable and faster.

[0119] Exemplarily, under load, by adjusting the resistance, the adaptive continuous time linear equalizer can provide an 8dB high frequency gain adjustment range for 24Gb / s data, and by adjusting the capacitance, the low frequency gain in the range of 100M-5GHz can be adjusted.

[0120] The following table shows the comparison of EW / EH detection time:

[0121]

[0122] Among them, when the eye diagram detector applied to the adaptive continuous time linear equalizer provided by the present application adopts the 28nm CMOS process, the time for detecting the eye width data and the eye height data is 2.90us and 3.28us respectively; when the eye diagram detector applied to the adaptive continuous time linear equalizer based on asynchronous sampling histogram adopts the 130nm CMOS process, the time for completing the detection of the eye height data is 1150us; for the eye diagram detector applied to the adaptive continuous time linear detector based on random sigma tracking eye diagram, the time for completing the detection of the eye contour data is 4793us. The adaptive continuous time linear equalizer proposed in the present application uses a non-uniform scanning eye diagram detector to detect the degree of eye diagram opening, which improves the speed of optimizing the equalization coefficient and breaks the trade-off between adaptation time and accuracy.

[0123] The following table shows the bandwidth and power consumption comparison of the adaptive continuous-time linear equalizer in 28nm CMOS process:

[0124]

[0125] Among them, the adaptive continuous time linear equalizer provided in this application has a bandwidth of 12GHz and a power consumption of 4.681mW; the bandwidth of the equalizer without TIS circuit structure is 8GHz and the power consumption is 3.240mW; the bandwidth of the programmable dual-path equalizer is 8GHz and the power consumption is 6.480mW; the bandwidth of the equalizer with TAS-TIS structure is 12GHz and the power consumption is 8.676mW; this application proposes a circuit structure of a signal adjustment module 1 with adjustable high and low frequencies and high bandwidth that is suitable for this application, and the power consumption is lower than the adaptive continuous time linear equalizer currently provided with a high-bandwidth circuit structure.

[0126] The second aspect of the present application provides a control method for an adaptive continuous time linear equalizer, which is applied to an adaptive continuous time linear equalizer described in any of the above embodiments, including: receiving a data signal; performing high-frequency gain processing on the data signal according to a gain coefficient; the gain coefficient is the amplification ratio of the data signal; obtaining eye height data and eye width data according to the data signal; obtaining an equalization coefficient according to the eye height data and eye width data; the equalization coefficient is the resistance adjustment value of the adjustable resistor and the capacitance adjustment value of the adjustable capacitor; adjusting the gain coefficient to the equalization coefficient, and controlling the signal adjustment module to operate according to the equalization coefficient; the signal adjustment module is configured with the adjustable resistor and the adjustable capacitor; wherein, when the signal adjustment module operates according to the equalization coefficient, the data signal achieves the target equalization effect. The effects of the above method embodiments can refer to the effects of the above adaptive continuous time linear equalizer embodiments, which will not be repeated here.

[0127] The present application provides an adaptive continuous time linear equalizer, which is usually used in a receiver and has the ability to eliminate ISI (inter symbol interference) of a transmission signal and improve the transmission data rate. The main circuit includes a signal conditioning module 1, an eye diagram calculation module 2 and an adaptive module 3. The eye height and eye width of the output signal of the signal conditioning module 1 are detected by the eye diagram calculation module 2, and then the state of the corresponding switch in the signal conditioning module 1 is switched by the adaptive module 3 to change the resistance of the adjustable resistor and the capacitance of the adjustable capacitor in the signal conditioning module circuit, thereby changing the high-frequency gain of the signal conditioning module 1 circuit, thereby realizing the balanced configuration of different channels. Among them, the signal conditioning module 1 adopts a high-low frequency adjustable low-power TAS-TIS (trans-admittance trans-impedance) structure, and the TAS circuit adopts two branches of HF (high pass) circuit and LF (low pass) circuit, which has the ability to adjust the low-frequency and high-frequency gain of the transmission signal. The TIS part is based on an inverter to reduce the influence of load capacitance on the signal bandwidth and thus expand the bandwidth. The eye diagram calculation module 2 uses non-uniform sampling and quantization to shorten the time for detecting the eye height and eye width, which is conducive to more quickly obtaining the adaptive equalization coefficient of the signal adjustment module 1. The adaptive continuous time linear equalizer provided by the present application can achieve equalization of high-speed signals while reducing the impact of the load of the subsequent circuit of the continuous time linear equalizer on the bandwidth.

[0128] The above specific implementation methods further explain in detail the purpose, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above are only specific implementation methods of the embodiments of the present application and are not used to limit the protection scope of the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. An adaptive continuous-time linear equalizer, characterized in that: include: A signal conditioning module (1), wherein the signal conditioning module (1) is configured with an adjustable resistor and an adjustable capacitor; the signal conditioning module (1) is configured as follows: receiving a data signal; According to a gain coefficient, high-frequency gain processing is performed on the data signal; the gain coefficient is the amplification ratio of the data signal by the signal adjustment module (1); An eye diagram calculation module (2), wherein the eye diagram calculation module (2) is configured to: Obtaining eye height data and eye width data according to the data signal; The adaptive module (3) is configured to: According to the eye height data and the eye width data, an equalization coefficient is obtained; the equalization coefficient is a resistance adjustment value of the adjustable resistor and a capacitance adjustment value of the adjustable capacitor; Adjusting the gain coefficient to the equalization coefficient, and controlling the signal adjustment module (1) to operate according to the equalization coefficient; When the signal adjustment module (1) operates according to the equalization coefficient, the data signal achieves a target equalization effect.

2. The adaptive continuous-time linear equalizer according to claim 1, characterized in that: The eye diagram calculation module (2) comprises: A phase interpolator (21), wherein the phase interpolator (21) is configured to: Obtaining eye width data according to the data signal; A digital-to-analog converter (22), wherein the digital-to-analog converter (22) is configured to: Eye height data is obtained according to the data signal.

3. The adaptive continuous time linear equalizer according to claim 2, characterized in that: The eye diagram to be tested includes: an eye detection area and an eye non-detection area; The eye diagram calculation module (2) also includes: A judging unit (23), wherein the judging unit (23) is configured to: Acquiring an image scanning area of ​​the phase interpolator (21) or the digital-to-analog converter (22); If the image scanning area is an eye detection area, generating a first control signal; If the image scanning area is an eye non-detection area, generating a second control signal; A control unit (24), wherein the control unit (24) is configured to: According to the first control signal, controlling the phase interpolator (21) or the digital-to-analog converter (22) to scan the eye diagram to be tested with a first preset step length; According to the second control signal, the phase interpolator (21) or the digital-to-analog converter (22) is controlled to scan the eye diagram to be measured with a second preset step length; the second preset step length is greater than the first preset step length.

4. The adaptive continuous-time linear equalizer according to claim 1, characterized in that: The adaptive module (3) is configured with a capacitance adjustment unit, and the capacitance adjustment unit is configured to perform a capacitance adjustment operation; the capacitance adjustment operation is configured as follows: The capacitance value of the adjustable capacitor is reduced according to a preset value to obtain a capacitance adjustment value; Acquiring eye height data and eye width data under the capacitance adjustment value; Calculating a real-time value of the sum of the eye height data and the eye width data; Determine whether the total real-time value is greater than the total reference value, and if not, obtain a target capacitance value based on the capacitance adjustment value; If so, the capacitance adjustment operation is repeatedly performed until the target capacitance value is obtained.

5. The adaptive continuous-time linear equalizer according to claim 4, characterized in that: The adaptive module (3) is configured with a resistance adjustment unit, and the resistance adjustment unit is configured to perform a resistance adjustment operation: the resistance adjustment operation is configured as follows: Increasing the resistance value of the adjustable resistor according to a preset value to obtain a resistance adjustment value; Obtaining eye height data and eye width data under the resistance adjustment value; Calculating a real-time value of the sum of the eye height data and the eye width data; Determine whether the total real-time value is greater than the total reference value, and if not, obtain a target resistance value based on the resistance adjustment value; If yes, the resistance adjustment operation is repeatedly performed until the target resistance value is obtained; The adaptive module (3) is further configured as: Based on the target capacitance value and the target resistance value, a balancing coefficient is obtained.

6. The adaptive continuous-time linear equalizer according to claim 5, characterized in that: The sum reference value is determined by the following steps: Acquiring eye height data and eye width data under a set environment; the set environment is configured such that the adjustable resistance is a minimum value and the adjustable capacitance is a maximum value; A total reference value of the eye height data and the eye width data is calculated.

7. The adaptive continuous-time linear equalizer according to claim 1, characterized in that: The signal conditioning module (1) is provided with a TAS circuit; The adjustable resistor and the adjustable capacitor are configured in the TAS circuit.

8. The adaptive continuous-time linear equalizer according to claim 7, characterized in that: The TAS circuit is configured with a high-pass circuit and a low-pass circuit; The low-pass circuit is an RC low-pass filter.

9. The adaptive continuous-time linear equalizer according to claim 7, characterized in that: The signal conditioning module (1) is further provided with a TIS circuit, wherein the TIS circuit is electrically connected to the TAS circuit; The TIS circuit is configured with a first inverter and a second inverter, and the first inverter and the second inverter are respectively connected to the TAS circuit.

10. A control method for an adaptive continuous time linear equalizer, applied to an adaptive continuous time linear equalizer as claimed in any one of claims 1 to 9, characterized in that: include: receiving a data signal; According to the gain coefficient, performing high-frequency gain processing on the data signal; The gain coefficient is the amplification ratio of the data signal; Obtaining eye height data and eye width data according to the data signal; Obtaining an equalization coefficient according to the eye height data and the eye width data; The equalization coefficient is the resistance adjustment value of the adjustable resistor and the capacitance adjustment value of the adjustable capacitor; The gain coefficient is adjusted to the equalization coefficient, and the signal adjustment module is controlled to operate according to the equalization coefficient; the signal adjustment module is configured with the adjustable resistor and the adjustable capacitor; When the signal adjustment module operates according to the equalization coefficient, the data signal achieves a target equalization effect.

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