Delay circuits, memories and storage systems

Abstract

The present disclosure provides a delay circuit, a memory and a storage system, and relates to the field of memory technology. The gate of the first N-type transistor of the delay circuit is connected to a voltage conversion circuit to receive a first gate control voltage; the gate of the second N-type transistor is connected to a voltage conversion circuit to receive a second gate control voltage; the voltage conversion circuit is used to generate a first gate control voltage and a second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is less than the second value; the absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is less than the fourth value. The embodiments of the present disclosure can improve the stability of the buffer time and improve the yield.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a delay circuit, a memory, and a storage system. Background Art

[0002] The delay unit is used to delay the signal for a certain period of time, that is, to make the signal move back a certain amount of time on the time axis. For example, in some timing control circuits, it is necessary to ensure that certain operations are performed after a specific delay time; in digital communication systems, it is necessary to align the signals transmitted from different paths at the receiving end so that they can be processed synchronously at the same time through appropriate delays.

[0003] The common delay circuit consists of a two-stage inverter and a voltage-controlled delay unit. By changing the gate voltage of the voltage-controlled delay unit, the charging and discharging current of the inverter can be controlled, thereby generating different delay times. However, in this structure, the process deviation in the chip manufacturing process has a huge impact on the accuracy of the delay time. Under different process angles, the variation of the delay time may be as high as 30%.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a delay circuit, a memory and a storage system, which are used to reduce the delay time deviation of the delay circuit caused by chip manufacturing reasons and improve the yield.

[0006] According to a first aspect of an embodiment of the present disclosure, a delay circuit is provided, comprising a first inverter, a second inverter, a first N-type transistor, a second N-type transistor and a voltage conversion circuit; a first end of the first inverter is used to receive a first voltage, a second end is connected to a first end of the first N-type transistor, and an input end is used to receive an input signal; a first end of the second inverter is connected to an output end of the first inverter, a first end is used to receive a first voltage, a second end is connected to a first end of the second N-type transistor, and an output end is used to output a buffered signal of the input signal; a second end of the first N-type transistor is grounded, and a gate is connected to the voltage conversion circuit to receive a first gate control voltage; The second end of the second N-type transistor is grounded, and the gate is connected to a voltage conversion circuit to receive a second gate control voltage; the voltage conversion circuit is used to generate a first gate control voltage and a second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is less than the second value; the absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is less than the fourth value.

[0007] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a first P-type transistor, a first end of the first P-type transistor is used to receive a second voltage, a gate and a second end of the first P-type transistor are connected to a first node, and the first node is used to output a first gate control voltage.

[0008] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a second P-type transistor, a first end of the second P-type transistor is used to receive a second voltage, a gate and a second end of the second P-type transistor are connected to a second node, and the second node is used to output a second gate control voltage.

[0009] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a first current source, which is used to generate a first current according to a second voltage and output the first current through an output terminal, and the first current decreases as the second voltage increases, and increases as the second voltage decreases; a first resistor, the first end of which is connected to the output terminal of the first current source, and the second end is grounded, and the first end of the first resistor is used to output a first gate control voltage.

[0010] In an exemplary embodiment of the present disclosure, the second gate control voltage is the same voltage as the first gate control voltage, and the gates of the first N-type transistor and the second N-type transistor are both connected to the first end of the first resistor.

[0011] In an exemplary embodiment of the present disclosure, the voltage conversion circuit further includes: a second resistor, a first end of which is connected to the output end of the first current source and a second end of which is grounded, and the first end of the second resistor is used to output the second gate control voltage.

[0012] In an exemplary embodiment of the present disclosure, the first current source includes: a third P-type transistor, a first end for receiving the second voltage, a gate and a second end connected to a third node; a fourth P-type transistor, a first end for receiving the second voltage, a gate connected to the third node, and a second end serving as an output end of the first current source.

[0013] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a second current source, which is used to generate a second current and output the second current through an output terminal, and the second current decreases when the second voltage increases, and increases when the second voltage decreases; a third resistor, a first end of which is connected to the output terminal of the second current source, a second end of which is used to receive the second voltage, and a first end of the third resistor is used to output a first gate control voltage.

[0014] In an exemplary embodiment of the present disclosure, the second gate control voltage is the first gate control voltage, and the gates of the first N-type transistor and the second N-type transistor are both connected to the first end of the first resistor.

[0015] In an exemplary embodiment of the present disclosure, the voltage conversion circuit further includes: a fourth resistor, a first end of which is connected to the output end of the second current source, a second end of which is used to receive the second voltage, and a first end of which is used to output the second gate control voltage.

[0016] In an exemplary embodiment of the present disclosure, the second current source includes: a third N-type transistor, a first end of which is grounded through a constant current source, a gate is connected to a third voltage, and a second end receives the second voltage through a fifth resistor; a fourth N-type transistor, a first end of which is grounded through a constant current source, a gate is connected to the third voltage, and a second end serves as an output end of the second current source.

[0017] According to a second aspect of an embodiment of the present disclosure, a memory is provided, comprising: a memory cell array; a peripheral circuit, the peripheral circuit being coupled to the memory cell array; the peripheral circuit comprising a delay circuit, the delay circuit comprising a first inverter, a second inverter, a first N-type transistor, a second N-type transistor and a voltage conversion circuit: a first end of the first inverter is used to receive a first voltage, a second end is connected to a second end of the first N-type transistor, and an input end is used to receive an input signal; a first end of the second inverter is connected to an output end of the first inverter, the first end is used to receive a first voltage, the second end is connected to a second end of the second N-type transistor, and the output end is used to output a buffered signal of the input signal; a first end of the first N-type transistor is grounded, a gate The first end of the second N-type transistor is grounded, and the gate is connected to the voltage conversion circuit to receive the second gate control voltage; the voltage conversion circuit is used to generate the first gate control voltage and the second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is less than the second value; the absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is less than the fourth value.

[0018] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a first P-type transistor, a first end of the first P-type transistor is used to receive a second voltage, a gate and a second end of the first P-type transistor are connected to a first node, and the first node is used to output a first gate control voltage.

[0019] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a second P-type transistor, a first end of the second P-type transistor is used to receive a second voltage, a gate and a second end of the second P-type transistor are connected to a second node, and the second node is used to output a second gate control voltage.

[0020] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a first current source, which is used to generate a first current according to a second voltage and output the first current through an output terminal, and the first current decreases as the second voltage increases, and increases as the second voltage decreases; a first resistor, the first end of which is connected to the output terminal of the first current source, and the second end is grounded, and the first end of the first resistor is used to output a first gate control voltage.

[0021] In an exemplary embodiment of the present disclosure, the first current source includes: a third P-type transistor, a first end for receiving the second voltage, a gate and a second end connected to a third node; a fourth P-type transistor, a first end for receiving the second voltage, a gate connected to the third node, and a second end serving as an output end of the first current source.

[0022] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes: a second current source, which is used to generate a second current and output the second current through an output terminal, and the second current decreases when the second voltage increases, and increases when the second voltage decreases; a third resistor, a first end of which is connected to the output terminal of the second current source, a second end of which is used to receive the second voltage, and a first end of the third resistor is used to output a first gate control voltage.

[0023] In an exemplary embodiment of the present disclosure, the second current source includes: a third N-type transistor, a first end of which is grounded through a constant current source, a gate is connected to a third voltage, and a second end receives the second voltage through a fifth resistor; a fourth N-type transistor, a first end of which is grounded through a constant current source, a gate is connected to the third voltage, and a second end serves as an output end of the second current source.

[0024] According to a third aspect of an embodiment of the present disclosure, a storage system is provided, comprising: a memory and a storage controller coupled to the memory, wherein: the memory comprises a storage cell array and a peripheral circuit, and the peripheral circuit is coupled to the storage cell array; the peripheral circuit comprises a delay circuit, and the delay circuit comprises a first inverter, a second inverter, a first N-type transistor, a second N-type transistor, and a voltage conversion circuit; the first end of the first inverter is used to receive a first voltage, the second end is connected to the second end of the first N-type transistor, and the input end is used to receive an input signal; the first end of the second inverter is connected to the output end of the first inverter, the first end is used to receive the first voltage, the second end is connected to the second end of the second N-type transistor, and the output end is used to output a buffered signal of the input signal; The first end of an N-type transistor is grounded, and the gate is connected to a voltage conversion circuit to receive a first gate control voltage; the first end of a second N-type transistor is grounded, and the gate is connected to a voltage conversion circuit to receive a second gate control voltage; the voltage conversion circuit is used to generate a first gate control voltage and a second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is less than the second value; the absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is less than the fourth value.

[0025] The disclosed embodiment provides a voltage conversion circuit to provide a gate voltage for a voltage-controlled delay unit of a delay circuit. When the threshold voltage of the voltage-controlled delay unit transistor shifts due to process angle, temperature, etc., the gate voltage of the transistor can be automatically adjusted to maintain a stable delay time of the delay circuit and improve chip yield.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0028] Figure 1 is a schematic structural diagram of a delay circuit in an exemplary embodiment of the present disclosure.

[0029] Figure 2 is a schematic diagram of a voltage conversion circuit in an embodiment of the present disclosure.

[0030] Figure 3 is a schematic diagram of a voltage conversion circuit in an embodiment of the present disclosure.

[0031] Figure 4 is a schematic diagram of a voltage conversion circuit in an embodiment of the present disclosure.

[0032] Figure 5 is a schematic diagram of a memory in an exemplary embodiment of the present disclosure.

[0033] Figure 6 is a schematic diagram of a storage system in an embodiment of the present disclosure.

[0034] Figure 7 A block diagram showing an exemplary system with a memory according to an embodiment of the present disclosure is shown.

[0035] Figure 8 A block diagram of a storage system is exemplarily shown.

[0036] Fig. 9 A block diagram of another storage system is shown as an example.

[0037] Fig.10 A schematic circuit diagram of a memory 300 including peripheral circuits provided in an embodiment of the present disclosure.

[0038] Fig.11 A schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0040] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0041] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 is a schematic structural diagram of a delay circuit in an exemplary embodiment of the present disclosure.

[0043] refer to Figure 1 The delay circuit 100 may include: a first inverter INV1, a second inverter INV2, a first N-type transistor MN1, a second N-type transistor MN2 and a voltage conversion circuit 1, wherein the first N-type transistor MN1 and the second N-type transistor MN2 may be referred to as a voltage-controlled delay unit 2.

[0044] The first end of the first inverter INV1 is used to receive the first voltage VP1, the second end is connected to the first end of the first N-type transistor MN1, and the input end is used to receive the input signal IN;

[0045] The first end of the second inverter INV2 is connected to the output end of the first inverter INV1, the first end is used to receive the first voltage VP1, the second end is connected to the first end of the second N-type transistor MN2, and the output end is used to output the delayed signal IN-D of the input signal IN;

[0046] The second terminal of the first N-type transistor MN1 is grounded, and the gate is connected to the voltage conversion circuit 1 to receive the first gate control voltage Vgate1;

[0047] The second terminal of the second N-type transistor MN2 is grounded, and the gate is connected to the voltage conversion circuit 1 to receive the second gate control voltage Vgate2;

[0048] The voltage conversion circuit 1 is used to generate a first gate control voltage Vgate1 and a second gate control voltage Vgate2 according to the second voltage VP2;

[0049] The absolute value of the difference between the first gate control voltage Vgate1 and the threshold voltage Vth of the first N-type transistor MN1 is a first value, the absolute value of the difference between the second voltage VP2 and the threshold voltage Vth of the first N-type transistor MN1 is a second value, and the first value is smaller than the second value;

[0050] The absolute value of the difference between the second gate control voltage Vgate2 and the threshold voltage Vth of the second N-type transistor MN2 is a third value, the absolute value of the difference between the second voltage VP2 and the threshold voltage Vth of the second N-type transistor MN2 is a fourth value, and the third value is smaller than the fourth value.

[0051] The delay time of the delay circuit 100 is controlled by the voltage-controlled delay unit 2, i.e., the first N-type transistor MN1 and the second N-type transistor MN2. As the process angle changes, the threshold voltage of the first N-type transistor MN1 and the second N-type transistor MN2 changes, which is higher or lower than the design value (ideal value). In the related art, the gate control voltage of the first N-type transistor MN1 and the second N-type transistor MN2 changes very little with the process angle, resulting in different delay times of the delay circuit at different process angles due to different threshold voltages of the first N-type transistor MN1 and the second N-type transistor MN2, almost the same gate control voltage, and different charging currents of the inverters. That is, the delay time of the delay circuit in the chips at different process angles is different.

[0052] In order to solve this problem, the embodiment of the present disclosure is based on a traditional delay circuit composed of a two-stage inverter and a voltage-controlled delay unit, and adds a voltage conversion circuit 1 to adjust the gate control voltage of the voltage-controlled delay unit 2, that is, the second voltage VP2, so as to control the gate voltage of the voltage-controlled delay unit 2, so that the charging current of the delay circuit at different process angles is almost the same, and the delay time of the delay circuit in the chips at different process angles is maintained to be the same.

[0053] It should be noted that the first voltage VP1 and the second voltage VP2 are voltages used to power multiple related circuits such as clock circuits and delay circuits in the chip (the second voltage VP2 provides gate control voltages for multiple delay circuits). They are generally generated by a constant voltage source and vary very little with the process angle, but may vary somewhat when the temperature changes drastically. In actual operation, the second voltage VP2 will vary with the process angle. At a fast (FF) process angle, VP2 will decrease; and at a slow (SS) process angle, VP2 will increase.

[0054] Process Corner is a way to describe the change in chip performance due to fluctuations in process parameters during integrated circuit manufacturing. In semiconductor manufacturing, it is difficult to ensure that the performance of each transistor is exactly the same, and process parameters (such as doping concentration, oxide layer thickness, photolithography accuracy, etc.) will vary within a certain range. The process corner defines the extreme conditions of these parameter changes, generally including fast, typical and slow process corners to characterize different process deviations.

[0055] The typical process corner is a process parameter condition that is usually referenced when designing integrated circuits. The threshold voltage of the N-type transistor is at a normal design value. At this point, the performance of the transistor meets the design expectations, and can stably implement various logic functions and signal processing tasks under normal operating voltage and frequency. Its process parameters such as doping concentration and oxide layer thickness are all within the ideal design range, so the threshold voltage is also the expected standard value, and its on and off characteristics meet the basic assumptions during circuit design. In the related art, the power supply voltage VP2 of the voltage-controlled delay unit 2 in the delay circuit is calculated based on this situation and is used in chip design and manufacturing.

[0056] At the fast process corner (Fast Corner), the threshold voltage of N-type transistors is usually low. This is because some factors in the manufacturing process may make the channel doping concentration of the transistor slightly lower than the typical case, or the oxide layer thickness may be slightly thinner. For example, a lower channel doping concentration will reduce the binding of electrons, making it easier for electrons to form a conductive channel at a lower gate voltage, resulting in a lower threshold voltage. A lower threshold voltage means that at the same driving voltage, the transistor is easier to turn on and can achieve a faster transition from the off state to the on state. Therefore, in this case, the switching speed of the N-type transistor will be faster. If the designed gate control voltage is based on the threshold voltage of the N-type transistor corresponding to the typical process corner, it will appear larger for the N-type transistor at this process corner, resulting in a larger current flowing through the N-type transistor at the fast process corner than the current flowing through the N-type transistor at the typical process corner. In the delay circuit, the delay time will be reduced.

[0057] For the slow corner, the threshold voltage of the N-type transistor will increase. Due to reasons such as excessive channel doping concentration or increased oxide layer thickness, the higher channel doping concentration causes more electrons to be bound, requiring a higher gate voltage to form a conductive channel, so that the transistor switching speed will be slower and a higher voltage will be required to drive the transistor to turn on. If the designed gate control voltage is based on the threshold voltage of the N-type transistor corresponding to the typical process corner, it will appear smaller for the N-type transistor under this process corner, resulting in a smaller current flowing through the N-type transistor under the slow process corner than the current flowing through the N-type transistor under the typical process corner. In the delay circuit, this will cause the delay time to increase.

[0058] In the related art, the gate control voltage of the two N-type transistors is the second voltage VP2. The second voltage VP2 that varies with the process angle can partially compensate for the threshold voltage offset of the N-type transistor, but it is far from enough. The maximum deviation of the delay time of the same delay circuit under different process angles can reach 30%.

[0059] In the disclosed embodiment, the gate control voltage provided by the voltage conversion circuit 1 is smaller when the N-type transistor is in a fast process angle, and is larger when the N-type transistor is in a slow process angle, thereby effectively compensating for the problem of delay time offset of the delay circuit caused by the change of the threshold voltage of the N-type transistor with the process angle, so that the delay time corresponding to the same delay circuit in different chips is basically the same.

[0060] Several embodiments are introduced below to implement the voltage conversion circuit 1 provided in the embodiment of the present disclosure.

[0061] Figure 2 is a schematic diagram of a voltage conversion circuit in an embodiment of the present disclosure.

[0062] refer to Figure 2 , in an exemplary embodiment, the voltage conversion circuit 1 may include:

[0063] The first P-type transistor MP1 has a first terminal for receiving a second voltage VP2, a gate and a second terminal connected to a first node N1, and the first node N1 is used to output a first gate control voltage Vgate1.

[0064] The second P-type transistor MP2 has a first terminal for receiving a second voltage VP2, a gate and a second terminal connected to a second node N2, and the second node N2 is used to output a second gate control voltage Vgate2.

[0065] exist Figure 2In the illustrated embodiment, the connection mode of the P-type transistor is a diode connection, that is, equivalent to a diode. In this case, since the gate oxide layer of the transistor is very thin, there is leakage current on the gate source of the first N-type transistor MN1 and the second N-type transistor MN2. Therefore, there is a current path that reaches the gate source of the first N-type transistor MN1 through the second voltage VP2 and the first P-type transistor MP1, and a current path that reaches the gate source of the second N-type transistor MN2 through the second voltage VP2 and the second P-type transistor MP2.

[0066] Since the gate leakage current increases and the threshold voltage of the first P-type transistor MP1 and the second P-type transistor MP2 decreases under the fast process corner (FF corner), the leakage current of the first P-type transistor MP1 and the second P-type transistor MP2 will also increase, thereby reducing the gate control voltage (Vgate1 and Vgate2) of the first N-type transistor MN1 and the second N-type transistor MN2. The lower gate control voltage reduces the increasing charge and discharge current of the two-stage inverter under the fast process corner, thereby extending the originally shortened output delay time, so that the delay time of the delay circuit 100 has a smaller deviation from the designed delay time.

[0067] Similarly, since the gate leakage current is reduced and the threshold voltage of the first P-type transistor MP1 and the second P-type transistor MP2 is increased under the slow process corner (SS corner), the leakage current of the first P-type transistor MP1 and the second P-type transistor MP2 will also be reduced, thereby increasing the gate control voltage (Vgate1 and Vgate2) of the first N-type transistor MN1 and the second N-type transistor MN2. The higher gate control voltage increases the charge and discharge current of the two-stage inverter that is constantly decreasing under the slow process corner, thereby shortening the originally extended output delay time, so that the delay time of the delay circuit 100 has a smaller deviation from the designed delay time.

[0068] By setting a diode-connected PMOS transistor to adjust the gate control voltage of the N-type transistor, the second voltage VP2 that varies with the process can be divided, thereby controlling the gate of the voltage-controlled delay unit 2, reducing the variation of the delay time by at least 10% under different process angles, and achieving higher accuracy. Compared with the existing design, Figure 2 The circuit shown in the embodiment has a simple structure, better performance, lower power consumption, and no additional cost.

[0069] In some embodiments, a corresponding P-type transistor may be provided for each N-type transistor of the voltage-controlled delay unit 2 in each delay circuit, such as Figure 2In some other embodiments, a P-type transistor may be provided to simultaneously provide a gate control voltage for each N-type transistor MN1 and MN2 of the voltage-controlled delay unit 2 to achieve circuit multiplexing, further simplify the circuit structure, and reduce costs.

[0070] Figure 3 is a schematic diagram of a voltage conversion circuit in an embodiment of the present disclosure.

[0071] refer to Figure 3 In some exemplary embodiments, the voltage conversion circuit 1 may include:

[0072] A first current source 31, configured to generate a first current I1 according to the second voltage VP2 and output the first current I1 through an output terminal, wherein the first current I1 decreases as the second voltage VP2 increases, and increases as the second voltage VP2 decreases;

[0073] The first resistor R1 has a first end connected to the output end of the first current source 31 and a second end grounded. The first end of the first resistor R1 is used to output the first gate control voltage Vgate1.

[0074] In an exemplary embodiment, the first current source 31 includes:

[0075] A third P-type transistor MP3, a first end of which is used to receive the second voltage VP2, and a gate and a second end of which are connected to a third node N3;

[0076] The fourth P-type transistor MP4 has a first end for receiving the second voltage VP2, a gate connected to the third node N3, and a second end serving as an output end of the first current source I1.

[0077] exist Figure 3 In the circuit shown, Vgate1 = VP2-I1*R1.

[0078] Under the fast process angle, the threshold voltage of the P-type transistor decreases, and the voltage of the third node N3, i.e., the gate control voltage of the fourth P-type transistor MP4, decreases, causing the current I1 to increase (the P-type transistor is turned on at a low voltage, and the smaller the gate control voltage, the greater the current). Since the first resistor R1 is not affected by the process angle, I1*R1 becomes larger at this time, and when the second voltage VP2 decreases slightly, the first gate control voltage Vgate1 decreases more, thereby effectively compensating for the threshold voltage drop of the first N-type transistor MN1, maintaining the charging current of the inverter stable, and maintaining the delay time of the delay circuit stable. The same is true for the slow process angle, which will not be repeated here.

[0079] In some embodiments, the second gate control voltage Vgate2 is the same as the first gate control voltage Vgate1, and the gates of the first N-type transistor MN1 and the second N-type transistor MN2 are both connected to the first end of the first resistor R1. In this case, the circuit structure can be simplified and the cost can be reduced.

[0080] In some other embodiments, the voltage conversion circuit 1 further includes:

[0081] The second resistor R2 has a first end connected to the output end of the first current source I and a second end grounded, and the first end of the second resistor R2 is used to output a second gate control voltage Vgate2. That is, a separate gate control voltage is provided for each N-type transistor in the voltage-controlled delay unit 2, further improving the regulation stability.

[0082] Figure 4 is a schematic diagram of a voltage conversion circuit in an embodiment of the present disclosure.

[0083] refer to Figure 4 , in an exemplary embodiment, the voltage conversion circuit 1 may include:

[0084] A second current source 41, used for generating a second current I2 and outputting the second current I2 through an output terminal, wherein the second current I2 decreases when the second voltage VP2 increases, and increases when the second voltage VP2 decreases;

[0085] The third resistor R3 has a first end connected to the output end of the second current source 41 , and a second end used for receiving the second voltage VP2 . The first end of the third resistor R3 is used for outputting the first gate control voltage Vgate1 .

[0086] In an exemplary embodiment, the second current source 41 includes:

[0087] A third N-type transistor MN3, a first end of which is grounded through a constant current source 42, a gate of which is connected to a third voltage V3, and a second end of which receives a second voltage VP2 through a fifth resistor R5;

[0088] The fourth N-type transistor MN4 has a first terminal connected to the ground through the constant current source 42 , a gate connected to the third voltage V3 , and a second terminal serving as an output terminal of the second current source 41 .

[0089] The third voltage V3 may be a separately set reference voltage, and the constant current source 42 provides a constant current I0.

[0090] for Figure 3 In the circuit shown, Vgate=VP2-I2*R3.

[0091] At the FF process angle, the threshold voltage of the third N-type transistor MN3 and the fourth N-type transistor MN4 is reduced, and the leakage current is increased. The source current of the third N-type transistor MN3 and the fourth N-type transistor MN4 is fixed by the constant current source 42. When the threshold voltage is reduced, the transconductance of the third N-type transistor MN3 and the fourth N-type transistor MN4 increases, the gate voltage of the fourth N-type transistor MN4 is fixed, the drain current, i.e., the second current I2 increases, the voltage drop on the third resistor R3 increases, and Vgate1 decreases. Therefore, when the second voltage VP2 decreases slightly, the first gate control voltage Vgate1 decreases more, thereby effectively compensating for the threshold voltage drop of the first N-type transistor MN1, maintaining the charging current of the inverter stable, and maintaining the delay time of the delay circuit stable. The same is true for the slow process angle, which will not be repeated here.

[0092] In an exemplary embodiment, the second gate control voltage Vgate2 is the first gate control voltage Vgate1, and the gates of the first N-type transistor MN1 and the second N-type transistor MN2 are both connected to the first end of the first resistor, thereby simplifying the circuit structure.

[0093] In some other embodiments, the voltage conversion circuit 1 further includes:

[0094] The fourth resistor R4 has a first end connected to the output end of the second current source 41, a second end for receiving the second voltage VP2, and a first end for outputting the second gate control voltage Vgate2. That is, a separate gate control voltage is provided for each N-type transistor in the voltage-controlled delay unit 2, further improving the regulation stability.

[0095] The circuits of each of the above-mentioned embodiments can provide gate control voltages for the voltage-controlled delay units of multiple delay circuits at the same time, thereby realizing circuit multiplexing without consuming too much production cost. Therefore, the benefits far outweigh the costs. The delay circuit of the disclosed embodiment can not only maintain the stability of the delay time when the process angle changes, but also maintain the stability of the delay time when the temperature changes, and has excellent performance.

[0096] Figure 5 is a schematic diagram of a memory in an exemplary embodiment of the present disclosure.

[0097] refer to Figure 5 , the memory 500 may include:

[0098] Memory cell array 51;

[0099] The peripheral circuit 52 is coupled to the memory cell array 51; the peripheral circuit 52 includes a delay circuit 100, and the delay circuit 100 includes a first inverter INV1, a second inverter INV2, a first N-type transistor MN1, a second N-type transistor MN2 and a voltage conversion circuit 1:

[0100] The first end of the first inverter INV1 is used to receive the first voltage VP1, the second end is connected to the second end of the first N-type transistor MN1, and the input end is used to receive an input signal;

[0101] The first end of the second inverter INV2 is connected to the output end of the first inverter INV1, the first end is used to receive the first voltage VP1, the second end is connected to the second end of the second N-type transistor MN2, and the output end is used to output a delayed signal of the input signal;

[0102] A first terminal of the first N-type transistor MN1 is grounded, and a gate is connected to the voltage conversion circuit 1 to receive a first gate control voltage Vgate1;

[0103] A first terminal of the second N-type transistor MN2 is grounded, and a gate thereof is connected to the voltage conversion circuit 1 to receive a second gate control voltage Vgate2;

[0104] The voltage conversion circuit 1 is used for generating a first gate control voltage Vgate1 and a second gate control voltage Vgate2 according to the second voltage VP2;

[0105] The absolute value of the difference between the first gate control voltage Vgate1 and the threshold voltage Vth of the first N-type transistor MN1 is a first value, the absolute value of the difference between the second voltage VP2 and the threshold voltage Vth of the first N-type transistor MN1 is a second value, and the first value is smaller than the second value;

[0106] The absolute value of the difference between the second gate control voltage Vgate2 and the threshold voltage Vth of the second N-type transistor MN2 is a third value, the absolute value of the difference between the second voltage VP2 and the threshold voltage Vth of the second N-type transistor MN2 is a fourth value, and the third value is smaller than the fourth value.

[0107] In an exemplary embodiment, the voltage conversion circuit 1 includes: a first P-type transistor, a first terminal of the first P-type transistor is used to receive a second voltage VP2, a gate and a second terminal of the first P-type transistor are connected to a first node, and the first node is used to output a first gate control voltage Vgate1.

[0108] The voltage conversion circuit 1 includes: a second P-type transistor, a first end of the second P-type transistor is used to receive a second voltage VP2, a gate and a second end of the second P-type transistor are connected to a second node, and the second node is used to output a second gate control voltage Vgate2.

[0109] The voltage conversion circuit 1 includes: a first current source, used to generate a first current according to a second voltage VP2 and output the first current through an output end, the first current decreases as the second voltage VP2 increases, and increases as the second voltage VP2 decreases; a first resistor, the first end of which is connected to the output end of the first current source and the second end is grounded, and the first end of the first resistor is used to output a first gate control voltage Vgate1.

[0110] The first current source includes: a third P-type transistor, a first end of which is used to receive the second voltage VP2, a gate and a second end are connected to a third node; a fourth P-type transistor, a first end of which is used to receive the second voltage VP2, a gate is connected to the third node, and a second end serves as the output end of the first current source.

[0111] The voltage conversion circuit 1 includes: a second current source, used to generate a second current and output the second current through an output end, the second current decreases when the second voltage VP2 increases, and increases when the second voltage VP2 decreases; a third resistor, a first end of which is connected to the output end of the second current source, a second end of which is used to receive the second voltage VP2, and a first end of the third resistor is used to output a first gate control voltage Vgate1.

[0112] The second current source includes: a third N-type transistor, a first end of which is grounded through a constant current source, a gate is connected to a third voltage, and a second end receives the second voltage VP2 through a fifth resistor; a fourth N-type transistor, a first end of which is grounded through a constant current source, a gate is connected to the third voltage, and a second end serves as the output end of the second current source.

[0113] The various embodiments of the delay circuit 100 are described in detail in Figure 1 to Figure 4 The corresponding description will not be repeated here.

[0114] In the peripheral circuit 52 , the delay circuit 100 is used in multiple places.

[0115] In the address decoding circuit, the delay circuit can be used to fine-tune the address signal. When multiple storage cells are accessed at the same time or there is jitter in the address signal, appropriate delay can ensure that the address signal is stable before the decoding operation. For example, in dynamic random access memory (DRAM), the address line needs to be sent to the decoder after a certain delay to avoid decoding errors due to the address signal changing too quickly. Because DRAM operates at a high speed, a slight jitter in the address signal may cause the decoder to misunderstand the address information. The delay circuit can make the address signal decoded at the appropriate time point in the clock cycle, improving the accuracy of address decoding.

[0116] During the data writing process, the delay circuit in the data read and write control module can be used to adjust the time to write data. For example, in a synchronous static random access memory (SRAM), when the write enable signal is valid, the data signal needs to be written into the storage unit after a certain delay time. This is because the circuit inside the storage unit (such as the switching action of the transistor) needs a certain amount of time to stabilize the state in order to correctly store the data. The delay circuit can ensure that the data is accurately written at the moment when the storage unit is ready to receive, preventing the situation where the data is written incorrectly or incompletely.

[0117] During the data reading process, the delay circuit can be used to control the effective time of reading the data. The data signal read from the storage unit may need to be delayed to match the timing requirements of the external circuit. For example, in Flash Memory, after reading the data, the data signal can be delayed to a time point synchronized with the system clock through the delay circuit, so that the read data can be received and processed by the subsequent circuit (such as a data buffer or processor) at the appropriate time.

[0118] For DRAM, refresh operations need to be performed regularly to maintain the correctness of stored data. The delay circuit set in the refresh circuit (for memories such as DRAM that need to be refreshed) can be used in the generation and transmission of refresh control signals. The refresh cycle is triggered by an internal timer or an external controller, and the refresh command needs to be appropriately delayed by the delay circuit before being sent to the memory cell array. This is because when the memory cell is refreshed, its internal capacitor needs a certain amount of time to complete the charging or discharging process to restore the data state. The delay circuit can ensure that the refresh signal arrives at a time point when the memory cell can effectively respond, thereby improving the efficiency and reliability of the refresh operation.

[0119] Therefore, the embodiments of the present disclosure maintain the stability of the delay circuit under various process corners, which can greatly improve the performance of the memory peripheral circuit and improve the memory performance.

[0120] Figure 6 is a schematic diagram of a storage system in an embodiment of the present disclosure.

[0121] refer to Figure 6In an exemplary embodiment, a memory system 600 may include a memory 500 and a memory controller 61 coupled to the memory, wherein: the memory 500 includes a memory cell array 51 and a peripheral circuit 52, the peripheral circuit 52 is coupled to the memory cell array 51; the peripheral circuit 52 includes a delay circuit 100, the delay circuit includes a first inverter, a second inverter, a first N-type transistor, a second N-type transistor and a voltage conversion circuit; the first end of the first inverter is used to receive a first voltage, the second end is connected to the second end of the first N-type transistor, and the input end is used to receive an input signal; the first end of the second inverter is connected to the output end of the first inverter, the first end is used to receive the first voltage, the second end is connected to the second end of the second N-type transistor, and the output end is used to output the input signal a buffer signal; a first end of the first N-type transistor is grounded, and a gate is connected to a voltage conversion circuit to receive a first gate control voltage; a first end of the second N-type transistor is grounded, and a gate is connected to a voltage conversion circuit to receive a second gate control voltage; the voltage conversion circuit is used to generate a first gate control voltage and a second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is less than the second value; the absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is less than the fourth value.

[0122] Figure 7 A block diagram of an exemplary system with a memory in an embodiment of the present disclosure is shown. System 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or any other suitable electronic device having a memory therein.

[0123] like Figure 7 As shown, the system 700 may include a host 708 and a storage system 702, the storage system 702 having one or more memories 500 and a memory controller 61. The host 708 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor) of an electronic device. The host 708 may be configured to send data to the memory 500 or receive data from the memory 500.

[0124] The memory 500 may be any memory in the present disclosure, for example, a non-volatile memory. The non-volatile memory may be a NAND flash memory (for example, a three-dimensional (3D) NAND flash memory).

[0125] In some embodiments, the memory controller 61 is coupled to the memory 500 and the host 708 and is configured to control the memory 500. The memory controller 61 may manage data stored in the memory 500 and communicate with the host 708.

[0126] In some embodiments, the memory controller 61 is configured to send commands to the memory 500 .

[0127] In some embodiments, the memory controller 61 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0128] In some embodiments, the memory controller 61 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which can be used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 61 can be configured to send commands to the memory 500 to cause the memory 500 to perform operations, such as read, erase, and program operations.

[0129] The memory controller 61 may also be configured to manage various functions regarding data stored or to be stored in the memory 500 , including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

[0130] In some embodiments, the memory controller 61 is also configured to process error correction codes (ECC) on data read from or written to the memory 500. The memory controller 61 may also perform any other suitable functions, such as formatting the memory 500. The memory controller 61 may communicate with an external device (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 61 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0131] The memory controller 61 and one or more memories 500 can be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the storage system 702 can be implemented and packaged into different types of terminal electronic products.

[0132] Figure 8 A block diagram of a storage system is shown as an example. Figure 8 As shown, the memory controller 61 and the single memory 500 may be integrated into the memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, a Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., an MMC card, an RS-MMC card, an MMCmicro card, etc.), an SD card (e.g., an SD card, a miniSD card, a microSD card, an SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 7 A memory card connector 204 coupled to a host 708 in the memory card connector.

[0133] Fig. 9 FIG. 1 is a block diagram of another storage system. Fig. 9 As shown, the memory controller 61 and the plurality of memories 500 may be integrated into the SSD 206. The SSD 206 may also include a processor that connects the SSD 206 to a host (e.g., Figure 7 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0134] Fig.10 A schematic circuit diagram of a memory 300 including a peripheral circuit provided in an embodiment of the present disclosure. The memory 500 may be Figure 5 The memory 500 or Figure 7 . The memory 500 may include a memory cell array 51 and a peripheral circuit 52 coupled to the memory cell array 51. The memory cell array 51 may be a NAND flash memory cell array, wherein the memory cells 506 are provided in the form of an array of memory strings 508 of the NAND flash memory, each memory string 508 extending vertically above a substrate (not shown).

[0135] In some embodiments, at least one functional module of the peripheral circuit 52 includes the delay circuit 100 provided in the embodiments of the present disclosure.

[0136] In some embodiments, each memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 506. Each memory cell 506 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0137] like Fig.10 As shown, each memory string 508 may include a source select gate (SSG) 510 at its source terminal and a drain select gate (DSG) 512 at its drain terminal. SSG 510 and DSG 512 may be configured to activate the selected memory string 508 during read and program operations.

[0138] In some embodiments, the sources of the memory strings 508 in the same block 504 are coupled via the same source line (Source Line, SL) 514 (e.g., a common SL). For example, all memory strings 508 in the same block 504 have an array common source (Array Common Source, ACS). Fig.10 As shown, the memory string 508 can be organized into a plurality of blocks 504, each of which can have a common source line 514 (e.g., coupled to ground). In some embodiments, each block 504 is a basic data unit for an erase operation, i.e., all memory cells 506 on the same block 504 are erased at the same time.

[0139] In some embodiments, the transistors of the DSG 512 of each memory string 508 are coupled to a corresponding bit line (BL) 516, and data can be read from or written to the bit line 516 via an output bus (not shown). Each memory string 508 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the DSG 512) or a deselection voltage (e.g., 0V) to the corresponding DSG 512 via one or more DSG lines 513 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the SSG 510) or a deselection voltage (e.g., 0V) to the corresponding SSG 510 via one or more SSG lines 515.

[0140] like Fig.10As shown, the memory cells 506 of the memory string 508 may be coupled via a word line (WL) 518, which selects which row of memory cells 506 are affected by read and program operations. The peripheral circuit 52 may be coupled to the memory cell array 51 via a bit line 516, a word line 518, a source line 514, an SSG line 515, and a DSG line 513. The peripheral circuit 52 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 51 by applying a voltage signal and / or a current signal to each memory cell 506 that is the target of the operation and sensing a voltage signal and / or a current signal from each memory cell 506 that is the target of the operation via the bit line 516, the word line 518, the source line 514, the SSG line 515, and the DSG line 513. The peripheral circuit 52 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0141] Fig.11 Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. Fig.11 As shown, the peripheral circuit 52 may include functional circuits, detection circuits, and adjustment circuits. The functional circuit includes one or more of a page delay circuit / sense amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, an input and output (IO) circuit 416, and a data bus 418. It should be understood that in some examples, it may also include Fig.11 Additional peripheral circuits not shown.

[0142] Fig.11 The peripheral circuit shown in the embodiment includes at least one detection circuit and at least one adjustment circuit, and each detection circuit is connected to a corresponding adjustment circuit. Each detection circuit may include a transistor of the same type as that in the corresponding functional circuit, and the corresponding adjustment circuit is used to adjust the magnitude of the power supply voltage of the corresponding functional circuit. The detection circuit includes a transistor of the same type as that in the corresponding functional circuit, and the detection circuit is used to generate and output a control signal through its output terminal using the transistor of the same type; the adjustment circuit is coupled to the corresponding detection circuit and the functional circuit respectively, and is used to receive and adjust the magnitude of the power supply voltage supplied to the corresponding functional circuit according to the control signal, so that the magnitude of the power supply voltage supplied to the functional circuit is adapted to the process angle of the transistor of the same type in the functional circuit.

[0143] For example, Fig.11In the embodiment, the detection circuit 1 includes transistors of the same type as those in the input-output circuit 616. The detection circuit 1 is used to generate a control signal using the transistors of the same type and output it to the adjustment circuit 1 through its output terminal. The adjustment circuit 1 is coupled to the detection circuit 1 and the input-output circuit 616 respectively, receives and adjusts the power supply voltage supplied to the input-output circuit 616 according to the control signal output by the detection circuit 1, so that the power supply voltage supplied to the input-output circuit 616 is adapted to the process angle of the transistors of the same type in the input-output circuit 616.

[0144] For another example, Fig.11 In the embodiment, the detection circuit 2 includes transistors of the same type as those in the voltage generator 610. The detection circuit 2 is used to generate a control signal using the transistors of the same type and output it to the adjustment circuit 2 through its output terminal. The adjustment circuit 2 is coupled to the detection circuit 2 and the voltage generator 610 respectively, receives and adjusts the power supply voltage supplied to the voltage generator 610 according to the control signal output by the detection circuit 2, so that the power supply voltage supplied to the voltage generator 610 is adapted to the process angle of the transistors of the same type in the voltage generator 610.

[0145] In other embodiments, corresponding detection circuits and adjustment circuits may be provided for other functional circuits in the peripheral circuits, and the present disclosure is not limited to the above examples.

[0146] In some embodiments, the page delay circuit / sense amplifier 604 can be configured to read data from the memory cell array 51 and program (write) data to the memory cell array 51 according to a control signal from the control logic unit 612. For example, the page delay circuit / sense amplifier 604 can store a page of programming data (write data) to be programmed into the memory cell array 51. For another example, the page delay circuit / sense amplifier 604 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / BL driver 606 can be configured to be controlled by the control logic unit 612, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 610.

[0147] The row decoder / WL driver 608 may be configured to be controlled by the control logic unit 612, and select / deselect the block 304 of the memory cell array 51 and select / deselect the word line 318 of the block 304. The row decoder / WL driver 608 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 610. In some embodiments, the row decoder / WL driver 608 may also select / deselect and drive the SSG line 314 and the DSG line 313. The voltage generator 610 may be configured to be controlled by the control logic unit 612, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, a source line voltage, etc. to be supplied to the memory cell array 51.

[0148] The control logic unit 612 may be coupled to each portion of the peripheral circuit 52 and configured to control the operation of each portion. The register 614 may be coupled to the control logic unit 612 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The input / output circuit 616 may be coupled to the control logic unit 612 and act as a control delay circuit to buffer the input / output circuit from the host ( Fig.11 The input / output circuit 616 may also be coupled to the column decoder / bit line driver 606 via the data bus 618, and act as a data I / O interface and data delay circuit to buffer data and relay it to or from the memory cell array 51.

[0149] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0150] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A delay circuit, characterized in that: The device comprises a first inverter, a second inverter, a first N-type transistor, a second N-type transistor and a voltage conversion circuit; The first end of the first inverter is used to receive a first voltage, the second end is connected to the first end of the first N-type transistor, and the input end is used to receive an input signal; The first end of the second inverter is connected to the output end of the first inverter, the first end is used to receive the first voltage, the second end is connected to the first end of the second N-type transistor, and the output end is used to output the buffer signal of the input signal; The second terminal of the first N-type transistor is grounded, and the gate is connected to the voltage conversion circuit to receive a first gate control voltage; The second terminal of the second N-type transistor is grounded, and the gate is connected to the voltage conversion circuit to receive a second gate control voltage; The voltage conversion circuit is used to generate the first gate control voltage and the second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is smaller than the second value; The absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is smaller than the fourth value.

2. The delay circuit according to claim 1, wherein: The voltage conversion circuit comprises: A first P-type transistor, wherein a first end of the first P-type transistor is used to receive the second voltage, a gate and a second end of the first P-type transistor are connected to a first node, and the first node is used to output the first gate control voltage.

3. The delay circuit according to claim 1 or 2, characterized in that: The voltage conversion circuit comprises: A second P-type transistor, wherein a first terminal of the second P-type transistor is used to receive the second voltage, a gate and a second terminal of the second P-type transistor are connected to a second node, and the second node is used to output the second gate control voltage.

4. The delay circuit according to claim 1, wherein: The voltage conversion circuit comprises: a first current source, configured to generate a first current according to the second voltage and output the first current through an output terminal, wherein the first current decreases as the second voltage increases and increases as the second voltage decreases; A first resistor has a first end connected to the output end of the first current source and a second end grounded. The first end of the first resistor is used to output the first gate control voltage.

5. The delay circuit according to claim 4, characterized in that The second gate control voltage is the same voltage as the first gate control voltage, and the gates of the first N-type transistor and the second N-type transistor are both connected to the first end of the first resistor.

6. The delay circuit according to claim 4, characterized in that The voltage conversion circuit further includes: A second resistor has a first end connected to the output end of the first current source and a second end grounded. The first end of the second resistor is used to output the second gate control voltage.

7. The delay circuit according to any one of claims 4 to 6, characterized in that: The first current source comprises: a third P-type transistor, a first terminal for receiving the second voltage, a gate and a second terminal connected to a third node; A fourth P-type transistor, having a first end for receiving the second voltage, a gate connected to the third node, and a second end serving as an output end of the first current source.

8. The delay circuit according to claim 1, wherein: The voltage conversion circuit comprises: a second current source, configured to generate a second current and output the second current through an output terminal, wherein the second current decreases when the second voltage increases, and increases when the second voltage decreases; A third resistor has a first end connected to the output end of the second current source, a second end used for receiving the second voltage, and a first end of the third resistor used for outputting the first gate control voltage.

9. The delay circuit according to claim 8, wherein: The second gate control voltage is the first gate control voltage, and the gates of the first N-type transistor and the second N-type transistor are both connected to the first end of the first resistor.

10. The delay circuit according to claim 8, wherein: The voltage conversion circuit further includes: A fourth resistor has a first end connected to the output end of the second current source, a second end used to receive the second voltage, and the first end of the fourth resistor is used to output the second gate control voltage.

11. The delay circuit according to any one of claims 8 to 10, characterized in that: The second current source comprises: a third N-type transistor, a first terminal of which is grounded through a constant current source, a gate of which is connected to a third voltage, and a second terminal of which receives the second voltage through a fifth resistor; A fourth N-type transistor, having a first terminal connected to the ground through the constant current source, a gate connected to the third voltage, and a second terminal serving as an output terminal of the second current source.

12. A memory, characterized in that: include: A memory cell array; A peripheral circuit, the peripheral circuit is coupled to the memory cell array; the peripheral circuit includes a delay circuit, the delay circuit includes a first inverter, a second inverter, a first N-type transistor, a second N-type transistor and a voltage conversion circuit: The first end of the first inverter is used to receive a first voltage, the second end is connected to the second end of the first N-type transistor, and the input end is used to receive an input signal; The first end of the second inverter is connected to the output end of the first inverter, the first end is used to receive the first voltage, the second end is connected to the second end of the second N-type transistor, and the output end is used to output the buffer signal of the input signal; A first terminal of the first N-type transistor is grounded, and a gate is connected to the voltage conversion circuit to receive a first gate control voltage; A first terminal of the second N-type transistor is grounded, and a gate is connected to the voltage conversion circuit to receive a second gate control voltage; The voltage conversion circuit is used to generate the first gate control voltage and the second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is smaller than the second value; The absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is smaller than the fourth value.

13. The memory according to claim 12, wherein: The voltage conversion circuit comprises: A first P-type transistor, wherein a first end of the first P-type transistor is used to receive the second voltage, a gate and a second end of the first P-type transistor are connected to a first node, and the first node is used to output the first gate control voltage.

14. The memory according to claim 12 or 13, characterized in that: The voltage conversion circuit comprises: A second P-type transistor, wherein a first terminal of the second P-type transistor is used to receive the second voltage, a gate and a second terminal of the second P-type transistor are connected to a second node, and the second node is used to output the second gate control voltage.

15. The memory according to claim 12, wherein: The voltage conversion circuit comprises: a first current source, configured to generate a first current according to the second voltage and output the first current through an output terminal, wherein the first current decreases as the second voltage increases and increases as the second voltage decreases; A first resistor has a first end connected to the output end of the first current source and a second end grounded. The first end of the first resistor is used to output the first gate control voltage.

16. The memory according to claim 15, characterized in that The first current source comprises: a third P-type transistor, a first terminal for receiving the second voltage, a gate and a second terminal connected to a third node; A fourth P-type transistor, having a first end for receiving the second voltage, a gate connected to the third node, and a second end serving as an output end of the first current source.

17. The memory according to claim 12, wherein: The voltage conversion circuit comprises: a second current source, configured to generate a second current and output the second current through an output terminal, wherein the second current decreases when the second voltage increases, and increases when the second voltage decreases; A third resistor has a first end connected to the output end of the second current source, a second end used for receiving the second voltage, and a first end of the third resistor used for outputting the first gate control voltage.

18. The memory according to claim 17, wherein: The second current source comprises: a third N-type transistor, a first terminal of which is grounded through a constant current source, a gate of which is connected to a third voltage, and a second terminal of which receives the second voltage through a fifth resistor; A fourth N-type transistor, having a first terminal connected to the ground through the constant current source, a gate connected to the third voltage, and a second terminal serving as an output terminal of the second current source.

19. A storage system, characterized in that: include: The invention comprises a memory and a memory controller coupled to the memory, wherein: The memory includes a memory cell array and a peripheral circuit, wherein the peripheral circuit is coupled to the memory cell array; the peripheral circuit includes a delay circuit, wherein the delay circuit includes a first inverter, a second inverter, a first N-type transistor, a second N-type transistor, and a voltage conversion circuit; The first end of the first inverter is used to receive a first voltage, the second end is connected to the second end of the first N-type transistor, and the input end is used to receive an input signal; The first end of the second inverter is connected to the output end of the first inverter, the first end is used to receive the first voltage, the second end is connected to the second end of the second N-type transistor, and the output end is used to output the buffer signal of the input signal; A first terminal of the first N-type transistor is grounded, and a gate is connected to the voltage conversion circuit to receive a first gate control voltage; A first terminal of the second N-type transistor is grounded, and a gate is connected to the voltage conversion circuit to receive a second gate control voltage; The voltage conversion circuit is used to generate the first gate control voltage and the second gate control voltage according to the second voltage; wherein the absolute value of the difference between the first gate control voltage and the threshold voltage of the first N-type transistor is a first value, the absolute value of the difference between the second voltage and the threshold voltage of the first N-type transistor is a second value, and the first value is smaller than the second value; The absolute value of the difference between the second gate control voltage and the threshold voltage of the second N-type transistor is a third value, the absolute value of the difference between the second voltage and the threshold voltage of the second N-type transistor is a fourth value, and the third value is smaller than the fourth value.

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