A multifunctional on / off circuit and method for testing and measuring instruments

Abstract

The present invention belongs to the technical field of measuring instrument power-on and power-off circuits, and particularly relates to a multifunctional power-on and power-off circuit and method for a test and measuring instrument. The circuit includes an RC charging circuit, a single-channel Smith buffer, an ultra-high-speed D trigger, an RC filtering circuit, a first NPN-type transistor, a second NPN-type transistor, an N-channel MOS transistor, and a P-channel MOS transistor. The method includes a power-on method, a forced power-off and shutdown method, a single-button execution of a custom function method, and a user interface shutdown method. The present invention uses simple devices to realize the necessary functions of multiple test and measuring instruments, realizes the power-on and forced power-off functions of long-pressing a button, and the custom function of single-clicking a button. Only two GPIOs are needed to complete the interaction with the CPU. The overall circuit is simple and easy to use, occupies a small space on the PCB, has extremely low standby power consumption, and is extremely cost-effective.

Description

Technical Field

[0001] The invention belongs to the technical field of measuring instrument on / off circuits, and in particular relates to a multifunctional on / off circuit and method for testing and measuring instruments. Background Art

[0002] The power on / off status management function of a test and measurement instrument is a basic element for an instrument to provide users with a good operating experience, and it is also an indispensable part of the design of the entire test and measurement instrument. The power on / off function is the first link for users to contact and recognize a test and measurement instrument. A good interactive experience of the power on / off function can bring convenience to users in using the entire instrument.

[0003] In a test and measurement instrument, most of the existing instrument power-on and power-off status management functions mainly rely on an MCU (Microcontroller Unit) chip or CPLD (Complex Programming Logic Device) main control chip to realize the power-on and power-off power management and various timing control applications. The existing instrument power-on and power-off status management method can realize that when the instrument is turned off, single-click the power-on button to turn on the instrument; when the instrument is turned on, single-click the power-on button to turn off the instrument.

[0004] The switch button of the traditional power on / off function circuit has a single function, which can only realize the power on and off of the whole machine by clicking the power on / off button. At the same time, the main control chip used in its design is relatively large in size, occupying more space on the PCB (Printed Circuit Board). Being in standby state for a long time will bring considerable power consumption, which can no longer fully meet the development needs of test and measurement instruments in the direction of intelligent and highly integrated design. Summary of the invention

[0005] In view of various deficiencies in the prior art, the inventor has designed a multifunctional on / off circuit for a test and measurement instrument through long-term practice. The circuit can be completed using simple logic devices, has low cost and low standby power consumption.

[0006] The invention discloses a multifunctional switch circuit for a test and measurement instrument, comprising an RC charging circuit, a single-channel Smith buffer, an ultra-high-speed D trigger, an RC filtering circuit, a first NPN transistor, a second NPN transistor, an N-channel MOS transistor, and a P-channel MOS transistor.

[0007] The RC charging circuit is composed of a variable resistor and a first capacitor, the input end of the RC charging circuit is connected to the standby power supply, the output end of the RC charging circuit is connected to the input end of the single-channel Smith buffer, the output end of the single-channel Smith buffer is connected to the clock end of the ultra-high-speed D flip-flop, the Q end of the ultra-high-speed D flip-flop is connected to the input end of the RC filter circuit, and the ultra-high-speed D flip-flop is used to respond to the single-channel Smith buffer and control the second NPN transistor at the back end to be turned on.

[0008] The RC filter circuit is composed of a fifth resistor and a third capacitor, and the RC filter circuit processes the D flip-flop output Q to eliminate high-frequency noise. The output end of the RC filter circuit is connected to the base of the second NPN transistor, the emitter of the second NPN transistor is grounded, the collector of the second NPN transistor is connected to the gate of the P-channel MOS transistor, the source of the P-channel MOS transistor is connected to an external input power supply, a sixth resistor is connected between the gate and source of the P-channel MOS transistor, and the drain of the P-channel MOS transistor is connected to the output power supply after switch control.

[0009] The base of the first NPN transistor is connected to the GPIO (General Purpose Input Output) output port of the CPU, the collector of the first NPN transistor is connected to the power supply after power-on, and the emitter of the first NPN transistor is connected to the RC charging circuit. The source of the N-channel MOS transistor is grounded, the gate of the N-channel MOS transistor is connected to the standby power supply circuit, and a second resistor is connected between the gate and source of the N-channel MOS transistor. The drain of the N-channel MOS transistor is connected to the GPIO input port of the CPU, and is connected to the power supply after power-on through a third resistor.

[0010] Furthermore, one end of the first capacitor C1 is connected in parallel with the first resistor R1.

[0011] Furthermore, the D terminal of the ultra-high-speed D flip-flop and The S end of the ultra-high-speed D trigger is connected to a standby power supply.

[0012] Furthermore, the R terminal of the ultra-high-speed D flip-flop is grounded through a second capacitor, and the R terminal of the ultra-high-speed D flip-flop is connected to a standby power supply through a fourth resistor.

[0013] Furthermore, the sixth capacitor and the seventh capacitor are connected between the drain of the P-channel MOS tube and the output power supply after switch control, and the fourth capacitor and the fifth capacitor are both connected to the source of the P-channel MOS tube.

[0014] The method for powering on is implemented by using the circuit of the present invention. When the measuring instrument is in the off state, the user long presses the power key, the voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer, the single-channel Smith buffer outputs a high-level pulse to the clock end of the ultra-high-speed D-type flip-flop, the D-type flip-flop takes effect, the level of the output end Q of the D-type flip-flop is converted, and a high-level signal is output to the second NPN-type transistor, reaching the conduction threshold of the second NPN-type transistor, so that the gate level of the P-channel MOS tube is pulled down to the ground and becomes 0, the P-channel MOS tube is turned on, and at this time the output power after the switch control is equal to the external input power, and the power-on is completed.

[0015] The method for forced power-off shutdown is realized by using the circuit of the present invention. When the test and measuring instrument is in the power-on state, the user long presses the power button, the voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer, the single-channel Smith buffer outputs a high-level pulse to the clock end of the ultra-high-speed D-type flip-flop, the level of the output end Q of the D-type flip-flop is converted, and the output becomes a low-level signal, so that the second NPN transistor is cut off, so that the gate level of the P-channel MOS tube returns to be consistent with the external input power supply, the P-channel MOS tube is cut off, the output power after the switch control stops outputting, the power supply of the test and measuring instrument is cut off, and the shutdown is completed.

[0016] The circuit described in the present invention is used to implement a method for executing a custom function by clicking a button. When a user clicks the power button, the switch is closed and turned on, raising the gate level of the N-channel MOS tube to 3.3V, and a voltage difference appears across the second resistor. The N-channel MOS tube is turned on, so that the drain level of the N-channel MOS tube is consistent with the source, and the level of the GPIO input port of the CPU changes from 1 to 0. This change will be monitored by the CPU system software process. After receiving this change, the corresponding shortcut command function will be executed.

[0017] The method for shutting down the user interface is realized by using the circuit described in the present invention. When the computer is turned on, the system defaults to configuring the GPIO output port of the CPU to output a low level. At this time, the collector of the first NPN transistor is connected to the power supply after power-on, which is 3.3V, and the emitter of the first NPN transistor is pulled down to a low level through the second resistor; when the user clicks the shutdown button in the system interface, the GPIO output port of the CPU is controlled to output a high level that lasts for τ seconds. At this time, the first NPN transistor is turned on for τ seconds, and the RC circuit completes charging. The voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer, and the single-channel Smith buffer outputs a high-level pulse to the clock end of the ultra-high-speed D flip-flop. The level of the output end Q of the D flip-flop is converted, and the output becomes a low-level signal, so that the second NPN transistor is turned off, so that the gate level of the P-channel MOS tube returns to be consistent with the external input power supply, the P-channel MOS tube is turned off, the output power after the switch control stops outputting, the power supply of the test and measurement instrument is cut off, and the shutdown is completed.

[0018] The beneficial effects of the present invention are:

[0019] 1) Multiple functions are realized around the switch button, including long pressing the switch button to realize the whole machine power on and off function, single clicking the switch button to realize custom functions, user interface shutdown function, forced power off function, rich and comprehensive functions.

[0020] 2) The total standby power consumption of the key components used is only 3.3V@2.5uA, and the permanent standby power consumption is greatly reduced. If timing control is required later, it is only necessary to add the main control chip to the circuit of the present invention.

[0021] 3) The devices used are all less than 10 pins, and the package is compact and occupies little space, which can leave more space for other functions and facilitate the overall design layout of the printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a design principle diagram of the switch circuit of the present invention.

[0023] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0024] S1-switch, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, R6-sixth resistor, RT-variable resistor, C1-first capacitor, C2-second capacitor, C3-third capacitor, C4-fourth capacitor, C5-fifth capacitor, C6-sixth capacitor, C7-seventh capacitor, V1-first NPN transistor, V2-N channel MOS transistor, V3-second NPN transistor, V4-P channel MOS transistor, D1-single Smith buffer, D2-ultra-high-speed D flip-flop, 3V3_SL-standby power supply, VDD_3V3-power supply after power-on, POWER_IN-external input power supply, POWER_OUT-output power supply after switch control, GPIO1-GPIO output port of CPU, GPIO2-GPIO input port of CPU. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and implementation examples. These implementation examples are described in sufficient detail so that those skilled in the art can understand and practice the present invention. Without departing from the spirit and scope of the present invention, logical, achievable and other changes may be made to the implementation. Therefore, the following detailed description should not be construed as limiting, and the scope of the present invention is limited only by the claims.

[0026] See also Figure 1 In order to meet the development needs of test and measurement instruments in the direction of intelligent and highly integrated design, the present invention proposes a multifunctional switch circuit for test and measurement instruments, including an RC charging circuit, a single-channel Smith buffer D1, an ultra-high-speed D trigger D2, an RC filtering circuit, a first NPN transistor V1, a second NPN transistor V3, an N-channel MOS transistor V2, and a P-channel MOS transistor V4.

[0027] The RC charging circuit is composed of a variable resistor RT and a first capacitor C1. One end of the first capacitor C1 is connected in parallel with the first resistor R1, and the first capacitor C1 releases the stored voltage through the first resistor R1. The RC charging circuit is used to realize the power-on and power-off functions and adjust the long-press button time. After pressing the switch S1, the standby power supply 3V3_SL will charge the first capacitor C1, and after the charging time τ seconds (τ=RT*C1), the trigger threshold of the single-channel Smith buffer D1 is reached.

[0028] The input end of the RC charging circuit is connected to the standby power supply 3V3_SL, the output end of the RC charging circuit is connected to the input end of the single Smith buffer D1, and the output end of the single Smith buffer D1 is connected to the clock end of the ultra-high-speed D flip-flop D2. The single Smith buffer D1 is used to process and determine the charging result of the RC charging circuit. The single Smith buffer D1 is powered by the standby power supply 3V3_SL. After the RC charging circuit is charged to the trigger threshold of the single Smith buffer D1 of 0.63*3.3V, the single Smith buffer D1 will output a high-level pulse to the clock pin of the ultra-high-speed D flip-flop D2.

[0029] The D terminal of the ultra-high-speed D flip-flop D2 and The Q end of the ultra-high-speed D trigger D2 is connected to the input end of the RC filter circuit, and the S end of the ultra-high-speed D trigger D2 is connected to the standby power supply 3V3_SL. The R end of the ultra-high-speed D trigger D2 is grounded through the second capacitor C2, and the second capacitor C2 plays a filtering role for the ultra-high-speed D trigger D2. The R end of the ultra-high-speed D trigger D2 is connected to the standby power supply 3V3_SL through the fourth resistor R4, and the fourth resistor R4 provides a pull-up resistor circuit for the D trigger to increase the current.

[0030] The ultra-high-speed D flip-flop is used to respond to the buffer and control the conduction of the second NPN transistor V3 at the back end. The ultra-high-speed D flip-flop D2 is powered by the standby power supply 3V3_SL. In the initial state, the Q pin of the D flip-flop will output a low-level signal. Output high level, when the clock pin of the D flip-flop receives a high level pulse from a single Smith buffer, the output changes, at this time D= =1, the D flip-flop output Q will become high level, controlling the second NPN transistor V3, and will become low.

[0031] The RC filter circuit is composed of a fifth resistor R5 and a third capacitor C3. The RC filter circuit processes the D flip-flop output Q to eliminate high-frequency noise. The output end of the RC filter circuit is connected to the base of the second NPN transistor V3.

[0032] The emitter of the second NPN transistor V3 is grounded, and the collector of the second NPN transistor V3 is connected to the gate of the P-channel MOS transistor V4.

[0033] The second NPN transistor V3 is used to control the on and off of the back-end P-channel MOS transistor V4. In the initial state, Ube=0V of the second NPN transistor V3, and its Vc=POWER_IN. When the high level output by the D flip-flop is received, the on threshold of the NPN transistor is reached, and Ube>0.7V is satisfied, so Vc=Ve=0V, and the on and off of the P-channel MOS transistor V4 is controlled.

[0034] The source of the P-channel MOS transistor V4 is connected to the external input power supply POWER_IN. The gate and source of the P-channel MOS transistor V4 are connected to a sixth resistor R6. The drain of the P-channel MOS transistor V4 is connected to the output power supply POWER_OUT after switch control.

[0035] The sixth capacitor C6 and the seventh capacitor C7 are connected between the drain of the P-channel MOS tube V4 and the output power supply POWER_OUT after switch control, and the sixth capacitor C6 and the seventh capacitor C7 are connected in parallel, and the sixth capacitor C6 and the seventh capacitor C7 provide energy storage for the circuit. The fourth capacitor C4 and the fifth capacitor C5 are both connected to the source of the P-channel MOS tube V4, and the fourth capacitor C4 and the fifth capacitor C5 are connected in parallel, and the fourth capacitor C4 and the fifth capacitor C5 also provide energy storage for the circuit.

[0036] The P-channel MOS tube V4 is used to switch the main power supply. In the initial state, the U GS =0V, not conducting. When the second NPN transistor V3 is conducting, U GS =0-POWER_IN, the P-channel MOS tube V4 is turned on, and POWER_OUT = POWER_IN. In this embodiment, the V4 device preferably uses a MOS tube with a large current carrying capacity, and its current carrying capacity is 5A-10A.

[0037] The base of the first NPN transistor V1 is connected to the GPIO output port GPIO1 of the CPU, the collector of the first NPN transistor V1 is connected to the power supply VDD_3V3 after power-on, and the emitter of the first NPN transistor V1 is connected to the RC charging circuit.

[0038] The first NPN transistor V1 is used for the shutdown function of the user software interface. The CPU controls the CPU's GPIO output port GPIO1 to output a high level for τ seconds (τ=RT*C1, same as above), that is, to simulate pressing the switch S1 for τ seconds. The function of the first NPN transistor V1 is the same as that of the RC charging circuit, both of which are charging paths, representing the two charging paths of the shutdown function, and the charging time is the same, both of which are τ seconds.

[0039] The source of the N-channel MOS transistor V2 is grounded, the gate of the N-channel MOS transistor V2 is connected to the standby power supply 3V3_SL circuit, and the second resistor R2 is connected between the gate and the source of the N-channel MOS transistor V2. The drain of the N-channel MOS transistor V2 is connected to the GPIO input port GPIO2 of the CPU, and is connected to the power supply VDD_3V3 after power-on through the third resistor R3, so as to pull up the GPIO input port GPIO2 of the CPU to a high level.

[0040] The N-channel MOS tube V2 is used for the user single-click button function and is used to respond to the single-click operation of the button. In the initial shutdown state, the level of the GPIO input port GPIO2 to the CPU is low. After booting up, the whole machine is powered on with VDD_3V3=3.3V, and the V G =V S =0V. When the instrument is powered on, click switch S1, and a voltage difference appears across the second resistor R2. At this time, the V G =3V3_SL=3.3V, V S =0V,U GS =3.3V, N-channel MOS tube V2 is turned on, so V D =V S =0V, the level of the CPU's GPIO input port GPIO2 changes from 1→0, and this change will be monitored by the software process. After the CPU receives this change, it will execute the corresponding preset function.

[0041] The present invention also proposes a method for starting up the test and measurement instrument using the power-on and power-off circuit. The method refers to a process in which when the test and measurement instrument is in a power-off state, the user long presses the power-on and power-off button to power on the test and measurement instrument.

[0042] When executing the power-on process of the present invention, the standby power supply 3V3_SL plays a major role. The flow path of this power supply in the device is switch S1→variable resistor RT, first capacitor C1→single-channel Smith buffer D1→ultra-high-speed D trigger D2→fifth resistor R5→second NPN transistor V3.

[0043] After the user presses the switch S1 for τ seconds, the voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer D1 (i.e., 2.079V), so that the single-channel Smith buffer D1 outputs a high-level pulse to the clock end of the ultra-high-speed D flip-flop D2; the D flip-flop takes effect, the level of the output end Q is converted, and a high-level signal is output to the second NPN transistor V3, reaching the conduction threshold of the second NPN transistor V3, so that the gate level of the P-channel MOS tube V4 is pulled down to ground and becomes 0, U GS =0-POWER_IN, the P-channel MOS tube V4 is turned on. At this time, the output power POWER_OUT after switch control is equal to the external input power POWER_IN, completing the power-on process.

[0044] The present invention also proposes a method for forcibly shutting down the test and measurement instrument using the switch circuit, which refers to the process of shutting down the test and measurement instrument when the user wants to end the use process when the test and measurement instrument is in the power-on state. It can also be used to forcibly disconnect the power of the test and measurement instrument when the resident program inside the test and measurement instrument crashes or freezes.

[0045] This process is basically the same as the circuit used when the power-on process is executed, and the standby power supply 3V3_SL also plays a major role. The flow path of this power supply in the device is switch S1→variable resistor RT, first capacitor C1→single-channel Smith buffer D1→ultra-high-speed D flip-flop D2→fifth resistor R5→second NPN transistor V3. The difference is that when the ultra-high-speed D flip-flop D2 is in the on state, the output terminal Q outputs a high-level signal. After the user presses the power button for τ seconds, the voltage on the capacitor in the RC charging circuit reaches the trigger threshold of 2.079V of the single-channel Smith buffer D1, and the single-channel Smith buffer D1 outputs a high-level pulse to the clock terminal of the ultra-high-speed D flip-flop D2. The level of the output terminal Q of the D flip-flop is converted, and the output becomes a low-level signal, so that the second NPN transistor V3 is turned off, so that the gate level of the P-channel MOS tube V4 returns to the same as the external input power supply POWER_IN, the P-channel MOS tube V4 is turned off, and the output power supply POWER_OUT after switch control stops outputting, and the power supply of the test and measuring instrument is cut off, realizing the shutdown process.

[0046] The present invention also proposes a method for using the power on / off circuit to realize single-clicking a button to execute a custom function. The method refers to a process in which when the test and measurement instrument is in a shutdown state, the user single-clicks the power on / off button to execute a preset shortcut instruction.

[0047] When the test and measurement instrument is in the power-on state, the power supply VDD_3V3 exists after power-on. At this time, the gate and source of the N-channel MOS tube V2 are both 0V, and the N-channel MOS tube V2 is cut off. Therefore, the level of the GPIO input port GPIO2 of the CPU is pulled up by the power supply VDD_3V3 after power-on through the third resistor R3, and is a high level; when the user clicks the power button, the switch S1 is closed and turned on, and the gate level of the N-channel MOS tube V2 is raised to 3.3V, and a voltage difference appears across the second resistor R2, and the N-channel MOS tube V2 is turned on, so that the drain level of the N-channel MOS tube V2 is consistent with the source, and the level of the GPIO input port GPIO2 of the CPU changes from 1→0, and this change will be monitored by the CPU system software process. After receiving this change, the corresponding shortcut instruction function will be executed.

[0048] The present invention also proposes a method for realizing user interface shutdown by using the power-on / off circuit, which refers to a process in which the user realizes shutdown by pressing the power-off button in the system interface when the test and measurement instrument is in the power-on state. It is basically the same as the forced power-off shutdown process, except that the implementation of this process does not require pressing the power-on / off button, but controls the GPIO output port GPIO1 of the CPU of the system to output a high level, simulating the action of pressing the power-on button.

[0049] When the computer is powered on, the system needs to configure the CPU's GPIO output port GPIO1 to output low by default. At this time, the collector of the first NPN transistor V1 is connected to the power supply VDD_3V3, which is 3.3V. The emitter of the first NPN transistor V1 is pulled down to a low level through the second resistor R2. When the user clicks the shutdown button in the system interface, the CPU's GPIO output port GPIO1 will be controlled to output a high level for τ seconds. At this time, the first NPN transistor V1 is turned on for τ seconds, and the RC circuit completes charging. The RC charging circuit The voltage on the capacitor in the circuit reaches the trigger threshold of 2.079V of the single-channel Smith buffer D1, so that the single-channel Smith buffer D1 outputs a high-level pulse to the clock end of D2, the level of the output end Q of the D flip-flop is converted, and the output becomes a low-level signal, so that the second NPN transistor V3 is turned off, so that the gate level of the P-channel MOS tube V4 returns to the same as the external input power supply POWER_IN, the P-channel MOS tube V4 is turned off, the output power supply POWER_OUT after switch control stops outputting, the power supply of the test and measuring instrument is cut off, and the shutdown is completed.

[0050] In this process, a certain interactive window can be added after the user clicks the shutdown button, such as prompting whether to confirm the shutdown action to avoid accidental actions. When the CPU's GPIO output port GPIO1 outputs a high level for τ seconds, a "shutting down" loading animation covering the entire display interface can appear to add more interactivity.

[0051] The detailed parameters of each device in this embodiment are shown in Table 1 and Table 2 below.

[0052] Table 1 Fixed values ​​of resistors and capacitors

[0053] Position No. parameter Position No. parameter R1 71.5kΩ R6 1MΩ R2 10kΩ C1 100μF R3 10kΩ C2 0.1μF R4 1MΩ C3 0.1μF R5 5.36kΩ C4-C7 10μF

[0054] Table 2 Other device parameters

[0055] Position No. Model parameters Introduction RT 3296W-1-203 Variable resistor, preset 20kΩ V1, V3 MMBT3904 NPN transistor V2 DMN1260UFA-7B N-channel MOS tube V4 SI7617DN P-channel MOS tube (select as needed) D1 SN74LVC1G17 Single Buffer with Schmitt-Trigger Inputs D2 NC7SZ74K8X Ultra-fast D flip-flop with reset and clear

[0056] According to the device used in this embodiment, the configuration method of the power-on long press time is as follows: the device SN74LVC1G17 uses 3.3V for power supply, so according to its VIH judgment standard, when the input voltage is greater than 2V, it can output a logic level 1. When the RC circuit is charging, if the initial voltage is 0V, according to the RC charging circuit calculation formula Calculation shows that when t=RC, a charging cycle can be completed, that is, Vt=0.63*Vcc=2.079V. We fix the capacitor C1 value to 100μF. We only need to change the resistor RT value to change the required time. For example, when RT=20kΩ and C1=100μF, τ=RC=20×10 3 ×100×10 -6=2S, that is, long press the button to charge for 2S to complete the boot process. The resistance value of RT is not recommended to be too large, and the recommended resistance value is within 50kΩ.

[0057] It is not possible to describe all possible combinations of components or methods for the purpose of describing the above-described embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is encompassed in a manner similar to the term "including," as explained by "including," used as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. A multifunctional on / off circuit for a test and measurement instrument, characterized in that: It includes an RC charging circuit, a single-channel Smith buffer, an ultra-high-speed D trigger, an RC filtering circuit, a first NPN transistor, a second NPN transistor, an N-channel MOS transistor, and a P-channel MOS transistor; The RC charging circuit is composed of a variable resistor and a first capacitor, the input end of the RC charging circuit is connected to the standby power supply, the output end of the RC charging circuit is connected to the input end of the single-channel Smith buffer, the output end of the single-channel Smith buffer is connected to the clock end of the ultra-high-speed D flip-flop, the Q end of the ultra-high-speed D flip-flop is connected to the input end of the RC filter circuit, and the ultra-high-speed D flip-flop is used to respond to the single-channel Smith buffer and control the second NPN transistor at the back end to be turned on; The RC filter circuit is composed of a fifth resistor and a third capacitor, and the RC filter circuit processes the output Q of the D flip-flop to eliminate high-frequency noise; The output end of the RC filter circuit is connected to the base of the second NPN transistor, the emitter of the second NPN transistor is grounded, the collector of the second NPN transistor is connected to the gate of the P-channel MOS transistor, the source of the P-channel MOS transistor is connected to an external input power supply, a sixth resistor is connected between the gate and source of the P-channel MOS transistor, and the drain of the P-channel MOS transistor is connected to the output power supply controlled by the switch; The base of the first NPN transistor is connected to the GPIO output port of the CPU, the collector of the first NPN transistor is connected to the power supply after power-on, and the emitter of the first NPN transistor is connected to the RC charging circuit; The source of the N-channel MOS tube is grounded, the gate of the N-channel MOS tube is connected to the standby power supply circuit, and a second resistor is connected between the gate and the source of the N-channel MOS tube; the drain of the N-channel MOS tube is connected to the GPIO input port of the CPU and is connected to the power supply after power-on through the third resistor.

2. The circuit according to claim 1, characterized in that One end of the first capacitor C1 is connected in parallel with the first resistor R1.

3. The circuit according to claim 1, characterized in that The D terminal of the ultra-high-speed D flip-flop and The S end of the ultra-high-speed D trigger is connected to a standby power supply.

4. The circuit according to claim 3, characterized in that The R terminal of the ultra-high-speed D flip-flop is grounded through a second capacitor, and the R terminal of the ultra-high-speed D flip-flop is connected to a standby power supply through a fourth resistor.

5. The circuit according to claim 1, characterized in that The sixth capacitor and the seventh capacitor are connected between the drain of the P-channel MOS tube and the output power supply after switch control, and the fourth capacitor and the fifth capacitor are both connected to the source of the P-channel MOS tube.

6. A method for starting up a computer using the circuit according to any one of claims 1 to 5, characterized in that: When the measuring instrument is in the off state, the user long presses the power button, the voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer, the single-channel Smith buffer outputs a high-level pulse to the clock end of the ultra-high-speed D-type flip-flop, the D-type flip-flop takes effect, the level of the output end Q of the D-type flip-flop is converted, and a high-level signal is output to the second NPN-type transistor, reaching the conduction threshold of the second NPN-type transistor, so that the gate level of the P-channel MOS tube is pulled down to the ground and becomes 0, the P-channel MOS tube is turned on, and the output power after the switch control is equal to the external input power, and the startup is completed.

7. A method for implementing forced power-off shutdown using the circuit described in any one of claims 1 to 5, characterized in that: When the test and measurement instrument is in the power-on state, the user long presses the power button, the voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer, and the single-channel Smith buffer outputs a high-level pulse to the clock end of the ultra-high-speed D-type flip-flop. The level of the output end Q of the D-type flip-flop is converted, and the output becomes a low-level signal, so that the second NPN transistor is cut off, so that the gate level of the P-channel MOS tube returns to the same as the external input power supply, the P-channel MOS tube is cut off, the output power after the switch control stops outputting, the power supply of the test and measurement instrument is cut off, and the shutdown is completed.

8. A method for implementing a custom function by single-clicking a button using the circuit described in any one of claims 1 to 5, characterized in that: The user clicks the power button, the switch closes and turns on, raising the gate level of the N-channel MOS tube to 3.3V, and a voltage difference appears across the second resistor. The N-channel MOS tube is turned on, so that the drain level of the N-channel MOS tube is consistent with the source, and the level of the CPU's GPIO input port changes from 1→0. This change will be monitored by the CPU system software process. After receiving this change, the corresponding shortcut command function will be executed.

9. A method for shutting down a user interface using the circuit according to any one of claims 1 to 5, characterized in that: When the computer is powered on, the system configures the CPU's GPIO output port to output a low level by default. At this time, the collector of the first NPN transistor is connected to the power supply after power-on, which is 3.3V, and the emitter of the first NPN transistor is pulled down to a low level through the second resistor. When the user clicks the shutdown button in the system interface, the CPU's GPIO output port will be controlled to output a high level for τ seconds. At this time, the first NPN transistor is turned on for τ seconds, and the RC circuit is charged. The voltage on the capacitor in the RC charging circuit reaches the trigger threshold of the single-channel Smith buffer. The single-channel Smith buffer outputs a high-level pulse to the clock end of the ultra-high-speed D flip-flop. The level of the output end Q of the D flip-flop is converted, and the output becomes a low-level signal, so that the second NPN transistor is turned off, so that the gate level of the P-channel MOS tube returns to the same as the external input power supply. The P-channel MOS tube is turned off, the output power after the switch control stops outputting, the power supply of the test and measurement instrument is cut off, and the shutdown is completed.

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