A level shift circuit based on high-voltage capacitor using gallium nitride full integration process

Abstract

The application discloses a level shift circuit based on a high-voltage capacitor by adopting a gallium nitride full integration process, comprising a noise-resistant level conversion unit, a noise clamping unit, a high-speed latch unit and a reset unit. The noise-resistant level conversion unit can realize conversion from a low-side input signal to a high-side output signal, and the symmetrical structure thereof can effectively suppress common-mode noise. The noise clamping unit functions to effectively suppress the influence of dVS / dt noise on the circuit and clamp the voltage of a key node to prevent breakdown. The high-speed latch unit functions to quickly restore an input pulse signal to a level signal. The reset unit functions to generate a pulse signal to open a switch tube and help the key node to discharge charges. The overall circuit can better solve the trade-off problem between circuit power consumption and transmission delay of a traditional level shift circuit, the problem of delay variation of the level shift circuit with VS and the problem of failure of the level shift circuit affected by dVS / dt noise.

Description

TECHNICAL FIELD

[0001] The present application relates to power integrated circuits, in particular to a level shift circuit based on high-voltage capacitors using a gallium nitride full integration process, which can be applied to the gate drive circuit of a gallium nitride power tube. BACKGROUND

[0002] Gallium nitride power devices prepared using third-generation semiconductor materials have excellent physical properties, such as wide bandgap, high electron mobility, high switching frequency, low on-resistance, high voltage resistance, and high temperature resistance, etc. When applied in power conversion systems, they can significantly improve the switching speed, conversion efficiency, and power density of the system. As the operating frequency of the system increases, the discrete driving scheme using silicon-based driving chips to drive gallium nitride devices will induce ringing, overshoot, and other problems due to the large driving loop parasitic inductance, which seriously affects the reliability of the system. To address this issue, a leadless packaging technology can be used as a compromise, but this will significantly increase the cost of chip packaging. To fundamentally solve these problems, the driving circuit can be integrated with the power device on the same chip using a gallium nitride process. This method not only takes full advantage of the high-frequency characteristics of gallium nitride devices, but also improves the reliability of the system, achieving the dual advantages of high-frequency application and stability.

[0003] Benefiting from the current mature N-type gallium nitride full integration process, a half-bridge driving circuit and a gallium nitride power device can be integrated on a single die to avoid the reliability problems faced by discrete solutions. The core part of the half-bridge driving circuit is a high-voltage level shift circuit, which converts low-voltage domain signals into high-voltage domain signals, thereby enabling low-voltage signal control over high-voltage circuit systems.

[0004] Currently, the main problems faced by traditional integrated gallium nitride process level shift circuits are as follows:

[0005] 1. When the low-side input signal is transmitted to the high-side circuit through the level shift circuit, there will be a large transmission delay between the low-side input signal and the high-side output signal. To reduce this delay, the on-current of the level shift high-voltage gallium nitride field effect transistor branch can be increased to increase the response speed of the high-side circuit. However, increasing the on-current will also increase the power consumption of the circuit. Therefore, there is a serious trade-off between the power consumption and transmission delay of the traditional integrated gallium nitride process level shift circuit.

[0006] 2. In the half-bridge circuit, the high and low side power drive tubes are alternately turned on, so that the half-bridge circuit output node VS will change between the bus voltage VBUS and the low side ground GND, where VS is the ground signal of the high side circuit, and because the switching rate of the gallium nitride power tube is fast, the rate of change of VS is very fast, and the dVS / dt noise signal generated by the parasitic capacitance of the high-voltage power tube is coupled to the high side of the level shift circuit, affecting the normal output signal of the circuit.

[0007] 3. When the half-bridge circuit is normally working, there will be a situation that the high side power tube is turned off and the low side power tube is not turned on during the high and low side output dead time, and the load inductance discharges the VS node for freewheeling. Because the gallium nitride transistor has no parasitic body diode, the reverse conduction voltage drop is large, about 3-5V, so the VS node voltage will drop to a large negative voltage. This makes it more difficult for the high side circuit to respond to the low side input signal, and it may not respond at all.

[0008] 4. In the half-bridge drive circuit, due to the existence of the level shift circuit, there is a difference in transmission delay between the low side channel output signal and the high side channel output signal. Although the delay unit can be added to the low side circuit to match the high and low side channel output delays, the delay of the delay unit in the low side circuit will change due to changes in process-voltage-temperature in the environment, and the delay of the traditional structure of the level shift circuit in the high side circuit will change with VS. Therefore, the traditional gallium nitride half-bridge chip often has the problem of poor delay matching characteristics of the high and low side channel circuits.

[0009] 5. Because the related technology of existing P-type gallium nitride devices is not mature, compared with N-type devices, the carrier mobility of P-type devices is very low and has no practical value. Therefore, existing commercial gallium nitride technology does not provide P-type devices, which makes it impossible to directly apply the mature CMOS circuit structure to the gallium nitride circuit. Using only N-type devices will make the circuit lose the effective pull-up mechanism, causing problems such as increased delay of circuit modules such as latch circuits. SUMMARY

[0010] The present application provides a gallium nitride full integration process based on a high-voltage capacitor level shift circuit, which can effectively improve the problems of traditional gallium nitride level shift circuits, such as large power consumption and poor delay matching, and can also resist the influence of dVS / dt noise and VS negative voltage, ensuring the reliability and stability of the power integrated circuit system.

[0011] In order to achieve the purpose of the application, the technical scheme adopted by the present application is as follows:

[0012] This invention provides a level shifting circuit based on a high-voltage capacitor using gallium nitride fully integrated technology, specifically including a noise-suppressing level conversion unit, a high-speed latch unit, a noise clamping unit, and a reset unit. The noise-suppressing level conversion unit converts the low-side input signal to the high-side output signal; its symmetrical structure effectively suppresses common-mode noise. The noise clamping unit effectively suppresses the impact of dVS / dt noise on the circuit and clamps the voltage of critical nodes to prevent breakdown. The high-speed latch unit quickly restores the input pulse signal to a level signal. The reset unit generates a pulse signal to turn on the switching transistor to help discharge charge at critical nodes. The input signal V... PWM Connect the input port of the noise immunity level conversion unit; the output port node of the noise immunity level conversion unit is V. SET and V RESET Connect the two input ports of the high-speed latch unit respectively; the output port node of the high-speed latch unit is V. HA and V HB Connect the two input ports of the reset unit to the reset unit respectively; connect the three output ports of the reset unit to the V of the noise level conversion unit. OP V OS V ON The node assists in improving the gate pull-down rate of the two gallium nitride transistors in the symmetrical structure of the noise level conversion unit, enhancing the circuit's response to high-frequency input signals; the noise clamping unit is connected to the V of the noise level conversion unit. OP V OS V ON node.

[0013] Furthermore, the noise level conversion unit includes a first enhancement-mode transistor, a second enhancement-mode transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first high-voltage capacitor, a second high-voltage capacitor, a third high-voltage capacitor, a first buffer, a second buffer, a third buffer, and a first inverter;

[0014] The drain of the first enhancement-mode transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the high-side power supply VB. The drain of the second enhancement-mode transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the high-side power supply VB. The sources of the first and second enhancement-mode transistors are connected together and connected to one end of the second high-voltage capacitor. The gate of the first enhancement-mode transistor is connected to one end of the first high-voltage capacitor. The gate of the second enhancement-mode transistor is connected to one end of the third high-voltage capacitor. One end of the third resistor is connected to one end of the first high-voltage capacitor. One end of the fourth resistor is connected to one end of the second high-voltage capacitor. One end of the fifth resistor is connected to one end of the third high-voltage capacitor. The other ends of the third, fourth, and fifth resistors are all connected to the high-side ground VS. The power rails of the first, second, and third buffers and the first inverter are VDD-GND. The input signal V PWMThe input port of the first buffer is connected with the input port of the first inverter, the output port of the first buffer is connected with one end of the first high-voltage capacitor, the input port of the second buffer is connected with the low-side ground GND, the output port of the second buffer is connected with one end of the second high-voltage capacitor, the input port of the third buffer is connected with the output port of the first inverter, and the output port of the third buffer is connected with one end of the third high-voltage capacitor.

[0015] Further, the power supply rail of the high-speed latch unit is VB-VS; the high-speed latch unit comprises a first diode, a second diode, a third diode, a fourth diode, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a third enhancement transistor, a fourth enhancement transistor, a fifth enhancement transistor, a sixth enhancement transistor, a first capacitor, a second capacitor and an output stage fourth buffer.

[0016] The gate of the third enhancement transistor is connected with the anode of the third diode and one end of the first capacitor, the drain of the third enhancement transistor is connected with one end of the sixth resistor, the source of the third enhancement transistor is connected with the other end of the first capacitor, the gate of the fifth enhancement transistor, the drain of the sixth enhancement transistor and one end of the eighth resistor, the gate of the fourth enhancement transistor is connected with the anode of the fourth diode and one end of the second capacitor, the drain of the fourth enhancement transistor is connected with one end of the seventh resistor, the source of the fourth enhancement transistor is connected with the other end of the second capacitor, the drain of the fifth enhancement transistor, the gate of the sixth enhancement transistor, one end of the ninth resistor and the input of the fourth buffer, the anode of the first diode is connected with the cathode of the third diode, the cathode of the first diode is connected with the high-side power supply VB, the anode of the second diode is connected with the cathode of the fourth diode, the cathode of the second diode is connected with the high-side power supply VB, the other ends of the sixth resistor and the seventh resistor are connected with the high-side power supply VB, the sources of the fifth enhancement transistor and the sixth enhancement transistor and the other ends of the eighth resistor and the ninth resistor are connected with the high-side ground VS.

[0017] Further, the power supply rail of the noise clamping unit is VB-VS. The noise clamping unit comprises a seventh enhancement transistor, an eighth enhancement transistor, a ninth enhancement transistor, a fifth diode, a sixth diode and a seventh diode; the drain of the seventh enhancement transistor is connected with the cathode of the fifth diode, the gate of the seventh enhancement transistor is connected with the gate of the ninth enhancement transistor, the gate and the drain of the eighth enhancement transistor, the drain of the eighth enhancement transistor is connected with the cathode of the sixth diode, the drain of the ninth enhancement transistor is connected with the cathode of the seventh diode, the anodes of the fifth diode, the sixth diode and the seventh diode and the sources of the seventh enhancement transistor, the eighth enhancement transistor and the ninth enhancement transistor are commonly connected with the high-side ground VS.

[0018] Further, the power rail of the reset unit is VB-VS, and the reset unit comprises a pulse generation module, a tenth enhancement transistor, an eleventh enhancement transistor, and a twelfth enhancement transistor; an input interface of the pulse generation module is connected to V HA , V HB of the high-speed latch unit, an output port of the pulse generation module outputs a Vctrl signal and is connected to gates of the tenth enhancement transistor, the eleventh enhancement transistor, and the twelfth enhancement transistor, sources of the tenth enhancement transistor, the eleventh enhancement transistor, and the twelfth enhancement transistor are commonly connected to a high-side ground VS, and drains of the tenth enhancement transistor, the eleventh enhancement transistor, and the twelfth enhancement transistor are respectively connected to V OP , V OS , V ON nodes of the anti-noise level conversion unit.

[0019] Further, the power rail of the pulse generation module is VB-VS, and the pulse generation module comprises an OR gate, a first AND gate, a second AND gate, a second inverter, a third inverter, a first delay, and a second delay; an output of the second inverter is connected to an input of the first delay, an output of the first delay and an input of the second inverter are simultaneously connected to two input ports of the first AND gate, an output of the third inverter is connected to an input of the second delay, an output of the second delay and an input of the third inverter are simultaneously connected to two input ports of the second AND gate, outputs of the first AND gate and the second AND gate are connected to two input ports of the OR gate, and an output port of the OR gate outputs the Vctrl signal.

[0020] Further, the first buffer, the second buffer, the third buffer, and the fourth buffer comprise a thirteenth enhancement transistor, a fourteenth enhancement transistor, and a fourth inverter; an input port of the fourth inverter is connected to a gate of the fourteenth enhancement transistor, an output port of the fourth inverter is connected to a gate of the thirteenth enhancement transistor, and a source of the thirteenth enhancement transistor is connected to a drain of the fourteenth enhancement transistor.

[0021] Further, the first buffer, the second buffer, and the third buffer enhance the driving capability of the input signal V PWM , and the fourth buffer in the output stage of the high-speed latch unit raises the high voltage of the signal V HA to the high-side power voltage VB; the resistance values of the first resistor and the second resistor are equal, the resistance values of the third resistor and the fifth resistor are equal, and the resistance value of the fourth resistor is greater than that of the third resistor and the fifth resistor; the capacitance values of the first high-voltage capacitor and the third high-voltage capacitor are equal, and the capacitance value of the second high-voltage capacitor is greater than that of the first high-voltage capacitor and the third high-voltage capacitor; the sizes of the first enhancement transistor and the second enhancement transistor are the same, and the size of the eighth enhancement transistor is smaller than that of the seventh enhancement transistor and the ninth enhancement transistor; and the size of the sixth diode is greater than that of the fifth diode and the seventh diode.

[0022] Further, the enhancement transistor, the resistance, the capacitance and the diode are all devices based on the gallium nitride process.

[0023] Further, the enhancement transistor is any one of an enhancement gallium nitride field effect N-type transistor, an N-enhanced high electron mobility transistor or a metal-oxide-semiconductor field effect transistor; the resistance is any one of a polysilicon resistance, a metal film resistance or a gallium nitride body resistance; the capacitance is any one of a transistor capacitance or a metal-insulator-metal capacitance; and the diode is any one of a Schottky diode or a gallium nitride transistor diode connection.

[0024] The level shift circuit based on the high-voltage capacitance in the gallium nitride full integration process has the following advantages:

[0025] (1) By placing the high-voltage capacitance between the low-side circuit (the circuit taking the low-side power supply VDD-low-side reference ground GND as the power supply rail) and the high-side circuit (the circuit taking the high-side power supply VB-high-side reference ground VS as the power supply rail), the direct current path between VB and GND is avoided when the input signal is transmitted in the level shift circuit, and the effective signal is transmitted to the high-side circuit in the form of current through the rapid change of the voltage of the lower plate of the capacitance. Although the current value between VB and GND is very large at this moment, it only lasts for a very short time, thereby better relieving the severe trade-off relationship between the power consumption and the transmission delay of the level shift circuit. By adding a reset unit, the high-side node voltage V OP , V ON and V OS are pulled down at a specific moment, so that the level shift circuit can respond to higher frequency signals.

[0026] (2) The dVS / dt noise mainly appears in the form of common mode, and the symmetric structure composed of the first enhancement transistor and the second enhancement transistor in the anti-noise level conversion unit and the noise clamping unit are used to eliminate the common mode noise. Since the capacitance value of the second high-voltage capacitance is greater than that of the first high-voltage capacitance and the third high-voltage capacitance, and the resistance value of the fourth resistance is greater than that of the third resistance and the fifth resistance, when VS changes rapidly in the negative direction, the voltage of the V OS node changes more than the V OP and V ON nodes in the same time, so that the first enhancement transistor and the second enhancement transistor remain in the off state, and the noise signal will not continue to be transmitted to the next stage, so that the output signal Vout is not affected by the noise. When VS changes rapidly in the positive direction, the noise clamping unit will clamp V OP , V ON and V OSThe three node voltages are clamped at approximately the same voltage value, and the first and second enhancement transistors also remain in the off state.

[0027] (3) The function and characteristics of the high-voltage capacitor-based level shift circuit of the present application are not sensitive to the voltage value of VS. As shown in Figure 3 , taking the left circuit of the anti-noise level conversion unit as an example, when the input signal V PWM changes rapidly from low to high, at this time, the maximum current output by the first buffer is approximately equal to the low-side power supply voltage VDD divided by the output impedance of the first buffer, and this current value is independent of VS. This current flows through the first high-voltage capacitor, generates a voltage drop on the third resistor, and charges the circuit node on the high side. Therefore, the low-side input signal V PWM is converted to V out by the circuit of the present application. The transmission delay characteristics of the circuit are almost independent of the voltage value of VS. Moreover, due to the bidirectional voltage withstand characteristics of the high-voltage capacitor, the minimum negative VS value that the circuit can tolerate is as low as the reverse withstand voltage value of the high-voltage capacitor, and this voltage value is almost the same as the forward withstand voltage value of the high-voltage capacitor. As shown in Figure 2 , the conventional circuit structure can only tolerate a higher negative VS value, and once the absolute value of the negative VS exceeds the trigger threshold of the RC filter circuit, the circuit cannot work normally.

[0028] (4) The delay of the high-voltage capacitor-based level shift circuit is almost independent of the voltage value of VS. In order to solve the problem of mismatched transmission delays of the high-side and low-side channels, a completely symmetrical circuit structure can be used, so that the high-side and low-side channels change by the same amount due to other factors, to ensure that the delays of the high-side and low-side channels are the same, achieving good delay matching effect. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a typical application diagram of the present application in a half-bridge driving chip and power supply system based on gallium nitride technology;

[0030] Figure 2 is a conventional level shift circuit structure diagram;

[0031] Figure 3 is an example diagram of the present application using a gallium nitride fully integrated process based on a high-voltage capacitor-based level shift circuit;

[0032] Figure 4 is an example diagram of a pulse generation module of the present application;

[0033] Figure 5 is an example diagram of a buffer of the present application;

[0034] Figure 6 is a signal waveform diagram of key nodes of an embodiment of the present application;

[0035] Figure 7 Brief waveform diagram of circuit delay of traditional circuit and circuit of the present application varying with high-side ground VS. DETAILED DESCRIPTION

[0036] The present application will be further described below with reference to the drawings and specific examples, which are presented herein for the purpose of illustration and description and are not intended to limit the scope of the present application.

[0037] Figure 1 Typical application diagram of the present application in a half-bridge driving chip and power system in a gallium nitride process, except that the high-voltage level shift circuit adopts a fully integrated gallium nitride capacitor type level shift circuit proposed by the present application, the rest of the structure is the same as the prior art. The half-bridge driving circuit includes a high-voltage basin region and a low-voltage basin region, wherein the high-side control circuit and the high-side drive are located in the high-voltage basin region; the input logic processing circuit, the low-side control circuit and the low-side drive are located in the low-voltage basin region; the high-voltage level shift circuit is connected between the two basin regions, responsible for signal transmission between the two regions. Gallium nitride power tube M H , M L respectively as the high-side power tube and the low-side power tube of the half-bridge, VBUS is the bus voltage of the half-bridge structure. The reference ground voltage of the low-voltage domain power supply rail is GND, and the power supply voltage is VDD; the floating reference ground voltage of the high-voltage domain power supply rail is VS, and the floating power supply voltage is VB. The voltage difference between VS and VB is usually consistent with the voltage difference between VDD and GND.

[0038] The input signal of the driving chip is V PWM signal, through the input logic processing circuit, two control signals are generated, one is used to control the switch of M L , and the other is used to control the switch of M H . The transmission path of V PWM signal to the gate control signal of M L is called low-side transmission channel; the transmission path of V PWM signal to the gate control signal of M H is called high-side transmission channel. Since M H and M L alternate switching, the voltage value of VS varies between GND and VBUS: during the opening of M L , M H is closed, and the voltage of VS is approximately equal to GND; during the opening of M H , M L is closed, and the voltage of VS is approximately equal to VBUS.

[0039] Since there is a difference between the power supply rail of the high basin region circuit and the power supply rail of the low basin region circuit, a level shift circuit is needed to transmit the control signal from the low basin region to the high basin region. Figure 2The traditional level shift circuit structure diagram comprises a pulse generation module, a level conversion unit, an RC filter unit and an RS latch unit.

[0040] The Pulse1 signal and the Pulse2 signal are connected to the gate of the first high voltage tube 120 and the second high voltage tube 121 of the level conversion unit respectively. When the narrow pulse signal enters the level conversion unit, the corresponding first high voltage tube 120 or the second high voltage tube 121 is turned on, and the drain voltage of the turned-on tube will be pulled low. The eighth diode 127 and the ninth diode 128 are used to prevent the high voltage tube from being broken down due to excessively high voltage. The level conversion unit converts the original low voltage domain signal VDD-GND into a high voltage domain signal VB-VS. The RC filter unit can enhance the ability of the enhancement circuit to resist dVS / dt noise. Finally, the filtered signal is restored and output by the RS latch unit, and the level shift process is completed.

[0041] During signal transmission, the traditional level shift circuit forms a direct current path between the high voltage VB and GND, resulting in a large loss. The traditional level shift circuit uses an RC filter unit to filter dVS / dt noise, which can cause a large transmission delay in the high-side transmission channel. The traditional level shift circuit can only withstand a relatively high VS negative voltage value. Once the absolute value of the negative VS exceeds the trigger threshold of the RC filter circuit, the circuit cannot work normally. There is a difference in transmission delay between the output signal of the low-side channel and the output signal of the high-side channel. Although a delay unit can be added to the low-side circuit to make the output delays of the high-side and low-side channels approximately equal, the delay of the delay unit in the low-side circuit will change due to changes in process-voltage-temperature in the environment, while the delay of the high-side circuit will change with VS. Therefore, the traditional gallium nitride half-bridge chip often has poor high-side and low-side channel circuit delay matching characteristics.

[0042] Figure 3 The specific structure diagram of the level shift circuit based on a high-voltage capacitor using a gallium nitride full integration process proposed by the present application retains the level conversion unit with similar functions in the traditional level shift circuit, and adds a high-speed latch unit, a noise clamping unit and a reset unit.

[0043] The anti-noise level conversion unit comprises a first enhancement transistor 100, a second enhancement transistor 101, a first resistor 102, a second resistor 103, a third resistor 104, a fourth resistor 105, a fifth resistor 106, a first high-voltage capacitor 107, a second high-voltage capacitor 108, a third high-voltage capacitor 109, a first buffer 110, a second buffer 111, a third buffer 112 and a first inverter 113; the drain of the first enhancement transistor 100 is connected to one end of the first resistor 102, the other end of the first resistor 102 is connected to a high-side power supply VB, the drain of the second enhancement transistor 101 is connected to one end of the second resistor 103, the other end of the second resistor 103 is connected to the high-side power supply VB, the sources of the first enhancement transistor 100 and the second enhancement transistor 101 are connected and connected to one end of the second high-voltage capacitor 108, the gate of the first enhancement transistor 100 is connected to one end of the first high-voltage capacitor 107, the gate of the second enhancement transistor 101 is connected to one end of the third high-voltage capacitor 109, one end of the third resistor 104 is connected to one end of the first high-voltage capacitor 107, one end of the fourth resistor 105 is connected to one end of the second high-voltage capacitor 108, one end of the fifth resistor 106 is connected to one end of the third high-voltage capacitor 109, and the other ends of the third resistor 104, the fourth resistor 105 and the fifth resistor 106 are commonly connected to a high-side ground VS; the power supply rails of the first buffer 110, the second buffer 111, the third buffer 112 and the first inverter 113 are VDD-GND; an input signal V PWM The input port of the first buffer 110 is connected to the input port of the first inverter 113, one end of the first high-voltage capacitor 107 is connected to the output port of the first buffer 110, the input port of the second buffer 111 is connected to a low-side ground GND, one end of the second high-voltage capacitor 108 is connected to the output port of the second buffer 111, the input port of the third buffer 112 is connected to the output port of the first inverter 113, and one end of the third high-voltage capacitor 109 is connected to the output port of the third buffer 112.

[0044] The high-speed latch unit comprises a first diode 200, a second diode 201, a third diode 202, a fourth diode 203, a sixth resistor 204, a seventh resistor 205, an eighth resistor 212, a ninth resistor 213, a third enhancement transistor 206, a fourth enhancement transistor 207, a fifth enhancement transistor 210, a sixth enhancement transistor 211, a first capacitor 208, a second capacitor 209, and an output stage fourth buffer 214; the gate of the third enhancement transistor 206 is connected to the anode of the third diode 202 and one end of the first capacitor 208, the drain of the third enhancement transistor 206 is connected to one end of the sixth resistor 204, the source of the third enhancement transistor 206 is connected to the other end of the first capacitor 208, the gate of the fifth enhancement transistor 210, the drain of the sixth enhancement transistor 211, and one end of the eighth resistor 212, the gate of the fourth enhancement transistor 207 is connected to the anode of the fourth diode 203 and one end of the second capacitor 209, the drain of the fourth enhancement transistor 207 is connected to one end of the seventh resistor 205, the source of the fourth enhancement transistor 207 is connected to the other end of the second capacitor 209, the drain of the fifth enhancement transistor 210, the gate of the sixth enhancement transistor 211, one end of the ninth resistor 213, and the input end of the fourth buffer 214, the anode of the first diode 200 is connected to the cathode of the third diode 202, the cathode of the first diode 200 is connected to a high-side power supply VB, the anode of the second diode 201 is connected to the cathode of the fourth diode 203, the cathode of the second diode 201 is connected to the high-side power supply VB, the other ends of the sixth resistor 204 and the seventh resistor 205 are connected to the high-side power supply VB, and the sources of the fifth enhancement transistor 210 and the sixth enhancement transistor 211 and the other ends of the eighth resistor 212 and the ninth resistor 213 are connected to a high-side ground VS.

[0045] The noise clamping unit comprises a seventh enhancement transistor 300, an eighth enhancement transistor 301, a ninth enhancement transistor 302, a fifth diode 303, a sixth diode 304, and a seventh diode 305; the drain of the seventh enhancement transistor 300 is connected to the cathode of the fifth diode 303, the gate of the seventh enhancement transistor 300 is connected to the gate of the ninth enhancement transistor 302, the gate and the drain of the eighth enhancement transistor 301, the drain of the eighth enhancement transistor 301 is connected to the cathode of the sixth diode 304, the drain of the ninth enhancement transistor 302 is connected to the cathode of the seventh diode 305, the anodes of the fifth diode 303, the sixth diode 304, and the seventh diode 305 and the sources of the seventh enhancement transistor 300, the eighth enhancement transistor 301, and the ninth enhancement transistor 302 are commonly connected to the high-side ground VS.

[0046] The reset unit comprises a pulse generation module, a tenth enhancement transistor 407, an eleventh enhancement transistor 408 and a twelfth enhancement transistor 409; an input interface of the pulse generation module is connected to the V HA , HB node of the high-speed latching unit, an output port of the pulse generation module outputs a Vctrl signal and is connected to the gates of the tenth enhancement transistor 407, the eleventh enhancement transistor 408 and the twelfth enhancement transistor 409, the sources of the tenth enhancement transistor 407, the eleventh enhancement transistor 408 and the twelfth enhancement transistor 409 are commonly connected to the high-side ground VS, and the drains of the tenth enhancement transistor 407, the eleventh enhancement transistor 408 and the twelfth enhancement transistor 409 are respectively connected to the V OP , OS , ON nodes of the anti-noise level conversion unit. The pulse generation module comprises an OR gate 400, a first AND gate 401, a second AND gate 402, a second inverter 405, a third inverter 406, a first delay timer 403 and a second delay timer 404; the output of the second inverter 405 is connected to the input of the first delay timer 403, the output of the first delay timer 403 and the input of the second inverter 405 are simultaneously connected to the two input ports of the first AND gate 401, the output of the third inverter 406 is connected to the input of the second delay timer 404, the output of the second delay timer 404 and the input of the third inverter 406 are simultaneously connected to the two input ports of the second AND gate 402, the outputs of the first AND gate 401 and the second AND gate 402 are connected to the two input ports of the OR gate 400, and the output port of the OR gate 400 outputs the Vctrl signal.

[0047] As shown in Figure 3 , Figure 4 and Figure 5 , assuming that the initial state of the input signal V PWM is low, the output signal V IP of the first buffer 110 is low, and V IN is high. The upper plate voltage V OP of the first high-voltage capacitor 107 is equal to the high-side ground voltage VS due to the pull-down action of the third resistor 104; the upper plate voltage V ON of the third high-voltage capacitor 109 is equal to the high-side ground voltage VS due to the pull-down action of the fifth resistor 106; and the upper plate voltage V OS of the fourth high-voltage capacitor 108 is equal to the high-side ground voltage VS due to the pull-down action of the fourth resistor 105. The first enhancement transistor 100 and the second enhancement transistor 101 remain in the closed state, and the enhancement transistor drain voltages V SET and V RESET remain high due to the pull-up action of the first resistor 102 and the second resistor 103.

[0048] When the input signal VPWM When the output voltage V IP of the first buffer 110 changes from low to high, the output current of the first buffer 110 flows through the third resistor 104 and the first high voltage capacitor 107, so that the upper plate voltage of the first high voltage capacitor 107 rises rapidly relative to the high-side ground VS in a short time, i.e., the gate voltage V OP of the first enhancement transistor 100 rises rapidly. IP When the output voltage V OP of the first buffer 110 changes from low to high, the output current of the first buffer 110 flows through the third resistor 104 and the first high voltage capacitor 107, so that the upper plate voltage of the first high voltage capacitor 107 rises rapidly relative to the high-side ground VS in a short time, i.e., the gate voltage V IS of the first enhancement transistor 100 rises rapidly. OS When the output voltage V OP of the first buffer 110 changes from low to high, the output current of the first buffer 110 flows through the third resistor 104 and the first high voltage capacitor 107, so that the upper plate voltage of the first high voltage capacitor 107 rises rapidly relative to the high-side ground VS in a short time, i.e., the gate voltage V SET of the first enhancement transistor 100 rises rapidly.

[0049] Due to the action of the first inverter 113, the V IN signal is inverted relative to the V IP signal, i.e., when the V IP signal changes from low to high, the V IN signal changes from high to low. Similarly, the output current of the third buffer 112 flows through the fifth resistor 106 and the third high voltage capacitor 109, and since the current direction is from the upper plate to the lower plate of the third high voltage capacitor 109, this makes the upper plate voltage of the third high voltage capacitor 109 drop rapidly relative to the high-side ground VS in a short time, i.e., the gate voltage V ON of the second enhancement transistor 101 drops rapidly. IN When the output voltage V OS of the third buffer 112 changes from high to low, the output current of the third buffer 112 flows through the fifth resistor 106 and the third high voltage capacitor 109, so that the upper plate voltage of the third high voltage capacitor 109 drops rapidly relative to the high-side ground VS in a short time, i.e., the gate voltage V RESET of the second enhancement transistor 101 drops rapidly.

[0050] During the conduction of the first enhancement transistor 100, the high-side power supply VB charges the source voltage V OS of the first enhancement transistor 100 through the first resistor 102 and the first enhancement transistor 100, but since the second high voltage capacitor 108 and the first resistor 102 have large values, and the first enhancement transistor 100 is turned on for a short time, the source voltage V OSIt will only rise slightly, which can be considered as V SET It remains at a low level during the conduction of the first enhancement transistor 100.

[0051] Assume the initial state input signal V PWM It is at a low level, and the previous state has been latched by the high-speed latch unit, i.e., V. HB High level, V HA When the input signal V is low, the fifth enhancement-mode transistor 210 is turned on, and the sixth enhancement-mode transistor 211 is turned off. PWM When V changes from low to high level SET Lowered, V RESET The gate voltage remains high, and the third enhancement-mode transistor 206 is turned off due to the decrease in gate voltage. Under the influence of the pull-down current of the eighth resistor 212 and the coupling current of the first capacitor 208, V... HB The voltage will decrease, eventually turning off the fifth enhancement-mode transistor 210; while the pull-up current provided by the seventh resistor 205 and the fourth enhancement-mode transistor 207 will cause V to decrease. HA It will rise, eventually turning on the sixth enhancement transistor 211, changing and latching the output state of Vout.

[0052] For the initial state input signal V PWM The condition for a high level is when the input signal V PWM When transitioning from a high level to a low level, due to the high symmetry of the circuit structure, its operation is similar to that of V. PWM The situation is similar when transitioning from a low level to a high level.

[0053] In order to obtain a higher voltage value and a longer duration during operation, V OP V ON and V OS In design, resistors with relatively large resistance values, such as the third resistor 104, the fourth resistor 105, and the fifth resistor 106, are often selected. This can lead to issues with V... IP and V IN After the change stops, V OP V ON and V OS It takes a considerable amount of time to return to the initial state equal to VS. When the circuit operates at higher frequencies, it may experience issues due to V... OP V ON and V OS Failure to promptly restore to the initial state led to logic instability. Therefore, a reset unit is required when the circuit operates at high frequencies. The pulse generation module in the reset unit reads V... HB and V HA The change when V HB and V HAAny one rising edge appears, a short pulse signal will be output, the pulse signal will control the tenth enhancement transistor 407, the eleventh enhancement transistor 408, the twelfth enhancement transistor 409 to open, the voltage V OP 、 ON and V OS is quickly pulled down to VS.

[0054] During the half-bridge system operation, since the high-side circuit reference ground is connected with the half-bridge circuit switching node, the high-side reference ground signal VS will appear a fast voltage change, which can be positive or negative. During the VS change, even if the voltage V IP 、V IN and V IS does not change, the voltage change across the high-voltage capacitor will also generate a displacement current, and a voltage drop will be generated on the third resistor 104, the fourth resistor 105 and the fifth resistor 106, which can cause the common capacitor type level shift circuit to be triggered incorrectly. Figure 2 The same is true for the traditional circuit shown, the first high-voltage tube 120 and the second high-voltage tube 121 in the off state have a large parasitic capacitance, which will cause a voltage drop on the tenth resistor 125 and the eleventh resistor 126 due to the displacement current, causing the latch unit to enter an indeterminate state.

[0055] For the circuit of the present application, when VS rapidly decreases in a short time, a displacement current will be generated on the first high-voltage capacitor 107, the second high-voltage capacitor 108 and the third high-voltage capacitor 109, the direction of which is from the lower plate to the upper plate. The displacement current generates a voltage drop on the third resistor 104, the fourth resistor 105 and the fifth resistor 106, which will cause the gate voltage V OP 、V ON and the source voltage V OS of the first enhancement transistor 100 and the second enhancement transistor 101 to rise. By setting the isolation capacitor value, the size of the enhancement transistor and the resistance value of the resistor, the second high-voltage capacitor 108 has a larger capacitance than the first high-voltage capacitor 107 and the third high-voltage capacitor 109, the eighth enhancement transistor 301 has a smaller size than the seventh enhancement transistor 300 and the ninth enhancement transistor 302, and the fourth resistor 105 has a larger resistance value than the third resistor 104 and the fifth resistor 106. Thus, the source voltage V OS of the first enhancement transistor 100 and the second enhancement transistor 101 is higher than the gate voltage V OP and V ONThe more the voltage rises in the same time, the gate-source voltage of the first and second enhancement transistors 100 and 101 remains below the threshold voltage Vth of the tube, and the first and second enhancement transistors 100 and 101 will not be turned on. The design of the present application can ensure that the first and second enhancement transistors 100 and 101 remain in the off state, and prevent the false triggering caused by the inconsistent changes of V OP and V ON In addition, in order to prevent the voltage V OP , V ON and V OS from rising unlimitedly and causing the device to break down, the noise clamping unit will be turned on when V OS is too high, clamping V OS voltage, and limiting the rise of V OP and V ON voltage by turning on the seventh and ninth enhancement transistors 300 and 302.

[0056] For the circuit of the present application, when VS rises rapidly in a short time, displacement current will be generated on the first, second and third high-voltage capacitors 107, 108 and 109, flowing from the upper plate to the lower plate. The displacement current generates a voltage drop on the third, fourth and fifth resistors 104, 105 and 106, which will cause the gate voltage V OP , V ON and the source voltage V OS of the first and second enhancement transistors 100 and 101 to drop.

[0057] When the high-voltage domain ground signal VS rises instantaneously, the gate voltage of the first and second enhancement transistors 100 and 101 drops relative to the high-voltage domain ground signal, and the fifth, sixth and seventh diodes 303, 304 and 305 are forward-biased, clamping the voltages of the three nodes V OP , V ON and V OS at approximately the same voltage value, preventing transistor breakdown and ensuring that the first and second enhancement transistors 100 and 101 remain off. By setting the size of the sixth diode 304 to be larger than that of the fifth and seventh diodes 303 and 305, it is ensured that even if the second high-voltage capacitor 108 has a larger capacitance and the displacement current is larger, the voltage of V OS can still be maintained at a level comparable to V OP , V ON .

[0058] Figure 6 A working waveform diagram of a level shift circuit based on high-voltage capacitors using a gallium nitride full integration process is proposed for the present application, when the input signal V PWMV IN falls, V IP rises. V OP rises, while V ON falls, but is clamped by the seventh diode 305 to be close to the voltage value of VS. After the first enhancement transistor 100 is turned on, V OS rises slightly, V SET node voltage falls, so that the third enhancement transistor 206 is turned off. V HB falls, but due to the bootstrap effect of the first capacitor 208, V HB falls faster. When the fifth enhancement transistor 210 is turned off due to the falling of V HB , V HA point voltage starts to rise, and due to the bootstrap effect of the second capacitor 209, the gate voltage of the fourth enhancement transistor 207 also rises, which makes the on-resistance of the fourth enhancement transistor 207 not decrease due to the rising of V HA , so V HA rises faster. The second diode 201 and the fourth diode 203 are used to prevent the gate voltage of the enhancement transistor 207 from being too high due to the bootstrap effect of the capacitor 209, which causes the device to break down; the first diode 200 and the third diode 202 are used to prevent the gate voltage of the third enhancement transistor 206 from being too high due to the bootstrap effect of the first capacitor 208, which causes the device to break down; if the device withstand voltage is sufficient, these diodes can be removed.

[0059] V HA and V HB signals enter the reset unit to generate Vctrl signals, so that the tenth enhancement transistor 407, the eleventh enhancement transistor 408, and the twelfth enhancement transistor 409 are turned on to assist in pulling down the potentials of V OP , V ON , and V OS points. As Figure 4 shown, when there is a Vctrl signal, V OP , V ON , and V OS in the falling process will be faster, so that the circuit can respond to higher frequency input signals.

[0060] Figure 7 A brief diagram of the relationship between the circuit delay of the conventional level shift circuit and the level shift circuit of the present application and the voltage value of VS. When VS is low, the first high-voltage tube 120 and the second high-voltage tube 121 of the conventional level shift circuit enter the linear region, and the generated pull-down current decreases, so the circuit delay is high when VS is low. The delay of the level shift circuit of the present application is based on high-voltage capacitors, and the delay of the level shift circuit is largely independent of the voltage value of VS, and the delay is hardly affected by the change of VS.

[0061] The above-mentioned enhancement-mode transistor, resistor, capacitor and diode are all devices based on gallium nitride technology. The above-mentioned enhancement-mode transistor is an enhancement-mode gallium nitride field effect N-type transistor, which can be an N-enhanced high electron mobility transistor or a metal-oxide-semiconductor field effect transistor; the resistor can be a polysilicon resistor, a metal film resistor, a gallium nitride bulk resistor; the capacitor can be a transistor capacitor, a metal-insulator-metal capacitor; the diode can be a Schottky diode or a gallium nitride transistor diode connection.

Claims

1. A level shift circuit based on high-voltage capacitor using gallium nitride full integration process, comprising noise immunity level conversion unit, noise clamping unit, high-speed latch unit, reset unit; the noise immunity level conversion unit realizes the conversion of low-side input signal to high-side output signal, and its symmetrical structure can suppress common-mode noise; the noise clamping unit suppresses the influence of dVS / dt noise on the circuit and clamps the voltage of the key node to prevent breakdown; the high-speed latch unit quickly restores the input pulse signal to a level signal; the reset unit generates a pulse signal to open the switch tube and help the key node to discharge charge; the input signal V PWM connects the input port of the noise immunity level conversion unit; the output port node of the noise immunity level conversion unit is V SET and V RESET respectively connect the two input ports of the high-speed latch unit; the output port node of the high-speed latch unit is V HA and V HB respectively connect the two input ports of the reset unit; the three output ports of the reset unit connect the V OP , V OS , V ON nodes of the noise immunity level conversion unit, which helps to improve the gate pull-down rate of the two gallium nitride transistors in the symmetrical structure of the noise immunity level conversion unit and enhance the response of the circuit to high-frequency input signals; the noise clamping unit connects the V OP , V OS , V ON nodes of the noise immunity level conversion unit; The anti-noise level conversion unit comprises a first enhancement transistor (100), a second enhancement transistor (101), a first resistor (102), a second resistor (103), a third resistor (104), a fourth resistor (105), a fifth resistor (106), a first high-voltage capacitor (107), a second high-voltage capacitor (108), a third high-voltage capacitor (109), a first buffer (110), a second buffer (111), a third buffer (112) and a first inverter (113); The drain of the first enhancement transistor (100) is connected to one end of the first resistor (102), the other end of the first resistor (102) is connected to the high-side power supply VB, the drain of the second enhancement transistor (101) is connected to one end of the second resistor (103), the other end of the second resistor (103) is connected to the high-side power supply VB, the source of the first enhancement transistor (100) and the source of the second enhancement transistor (101) are connected and connected to one end of the second high-voltage capacitor (108), the gate of the first enhancement transistor (100) is connected to one end of the first high-voltage capacitor (107), the gate of the second enhancement transistor (101) is connected to one end of the third high-voltage capacitor (109), one end of the third resistor (104) is connected to one end of the first high-voltage capacitor (107), one end of the fourth resistor (105) is connected to one end of the second high-voltage capacitor (108), one end of the fifth resistor (106) is connected to one end of the third high-voltage capacitor (109), and the other ends of the third resistor (104), the fourth resistor (105) and the fifth resistor (106) are commonly connected to the high-side ground VS; the power supply rail of the first buffer (110), the second buffer (111), the third buffer (112) and the first inverter (113) is VDD-GND; the input signal V PWM The input port of the first buffer (110) is connected to the input port of the first inverter (113), one end of the first high-voltage capacitor (107) is connected to the output port of the first buffer (110), the input port of the second buffer (111) is connected to the low-side ground GND, one end of the second high-voltage capacitor (108) is connected to the output port of the second buffer (111), the input port of the third buffer (112) is connected to the output port of the first inverter (113), and one end of the third high-voltage capacitor (109) is connected to the output port of the third buffer (112). The power supply rail of the high-speed latch unit is VB-VS; the high-speed latch unit comprises a first diode (200), a second diode (201), a third diode (202), a fourth diode (203), a sixth resistor (204), a seventh resistor (205), an eighth resistor (212), a ninth resistor (213), a third enhancement transistor (206), a fourth enhancement transistor (207), a fifth enhancement transistor (210), a sixth enhancement transistor (211), a first capacitor (208), a second capacitor (209) and an output stage fourth buffer (214); The gate of the third enhancement transistor (206) is connected with the anode of the third diode (202) and one end of the first capacitor (208), the drain of the third enhancement transistor (206) is connected with one end of the sixth resistor (204), the source of the third enhancement transistor (206) is connected with the other end of the first capacitor (208), the gate of the fifth enhancement transistor (210), the drain of the sixth enhancement transistor (211) and one end of the eighth resistor (212), the gate of the fourth enhancement transistor (207) is connected with the anode of the fourth diode (203) and one end of the second capacitor (209), the drain of the fourth enhancement transistor (207) is connected with one end of the seventh resistor (205), the source of the fourth enhancement transistor (207) is connected with the other end of the second capacitor (209), the drain of the fifth enhancement transistor (210), the gate of the sixth enhancement transistor (211), one end of the ninth resistor (213) and the input end of the fourth buffer (214), the anode of the first diode (200) is connected with the cathode of the third diode (202), the cathode of the first diode (200) is connected with the high-side power supply VB, the anode of the second diode (201) is connected with the cathode of the fourth diode (203), the cathode of the second diode (201) is connected with the high-side power supply VB, the other ends of the sixth resistor (204) and the seventh resistor (205) are connected with the high-side power supply VB, the sources of the fifth enhancement transistor (210) and the sixth enhancement transistor (211) and the other ends of the eighth resistor (212) and the ninth resistor (213) are connected with the high-side ground VS. The power supply rail of the noise clamping unit is VB-VS, and the noise clamping unit comprises a seventh enhancement transistor (300), an eighth enhancement transistor (301), a ninth enhancement transistor (302), a fifth diode (303), a sixth diode (304) and a seventh diode (305); the drain of the seventh enhancement transistor (300) is connected to the cathode of the fifth diode (303), the gate of the seventh enhancement transistor (300) is connected to the gate and the drain of the eighth enhancement transistor (301) and the gate of the ninth enhancement transistor (302), the drain of the eighth enhancement transistor (301) is connected to the cathode of the sixth diode (304), the drain of the ninth enhancement transistor (302) is connected to the cathode of the seventh diode (305), and the anodes of the fifth diode (303), the sixth diode (304) and the seventh diode (305) and the sources of the seventh enhancement transistor (300), the eighth enhancement transistor (301) and the ninth enhancement transistor (302) are connected to the high-side ground VS. The power supply rail of the reset unit is VB-VS, comprising a pulse generation module, a tenth enhancement transistor (407), an eleventh enhancement transistor (408) and a twelfth enhancement transistor (409); the input interface of the pulse generation module is connected with the V HA , V HB node of the high-speed latch unit, the output port of the pulse generation module outputs a Vctrl signal and is connected with the gates of the tenth enhancement transistor (407), the eleventh enhancement transistor (408) and the twelfth enhancement transistor (409), the sources of the tenth enhancement transistor (407), the eleventh enhancement transistor (408) and the twelfth enhancement transistor (409) are commonly connected with the high-side ground VS, and the drains of the tenth enhancement transistor (407), the eleventh enhancement transistor (408) and the twelfth enhancement transistor (409) are respectively connected with the V OP , V OS , V ON nodes of the anti-noise level conversion unit.

2. The high-voltage capacitor-based level shifter circuit based on a gallium nitride fully integrated process according to claim 1, wherein, The power supply rail of the pulse generation module is VB-VS, and the pulse generation module comprises an OR gate (400), a first AND gate (401), a second AND gate (402), a second inverter (405), a third inverter (406), a first delay (403) and a second delay (404); the output of the second inverter (405) is connected to the input of the first delay (403), the output of the first delay (403) and the input of the second inverter (405) are simultaneously connected to two input ports of the first AND gate (401), the output of the third inverter (406) is connected to the input of the second delay (404), the output of the second delay (404) and the input of the third inverter (406) are simultaneously connected to two input ports of the second AND gate (402), and the outputs of the first AND gate (401) and the second AND gate (402) are connected to two input ports of the OR gate (400), and the output port of the OR gate (400) outputs a Vctrl signal.

3. The high-voltage capacitor-based level shifter circuit based on a gallium nitride fully integrated process according to claim 2, wherein, The first buffer (110), the second buffer (111), the third buffer (112) and the fourth buffer (214) comprise a thirteenth enhancement transistor (115), a fourteenth enhancement transistor (116) and a fourth inverter (114); the input port of the fourth inverter (114) is connected to the gate of the fourteenth enhancement transistor (116), the output port of the fourth inverter (114) is connected to the gate of the thirteenth enhancement transistor (115), and the source of the thirteenth enhancement transistor (115) is connected to the drain of the fourteenth enhancement transistor (116).

4. The high-voltage capacitor-based level shifter circuit based on a gallium nitride fully integrated process according to claim 3, wherein, The first buffer (110), the second buffer (111) and the third buffer (112) enhance the driving ability of the input signal V PWM The output stage fourth buffer (214) in the high-speed latch unit raises the high level voltage of the signal V HA to the high side power supply voltage VB; the resistance values of the first resistor (102) and the second resistor (103) are equal, the resistance values of the third resistor (104) and the fifth resistor (106) are equal, and the resistance value of the fourth resistor (105) is greater than that of the third resistor (104) and the fifth resistor (106); the capacitance values of the first high voltage capacitor (107) and the third high voltage capacitor (109) are equal, and the capacitance value of the second high voltage capacitor (108) is greater than that of the first high voltage capacitor (107) and the third high voltage capacitor (109); the sizes of the first enhancement transistor (100) and the second enhancement transistor (101) are the same, the size of the eighth enhancement transistor (301) is smaller than that of the seventh enhancement transistor (300) and the ninth enhancement transistor (302); and the size of the sixth diode (304) is greater than that of the fifth diode (303) and the seventh diode (305).

5. The high-voltage capacitor-based level shifter circuit based on a gallium nitride fully integrated process according to claim 4, wherein, The enhancement transistor, the resistance, the capacitor and the diode are all devices based on a gallium nitride process.

6. The high-voltage capacitor-based level shifter circuit based on a gallium nitride fully integrated process according to claim 5, wherein, The enhancement transistor is an enhancement-type gallium nitride field effect N-type transistor, and is any one of an N enhancement-type high electron mobility transistor and a metal-oxide-semiconductor field effect transistor; the resistance is any one of a polysilicon resistance, a metal film resistance and a gallium nitride body resistance; the capacitor is any one of a transistor capacitor and a metal-insulator-metal capacitor; and the diode is any one of a Schottky diode and a gallium nitride transistor diode connection.

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