Low power capacitance-to-digital converter based on sar logic and coarse-fine binary counter

Abstract

The application relates to a low-power consumption capacitor-digital converter based on SAR logic and a coarse-fine binary counter, and relates to a low-power consumption capacitor-digital converter.The application is used to solve the problem that a micro-capacitance measurement circuit cannot meet the requirements of a large dynamic range, low noise and good anti-stray property.The application comprises an ultra-low-power consumption relaxation oscillator, an asynchronous tracking algorithm circuit, a coarse-fine binary counter, a bootstrap switch circuit and a full-differential SAR logic capacitor-digital converter; the ultra-low-power consumption relaxation oscillator is used to generate a clock signal Scan, the clock signal Scan is an input signal of the asynchronous tracking algorithm circuit, the coarse-fine binary counter and the bootstrap switch circuit; the asynchronous tracking algorithm circuit is used to generate a clock signal Valid, the clock signal Valid is a clock signal of the coarse-fine binary counter; the coarse-fine binary counter is used to generate a control signal of the full-differential SAR logic capacitor-digital converter and control a switch timing sequence.The application belongs to the technical field of analog-digital conversion and capacitor sensor interface circuit.

Description

TECHNICAL FIELD

[0001] The application relates to a low-power capacitor digital converter, and belongs to the technical field of analog-to-digital conversion and capacitor sensor interface circuit. BACKGROUND

[0002] The use of capacitive characteristics to detect physical quantities is widely used in industrial process control, measurement and instrument systems. Although the application type puts forward different performance requirements for the sensor interface circuit, people have been committed to improving the energy efficiency of the interface circuit, and the CDC proposed in this paper is applied to the unattended ZC sensing system. The frequency of the sound sensor is 200-2 kHz and the frequency of the vibration sensor is 50 Hz, which can be equivalent to a variable capacitor. The capacitance value of the capacitor changes with the frequency of the detected signal, and the CDC can measure the capacitance value of the sensor. The frequency value of the sensor can be further obtained through the output. Finally, the digital code stream is output and wirelessly transmitted to the host computer.

[0003] Since the capacitive sensor does not consume static power consumption, the power consumption of the capacitive sensing system will be limited by the readout circuit, which is usually a capacitor digital converter (CDC). For use in a watchdog circuit, an ultra-low-power readout circuit is required. In the nW-level wireless sensing nodes applied to biological implantable telemetry, intelligent medical treatment, panel control and environmental monitoring, an ultra-low-power readout circuit is required to achieve high functionality for the system, especially for wearable devices and handheld applications. Currently, this design application still has challenges.

[0004] Due to the better user interface and excellent signal processing capability of the digital system compared with the analog system, the latest trend of the capacitive sensing interface circuit is to directly digitize the sensor capacitance instead of converting the capacitance into a voltage and then digitizing the output voltage. Direct digitization has lower complexity, smaller area and lower power consumption; in the "semi-digital" method, the capacitor can be used to modulate the period or pulse width of a digital signal; however, this method requires a time-to-digital converter to provide a digital output code, such as a fast digital counter and a stable high-frequency oscillator, which hinders its use in low-power applications.

[0005] A more attractive method for capacitor digital conversion (CDC) is to use a delta-sigma modulator; however, the oversampling and digital decimation filtering required by the delta-sigma architecture will bring huge power consumption; in addition, the capacitance range of the delta-sigma interface is limited, and it cannot avoid modulator overload; in order to increase the capacitance range of the delta-sigma interface circuit, someone has proposed a successive approximation register (SAR) algorithm to adjust the modulator reference capacitor; however, the SAR step is only used for initial coarse calibration, and the sensor digitization is still performed using the delta-sigma modulator.

[0006] The capacitor-to-digital converter (CDC) architecture, which relies entirely on the SAR algorithm, eliminates the need for oversampling, thereby effectively reducing power consumption and relaxing the requirements for the analog block. Furthermore, the digital output code can be provided directly without digital filtering, further reducing power consumption. Successive approximation register (SAR) analog-to-digital converters (ADCs) are considered ideal architectures for biomedical signal processing systems due to their small area and low power consumption. However, with technological advancements and lower power supply voltages, extending these advantages to high-resolution designs is challenging due to the excessive power dissipation of capacitor-to-analog converters (CDACs), attracting significant attention from industry and academia.

[0007] Furthermore, the capacitance-to-digital converter must be stable against external interference to limit power consumption detection errors. The capacitance change of micro-capacitance sensors is often very small, making the influence of cable stray capacitance very significant. Moreover, stray capacitance varies with many factors such as temperature, structure, location, internal and external electric field distribution, and device selection, and the measured capacitance varies over a large range. Therefore, micro-capacitance measurement circuits must meet requirements such as large dynamic range, low noise, and good stray capacitance resistance. Summary of the Invention

[0008] To address the problem that micro-capacitance measurement circuits cannot meet the requirements of large dynamic range, low noise, and good anti-spurious properties, this invention proposes a low-power capacitance digital converter based on SAR logic and coarse-fine binary counters.

[0009] The technical solution adopted by the present invention to solve the above problems is as follows: The present invention includes an ultra-low power relaxation oscillator, an asynchronous tracking algorithm circuit, a coarse and fine binary counter, a bootstrap switching circuit, and a fully differential SAR logic capacitor digital-to-analog converter.

[0010] An ultra-low power relaxation oscillator is used to generate a clock signal Scan, which is the input signal for the asynchronous tracking algorithm circuit, the coarse-fine binary counter, and the bootstrap switch circuit.

[0011] The asynchronous tracking algorithm circuit is used to generate the clock signal Valid, which is the clock signal of the coarse-fine binary counter;

[0012] The coarse-fine binary counter is used to generate control signals for the fully differential SAR logic capacitor digital-to-analog converter and to control the switching timing.

[0013] Furthermore, the ultra-low power relaxation oscillator includes a nanoampere-level reference generation circuit, a low-power comparator, a T flip-flop, and a trimming circuit.

[0014] One end of the low-power comparator is connected to the charging capacitor C INT The other end of the low-power comparator is connected to V. REF connect;

[0015] The current I of the nanoampere bandgap reference generation circuit REF For charging capacitor C INT Charging, in the charging capacitor C INT The upward slope is generated as follows voltage V INT When V INT >V REF At that time, the comparator periodically resets V. INT ;

[0016] The Scan clock signal period is

[0017] The low-power comparator employs a low-power comparator structure consisting of a two-stage open-loop operational amplifier cascaded with an inverter and a latch, using high-threshold devices. REF This indicates the reference voltage output by the nanoampere-level reference generation circuit.

[0018] Furthermore, the nanoampere reference generation circuit uses self-cascaded NMOS transistors instead of resistors.

[0019] Furthermore, the asynchronous tracking algorithm circuit includes a low-noise dynamic comparator, a self-oscillating loop, and reset logic.

[0020] Furthermore, the coarse-fine binary counter uses a combination of a 4-bit coarse CDAC and an 8-bit fine CDAC to optimize the switching timing.

[0021] Furthermore, the bootstrap switching circuit is a 10-transistor structure.

[0022] Furthermore, the fully differential SAR logic capacitor digital-to-analog converter includes a 12-bit fully differential capacitor array, a charge injection cancellation switch, a reset switch, and a pull-up switch.

[0023] The beneficial effects of this invention are:

[0024] Compared to other capacitance-to-digital converters, the 12-bit SAR algorithm proposed in this invention uses a coarse-fine capacitor array to perform in the capacitance domain, thereby enabling the digitization of a large range of capacitances within a compact area. This achieves high-precision measurement while effectively reducing circuit power consumption, with the lowest power consumption reaching the nW level.

[0025] This invention employs an asynchronous tracking algorithm, which periodically triggers the CDC through an ultra-low power relaxation oscillator to achieve power consumption in sync with the switching frequency;

[0026] This invention employs a differential architecture and intrinsic CDS sampling, which is insensitive to charge injection and offset voltage, and is resistant to noise coupling;

[0027] Compared with traditional capacitance detection circuits, this invention uses a coarse-fine binary counter to effectively reduce system power consumption to the nW level. The power consumption depends on the frequency of capacitance digitization in the application scenario, and can be ignored when there are no capacitance switching events. Secondly, the circuit has strong anti-interference ability against common-mode noise and external interference caused by capacitance detection. Finally, it has high measurement accuracy, with a resolution of up to 12 bits. Attached Figure Description

[0028] Figure 1 This is the overall logic block diagram of the capacitor-to-digital converter;

[0029] Figure 2 This is a schematic diagram of an ultra-low power relaxation oscillator;

[0030] Figure 3 This is a schematic diagram of a low-power comparator in an ultra-low-power relaxation oscillator;

[0031] Figure 4 This is a schematic diagram of an asynchronous tracking algorithm circuit;

[0032] Figure 5 This is a schematic diagram of a low-noise dynamic comparator in an asynchronous tracking algorithm circuit;

[0033] Figure 6 This is a schematic diagram of a coarse-to-fine binary counter coarse enable signal generation circuit;

[0034] Figure 7 This is a schematic diagram of a bootstrap switch circuit. Detailed Implementation

[0035] Specific implementation method one: as follows Figures 1 to 7 As shown, the low-power capacitor digital converter based on SAR logic and coarse-fine binary counter includes an ultra-low power relaxation oscillator 101, an asynchronous tracking algorithm circuit 102, a coarse-fine binary counter 103, a bootstrap switch circuit 104, and a fully differential SAR logic capacitor digital-to-analog converter 105.

[0036] The ultra-low power relaxation oscillator 101 is used to generate the clock signal Scan, which is the input signal of the asynchronous tracking algorithm circuit 102, the coarse and fine binary counter 103 and the bootstrap switch circuit 104.

[0037] The asynchronous tracking algorithm circuit 102 is used to generate the clock signal Valid, which is the clock signal of the coarse-fine binary counter 103.

[0038] The coarse-fine binary counter 102 is used to generate control signals for the fully differential SAR logic capacitor digital-to-analog converter 105 and to control the switching timing.

[0039] Wherein, the input to be measured capacitor is connected to one end of the full differential CDAC, after the capacitance changes, through the CDAC into digital signal.

[0040] Specific implementation two: as Figures 1 to 7 The ultra-low power relaxation oscillator 101 includes nano-amp reference generating circuit, low power comparator, T flip-flop and trimming circuit;

[0041] One end of the low power comparator is connected with the charging capacitor C INT The other end of the low power comparator is connected with V REF ;

[0042] The current I REF of the nano-amp bandgap reference generating circuit charges the capacitor C INT , and generates a voltage V INT with a rising slope of on the capacitor C INT ; When V INT >V REF , the comparator periodically resets V INT ;

[0043] The period of the scan clock signal is

[0044] The low power comparator adopts the low power comparator structure of two-stage open-loop operational amplifier cascaded with inverter and latch of high threshold device, V REF represents the reference voltage output by the nano-amp reference generating circuit.

[0045] Specific implementation three: as Figures 1 to 7 The nano-amp reference generating circuit adopts self-cascaded NMOS transistor instead of resistor.

[0046] Wherein, according to the relationship between the output reference voltage and the current, the influence of temperature on the bandgap reference is further reduced.

[0047] Specific implementation four: as Figures 1 to 7 The asynchronous tracking algorithm circuit 102 includes low noise dynamic comparator, self-oscillating loop and reset logic.

[0048] Wherein, the dynamic logic makes the CDC take the digital output stored in the previous conversion period as the starting point, and only update its digital output when the capacitance changes;

[0049] The self-oscillating loop formed by the delay (about 30ns) between the comparator clock signal and the comparator enable signal provides clock signals for the comparator and the counter;

[0050] The Finish signal is generated by the output of the comparator connected to the D flip-flop, which controls the CDC to stop conversion only after the output of the comparator changes sign three times;

[0051] When the self-oscillation loop outputs 12 clock cycles, the comparison is completed, and the reset logic immediately turns off the self-oscillation loop, ensuring that the power consumption of the CDC can be negligible in the absence of touch events. In contrast, the conventional SAR CDC has a power consumption limitation: even if the input capacitance of the capacitive sensor does not change, the complete SAR algorithm needs to be executed in each conversion period. If the capacitance to be measured does not change, the corresponding SAR cycle is unnecessary, which wastes unnecessary power consumption.

[0052] Specific embodiment five: as shown in Figures 1 to 7 The coarse-fine binary counter 102 adopts a combination of 4-bit coarse CDAC and 8-bit fine CDAC to optimize the switching timing.

[0053] In which, each time the capacitance is converted, the voltage comparison is first performed by the 8-bit fine CDAC, and when the capacitance change ΔC exceeds the comparison range of the 8-bit fine CDAC, the 4-bit coarse CDAC starts to work, thereby reducing the middle code conversion caused by the small change of the sensor capacitance, greatly reducing the power consumption of the circuit, and realizing high-precision detection.

[0054] Specific embodiment six: as shown in Figures 1 to 7 The bootstrap switch circuit 104 is a 10-tube structure.

[0055] In which, the 10-tube structure adopts a deep N-well process, and the size of all MOS tubes is kept at a small value, and the size of the switching tube is kept at a large value. The enable signal is connected to the gate end of Ms after passing through the AND operation circuit, and the bootstrap switch circuit is turned off during the non-capacitance conversion period, thereby effectively reducing the system power consumption.

[0056] Specific embodiment seven: as shown in Figures 1 to 7 The full-differential SAR logic capacitance-to-digital converter 105 includes a 12-bit full-differential capacitance array, a charge injection cancellation switch, a reset switch, and a pull-up switch.

[0057] In which, the capacitance array adopts an optimized switching timing, i.e. a combination of 8-bit fine CDAC and 4-bit coarse CDAC. The full-differential structure has relatively strong anti-interference performance for common-mode interference and external input noise (i.e. external interference coupled into the sensor through a touch event);

[0058] The analog quantity V OUT Through the formula Operation can be obtained, where C0 is the capacitance at the previous time, ΔC is the capacitance change to be measured, C SARThe total capacitance of the 12-bit capacitor array.

[0059] Embodiment

[0060] As shown in the Figure 2 ultra-low power relaxation oscillator 101 is composed of nano-amp reference generating circuit, low-power comparator, T flip-flop, delay circuit and charging capacitor;

[0061] wherein C1 and C2 are trimming capacitors, the value of the charging capacitor can be changed by controlling M1 and M2, and then the frequency of the clock signal Scan is changed; the output V OUT of the low-power comparator is a short pulse with very low duty cycle, which may not accurately trigger the CDC due to the low duty cycle; in order to increase the duty cycle of the short pulse, a T flip-flop (TFF) is connected after the low-power comparator, which generates a stable clock with 50% duty cycle; at the same time, an inverter chain is connected after the T flip-flop to obtain a clock with steep edges;

[0062] When working, the current I REF generated by the nano-amp reference generating circuit charges the capacitor C INT , and a voltage V INT with a rising slope of is generated on C INT ; When V INT >V REF , the comparator periodically resets V INT . The period of the generated Scan clock signal is The I REF and V REF output by the nano-amp reference generating circuit have similar temperature characteristics, so the oscillation frequency is less affected by temperature, improving the stability of the oscillator circuit;

[0063] As shown in the Figure 3 , this part of the low-power comparator is composed of a two-stage preamplifier, an inverter chain and a latch module, all devices of the low-power comparator use high threshold devices to achieve low operating current and low leakage, and a PMOS input pair is used, and the comparator works under low input common-mode voltage;

[0064] The specific connection mode is as follows, wherein M1, M2, M3, M6, M8, M10 and M12 are PMOS tubes, and M4, M5, M7, M9, M11 and M13 are NMOS tubes:

[0065] The gate end of M2 and M3 is as positive and negative input Vref and Vint, the source end of M2 and M3 is connected to the drain end of M1, the drain end of M2 is connected to the drain end of M4, the drain end of M3 is connected to the drain end of M5, the source end of all PMOS tubes except M2 and M3 is connected to the highest potential Vdd, and the source end of all NMOS tubes is connected to the ground, wherein the gate end of M1 is as bias input Vbias, the drain end of M4 is connected to the gate end and the gate end of M5, the gate end of M6 is connected to Vbias, the drain end of M6 is connected to the drain end of M7, the gate end of M7 is connected to the drain end of M5, the gate end of M8 is connected to the drain end of M7, the drain end of M8 is connected to the drain end of M9, the gate end of M9 is connected to the drain end of M7, the gate end of M10 is connected to the drain end of M9, the drain end of M10 is connected to the drain end of M11, the gate end of M11 is connected to the drain end of M9, the gate end of M12 is connected to the drain end of M11, the drain end of M12 is connected to the drain end of M13, and the gate end of M13 is connected to the drain end of M11. The substrate of all PMOS tubes is connected to the highest potential Vdd, and the substrate of NMOS tubes is connected to the ground.

[0066] As shown in Figure 4 The asynchronous tracking algorithm circuit 102 is composed of a low-noise dynamic comparator, a self-oscillation loop and a reset logic;

[0067] The asynchronous tracking algorithm mainly realizes great reduction of static power consumption and use of fewer MOS tubes. The conventional SAR CDC has a power consumption limitation: even if the input capacitance of the capacitive sensor does not change, a complete SAR algorithm needs to be executed in each conversion period. If the to-be-measured capacitance does not change, the corresponding SAR cycle is unnecessary, and unnecessary power consumption is wasted. The present patent proposes a more efficient algorithm. The dynamic logic enables the CDC to take the digital output stored in the previous conversion period as a starting point, and update the digital output only when the capacitance changes. In the case of the same power consumption, higher capacitance digital conversion precision can be realized.

[0068] Firstly, two output voltages Vs1 and Vs2 of the full differential CDAC are respectively as positive and negative input ends of the dynamic comparator, and the comparison result output by the comparator is connected to an inverter chain and input into a coarse-fine binary counter; then, a self-oscillation loop based on the delay (about 30 ns) between the clock signal of the comparator and the delay signal generates a clock signal Valid, and the Valid signal is again as a clock signal of the coarse-fine binary counter; the self-oscillation loop includes two delay modules (Delay1 and Delay2) which are inserted into the self-oscillation loop as the inverter chain to improve the steepness of the generated clock edge and improve the conversion rate;

[0069] Delayl is designed to provide a delay of about 3ns to meet the requirement of the logic generating the Finish signal, Delay2 is able to provide a delay of about 12ns required to ensure the stability of the CDAC, when the Finish signal is low, the self-oscillating loop works to provide clock signals for the comparator and the counter. In order to reduce the false decision as much as possible to save power and improve the conversion accuracy, the Finish signal only stops the whole system from converting after the output of the comparator changes the sign three times;

[0070] As shown in Figure 5 the low noise dynamic comparator differential input will be amplified by two gain stages before driving the latch, thus reducing the total input reference noise and mismatch of the latch and improving the capacitance conversion accuracy; the working principle is as follows:

[0071] After the clock rising edge, the voltage of the Di node decreases at a rate depending on the input voltage, at t=t0, Gm1 amplifies the differential input, the output of Gm1 (Di+ and Di-) is connected to the Gm2 pair and further amplifies the differential input, and then the output is latched by the latch; the noise of the first stage of amplification circuit can be represented as: Since the flicker noise is much smaller than the thermal noise, the main source of noise comes from the first term, in order to reduce the equivalent input noise of the first stage of amplification, the transconductance of the input pair of the comparator should be large enough;

[0072] The specific structure of the low-noise dynamic comparator used in this part of the circuit is as follows: The comparator consists of two preamplifiers Gm1 and Gm2 and a regenerative latch, with the following connection method: (where M4, M5, M6, M7, M10, and M12 are PMOS transistors, and M1, M2, M3, M8, M9, M11, M13, M14, and M15 are NMOS transistors): The gate terminals of M3, M4, and M5 serve as the clock CLK input terminals; the source terminal of M3 is grounded; the drain terminal of M3 is connected to the source terminals of M1 and M2; the drain terminal of M4 is connected to the drain terminal of M1; the source terminal of M4 is connected to the highest potential Vdd; the drain terminal of M5 is connected to the drain terminal of M2; the source terminal of M5 is connected to the highest potential Vdd; the gate terminals of M1 and M2 serve as the inputs Vp and Vn of Gm1, respectively; the gate terminal of M6 is connected to the drain terminal of M1; the drain terminal of M6 is connected to M... The drain of M8 is connected to the source of M6, and the source of M6 is connected to the highest potential Vdd. The gate of M7 is connected to the gate of M14, the drain of M7 is connected to the drain of M14, and the source of M7 is connected to the highest potential Vdd. The gate of M8 is connected to the gate of M6, and the source of M8 is grounded. The gate of M9 is connected to the gate of M8, the drain of M9 is connected to the drain of M10, and the source of M9 is grounded. The source of M10 is connected to the drain of M6, and the drain of M10... The gate of M12 is connected to the gate of M11, the drain of M11 is connected to the drain of M10, the source of M11 is grounded, the gate of M12 is connected to the gate of M13, the source of M12 is connected to the drain of M14, the drain of M12 is connected to the drain of M13, the source of M13 is grounded, the source of M14 is grounded, the gate of M15 is connected to the gate of M14, the drain of M15 is connected to the drain of M13, and the source of M15 is grounded. The substrates of all PMOS transistors are connected to the highest potential Vdd, and the substrates of all NMOS transistors are grounded.

[0073] like Figure 1 As shown, the coarse-fine binary counter 103 is implemented by a logic control circuit, which is mainly used to generate the control signal for the charge injection cancellation switch in the fully differential SAR CDAC circuit.

[0074] In traditional SAR CDACs, if the complete SAR algorithm is always executed, each capacitor in the capacitor array will have switching activity that consumes power, especially during the CDAC's intermediate code conversion, which will consume a large amount of energy. To avoid this, the CDAC implementation proposed in this invention is a combination of an 8-bit coarse CDAC and a 4-bit fine CDAC. The corresponding switching control signals are generated by coarse and fine binary counters to achieve V S1 and V S2 First, it is boosted through an 8-bit fine CDAC, if V S1 and V S2 The difference exceeds the range of the 8-bit fine CDAC, and is then boosted by the 4-bit coarse CDAC, ultimately making V... S1 =V S2 Therefore, when the capacitance change is small In a SAR cycle, only 8-bit small capacitances in the capacitor array consume current, and for this fine conversion, the technique reduces the maximum CDAC capacitance conversion power consumption by about 16 times;

[0075] The coarse-fine binary counter is composed of n D flip-flops and a coarse enable signal generating circuit. First, the clock signal Valid generated by the asynchronous tracking algorithm circuit is taken as the clock input of the D flip-flop, and the clock signal Scan generated by the relaxation oscillator is taken as the reset signal of the D flip-flop, to generate 13 clock signals CLK1-CLK13, wherein CLK13 is used to reset the asynchronous tracking algorithm circuit, and when the CDAC completes the comparison of 12 clock cycles, the self-oscillation loop in the asynchronous tracking algorithm is timely closed to reduce power consumption, and the self-oscillation loop is triggered again when the next comparison starts; then, the clock signals CLK1-CLK12 are taken as the clock of the D flip-flop, and the output result of the comparator in the asynchronous tracking algorithm circuit is taken as the input of the D flip-flop, to generate the switch control signal in the CDAC; at the same time, the Scan signal is taken as the clock and set signal of the D flip-flop, and the CDAC switch control signal generated is taken as the input of the D flip-flop, to finally generate the 12-bit digital output signal, i.e. the final digital output of the circuit;

[0076] To realize the coarse-fine binary counter, a coarse enable signal generating circuit is designed, which is composed of NOR gate logic, AND gate logic, OR gate logic, delay module and D flip-flop, as shown in Figure 6

[0077] The switch control signal of the 8-bit fine CDAC is taken as the input of the coarse enable signal generating circuit, and after passing through the NOR operation circuit and the AND operation circuit, the output signal passes through the OR operation again, and the output signal of the OR gate is taken as the input of the D flip-flop, and the clock signal CLK8 passes through the delay module Delay to be taken as the clock signal of the D flip-flop, so as to generate the coarse enable signal, so that the capacitance change starts to work when the 4-bit coarse CDAC starts to work.

[0078] As shown in Figure 1 The bootstrap switch circuit (104) is mainly used to improve the gate voltage of the switch tube and improve the sampling linearity. After Vs1 and Vs2 complete reset and pull-up, the change of Vs1 caused by the to-be-measured capacitance change is transmitted to the capacitor array by the switch tube in the bootstrap switch circuit for comparison;

[0079] When the clock signal CLK is at a low level, the capacitor C1 is charged to the highest potential Vdd, and at this time, M4 and M9 are turned off; when CLK jumps to a high level, M4 and M9 are turned on, and since the voltage across the capacitor cannot be suddenly changed, the V GS of the switch tube Ms is clamped to Vdd, that is, V G ​=V IN +Vdd ensures that Vs1 can be fully transferred to the capacitor array. The bootstrap switching circuit uses a deep N-well process, keeping the size of all MOSFETs relatively small and the size of the transfer transistors relatively large, where C1 should be much larger than the parasitic capacitance;

[0080] Meanwhile, the output and enable signal of M4 are connected to the gate of Ms through an AND gate circuit. The specific connection method of this part of the circuit is as follows (where M1, M3, and M4 are PMOS transistors, and M2, M5, M6, M7, M8, M9, and M10 are NMOS transistors): The source of the sampling switch transistor Ms is used as the input Vin, the drain of Ms is used as the output Vout, the gate of Ms is connected to the output of the AND gate circuit, the gate of M1 is connected to the clock signal CLK, the source of M1 is connected to the highest potential Vdd, the drain of M1 is connected to the drain of M2, the gate of M2 is connected to the clock signal CLK, the source of M2 is connected to the drain of M7, and the gate of M3... The drain of M4 is connected to the source of M3, which is connected to the highest potential Vdd. The drain of M3 is connected to one end of capacitor C1. The gate of M4 is connected to the drain of M8. The source of M4 is connected to the drain of M3. The drain of M4 is connected to the source of M5. The gate of M5 is connected to the highest potential Vdd. The drain of M5 is connected to the source of M6. The gate of M6 is connected to the clock signal CLKb. The drain of M6 is grounded. The gate of M7 is connected to CLKb. The source of M7 is grounded. The gate of M8 is connected to the drain of M4. The source of M8 is connected to the drain of M7. The gate of M9 is connected to the gate of Ms. The source of M9 is connected to the source of M8. The drain of M9 is connected to the source of Ms. All NMOS substrates except Ms are grounded. All PMOS substrates are connected to the highest potential Vdd. The substrate of Ms is connected to the input Vin.

[0081] like Figure 1 As shown, the fully differential SAR logic capacitor digital-to-analog converter 105 consists of a reset and pull-up switch, a charge injection cancellation switch, and a 12-bit fully differential capacitor array.

[0082] A capacitor array with optimized switching timing is employed, consisting of a combination of an 8-bit fine CDAC and a 4-bit coarse CDAC. First, at the start of each conversion, Vs1 and Vs2 are reset to zero potential via a reset switch. Then, a bootstrap switch pulls the voltages on the capacitor under test, Vs1 and Vs2, up to Vdd. Since the lower limit of the common-mode input range of the comparator in the asynchronous tracking algorithm circuit is determined by the threshold voltage of the NMOS transistor, the pull-up function ensures that Vs1 and Vs2 remain within the common-mode range even under large sensor capacitance changes. Assuming C0 is the capacitance at the previous moment, ΔC is the change in capacitance under test, and C... SAR Given the total capacitance of the 12-bit capacitor array, after reset and pull-up, the total charge in the upper half of the CDAC is (C0 + C...). SARVdd, then the capacitance under test changes, the gate voltage bootstrap switch circuit opens, the voltage change caused by the capacitance under test is transmitted to the 12-bit capacitance array in the CDAC, that is, the change of Vs1, finally Vs1 and the voltage Vc on the capacitance under test change to the same value Vout, Vout is compared with Vs2 first through the 8-bit fine CDAC, when , then through the 4-bit coarse CDAC, finally a 12-bit digital output is generated; since the total charge amount remains unchanged, at this time the total charge amount of the upper half of the CDAC is (C0+C SAR +ΔC)Vout=(C0+C SAR )Vdd;

[0083] In summary, the analog quantity V OUT corresponding to the digital output of the CDAC can be obtained by the formula ; in addition, the full differential structure has quite strong anti-interference ability to common mode interference and external input noise (that is, external interference coupled into the sensor through touch events); due to the mismatch between the capacitors, a small part of the external environmental interference will still appear as a differential voltage, but in actual application, this mismatch interference can be ignored; since the asynchronous tracking algorithm is only sensitive to the change of the capacitance under test in a short time, it can suppress low-frequency interference, so the influence of external interference can be greatly reduced; the capacitor switch in the CDAC adopts a charge injection cancellation switch; at the moment when the switch is turned off, the MOS device will generate channel charge injection error when working, which introduces noise; in order to reduce noise and improve capacitance detection accuracy, a charge injection cancellation switch is adopted.

[0084] As shown in Figure 7 , the structure of the charge injection cancellation switch in this part of the circuit is as follows: the charge injection cancellation switch is composed of a CMOS transmission gate, and the specific connection mode is as follows (wherein M1, M2 and M3 are PMOS transistors, and M4, M5 and M6 are NMOS transistors): the source end of M1 is connected as an input end Vin, the gate end of M1 is connected with a switch control signal S, the drain end of M1 is connected with the source end of M1, the gate end of M2 is connected with a switch control signal S~, the source end of M2 is connected with the drain end of M1, the drain end of M2 is connected with the source end of M3, the gate end of M3 is connected with a control signal S, the drain end of M3 is connected with the source end of M3, the gate end of M4 is connected with a control signal S~, the drain end of M4 is connected as an input end Vin, the source end of M4 is connected with the drain end of M4 and the drain end of M1, the gate end of M5 is connected with a control signal S, the drain end of M5 is connected with the source end of M4, the source end of M5 is connected with the drain end of M6, the gate end of M6 is connected with a control signal S~, the drain end of M6 is connected with the source end of M6 and the source end of M3, and the drain end of M6 is connected as an output end Vout. The substrates of all PMOS transistors are connected with the highest potential Vdd, and the substrates of all NMOS transistors are connected with the ground.

[0085] Working principle

[0086] The present application converts the varied to-be-measured capacitance into a 12-bit digital output, and the corresponding analog quantity is V OUT The relationship between the capacitance change and V OUT is as follows: Wherein, C0 is the capacitance at the previous moment, ΔC is the to-be-measured capacitance change, and CSAR is the total capacitance of the 12-bit capacitance array. Since there may be weak residual charges in each capacitance when the circuit starts to work, which causes a large error in the experimental results, V S1 and V S2 are first reset to zero level, and then pulled up to V DD through the bootstrap switch. After the reset and pull-up are completed, the input voltage change caused by the capacitance change is transmitted to the capacitance array by the bootstrap switch. Since the lower limit of the common-mode input range of the comparator is defined by the threshold voltage of the NMOS device, the pull-up function realized by the bootstrap switch ensures that V S1 and V S2 are always within the common-mode range of the comparator, thereby expanding the capacitance detection range. In the conventional switch timing SAR CDAC, the complete SAR algorithm is executed in each conversion period, that is, each capacitance in the capacitance array consumes current, even if the capacitance of the sensor does not change. Therefore, the corresponding SAR cycle is unnecessary and increases the power consumption of the circuit. The asynchronous tracking algorithm module and the coarse-fine binary counter proposed in the circuit first increase V S1 and V S2 through the 8-bit fine CDAC, and then increase V S1 and V S2 through the 4-bit coarse CDAC, so as to finally make V S1 = V S2 . Therefore, when the capacitance change is small In one SAR cycle, only the 8-bit small capacitance in the capacitance array consumes current, thereby effectively reducing the power consumption. The asynchronous tracking algorithm circuit simultaneously generates an output signal (Finish) to output the digital code latched by the CDAC control logic part, and in the next conversion device, the counter will load the previous code and perform incremental calculation to make V S1 = V S2 again. Therefore, when ΔC changes, the CDC works, and this fine conversion greatly reduces the power consumption of the circuit and improves the accuracy of the CDC. After completing a capacitance conversion, the coarse-fine binary counter immediately outputs a reset signal Valid_RST to reset the clock signal Valid, thereby closing the self-oscillation loop and further reducing the power consumption of the asynchronous tracking algorithm circuit.

[0087] The proposed SAR logic CDAC is a fully differential structure, so the environmental interference coupled to the two inputs of the CDC will appear as a common-mode voltage and be eliminated, and it has strong anti-interference to common-mode interference and frequency noise (i.e. external interference coupled into the sensor through detection events). In addition, the low-noise dynamic comparator in the asynchronous tracking algorithm circuit adopts a two-stage amplification structure, Gm1 amplifies the differential output, and the Gm1 output is connected to Gm2 for further amplification. Compared with traditional comparators, the differential input will be amplified by two gain stages before driving the latch, thereby reducing the total input reference noise and mismatch of the latch.

[0088] The capacitance conversion is periodically triggered by the ultra-low power relaxation oscillator. Since the CDC is widely used in different scenarios, a trimming circuit needs to be added to the ultra-low power relaxation oscillator to output different frequency clock signals Scan. The current I REF The C INT is charged, and a voltage V INT with a rising slope of is generated on the C INT When V INT >V REF , the comparator periodically resets V INT . The generated Scan clock signal has a period of Since I REF , V REF have similar temperature characteristics, the oscillation frequency is independent of temperature.

[0089] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above, it is not intended to limit the present application. Any skilled person in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the present application, and any simple modification, equivalent replacement and improvement of the above embodiments within the scope of the technical solution of the present application, according to the technical essence of the present application, within the spirit and principles of the present application, are all within the protection scope of the present application.

Claims

1. A low-power capacitance-to-digital converter based on SAR logic and coarse-fine binary counter, characterized in that, The application relates to a low-power consumption relaxation oscillator (101), an asynchronous tracking algorithm circuit (102), a coarse-fine binary counter (103), a bootstrap switch circuit (104) and a full-differential SAR logic capacitor digital-to-analog converter (105); The low-power consumption relaxation oscillator (101) is used for generating a clock signal Scan, which is an input signal of the asynchronous tracking algorithm circuit (102), the coarse-fine binary counter (103) and the bootstrap switch circuit (104); The asynchronous tracking algorithm circuit (102) is used for generating a clock signal Valid, which is a clock signal of the coarse-fine binary counter (103); The coarse-fine binary counter (102) is used for generating a control signal of the full-differential SAR logic capacitor digital-to-analog converter (105) and controlling switch timing; The low-power consumption relaxation oscillator (101) comprises a nano-ampere level reference generation circuit, a low-power consumption comparator, a T flip-flop and a trimming circuit; One end of the low-power comparator is connected with the charging capacitor C INT The other end of the low-power comparator is connected with V REF Connection; Current I of a nanoamp bandgap reference generation circuit REF To charge capacitor C INT Charging, at the charging capacitor C INT The voltage V is generated with a rising slope INT When V INT > V REF , the comparator periodically resets V INT ; The scan clock signal period is ; The low-power comparator adopts a low-power comparator structure of a two-stage open-loop operational amplifier cascaded with inverters and latches of high threshold devices, V REF represents a reference voltage output by the nano-ampere level reference generation circuit; The nano-ampere level reference generation circuit adopts a self-cascaded NMOS transistor instead of a resistor; The asynchronous tracking algorithm circuit (102) comprises a low-noise dynamic comparator, a self-oscillation loop and reset logic; The coarse-fine binary counter (102) adopts a combination of a 4-bit coarse CDAC and an 8-bit fine CDAC to optimize switch timing; The bootstrap switch circuit (104) is a 10-tube structure; The full-differential SAR logic capacitor digital-to-analog converter (105) comprises a 12-bit full-differential capacitor array, a charge injection offset switch, a reset switch and a pull-up switch.

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