Hybrid nested noise-shaping architecture suitable for noise-shaping SAR ADCs

Abstract

The application provides a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a dynamic working closed-loop cascode FIA as a residual amplifier to reduce power consumption by eliminating the static current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through the nested second-order CIFF and second-order EF noise shaping loops to achieve high precision in noise shaping at the same oversampling rate, and integrates the sampling noise cancellation (SNC) method to reduce the capacitance of the sampling capacitor to save chip area; the architecture adopts a closed-loop cascode FIA as a residual amplifier and CIFF and EF as noise shaping loops to solve the problem that the traditional noise shaping SAR ADC is difficult to simultaneously achieve high precision and low power consumption. In addition, the sampling KT / C noise cancellation (SNC) technology is integrated to reduce the capacitance of the sampling capacitor and save chip area.

Description

Technical Field

[0001] This invention relates to the field of noise processing technology, and in particular to a novel hybrid nested noise shaping architecture suitable for noise-shaping SAR ADCs. Background Technology

[0002] Noise shaping involves inputting the residual voltage from the analog-to-digital converter (ADC) quantization into a noise shaping architecture and then feeding the output of the noise shaping architecture back to the ADC. This process shapes the ADC's quantization noise to a higher frequency, thereby improving the ADC's accuracy. Noise-shaped ADCs require the addition of a loop filter to the original ADC to form a noise shaping loop. Common noise shaping loops include cascade integrator feed-forward (CIFF) and error feedback (EF) loops. Among various noise-shaped ADCs, the successive approximation register (SAR) ADC has attracted considerable attention due to its superior power efficiency and ease of digital implementation compared to SAR ADCs.

[0003] Currently, the publicly disclosed noise shaping architectures mainly fall into the following categories, and their architectures and disadvantages are as follows:

[0004] (1) An infinite impulse response (IIR) filter is formed by using a closed-loop active amplifier to construct a noise shaping architecture. However, this will significantly increase the power consumption of the ADC.

[0005] (2) By sharing the charge between capacitors, a completely passive loop filter is formed to constitute a noise shaping architecture. However, since the charge sharing between capacitors leads to the gradual attenuation of the transmitted signal, the noise shaping effect is poor and cannot achieve very high accuracy;

[0006] (3) A noise shaping architecture is constructed by using an open-loop dynamic amplifier and a passive switched capacitor to form a loop filter. The gain of the open-loop dynamic amplifier can compensate for the signal attenuation caused by charge sharing between capacitors. However, the gain of the open-loop dynamic amplifier will vary greatly with process-voltage-temperature (PVT) fluctuations, and usually requires an additional gain calibration circuit.

[0007] (4) A noise shaping architecture is constructed by using an open-loop floating inverter amplifier (FIA) with a switched capacitor as a loop filter. Compared with a regular open-loop dynamic amplifier, the open-loop FIA has better PVT robustness, but the open-loop FIA is limited by the trade-off between the load capacitor value and the output linearity, and is not suitable for high-precision noise-shaping SAR ADCs. Summary of the Invention

[0008] This invention proposes a novel hybrid nested noise shaping architecture suitable for noise-shaping SAR ADCs. This architecture employs a closed-loop cascode FIA ​​as the residual amplifier and CIFF and EF as the noise shaping loops to address the challenge of achieving both high accuracy and low power consumption in traditional noise-shaping SAR ADCs. Furthermore, it integrates sampling noise cancellation (SNC) technology to reduce the capacitance of the sampling capacitor and save chip area.

[0009] The present invention adopts the following technical solution.

[0010] A novel hybrid nested noise shaping architecture for noise-shaping SAR ADCs is characterized by: employing a dynamically operating closed-loop cascode FIA ​​as a residual amplifier to reduce power consumption by eliminating amplifier quiescent current and removing gain calibration circuitry; performing fourth-order noise shaping through nested second-order CIFF and second-order EF noise shaping loops to achieve high accuracy at the same oversampling rate; and reducing the sampling capacitor value by integrating sampling KT / C noise cancellation (SNC) to save chip area.

[0011] The top-level circuit of the shaping architecture is as follows: Figure 1 As shown in section a, it includes a CIFF noise shaping loop, an EF noise shaping loop, a residual amplifier, and a sampling noise cancellation module (SNC); the top-level circuit is connected via port V. DACN V DACP It is connected to the SAR ADC via a capacitive digital-to-analog converter (CDAC) through port V. P V N Connect to the comparator of the SAR ADC.

[0012] The noise source and noise shaping implementation process of the nested noise shaping architecture are as follows:

[0013] (1) The noise sources processed by the noise shaping architecture mainly include two parts:

[0014] ①After completing one quantization, the SAR ADC will generate quantization noise, which is uniformly distributed in the range from 0 Hz to half the sampling frequency;

[0015] ②Sampling noise generated when the SAR ADC samples the input signal. Both quantization noise and sampling noise of the SAR ADC are transmitted through port V. DACP and V DACN It is passed into the noise shaping architecture.

[0016] (2) The noise shaping process is as follows. ① First, after the SAR ADC samples the input signal, the sampled noise is processed through port V. DACP and V DACN The sampling noise is canceled by the SNC circuit in the noise shaping architecture. Secondly, after the SAR ADC completes the quantization process of the current cycle, the generated quantization noise is extracted and amplified by the residual amplifier. Thirdly, the amplified quantization noise is simultaneously fed into the CIFF noise shaping loop and the EF noise shaping loop. These loops perform high-pass filtering on the quantization noise, suppressing low-frequency (within the signal bandwidth) quantization noise. Finally, the filtered quantization noise is passed through port V. P V N V DACP V DACN The signal is then transmitted back to the SAR ADC and participates in the quantization process of the next cycle. At this time, the influence of quantization noise in the frequency range of the signal bandwidth is suppressed, and the noise shaping effect is finally achieved.

[0017] Specific circuit component connections are as follows: Figures 1-3 As shown. The top-level circuit consists of switches S1 to S2. 52 Capacitor C DELN Capacitor C DELP Capacitor C FIR1N Capacitor C FIR1P Capacitor C FIR2N Capacitor C FIR2P Capacitor C EXAN Capacitor C EXAP Capacitor C SUMN Capacitor C SUMP Capacitor C SNCN Capacitor C SNCP Capacitor C INT1N Capacitor C INT1P Capacitor C RESN Capacitor C RESP Capacitor C INT2_1Capacitor C INT2_2 Capacitor C INT2_3 Capacitor C INT2_4 And amplifier G, amplifier G NC composition.

[0018] One end of switch S1 is connected to port V. CM The other end is connected to switch S3, switch S5, and capacitor C. DELP One end of switch S2 is connected to port V. CM The other end is connected to switch S4, switch S6, and capacitor C. DELN One end of switch S3 is connected to port V. DACP The other end is connected to switch S1, switch S5, and capacitor C. DELP One end of switch S4 is connected to port V. DACN The other end is connected to switch S2, switch S6, and capacitor C. DELN One end of switch S5 is connected to switch S7 and capacitor C. FIR2P One end is connected to switch S1, switch S3, and capacitor C. DELP One end of switch S6 is connected to switch S8 and capacitor C. FIR2N One end is connected to switch S2, switch S4, and capacitor C. DELN One end of switch S7 is connected to port V. ON The other end is connected to switch S5 and capacitor C. FIR2P One end of switch S8 is connected to port V. OP The other end is connected to switch S6 and capacitor C. FIR2N One end of switch S9 is connected to port V. DACP The other end is connected to switch S. 11 and capacitor C FIR1P One end; switch S 10 One end is connected to port V DACN The other end is connected to switch S. 12 and capacitor C FIR1N One end; switch S 11 One end is connected to port V OP The other end is connected to switch S9 and capacitor C. FIR1P One end; switch S 12 One end is connected to port V ON The other end is connected to switch S. 10 and capacitor C FIR1N One end; switch S 13 One end is connected to port V CM The other end is connected to port V. ON Switch S14 One end is connected to port V CM The other end is connected to port V. OP Switch S 15 One end is connected to port V DACP The other end is connected to the positive (+) input terminal (V) of amplifier G. IP2 ), switch S 17 and capacitor C EXAP One end; switch S 16 One end is connected to port V DACN The other end is connected to the negative (-) input terminal (V) of amplifier G. IN2 ), switch S 18 and capacitor C EXAN One end; switch S 17 One end is connected to the positive (+) input terminal (V) of amplifier G. IP2 ), switch S 15 and capacitor C EXAP One end is connected to port V. CM Switch S 18 One end is connected to the negative (-) input terminal (V) of amplifier G. IN2 ), switch S 16 and capacitor C EXAN The other end is connected to port V. CM Switch S 19 One end is connected to port V DACP The other end is connected to port V. CM Switch S 20 One end is connected to port V DACN The other end is connected to port V. CM Switch S 21 One end is connected to node ① (e.g.) Figure 1 As shown in part a (the other nodes in this example are represented in the same way), the other end is connected to port V. CM Switch S 22 One end is connected to node ②, and the other end is connected to port V. CM Switch S 23 One end is connected to port V DACP The other end is connected to switch S. 27 and capacitor C SNCP One end; switch S 24 One end is connected to port V DACN The other end is connected to switch S. 28 and capacitor C SNCN One end; switch S 25 One end is connected to node ①, and the other end is connected to switch S. 29 and capacitor C SNCP One end; switch S 26One end is connected to node ②, and the other end is connected to switch S. 30 and capacitor C SNCN One end; switch S 27 One end is connected to amplifier G NC The positive (+) output terminal (V OUTP1 The other end is connected to switch S. 23 and capacitor C SNCP One end; switch S 28 One end is connected to amplifier G NC The negative (-) output terminal (V) OUTN1 The other end is connected to switch S. 24 and capacitor C SNCN One end; switch S 29 One end is connected to port V CM The other end is connected to switch S. 25 and capacitor C SNCP One end; switch S 30 One end is connected to port V CM The other end is connected to switch S. 26 and capacitor C SNCN One end; switch S 31 One end is connected to port V CM The other end is connected to switch S. 33 and capacitor C RESP One end; switch S 32 One end is connected to port V CM The other end is connected to switch S. 34 and capacitor C RESN One end; switch S 33 One end is connected to node ①, and the other end is connected to switch S. 31 and capacitor C RESP One end; switch S 34 One end is connected to node ②, and the other end is connected to switch S. 32 and capacitor C RESN One end; switch S 35 One end is connected to node ③, and the other end is connected to switch S. 39 and capacitor C INT1P One end; switch S 36 One end is connected to node ④, and the other end is connected to switch S. 46 and capacitor C INT1N One end; switch S 37 One end is connected to node ③, and the other end is connected to port V. OP Switch S 38 One end is connected to node ④, and the other end is connected to port V. ON Switch S 39 One end is connected to switch S35 and capacitor C INT1P One end is connected to switch S. 42 and capacitor C INT2_1 One end; switch S 40 One end is connected to node ③, and the other end is connected to switch S. 41 and capacitor C INT2_1 One end; switch S 41 One end is connected to switch S 40 and capacitor C INT2_1 One end is connected to switch S. 45 and capacitor C INT2_2 One end; switch S 42 One end is connected to node ④, and the other end is connected to switch S. 39 and capacitor C INT2_1 One end; switch S 43 One end is connected to node ③, and the other end is connected to switch S. 44 and capacitor C INT2_2 One end; switch S 44 One end is connected to port V P The other end is connected to switch S. 43 and capacitor C INT2_2 One end; switch S 45 One end is connected to node ④, and the other end is connected to switch S. 41 and capacitor C INT2_2 One end; switch S 46 One end is connected to switch S 36 and capacitor C INT1N One end is connected to switch S. 47 and capacitor C INT2_3 One end; switch S 47 One end is connected to node ③, and the other end is connected to switch S. 46 and capacitor C INT2_3 One end; switch S 48 One end is connected to switch S 49 and capacitor C INT2_3 One end is connected to switch S. 50 and capacitor C INT2_4 One end; switch S 49 One end is connected to node ④, and the other end is connected to switch S. 48 and capacitor C INT2_3 One end; switch S 50 One end is connected to node ③, and the other end is connected to switch S. 48 and capacitor C INT2_4 One end; switch S 51 One end is connected to port V N The other end is connected to switch S.52 and capacitor C INT2_4 One end; switch S 52 One end is connected to node ④, and the other end is connected to switch S. 51 and capacitor C INT2_4 One end; capacitor C DELN One end is connected to port V CM The other end is connected to one end of switches S2, S4, and S6; capacitor C DELN One end is connected to port V CM The other end is connected to one end of switches S1, S3, and S5; capacitor C FIR1N One end is connected to port V CM The other end is connected to switch S. 10 and switch S 12 One end; capacitor C FIR1P One end is connected to port V CM The other end is connected to switch S9 and switch S. 11 One end; capacitor C FIR2N One end is connected to port V CM The other end is connected to one end of switch S6 and switch S8; capacitor C FIR2P One end is connected to port V CM The other end is connected to one end of switch S5 and switch S7; capacitor C EXAN One end is connected to port V OP The other end is connected to the negative (-) input terminal (V) of amplifier G. IN2 ), switch S 16 and switch S 18 One end; capacitor C EXAP One end is connected to port V ON The other end is connected to the positive (+) input terminal (V) of amplifier G. IP2 ), switch S 15 and switch S 17 One end; capacitor C SUMN One end is connected to port V DACN The other end is connected to node ②; capacitor C SUMP One end is connected to port V DACP The other end is connected to node ①; capacitor C SNCN One end is connected to switch S 24 and switch S 28 One end is connected to switch S. 26 and switch S 30 One end; capacitor C SNCP One end is connected to switch S 23 and switch S 27 One end is connected to switch S. 25and switch S 29 One end; capacitor C INT1N One end is connected to node ②, and the other end is connected to switch S. 36 and switch S 46 One end; capacitor C INT1P One end is connected to node ①, and the other end is connected to switch S. 35 and switch S 39 One end; capacitor C RESN One end is connected to node ④, and the other end is connected to switch S. 32 and switch S 34 One end; capacitor C RESP One end is connected to node ③, and the other end is connected to switch S. 31 and switch S 33 One end; capacitor C INT2_1 One end is connected to switch S 39 and switch S 42 One end is connected to switch S. 40 and switch S 41 One end; capacitor C INT2_2 One end is connected to switch S 41 and switch S 45 One end is connected to switch S. 43 and switch S 44 One end; capacitor C INT2_3 One end is connected to switch S 46 and switch S 47 One end is connected to switch S. 48 and switch S 49 One end; capacitor C INT2_4 One end is connected to switch S 48 and switch S 50 One end is connected to switch S. 51 and switch S 52 One end; the positive (+) input terminal (V) of amplifier G. IP2 ) Connecting switch S 15 Switch S 17 and capacitor C EXAP One end, negative (-) input terminal (V IN2 ) Connecting switch S 16 Switch S 18 and capacitor C EXAN One end, positive output terminal (V OUTP2 Connection port V OP negative (-) output terminal (V) OUTN2 Connection port V ON Amplifier G NC The positive (+) input terminal (V IP1Connect node ①, negative (-) input terminal (V) IN1 Connect node ②, positive output terminal (V) OUTP1 ) Connecting switch S 27 One end, negative (-) output terminal (V OUTN1 ) Connecting switch S 28 One end.

[0019] The noise shaping workflow of the shaping architecture is as follows: First, the SAR ADC samples the noise voltage through V... DACP and V DACN The signal is passed to the SNC circuit to be canceled out. Then, the current-cycle residual voltage obtained after SAR ADC quantization is input to the hybrid nested noise shaping architecture, amplified by its residual amplifier, and then input to the CIFF and EF noise shaping loops respectively. Finally, the output voltages of the CIFF and EF noise shaping loops are respectively passed to V... P V N and V DACP V DACN The data is transmitted back to the SAR ADC via the port to achieve noise shaping.

[0020] The input voltage signal of the residual amplifier is V DACP and V DACN The output is V OP and V ON After the input signal is quantized by SARADC, the residual voltage of the current period is obtained. This residual voltage is amplified by the residual amplifier and then input into the CIFF and EF noise shaping loops.

[0021] The SNC circuit is independent of the rest of the hybrid nested noise shaping architecture and includes multiple capacitors and switches;

[0022] In the sampling noise cancellation module (SNC) section of the shaping architecture, if the sampling KT / C noise cannot be shaped, it is all passed to the output terminal. A large sampling capacitor is used to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be used while maintaining the same accuracy requirements, reducing the circuit area overhead and making the ADC easier to be driven by the front-end circuit. The working process of SNC includes an extraction stage and an elimination stage.

[0023] Amplifier G used in the SNC circuit NC ( Figure 1 The middle is represented as G NC It adopts an open-loop FIA architecture, and its circuit is as follows: Figure 2 As shown, M N1 M N2 M P1 MP2 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage.

[0024] Let M N× Both represent N-type metal-oxide-semiconductor field-effect transistors (MOS), M P× Both represent P-type metal-oxide-semiconductor field-effect transistors (MOS), among which × Representing any number, in the SNC circuit, M N1 M N2 M P1 M P2 As an input transistor, C is used to invert and amplify the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage;

[0025] Amplifier G NC The circuit consists of switch S 53 ~S 56 Capacitor C RSV1 and transistor M N1 Transistor M N2 Transistor M P1 Transistor M P2 Among them, switch S 53 One end is connected to the power supply V DD The other end is connected to switch S. 55 and capacitor C RSV1 One end; switch S 54 One end is connected to ground (GND), and the other end is connected to switch S. 56 and capacitor C RSV1 One end; switch S 55 One end is connected to switch S 53 and capacitor C RSV1 One end is connected to transistor M. P1 Source terminal and transistor M P2 Source end; switch S 56 One end is connected to switch S 54 and capacitor C RSV1 One end is connected to transistor M. N1 Source and transistor M N2 Source terminal; transistor M P1 Source terminal connected to transistor M P2 Source and switch S 55 At one end, transistor M P1 The drain terminal is connected to amplifier G. NC Negative (-) output terminal (V) OUTN1 ), transistor M P1 Gate-connected amplifier GNC Positive (+) input terminal (V IP1 ); transistor M P2 Source terminal connected to transistor M P1 Source and switch S 55 At one end, transistor M P2 The drain terminal is connected to amplifier G. NC Positive (+) output terminal (V OUTP1 ), transistor M P2 Gate-connected amplifier G NC Negative (-) input terminal (V) IN1 ); transistor M N1 Source terminal connected to transistor M N2 Source and switch S 56 At one end, transistor M N1 The drain terminal is connected to amplifier G. NC Negative (-) output terminal (V) OUTN1 ), transistor M N1 Gate-connected amplifier G NC Positive (+) input terminal (V IP1 ); transistor M N2 Source terminal connected to transistor M N1 Source and switch S 56 At one end, transistor M N2 The drain terminal is connected to amplifier G. NC Positive (+) output terminal (V OUTP1 ), transistor M N2 Gate-connected amplifier G NC Negative (-) input terminal (V) IN1 ).

[0026] Its workflow is as follows:

[0027] ① When it is in the reset phase, the energy storage capacitor C RSV1 Charge;

[0028] ② When it is in the amplification stage, the power supply is disconnected and the power is supplied through the energy storage capacitor so that the open-loop FIA is in dynamic working condition, and low power consumption is achieved by taking advantage of its characteristic of having no static current.

[0029] In the extraction stage of the SNC noise cancellation process, the input signal and the sampled noise voltage are processed through V... DACP and V DACN The port is passed to amplifier G NC At the input terminal, the input signal and the sampled noise voltage are amplified by amplifier G. NC Amplified and stored in capacitor C SNCN C SNCP middle;

[0030] In the noise cancellation phase of the SNC noise cancellation process, capacitor CSNCN C SNCP With C SUMN C SUMP Charge sharing is performed, transferring the sampled noise voltage to capacitor C. SUMN C SUMP In the middle, and the capacitor C SUMN C SUMP The sampling noise voltage and V DACP V DACN The sampling noise voltages input from the port are inversely polar and can be canceled out.

[0031] The residual amplifier circuit includes a closed-loop cascode FIA, switches, and capacitors. During its operation, the cascode FIA ​​circuit, such as... Figure 3 As shown, M N3 M N4 M P3 M P4 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​(cascode transistor) adds a cascode transistor M... N5 M N6 M P5 M P6 To increase the output impedance and achieve high DC gain, the cascode FIA ​​is used as an amplifier in a closed-loop structure to reduce static gain error, and its operation is the same as that of an open-loop FIA.

[0032] The amplifier G circuit consists of switch S 57 ~S 60 Capacitor C RSV2 Transistor M N3 M N4 M P3 M P4 and transistor M N5 M N6 M P5 M P6 .

[0033] Among them, switch S 57 One end is connected to the power supply V DD The other end is connected to switch S. 59 and capacitor C RSV2 One end; switch S 58 One end is connected to ground (GND), and the other end is connected to switch S. 60 and capacitor C RSV2 One end; switch S 59 One end is connected to switch S 57 and capacitor C RSV2 One end is connected to transistor M.P3 Source and transistor M P4 Source end; switch S 60 One end is connected to switch S 58 and capacitor C RSV2 One end is connected to transistor M. N3 Source and transistor M N4 Source terminal; transistor M P3 Source terminal connected to transistor M P4 Source and switch S 59 At one end, transistor M P3 The drain terminal is connected to transistor M P5 Source end, transistor M P3 The gate terminal is connected to the positive (+) input terminal (V) of the amplifier G. IP2 ); transistor M P4 Source terminal connected to transistor M P3 Source and switch S 59 At one end, transistor M P4 The drain terminal is connected to transistor M P6 Source end, transistor M P4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V). IN2 ); transistor M N3 Source terminal connected to transistor M N4 Source and switch S 60 At one end, transistor M N3 The drain terminal is connected to transistor M N5 Source end, transistor M N3 The gate terminal is connected to the positive (+) input terminal (V) of the amplifier G. IP2 ); transistor M N4 Source terminal connected to transistor M N3 Source and switch S 60 At one end, transistor M N4 The drain terminal is connected to transistor M N6 Source end, transistor M N4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V). IN2 ); transistor M P5 Source terminal connected to transistor M P3 Drain terminal, transistor M P5 The drain terminal is connected to the negative (-) output terminal (V) of the amplifier G. OUTN2 ), transistor M P5 Gate terminal connection port V CM Transistor M P6 Source terminal connected to transistor M P4 Drain terminal, transistor M P6 The drain terminal is connected to the positive (+) output terminal (V) of the amplifier G. OUTP2 ), transistor M P6 Gate terminal connection port V CMTransistor M N5 Source terminal connected to transistor M N3 Drain terminal, transistor M N5 The drain terminal is connected to the negative (-) output terminal (V) of the amplifier G. OUTN2 ), transistor M N5 Gate terminal connection port V CM Transistor M N6 Source terminal connected to transistor M N4 Drain terminal, transistor M N6 The drain terminal is connected to the positive (+) output terminal (V) of the amplifier G. OUTP2 ), transistor M N6 Gate terminal connection port V CM .

[0034] In the voltage signal of the CIFF noise shaping loop, the input is V. OP and V ON The output is V P and V N CIFF noise shaping loop circuit capacitor C RESN C RESP C INT1N C INT1P C INT2_1 C INT2_2 C INT2_3 C INT2_4 It is composed of a second-order passive IIR filter formed by each switch;

[0035] The workflow of the CIFF noise shaping loop is as follows:

[0036] ①Switch S 31 S 32 S 37 S 38 Close, switch S 31 S 32 S 37 S 38 When the other switches of the module to which it belongs are turned off, the amplified residual voltage is stored in capacitor C. RESN C RESP superior;

[0037] ②Switch S 33 S 34 S 35 S 36 Close, switch S 33 S 34 S 35 S 36 The other switches of the module to which it belongs are off, at which point the capacitor C passes through. RESN C RESP and C INT1N CINT1P Charge sharing between them enables the first-stage integration;

[0038] ③ Switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52 Close, switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52 Disconnect the other switches of the module to which it belongs, and disconnect capacitor C. INT2_1 C INT2_2 C INT2_3 C INT2_4 Connected in parallel with capacitor C RESN C RESP Charge sharing is performed in a fully differential circuit to achieve the second-stage integration;

[0039] ④ Switch S 39 S 41 S 44 S 46 S 48 S 51 Close the switch, and open the other switches. At this time, capacitor C... INT2_1 C INT2_2 Connected in series to V P Terminal, capacitor C INT2_3 C INT2_4 Connected in series to V N The terminal is used to amplify the second-stage integral voltage by four times, while the capacitor C... INT1P C INT2_1 C INT2_2 Series connection, capacitor C INT1N C INT2_3 C INT2_4 Therefore, the integrating voltages of the first and second stages are both connected in series, so they both pass through V. P and V N Transmitted back to the SAR ADC.

[0040] In the voltage signal of the EF noise shaping loop, the input is V. OP and V ON The output is V DACP and VDACN The EF noise shaping loop uses capacitors C with the same capacitance value. FIR1N C FIR1P C FIR2N C FIR2P C DELN C DELP It consists of a second-order passive finite impulse response (FIR) filter composed of various switches;

[0041] The workflow of the EF noise shaping loop is as follows:

[0042] ① With switches S1 and S2 closed and the rest of the switches open, capacitor C... DELN C DELP Reset;

[0043] ② With switches S5 and S6 closed and the rest of the switches open, capacitor C is... FIR2N C FIR2P The voltage stored in the previous cycle, which is the residual voltage amplified by the residual amplifier in the previous cycle, is transferred to capacitor C through charge sharing. DELN C DELP superior;

[0044] ③ Switches S7, S8, S 11 S 12 With the switch closed and the other switches open, the residual voltage of the previous cycle, amplified by the residual amplifier, is stored in capacitor C. FIR1N C FIR1P and C FIR2N C FIR2P superior;

[0045] ④ Switches S3, S4, S9, S 10 Close the switch, and open the other switches, according to... Figure 1 The connection relationship in part a, capacitor C FIR1N C FIR1P and C DELN C DELP The voltage on is transferred to V DACP and V DACN port.

[0046] This invention proposes a novel hybrid nested noise shaping architecture suitable for noise-shaping SAR ADCs. This architecture employs a closed-loop cascode FIA ​​as the residual amplifier and CIFF and EF as the noise shaping loop to address the challenge of achieving both high accuracy and low power consumption in traditional noise-shaping SAR ADCs. Furthermore, it integrates sampling KT / C noise cancellation (SNC) technology to reduce the capacitance of the sampling capacitor and save chip area.

[0047] This invention is an innovation in noise shaping architecture, applicable to noise-shaped SAR ADCs. It retains the advantages of traditional noise shaping architectures while improving accuracy while maintaining low power consumption. Therefore, it can be used for sampling and quantizing weak signals, such as temperature signals, biological signals, and weak current signals, in noise-shaped SAR ADCs. Noise-shaped SAR ADCs employing this architecture can be applied in fields such as precision data acquisition systems, communication systems, medical equipment, audio signal processing, and image sensors.

[0048] This invention represents an innovative optimization of noise shaping architecture. This novel architecture achieves fourth-order noise shaping for SAR ADCs, employing a closed-loop cascode FIA ​​as the residual amplifier, achieving high accuracy while maintaining low power consumption. The architecture integrates a sampling noise cancellation (SNC) module, allowing the ADC to use smaller sampling capacitors while maintaining the same accuracy requirements, reducing area overhead and making the ADC easier to drive by preceding circuitry. This invention is compatible with multiple mainstream integrated circuit design platforms such as Cadence, PSpice, and Hspice.

[0049] The architecture described in this invention has the following advantages:

[0050] (1) The novel hybrid nested noise shaping architecture of the present invention can achieve fourth-order noise shaping through CIFF and EF noise shaping loops, and can achieve higher accuracy at the same oversampling ratio (OSR);

[0051] (2) The closed-loop cascode FIA ​​in the novel hybrid nested noise shaping architecture of the present invention is dynamic and has no static current in the traditional amplifier, which can effectively reduce power consumption;

[0052] (3) In the architecture of this invention, compared with the open-loop FIA, the output linearity of the closed-loop cascode FIA ​​is improved, and it is not limited by the capacitance value of the output load capacitor, thus further optimizing the accuracy;

[0053] (4) The closed-loop cascode FIA ​​has good PVT robustness and does not require any gain calibration circuit, further reducing power consumption.

[0054] The advantages of this invention also include:

[0055] (1) High precision: The SAR ADC can achieve fourth-order noise shaping through this novel hybrid nested noise shaping architecture, achieving higher precision under the same OSR. At the same time, since the closed-loop cascode FIA ​​is used as the residual amplifier in this noise shaping architecture, it is not limited by the trade-off between the output load capacitor value and the output linearity. Therefore, the overall KT / C noise can be reduced by increasing the load capacitor, thereby achieving a high-precision SAR ADC.

[0056] (2) Low power consumption: This novel hybrid nested noise shaping architecture employs fully dynamic operation without using any modules that consume quiescent current. Furthermore, the closed-loop cascode FIA ​​requires no additional gain calibration circuitry. Therefore, this ADC exhibits low power consumption.

[0057] (3) Good PVT robustness: Since the closed-loop common source cascode FIA ​​is used as the residual amplifier, its gain has good PVT robustness, thus the noise transfer function (NTF) of this hybrid nested noise shaping architecture also has good PVT robustness. Attached Figure Description

[0058] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0059] Appendix Figure 1 This is the novel hybrid nested noise shaping architecture described in this invention (part a is the top-level circuit diagram, and part b is the timing diagram of the corresponding switch control signals).

[0060] Appendix Figure 2 It is an open-loop FIA amplifier ( Figure 1 China G NC The circuit diagram is shown below.

[0061] Appendix Figure 3 It is a common-source cascode FIA ​​amplifier ( Figure 1 The circuit diagram of G). Detailed Implementation

[0062] As shown in the figure, a novel hybrid nested noise shaping architecture suitable for noise-shaping SAR ADCs is characterized by: the shaping architecture using a dynamically operating closed-loop cascode FIA ​​as a residual amplifier to reduce power consumption by eliminating the amplifier's quiescent current and removing the gain calibration circuit; the shaping architecture performing fourth-order noise shaping through nested second-order CIFF and second-order EF noise shaping loops to achieve high accuracy in noise shaping at the same oversampling rate; and the shaping architecture reducing the capacitance of the sampling capacitor to save chip area by integrating sampling KT / C noise cancellation (SNC) methods.

[0063] The top-level circuit of the shaping architecture is as follows: Figure 1 As shown in section a, it includes a CIFF noise shaping loop, an EF noise shaping loop, a residual amplifier, and a sampling noise cancellation module (SNC); the top-level circuit is connected via port V. DACN V DACP It is connected to the SAR ADC via a capacitive digital-to-analog converter (CDAC) through port V. P V N Connect to the comparator of the SAR ADC.

[0064] The noise source and noise shaping implementation process of the nested noise shaping architecture are as follows:

[0065] (1) The noise sources processed by the noise shaping architecture mainly include two parts:

[0066] ①After completing one quantization, the SAR ADC will generate quantization noise, which is uniformly distributed in the range from 0 Hz to half the sampling frequency;

[0067] ②Sampling noise generated when the SAR ADC samples the input signal. Both quantization noise and sampling noise of the SAR ADC are transmitted through port V. DACP and V DACN It is passed into the noise shaping architecture.

[0068] (2) The noise shaping process is as follows. ① First, after the SAR ADC samples the input signal, the sampled noise is processed through port V. DACP and V DACNThe sampling noise is canceled by the SNC circuit in the noise shaping architecture. Secondly, after the SAR ADC completes the quantization process of the current cycle, the generated quantization noise is extracted and amplified by the residual amplifier. Thirdly, the amplified quantization noise is simultaneously fed into the CIFF noise shaping loop and the EF noise shaping loop. These loops perform high-pass filtering on the quantization noise, suppressing low-frequency (within the signal bandwidth) quantization noise. Finally, the filtered quantization noise is passed through port V. P V N V DACP V DACN The signal is then transmitted back to the SAR ADC and participates in the quantization process of the next cycle. At this time, the influence of quantization noise in the frequency range of the signal bandwidth is suppressed, and the noise shaping effect is finally achieved.

[0069] Specific circuit component connections are as follows: Figures 1-3 As shown. The top-level circuit consists of switches S1 to S2. 52 Capacitor C DELN Capacitor C DELP Capacitor C FIR1N Capacitor C FIR1P Capacitor C FIR2N Capacitor C FIR2P Capacitor C EXAN Capacitor C EXAP Capacitor C SUMN Capacitor C SUMP Capacitor C SNCN Capacitor C SNCP Capacitor C INT1N Capacitor C INT1P Capacitor C RESN Capacitor C RESP Capacitor C INT2_1 Capacitor C INT2_2 Capacitor C INT2_3 Capacitor C INT2_4 And amplifier G, amplifier G NC Composition. One end of switch S1 is connected to port V. CM The other end is connected to switch S3, switch S5, and capacitor C. DELP One end of switch S2 is connected to port V. CM The other end is connected to switch S4, switch S6, and capacitor C. DELN One end of switch S3 is connected to port V. DACP The other end is connected to switch S1, switch S5, and capacitor C. DELP One end of switch S4 is connected to port V. DACN The other end is connected to switch S2, switch S6, and capacitor C. DELNOne end of switch S5 is connected to switch S7 and capacitor C. FIR2P One end is connected to switch S1, switch S3, and capacitor C. DELP One end of switch S6 is connected to switch S8 and capacitor C. FIR2N One end is connected to switch S2, switch S4, and capacitor C. DELN One end of switch S7 is connected to port V. ON The other end is connected to switch S5 and capacitor C. FIR2P One end of switch S8 is connected to port V. OP The other end is connected to switch S6 and capacitor C. FIR2N One end of switch S9 is connected to port V. DACP The other end is connected to switch S. 11 and capacitor C FIR1P One end; switch S 10 One end is connected to port V DACN The other end is connected to switch S. 12 and capacitor C FIR1N One end; switch S 11 One end is connected to port V OP The other end is connected to switch S9 and capacitor C. FIR1P One end; switch S 12 One end is connected to port V ON The other end is connected to switch S. 10 and capacitor C FIR1N One end; switch S 13 One end is connected to port V CM The other end is connected to port V. ON Switch S 14 One end is connected to port V CM The other end is connected to port V. OP Switch S 15 One end is connected to port V DACP The other end is connected to the positive (+) input terminal (V) of amplifier G. IP2 ), switch S 17 and capacitor C EXAP One end; switch S 16 One end is connected to port V DACN The other end is connected to the negative (-) input terminal (V) of amplifier G. IN2 ), switch S 18 and capacitor C EXAN One end; switch S 17 One end is connected to the positive (+) input terminal (V) of amplifier G. IP2 ), switch S 15 and capacitor C EXAPOne end is connected to port V. CM Switch S 18 One end is connected to the negative (-) input terminal (V) of amplifier G. IN2 ), switch S 16 and capacitor C EXAN The other end is connected to port V. CM Switch S 19 One end is connected to port V DACP The other end is connected to port V. CM Switch S 20 One end is connected to port V DACN The other end is connected to port V. CM Switch S 21 One end is connected to node ① (e.g.) Figure 1 As shown in part a (the other nodes in this example are represented in the same way), the other end is connected to port V. CM Switch S 22 One end is connected to node ②, and the other end is connected to port V. CM Switch S 23 One end is connected to port V DACP The other end is connected to switch S. 27 and capacitor C SNCP One end; switch S 24 One end is connected to port V DACN The other end is connected to switch S. 28 and capacitor C SNCN One end; switch S 25 One end is connected to node ①, and the other end is connected to switch S. 29 and capacitor C SNCP One end; switch S 26 One end is connected to node ②, and the other end is connected to switch S. 30 and capacitor C SNCN One end; switch S 27 One end is connected to amplifier G NC The positive (+) output terminal (V OUTP1 The other end is connected to switch S. 23 and capacitor C SNCP One end; switch S 28 One end is connected to amplifier G NC The negative (-) output terminal (V) OUTN1 The other end is connected to switch S. 24 and capacitor C SNCN One end; switch S 29 One end is connected to port V CM The other end is connected to switch S. 25 and capacitor C SNCP One end; switch S30 One end is connected to port V CM The other end is connected to switch S. 26 and capacitor C SNCN One end; switch S 31 One end is connected to port V CM The other end is connected to switch S. 33 and capacitor C RESP One end; switch S 32 One end is connected to port V CM The other end is connected to switch S. 34 and capacitor C RESN One end; switch S 33 One end is connected to node ①, and the other end is connected to switch S. 31 and capacitor C RESP One end; switch S 34 One end is connected to node ②, and the other end is connected to switch S. 32 and capacitor C RESN One end; switch S 35 One end is connected to node ③, and the other end is connected to switch S. 39 and capacitor C INT1P One end; switch S 36 One end is connected to node ④, and the other end is connected to switch S. 46 and capacitor C INT1N One end; switch S 37 One end is connected to node ③, and the other end is connected to port V. OP Switch S 38 One end is connected to node ④, and the other end is connected to port V. ON Switch S 39 One end is connected to switch S 35 and capacitor C INT1P One end is connected to switch S. 42 and capacitor C INT2_1 One end; switch S 40 One end is connected to node ③, and the other end is connected to switch S. 41 and capacitor C INT2_1 One end; switch S 41 One end is connected to switch S 40 and capacitor C INT2_1 One end is connected to switch S. 45 and capacitor C INT2_2 One end; switch S 42 One end is connected to node ④, and the other end is connected to switch S. 39 and capacitor C INT2_1 One end; switch S 43 One end is connected to node ③, and the other end is connected to switch S.44 and capacitor C INT2_2 One end; switch S 44 One end is connected to port V P The other end is connected to switch S. 43 and capacitor C INT2_2 One end; switch S 45 One end is connected to node ④, and the other end is connected to switch S. 41 and capacitor C INT2_2 One end; switch S 46 One end is connected to switch S 36 and capacitor C INT1N One end is connected to switch S. 47 and capacitor C INT2_3 One end; switch S 47 One end is connected to node ③, and the other end is connected to switch S. 46 and capacitor C INT2_3 One end; switch S 48 One end is connected to switch S 49 and capacitor C INT2_3 One end is connected to switch S. 50 and capacitor C INT2_4 One end; switch S 49 One end is connected to node ④, and the other end is connected to switch S. 48 and capacitor C INT2_3 One end; switch S 50 One end is connected to node ③, and the other end is connected to switch S. 48 and capacitor C INT2_4 One end; switch S 51 One end is connected to port V N The other end is connected to switch S. 52 and capacitor C INT2_4 One end; switch S 52 One end is connected to node ④, and the other end is connected to switch S. 51 and capacitor C INT2_4 One end; capacitor C DELN One end is connected to port V CM The other end is connected to one end of switches S2, S4, and S6; capacitor C DELN One end is connected to port V CM The other end is connected to one end of switches S1, S3, and S5; capacitor C FIR1N One end is connected to port V CM The other end is connected to switch S. 10 and switch S 12 One end; capacitor C FIR1P One end is connected to port V CMThe other end is connected to switch S9 and switch S. 11 One end; capacitor C FIR2N One end is connected to port V CM The other end is connected to one end of switch S6 and switch S8; capacitor C FIR2P One end is connected to port V CM The other end is connected to one end of switch S5 and switch S7; capacitor C EXAN One end is connected to port V OP The other end is connected to the negative (-) input terminal (V) of amplifier G. IN2 ), switch S 16 and switch S 18 One end; capacitor C EXAP One end is connected to port V ON The other end is connected to the positive (+) input terminal (V) of amplifier G. IP2 ), switch S 15 and switch S 17 One end; capacitor C SUMN One end is connected to port V DACN The other end is connected to node ②; capacitor C SUMP One end is connected to port V DACP The other end is connected to node ①; capacitor C SNCN One end is connected to switch S 24 and switch S 28 One end is connected to switch S. 26 and switch S 30 One end; capacitor C SNCP One end is connected to switch S 23 and switch S 27 One end is connected to switch S. 25 and switch S 29 One end; capacitor C INT1N One end is connected to node ②, and the other end is connected to switch S. 36 and switch S 46 One end; capacitor C INT1P One end is connected to node ①, and the other end is connected to switch S. 35 and switch S 39 One end; capacitor C RESN One end is connected to node ④, and the other end is connected to switch S. 32 and switch S 34 One end; capacitor C RESP One end is connected to node ③, and the other end is connected to switch S. 31 and switch S 33 One end; capacitor C INT2_1 One end is connected to switch S 39 and switch S42 One end is connected to switch S. 40 and switch S 41 One end; capacitor C INT2_2 One end is connected to switch S 41 and switch S 45 One end is connected to switch S. 43 and switch S 44 One end; capacitor C INT2_3 One end is connected to switch S 46 and switch S 47 One end is connected to switch S. 48 and switch S 49 One end; capacitor C INT2_4 One end is connected to switch S 48 and switch S 50 One end is connected to switch S. 51 and switch S 52 One end; the positive (+) input terminal (V) of amplifier G. IP2 ) Connecting switch S 15 Switch S 17 and capacitor C EXAP One end, negative (-) input terminal (V IN2 ) Connecting switch S 16 Switch S 18 and capacitor C EXAN One end, positive output terminal (V OUTP2 Connection port V OP negative (-) output terminal (V) OUTN2 Connection port V ON Amplifier G NC The positive (+) input terminal (V IP1 Connect node ①, negative (-) input terminal (V) IN1 Connect node ②, positive output terminal (V) OUTP1 ) Connecting switch S 27 One end, negative (-) output terminal (V OUTN1 ) Connecting switch S 28 One end.

[0070] The noise shaping workflow of the shaping architecture is as follows: First, the SAR ADC samples the noise voltage through V... DACP and V DACN The signal is passed to the SNC circuit to be canceled out. Then, the current-cycle residual voltage obtained after SAR ADC quantization is input to the hybrid nested noise shaping architecture, amplified by its residual amplifier, and then input to the CIFF and EF noise shaping loops respectively. Finally, the output voltages of the CIFF and EF noise shaping loops are respectively passed to V...P V N and V DACP V DACN The data is transmitted back to the SAR ADC via the port to achieve noise shaping.

[0071] The input voltage signal of the residual amplifier is V DACP and V DACN The output is V OP and V ON After the input signal is quantized by SARADC, the residual voltage of the current period is obtained. This residual voltage is amplified by the residual amplifier and then input into the CIFF and EF noise shaping loops.

[0072] The SNC circuit is independent of the rest of the hybrid nested noise shaping architecture and includes multiple capacitors and switches;

[0073] In the sampling noise cancellation module (SNC) section of the shaping architecture, if the sampling KT / C noise cannot be shaped, it is all passed to the output terminal. A large sampling capacitor is used to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be used while maintaining the same accuracy requirements, reducing the circuit area overhead and making the ADC easier to be driven by the front-end circuit. The working process of SNC includes an extraction stage and an elimination stage.

[0074] Amplifier G used in the SNC circuit NC ( Figure 1 The middle is represented as G NC It adopts an open-loop FIA architecture, and its circuit is as follows: Figure 2 As shown, M N1 M N2 M P1 M P2 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage.

[0075] Let M N× Both represent N-type metal-oxide-semiconductor field-effect transistors (MOS), M P× Both represent P-type metal-oxide-semiconductor field-effect transistors (MOS), among which × Representing any number, in the SNC circuit, M N1 M N2 M P1 M P2 As an input transistor, C is used to invert and amplify the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage;

[0076] Amplifier G NC The circuit consists of switch S 53 ~S 56 Capacitor C RSV1 and transistor M N1 Transistor M N2 Transistor M P1 Transistor M P2 Among them, switch S 53 One end is connected to the power supply V DD The other end is connected to switch S. 55 and capacitor C RSV1 One end; switch S 54 One end is connected to ground (GND), and the other end is connected to switch S. 56 and capacitor C RSV1 One end; switch S 55 One end is connected to switch S 53 and capacitor C RSV1 One end is connected to transistor M. P1 Source and transistor M P2 Source end; switch S 56 One end is connected to switch S 54 and capacitor C RSV1 One end is connected to transistor M. N1 Source and transistor M N2 Source terminal; transistor M P1 Source terminal connected to transistor M P2 Source and switch S 55 At one end, transistor M P1 The drain terminal is connected to amplifier G. NC Negative (-) output terminal (V) OUTN1 ), transistor M P1 Gate-connected amplifier G NC Positive (+) input terminal (V IP1 ); transistor M P2 Source terminal connected to transistor M P1 Source and switch S 55 At one end, transistor M P2 The drain terminal is connected to amplifier G. NC Positive (+) output terminal (V OUTP1 ), transistor M P2 Gate-connected amplifier G NC Negative (-) input terminal (V) IN1 ); transistor M N1 Source terminal connected to transistor M N2 Source and switch S 56 At one end, transistor M N1 The drain terminal is connected to amplifier G. NC Negative (-) output terminal (V) OUTN1), transistor M N1 Gate-connected amplifier G NC Positive (+) input terminal (V IP1 ); transistor M N2 Source terminal connected to transistor M N1 Source and switch S 56 At one end, transistor M N2 The drain terminal is connected to amplifier G. NC Positive (+) output terminal (V OUTP1 ), transistor M N2 Gate-connected amplifier G NC Negative (-) input terminal (V) IN1 ).

[0077] Its workflow is as follows:

[0078] ① When it is in the reset phase, the energy storage capacitor C RSV1 Charge;

[0079] ② When it is in the amplification stage, the power supply is disconnected and the power is supplied through the energy storage capacitor so that the open-loop FIA is in dynamic working condition, and low power consumption is achieved by taking advantage of its characteristic of having no static current.

[0080] In the extraction stage of the SNC noise cancellation process, the input signal and the sampled noise voltage are processed through V... DACP and V DACN The port is passed to amplifier G NC At the input terminal, the input signal and the sampled noise voltage are amplified by amplifier G. NC Amplified and stored in capacitor C SNCN C SNCP middle;

[0081] In the noise cancellation phase of the SNC noise cancellation process, capacitor C SNCN C SNCP With C SUMN C SUMP Charge sharing is performed, transferring the sampled noise voltage to capacitor C. SUMN C SUMP In the middle, and the capacitor C SUMN C SUMP The sampling noise voltage and V DACP V DACN The sampling noise voltages input from the port are inversely polar and can be canceled out.

[0082] The residual amplifier circuit includes a closed-loop cascode FIA, switches, and capacitors. During its operation, the cascode FIA ​​circuit, such as... Figure 3 As shown, M N3 M N4 M P3 MP4 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​(cascode transistor) adds a cascode transistor M... N5 M N6 M P5 M P6 To increase the output impedance and achieve high DC gain, the cascode FIA ​​is used as an amplifier in a closed-loop structure to reduce static gain error, and its operation is the same as that of an open-loop FIA.

[0083] The amplifier G circuit consists of switch S 57 ~S 60 Capacitor C RSV2 Transistor M N3 M N4 M P3 M P4 and transistor M N5 M N6 M P5 M P6 Among them, switch S 57 One end is connected to the power supply V DD The other end is connected to switch S. 59 and capacitor C RSV2 One end; switch S 58 One end is connected to ground (GND), and the other end is connected to switch S. 60 and capacitor C RSV2 One end; switch S 59 One end is connected to switch S 57 and capacitor C RSV2 One end is connected to transistor M. P3 Source and transistor M P4 Source end; switch S 60 One end is connected to switch S 58 and capacitor C RSV2 One end is connected to transistor M. N3 Source and transistor M N4 Source terminal; transistor M P3 Source terminal connected to transistor M P4 Source and switch S 59 At one end, transistor M P3 The drain terminal is connected to transistor M P5 Source end, transistor M P3 The gate terminal is connected to the positive (+) input terminal (V) of the amplifier G. IP2 ); transistor M P4 Source terminal connected to transistor M P3 Source and switch S 59 At one end, transistor MP4 The drain terminal is connected to transistor M P6 Source end, transistor M P4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V). IN2 ); transistor M N3 Source terminal connected to transistor M N4 Source and switch S 60 At one end, transistor M N3 The drain terminal is connected to transistor M N5 Source end, transistor M N3 The gate terminal is connected to the positive (+) input terminal (V) of the amplifier G. IP2 ); transistor M N4 Source terminal connected to transistor M N3 Source and switch S 60 At one end, transistor M N4 The drain terminal is connected to transistor M N6 Source end, transistor M N4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V). IN2 ); transistor M P5 Source terminal connected to transistor M P3 Drain terminal, transistor M P5 The drain terminal is connected to the negative (-) output terminal (V) of the amplifier G. OUTN2 ), transistor M P5 Gate terminal connection port V CM Transistor M P6 Source terminal connected to transistor M P4 Drain terminal, transistor M P6 The drain terminal is connected to the positive (+) output terminal (V) of the amplifier G. OUTP2 ), transistor M P6 Gate terminal connection port V CM Transistor M N5 Source terminal connected to transistor M N3 Drain terminal, transistor M N5 The drain terminal is connected to the negative (-) output terminal (V) of the amplifier G. OUTN2 ), transistor M N5 Gate terminal connection port V CM Transistor M N6 Source terminal connected to transistor M N4 Drain terminal, transistor M N6 The drain terminal is connected to the positive (+) output terminal (V) of the amplifier G. OUTP2 ), transistor M N6 Gate terminal connection port V CM .

[0084] In the voltage signal of the CIFF noise shaping loop, the input is V. OP and V ON The output is V P and VN CIFF noise shaping loop circuit capacitor C RESN C RESP C INT1N C INT1P C INT2_1 C INT2_2 C INT2_3 C INT2_4 It is composed of a second-order passive IIR filter formed by each switch;

[0085] The workflow of the CIFF noise shaping loop is as follows:

[0086] ①Switch S 31 S 32 S 37 S 38 Close, switch S 31 S 32 S 37 S 38 When the other switches of the module to which it belongs are turned off, the amplified residual voltage is stored in capacitor C. RESN C RESP superior;

[0087] ②Switch S 33 S 34 S 35 S 36 Close, switch S 33 S 34 S 35 S 36 The other switches of the module to which it belongs are off, at which point the capacitor C passes through. RESN C RESP and C INT1N C INT1P Charge sharing between them enables the first-stage integration;

[0088] ③ Switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52 Close, switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52Disconnect the remaining switches of the module to which it belongs, and turn off C. INT2_1 C INT2_2 C INT2_3 C INT2_4 Connected in parallel with C RESN C RESP Charge sharing is performed in a fully differential circuit to achieve the second-stage integration;

[0089] ④ Switch S 39 S 41 S 44 S 46 S 48 S 51 Close the switch, and open the other switches. At this time, capacitor C... INT2_1 C INT2_2 Connected in series to V P Terminal, capacitor C INT2_3 C INT2_4 Connected in series to V N The terminal is used to amplify the second-stage integral voltage by four times, while the capacitor C... INT1P C INT2_1 C INT2_2 Series connection, capacitor C INT1N C INT2_3 C INT2_4 Therefore, the integrating voltages of the first and second stages are both connected in series, so they both pass through V. P and V N Transmitted back to the SAR ADC.

[0090] In the voltage signal of the EF noise shaping loop, the input is V. OP and V ON The output is V DACP and V DACN The EF noise shaping loop uses capacitors C with the same capacitance value. FIR1N C FIR1P C FIR2N C FIR2P C DELN C DELP It consists of a second-order passive finite impulse response (FIR) filter composed of various switches;

[0091] The workflow of the EF noise shaping loop is as follows:

[0092] ① With switches S1 and S2 closed and the rest of the switches open, capacitor C... DELN C DELP Reset;

[0093] ② With switches S5 and S6 closed and the rest of the switches open, capacitor C is... FIR2N CFIR2P The voltage stored in the previous cycle, which is the residual voltage amplified by the residual amplifier in the previous cycle, is transferred to capacitor C through charge sharing. DELN C DELP superior;

[0094] ③ Switches S7, S8, S 11 S 12 With the switch closed and the other switches open, the residual voltage of the previous cycle, amplified by the residual amplifier, is stored in capacitor C. FIR1N C FIR1P and C FIR2N C FIR2P superior;

[0095] ④ Switches S3, S4, S9, S 10 Close the switch, and open the other switches, according to... Figure 1 The connection relationship in part a, capacitor C FIR1N C FIR1P and C DELN C DELP The voltage on is transferred to V DACP and V DACN port.

[0096] Example:

[0097] In this example, the top-level circuit of the novel hybrid nested noise shaping architecture is as follows: Figure 1 As shown in section a, it consists of a CIFF noise shaping loop, an EF noise shaping loop, a residual amplifier, and a sampling noise cancellation module (hereinafter referred to as SNC), respectively. DACN V DACP and V P V N These are the ports that connect to the SAR ADC's capacitive digital-to-analog converter (CDAC) and comparator, respectively.

[0098] The timing of the novel hybrid nested noise shaping architecture is as follows: Figure 1 As shown in part b (Φ in this example) XX For the control signal of the switch, where " XX " represents the name of any signal. When Φ XX When the voltage is high, the switch is closed, Φ XX The switch is off when the level is low. Default and Φ XXThe switch states are represented in reverse. (All switch control signals in this invention use the same representation as above). The overall workflow is as follows: First, the SAR ADC samples the noise voltage through V... DACP and V DACN The signal is passed to the SNC circuit to be canceled out. Then, the current-cycle residual voltage obtained after SAR ADC quantization is input to the hybrid nested noise shaping architecture, amplified by its residual amplifier, and then the amplified residual voltage is input to the CIFF and EF noise shaping loops respectively. The output voltages of the CIFF and EF noise shaping loops are respectively passed through V... P V N and V DACP V DACN The data is transmitted back to the SAR ADC via the port to achieve noise shaping.

[0099] The specific descriptions of each module in the architecture are as follows:

[0100] (1) Sampling noise cancellation module SNC (its port V DACP and V DACN (All are bidirectional input / output ports). Since sampling KT / C noise cannot be shaped and is entirely transmitted to the output, a large sampling capacitor is required to reduce it. By using SNC technology to reduce sampling KT / C noise, a smaller sampling capacitor can be tolerated while maintaining the same accuracy requirements, reducing area overhead and making the ADC easier to drive by the preceding circuitry. The SNC technology operates in two stages: "extraction" and "elimination."

[0101] ① Extraction. At switch S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 53 S 54 Disconnect, switch S 27 S 28 S 29 S 30 S 55 S 56 During the closed period, the input signal and the sampled noise voltage pass through V DACP and V DACN The port is passed to amplifier G NC At the input terminal, the input signal and the sampled noise voltage are amplified by amplifier G. NC Amplified and stored in capacitor C SNCN C SNCP middle.

[0102] ② Eliminate. When switch S 19 S 20 S 21 S 22 S 27 S 28 S 29 S 30 S 55 S 56 Disconnect, switch S 23 S 24 S 25 S 26 S 53 S 54 When closed, capacitor C SNCN C SNCP With C SUMN C SUMP Charge sharing is performed, transferring the sampled noise voltage to capacitor C. SUMN C SUMP In the middle, and the capacitor C SUMN C SUMP The sampling noise voltage and V DACP V DACN The sampling noise voltages input from the port are in opposite polarities and can be canceled out.

[0103] Amplifier used in SNC circuits ( Figure 1 The middle is represented as G NC ) is an open-loop FIA, such as Figure 2 As shown, M N1 M N2 M P1 M P2 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage. Its working process is as follows: ① When switch S... 53 S 54 Close, switch S 55 S 56 When disconnected, it is in the reset phase, at which time the energy storage capacitor C... RSV1 ② Charge; ② When switch S 53 S 54 Disconnect, switch S 55 S 56 When closed, it is in the amplification stage. At this time, the power supply is disconnected and the power is supplied through the energy storage capacitor. Therefore, the open-loop FIA works dynamically and has no static current, thus having low power consumption characteristics.

[0104] (2) Residual amplifier (input is V) DACP and V DACN The output is V OPand V ON After the input signal is quantized by the SAR ADC, the residual voltage for the current period is obtained. This voltage is amplified by the residual amplifier and then input into the CIFF and EF noise shaping loops. The residual amplifier circuit consists of a closed-loop cascode FIA ​​(cas-source cascode FIA). Figure 1 The circuit consists of G, switches, and capacitors, and its operation is divided into two stages: ① Switches S7, S8, and S... 11 S 12 S 13 S 14 S 17 S 18 S 31 S 32 S 37 S 38 S 57 S 58 Close the switch, and open the other switches. At this time, capacitor C... FIR1N C FIR1P C FIR2N C FIR2P C RESN C RESP One end is connected to V CM (ADC common-mode voltage) reset; ② Switches S7, S8, S 11 S 12 S 15 S 16 S 31 S 32 S 37 S 38 S 59 S 60 With the switch closed and the other switches open, the residual amplifier amplifies the voltage and stores the amplified residual voltage in capacitor C. FIR1N C FIR1P C FIR2N C FIR2P C RESN C RESP middle.

[0105] Among them, common source common gate FIA ​​( Figure 1 The circuit represented by G is as follows: Figure 3 As shown, M N3 M N4 M P3 M P4 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​(Cascode Acoustic Amplifier) ​​adds a cascode transistor (M... N5 M N6 MP5 M P6 By increasing the output impedance, a high DC gain can be achieved. Therefore, using a cascode FIA ​​as an amplifier in a closed-loop configuration reduces static gain error. Its operation is the same as that of an open-loop FIA and will not be repeated here.

[0106] (3) CIFF noise shaping loop (input is V) OP and V ON The output is V P and V N CIFF noise shaping loop circuit capacitor C RESN C RESP C INT1N C INT1P C INT2_1 C INT2_2 C INT2_3 C INT2_4 The second-order passive IIR filter, formed by the switches, operates as follows: ① Switch S 31 S 32 S 37 S 38 With the switch closed and the other switches open, the amplified residual voltage is stored in capacitor C. RESN C RESP Up; ② Switch S 33 S 34 S 35 S 36 When the switch is closed and the other switches are open, the capacitor C flows through. RESN C RESP and C INT1N C INT1P The first-stage integration is achieved through charge sharing between the two sides; ③ Switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52 Close the switch, open the other switches, and open the capacitor C. INT2_1 C INT2_2 C INT2_3 C INT2_4 Connected in parallel with capacitor C RESN C RESP Charge sharing is performed in a fully differential circuit to achieve the second-stage integration; ④ Switch S 39 S 41 S 44 S 46 S 48 S51 Close the switch, and open the other switches. At this time, capacitor C... INT2_1 C INT2_2 Connected in series to V P Terminal, capacitor C INT2_3 C INT2_4 Connected in series to V N The terminal is used to amplify the second-stage integral voltage by four times, while the capacitor C... INT1P C INT2_1 C INT2_2 Series connection, capacitor C INT1N C INT2_3 C INT2_4 Therefore, the integrating voltages of the first and second stages are both connected in series, so they both pass through V. P and V N Transmitted back to the SAR ADC.

[0107] (4) EF noise shaping loop (input is V) OP and V ON The output is V DACP and V DACN The EF noise shaping loop uses capacitors C with the same capacitance value. FIR1N C FIR1P C FIR2N C FIR2P C DELN C DELP This is a second-order passive finite impulse response (FIR) filter composed of various switches. Its operation is as follows: ① Switches S1 and S2 are closed, and the remaining switches are open, affecting capacitor C... DELN C DELP Reset; ② Close switches S5 and S6, and open the rest of the switches, then open capacitor C. FIR2N C FIR2P The voltage stored in the previous cycle (which is the residual voltage amplified by the residual amplifier in the cycle before that) is transferred to C through charge sharing. DELN C DELP Above; ③ Switches S7, S8, S 11 S 12 With the switch closed and the other switches open, the residual voltage of the previous cycle, amplified by the residual amplifier, is stored in capacitor C. FIR1N C FIR1P and C FIR2N C FIR2P Above; ④ Switches S3, S4, S9, S 10 Close the switch, open the other switches, and open the capacitor C. FIR1N C DELN and C FIR1P C DELP The voltage on each is transferred to V DACNand V DACP port.

Claims

1. A hybrid nested noise shaping architecture suitable for noise-shaping SAR ADCs, characterized in that: The shaping architecture uses a dynamically operating closed-loop cascode FIA ​​as a residual amplifier to reduce power consumption by eliminating the amplifier's quiescent current and removing the gain calibration circuit. The shaping architecture performs fourth-order noise shaping through nested second-order CIFF and second-order EF noise shaping loops to achieve high accuracy in noise shaping at the same oversampling rate. The shaping architecture reduces the capacitance of the sampling capacitor by integrating the sampling noise cancellation (SNC) method to save chip area. The top-level circuit of the shaping architecture includes a CIFF noise shaping loop, an EF noise shaping loop, a residual amplifier, and a sampling noise cancellation module (SNC); the top-level circuit is connected via port V. DACN V DACP Connected to the SAR ADC's capacitive digital-to-analog converter (CDAC) via port V P V N Connected to the comparator of the SAR ADC; The noise shaping workflow of the shaping architecture is as follows: First, the SAR ADC samples the noise voltage through V... DACP and V DACN The signal is passed to the SNC circuit to be canceled out. Then, the current-cycle residual voltage obtained after SAR ADC quantization is input to the hybrid nested noise shaping architecture, amplified by its residual amplifier, and then the amplified residual voltage is input to the CIFF and EF noise shaping loops respectively. Finally, the output voltages of the CIFF and EF noise shaping loops are respectively passed to V... P V N and V DACP V DACN The data is transmitted back to the SAR ADC via the port to achieve noise shaping. The input voltage signal of the residual amplifier is V DACP and V DACN The output is V OP and V ON After the input signal is quantized by the SAR ADC, the residual voltage of the current period is obtained. This residual voltage is amplified by the residual amplifier and then input into the CIFF and EF noise shaping loops. The SNC circuit is independent of the rest of the hybrid nested noise shaping architecture and includes multiple capacitors and switches; In the sampling noise cancellation module (SNC) section of the shaping architecture, if the sampling KT / C noise cannot be shaped, it is all passed to the output terminal. A large sampling capacitor is used to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be used while maintaining the same accuracy requirements, reducing the circuit area overhead and making the ADC easier to be driven by the front-end circuit. The working process of SNC includes an extraction stage and an elimination stage.

2. The hybrid nested noise shaping architecture for noise-shaping SAR ADCs according to claim 1, characterized in that: Amplifier G used in the SNC circuit NC An open-loop FIA architecture is adopted, with M... N× Both represent N-type metal-oxide-semiconductor field-effect transistors (MOS), M P× Both represent P-type metal-oxide-semiconductor field-effect transistors (MOS), among which × Representing any number, in the SNC circuit, M N1 M N2 M P1 M P2 As an input transistor, C is used to invert and amplify the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage; its working process is as follows: ① When it is in the reset phase, the energy storage capacitor C RSV1 Charge; ② When it is in the amplification stage, the power supply is disconnected and the power is supplied through the energy storage capacitor so that the open-loop FIA is in dynamic working condition, and low power consumption is achieved by taking advantage of its characteristic of having no static current.

3. The hybrid nested noise shaping architecture for noise-shaping SAR ADCs according to claim 2, characterized in that: In the extraction phase of the SNC noise cancellation process, the input signal and the sampled noise voltage are processed through V... DACP and V DACN The port is passed to amplifier G NC At the input terminal, the input signal and the sampled noise voltage are amplified by amplifier G. NC Amplified and stored in capacitor C SNCN C SNCP middle; In the noise cancellation phase of the SNC noise cancellation process, capacitor C SNCN C SNCP With C SUMN C SUMP Charge sharing is performed, transferring the sampled noise voltage to capacitor C. SUMN C SUMP In the middle, and the capacitor C SUMN C SUMP The sampling noise voltage and V DACP V DACN The sampling noise voltages input from the port are inversely polar and can be canceled out.

4. The hybrid nested noise shaping architecture for noise-shaping SAR ADCs according to claim 2, characterized in that: The residual amplifier circuit includes a closed-loop cascode FIA, switches, and capacitors. During its operation, in the cascode FIA ​​circuit, M... N3 M N4 M P3 M P4 As an input transistor, C performs the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage; the cascode FIA ​​adds a cascode transistor M. N5 M N6 M P5 M P6 To increase the output impedance and achieve high DC gain, the cascode FIA ​​is used as an amplifier in a closed-loop structure to reduce static gain error, and its operation is the same as that of an open-loop FIA.

5. The hybrid nested noise shaping architecture for noise-shaping SAR ADCs according to claim 4, characterized in that: In the voltage signal of the CIFF noise shaping loop, the input is V. OP and V ON The output is V P and V N CIFF noise shaping loop circuit capacitor C RESN C RESP C INT1N C INT1P C INT2_1 C INT2_2 C INT2_3 C INT2_4 It is composed of a second-order passive IIR filter formed by each switch; The workflow of the CIFF noise shaping loop is as follows: ①Switch S 31 S 32 S 37 S 38 Close, switch S 31 S 32 S 37 S 38 When the other switches of the module to which it belongs are turned off, the amplified residual voltage is stored in capacitor C. RESN C RESP superior; ②Switch S 33 S 34 S 35 S 36 Close, switch S 33 S 34 S 35 S 36 The other switches of the module to which it belongs are off, at which point the capacitor C passes through. RESN C RESP and C INT1N C INT1P Charge sharing between them enables the first-stage integration; ③ Switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52 Close, switch S 31 S 32 S 40 S 42 S 43 S 45 S 47 S 49 S 50 S 52 Disconnect the other switches of the module to which it belongs, and disconnect capacitor C. INT2_1 C INT2_2 C INT2_3 C INT2_4 Connected in parallel with capacitor C RESN C RESP Charge sharing is performed in a fully differential circuit to achieve the second-stage integration; ④ Switch S 39 S 41 S 44 S 46 S 48 S 51 Close the switch, and open the other switches. At this time, capacitor C... INT2_1 C INT2_2 Connected in series to V P Terminal, capacitor C INT2_3 C INT2_4 Connected in series to V N The terminal is used to amplify the second-stage integral voltage by four times, while the capacitor C... INT1P C INT2_1 C INT2_2 Series connection, capacitor C INT1N C INT2_3 C INT2_4 Therefore, the integrating voltages of the first and second stages are both connected in series, so they both pass through V. P and V N Transmitted back to the SAR ADC.

6. The hybrid nested noise shaping architecture for noise-shaping SAR ADCs according to claim 4, characterized in that: In the voltage signal of the EF noise shaping loop, the input is V. OP and V ON The output is V DACP and V DACN ; The EF noise shaping loop uses capacitors C with the same capacitance value. FIR1N C FIR1P C FIR2N C FIR2P C DELN C DELP It is composed of a second-order passive finite impulse response (FIR) filter consisting of various switches; The workflow of the EF noise shaping loop is as follows: ① With switches S1 and S2 closed and the rest of the switches open, capacitor C... DELN C DELP Reset; ② With switches S5 and S6 closed and the rest of the switches open, capacitor C is... FIR2N C FIR2P The voltage stored in the previous cycle, which is the residual voltage amplified by the residual amplifier in the previous cycle, is transferred to capacitor C through charge sharing. DELN C DELP superior; ③ Switches S7, S8, S 11 S 12 With the switch closed and the other switches open, the residual voltage of the previous cycle, amplified by the residual amplifier, is stored in capacitor C. FIR1N C FIR1P and C FIR2N C FIR2P superior; ④ Switches S3, S4, S9, S 10 Close the switch, open the other switches, and open the capacitor C. FIR1N C FIR1P and C DELN C DELP The voltage on is transferred to V DACP and V DACN port.

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