Data acquisition method, chip and electronic equipment

Abstract

The invention relates to the technical field of data acquisition, and discloses a data acquisition method, a chip and electronic equipment. The data acquisition method comprises the steps that a digital control module receives a data acquisition instruction, generates a channel selection signal based on the data acquisition instruction, sends the channel selection signal to an analog-to-digital conversion module, and sends a release signal to a time management unit based on the data acquisition instruction; the time management unit sends a clock control signal to the analog-to-digital conversion module based on the release signal; the analog-to-digital conversion module selects a first channel based on the channel selection signal and acquires first data according to a first acquisition speed corresponding to the clock control signal; and after the acquisition of the first data is completed, switching from the first channel to the second channel based on the channel selection signal, and acquiring the second data according to a second acquisition speed corresponding to the clock control signal. According to the application, the channel connected with the analog-to-digital conversion module is automatically switched according to the data acquired by the analog-to-digital conversion module.

Description

Technical Field

[0001] The present application relates to the field of data acquisition technology, and in particular to a data acquisition method, chip and electronic device. Background Art

[0002] The analog to digital converter (ADC) is an interface circuit between analog circuits and digital circuits. The ADC is used to sample the analog signal input by the analog circuit, obtain the sampled signal, and convert the sampled signal into a digital signal for the digital circuit to read. Among them, the analog signal includes voltage signal, current signal, temperature signal, etc.

[0003] Normally, the ADC can only implement single-channel signal sampling within a time period, for example, the ADC collects voltage signals through the first channel within the time period [12:00, 14:00]. For scenarios where different analog signals need to be collected within a time period, for example, both voltage signals and current signals need to be collected within the time period [12:00, 14:00], the main control (such as a main control chip or a microcontroller) is usually required to switch the sampling channel of the ADC through software programming to collect multiple signals through different channels. For example, after the main control detects that the ADC has completed the collection of the voltage signal collected through the first channel within the time period [12:00, 14:00], it switches the channel connected to the ADC from the first channel to the second channel to collect the current signal through the second channel.

[0004] However, the master control (such as a master control chip or a microcontroller) manually switches the sampling channel of the ADC. For example, the process of the master control switching the sampling channel of the ADC through software programming involves modifying the configuration register of the ADC. If the channel switching operation is too frequent, a large amount of resources will be occupied, thereby reducing the processing efficiency of the master control. Summary of the invention

[0005] In order to automatically switch acquisition channels within a period of time to acquire multiple analog quantities, an embodiment of the present application provides a data acquisition method, a chip, and an electronic device.

[0006] In a first aspect, an embodiment of the present application provides a data acquisition method, which is applied to an electronic device, wherein the electronic device includes an analog-to-digital conversion module and a digital control module, wherein the digital control module includes a state detection unit and a time management unit, and the data acquisition method includes: the state detection unit receives a data acquisition instruction, generates a channel selection signal based on the data acquisition instruction, sends the channel selection signal to the analog-to-digital conversion module, and sends a release signal to the time management unit based on the data acquisition instruction; the time management unit receives the release signal, and sends a clock control signal to the analog-to-digital conversion module based on the release signal, wherein the clock control signal is used to control the acquisition speed of the analog-to-digital conversion module; the analog-to-digital conversion module receives the clock control signal and the channel selection signal, selects the first channel based on the channel selection signal, and acquires the first data at the first acquisition speed corresponding to the clock control signal; and, after completing the acquisition of the first data, switches from the first channel to the second channel based on the channel selection signal and acquires the second data at the second acquisition speed corresponding to the clock control signal.

[0007] The present application sends a channel selection signal to the digital-to-analog conversion module through a state detection unit to switch the channel connected to the digital-to-analog conversion module according to the data collected by the digital-to-analog conversion module, thereby realizing automatic switching of the channel connected to the digital-to-analog conversion module.

[0008] In a possible implementation, the channel selection signal includes a first channel signal and a second channel signal; the method also includes: the digital control module sends the first channel signal to the analog-to-digital conversion module; the analog-to-digital conversion module receives the clock control signal and the first channel signal, selects the first channel based on the first channel signal, and collects first data at a first collection speed corresponding to the clock control signal, and sends the collected first data to the digital control module; after receiving the first data, the digital control module sends the second channel signal to the analog-to-digital conversion module; the analog-to-digital conversion module receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal, and collects second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the digital control module.

[0009] In one possible implementation, when the state detection unit receives the collection data corresponding to the data collection instruction, it sends a shutdown signal to the time management unit, wherein the collection data includes first data and second data, and the shutdown signal is used to instruct the time management unit to stop sending the clock control signal to the analog-to-digital conversion module.

[0010] In a possible implementation, the first channel and the second channel are the same; or, the first channel and the second channel are different.

[0011] In a possible implementation, the data collection instruction includes the conversion times of the channel.

[0012] In a possible implementation, the state detection unit includes a main detection unit and a slave detection unit; the method also includes: the digital control module sends a second channel signal to the analog-to-digital conversion module through the main detection unit; when the analog-to-digital conversion module collects the second data, the digital control module receives a temporary collection instruction from the slave detection unit, generates a temporary channel signal based on the temporary collection instruction, and sends an interrupt signal to the main detection unit; the main detection unit responds to the interrupt signal and sends a pause signal to the analog-to-digital conversion module to stop the analog-to-digital conversion module from collecting the second data, and sends a first start signal to the slave detection unit; the slave detection unit responds to the first start signal and sends the temporary channel signal to the analog-to-digital conversion module; the analog-to-digital conversion module receives the clock control signal and the temporary channel signal, selects a third channel based on the temporary channel signal and collects the third data at a third collection speed corresponding to the clock control signal, and sends the third data to the slave detection unit after completing the collection of the third data.

[0013] In a possible implementation, the method also includes: when the detection unit receives the third data, the detection unit sends a second start signal to the main detection unit; the main detection unit sends a second channel signal to the analog-to-digital conversion module in response to the second start signal; the analog-to-digital conversion module receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal and collects the second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the main detection unit.

[0014] In a possible implementation, the digital control module includes a master detection unit and a slave detection unit, and the method further includes: in response to the master detection unit acquiring the alternating instruction, the master detection unit sends a third start signal to the slave detection unit after receiving the first data; the slave detection unit acquires the third start signal and sends a third channel signal to the analog-to-digital conversion module; the analog-to-digital conversion module receives the clock control signal and the third channel signal, selects the third channel based on the third channel signal, and acquires the third data at a third acquisition speed corresponding to the clock control signal, and sends the acquired third data to the slave detection unit; the slave detection unit acquires the third data and sends a fourth start signal to the master detection unit; the master detection unit acquires the fourth start signal and sends a second channel signal to the analog-to-digital conversion module; the analog-to-digital conversion module receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal, and acquires the second data at a second acquisition speed corresponding to the clock control signal, and sends the acquired second data to the master detection unit.

[0015] In one possible implementation, both the master detection unit and the slave detection unit include a monitoring unit, which is used to generate an alarm signal when detecting the data sent by the analog-to-digital conversion module, corresponding to an alarm threshold of determining that the data sent by the analog-to-digital conversion module is greater than the data sent by the analog-to-digital conversion module.

[0016] In a second aspect, an embodiment of the present application provides a chip, which includes a processor and a data interface. The processor reads instructions stored in a memory through the data interface to execute any data acquisition method provided by the first aspect and various possible implementations of the first aspect.

[0017] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory for storing instructions executed by one or more processors of the electronic device; and a processor, which is one of the processors of the electronic device, for executing the instructions stored in the memory to implement any data acquisition method provided by the first aspect and various possible implementations of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A structural schematic diagram of a data acquisition system is shown;

[0019] Figure 2a According to an embodiment of the present application, a structural schematic diagram of a data acquisition system is shown;

[0020] Figure 2b According to an embodiment of the present application, a structural schematic diagram of another data acquisition system is shown;

[0021] Figure 3a According to an embodiment of the present application, a structural schematic diagram of an ADC controller is shown;

[0022] Figure 3b According to an embodiment of the present application, a structural schematic diagram of an ADC controller is shown;

[0023] Figure 4 According to an embodiment of the present application, a schematic diagram of changes in the working state of a finite state machine (FSM) of an ADC controller is shown;

[0024] Figure 5 According to an embodiment of the present application, a flow chart of a data collection method is shown;

[0025] Figure 6 According to an embodiment of the present application, a flow chart of another data collection method is shown;

[0026] Figure 7 According to an embodiment of the present application, a flow chart of another data collection method is shown;

[0027] Figure 8a to Figure 8h According to an embodiment of the present application, a schematic diagram of the timing of each module acquiring a signal during data acquisition is shown;

[0028] Fig. 9 According to an embodiment of the present application, a structural schematic diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0029] The following first introduces the ADC sampling process.

[0030] like Figure 1 As shown, the input / output (IOs) is connected to a first end of a multiplexer (MUX), a second end of the MUX is connected to a first end of an analog-to-digital converter (AnalogADC), a second end of the analog-to-digital converter is connected to a first end of a digital core, and a second end of the digital core is connected to an interrupt pin (PAD_INT).

[0031] Among them, IOs are used to connect different analog signals. MUX is used to obtain the selection signal sent by the analog-to-digital converter, and selects a channel from multiple IOs pins according to the selection signal sent by the analog-to-digital converter to sample the analog signal, and sends the sampled analog signal to the analog-to-digital converter. Exemplarily, MUX can switch between multiple IOs pins according to the selection signal sent by the analog-to-digital converter, so as to sample analog signals of different channels. Further, the analog-to-digital converter converts the analog signal sent by MUX into a digital signal and sends it to the digital core, so that the digital core can further process and analyze the digital signal. The interrupt pin is used to send a read signal to the master control so that the master control reads the collected signal.

[0032] Specifically, Figure 1 As shown, the digital core includes a central processing unit (CPU), a static random access memory (SRAM), an ADC controller (ADCCTRL), a direct memory access (DMA), and a clock management unit (CMU). The CPU, SRAM, ADC controller, DMA, and CMU transmit corresponding data to each other through an advanced peripheral bus (APB BUS).

[0033] The CPU is used to obtain the selection signal sent by the external master control and send the selection signal to the ADC controller. The CMU is responsible for the generation, distribution and control of the clock signal. For example, the CMU can generate a clock signal for controlling the state of the digital-to-analog converter and send the clock signal to the ADC controller.

[0034] The ADC controller is used to obtain the selection signal sent by the CPU and send the selection signal to the digital-to-analog converter; obtain and store the digital signal sent by the digital-to-analog converter; obtain the clock signal sent by the CMU, and control the state of the digital-to-analog converter based on the clock signal to ensure that the digital-to-analog converter samples and converts at a predetermined rate; for example, the ADC controller can configure the digital-to-analog converter to be in an idle (IDLE) state, a setup (SETUP) state, and an enabled (ENABLE) state; wherein, when the digital-to-analog converter is in an idle state, the digital-to-analog converter waits for the clock signal to start a new conversion cycle; when the digital-to-analog converter is in a setup state, the digital-to-analog converter prepares to start sampling according to the clock signal; when the digital-to-analog converter is in an enabled state, the digital-to-analog converter has started sampling and is converting the collected analog signal into a digital signal.

[0035] DMA is used to obtain the digital signal stored in the ADC controller and send the digital signal to SRAM. SRAM is used to store the digital signal sent by DMA.

[0036] Understandably, Figure 1 In the structure shown, the CPU can obtain the selection signal sent by the external master control and send the selection signal to the ADC controller. The CMU can generate a clock signal and send the clock signal to the ADC controller. The ADC controller can send the selection signal and the clock signal to the digital-to-analog converter. The digital-to-analog converter can switch from an idle state to a set state based on the clock signal, and the digital-to-analog converter can send the selection signal to the MUX. The MUX can select an analog signal of a channel from multiple IOs pins according to the selection signal sent by the digital-to-analog converter, and send the analog signal to the digital-to-analog converter. The digital-to-analog converter can switch from a set state to an enabled state based on the clock signal, collect analog signals based on the clock signal, convert the collected analog signals into digital signals, and send the digital signals to the ADC controller. The ADC controller obtains and stores digital signals. The DMA obtains the digital signals stored by the ADC controller and sends the digital signals to the SRAM to store the digital signals sent by the DMA through the SRAM. In some embodiments, the digital signal can also be stored at a specific address through the DMA, and then the master control is notified to read the conversion result through the interrupt pin.

[0037] In order to automatically switch the acquisition channel within a period of time to collect multiple analog quantities, an embodiment of the present application provides a data acquisition method, which includes: pre-setting a state detection unit and a time management unit in an ADC controller. The state detection unit obtains a selection signal sent by the main control, generates an acquisition signal of at least one acquisition channel based on the selection signal, and sends a release signal to the time management unit. The time management unit sends a clock control signal to an analog-to-digital conversion module (or analog-to-digital converter) based on the release signal, and the analog-to-digital conversion module selects a channel based on the acquisition signal of at least one acquisition channel and collects data at the acquisition speed corresponding to the clock control signal.

[0038] For example, for a scenario where both voltage signals and current signals need to be collected within the time period [12:00, 14:00], the state detection unit obtains the selection signal for collecting voltage signals and current signals sent by the master control, generates voltage collection signals and current collection signals based on the selection signal, and sends a release signal to the time management unit. The state detection unit sends a voltage collection signal to the analog-to-digital conversion module, and the time management unit sends a clock control signal to the analog-to-digital conversion module based on the release signal. The analog-to-digital conversion module connects the collection channel of the voltage signal based on the voltage collection signal, and collects the voltage signal based on the first collection speed corresponding to the clock control signal. After the state detection unit detects that the analog-to-digital conversion module has completed the collection of the voltage signal, it sends a current collection signal to the analog-to-digital conversion module, so that the analog-to-digital conversion module connects the collection channel of the current signal, and collects the current signal based on the second collection speed corresponding to the clock control signal. After the state detection unit detects that the analog-to-digital conversion module has completed the collection of the current signal, it controls the analog-to-digital conversion module to enter an idle state.

[0039] In this way, the state detection unit can switch the channel connected to the analog-to-digital conversion module according to the data collected by the analog-to-digital conversion module, thereby realizing the need for the main control to manually switch the sampling channel of the ADC, and realizing automatic switching of the channel connected to the analog-to-digital conversion module, avoiding modification of the configuration register of the ADC and improving the processing efficiency of the main control.

[0040] In the embodiment of the present application, in order to improve the sampling accuracy of the analog-to-digital conversion module, ADC_CMU can be set in the ADC controller to monitor the working state of the ADC controller through ADC_CMU, and generate a PCLK_GATE signal when it is determined that the ADC controller is in the working state. In this way, ADC_CMU can directly obtain the working state of the ADC controller, generate a PCLK_GATE signal when the ADC controller is working, avoid the time lag between the WORK_STATE signal and the PCLK_GATE signal, that is, avoid the time lag between the WORK_STATE signal and the PCLK_DIV signal, avoid the deviation of the analog-to-digital conversion module during the sampling process, and improve the sampling accuracy of the analog-to-digital conversion module.

[0041] The data acquisition method provided in the embodiment of the present application can be applied to a data acquisition system. The structure of the data acquisition system is as follows: Figure 2a As shown, it includes a signal acquisition module 100, an analog-to-digital conversion module 200 and a digital core module 300. The function and structure of each module are introduced below.

[0042] The signal acquisition module 100 is used to obtain the selection signal sent by the analog-to-digital conversion module 200, and select a channel from multiple IOs pins to sample the analog signal according to the selection signal sent by the analog-to-digital conversion module 200, and send the sampled analog signal to the analog-to-digital conversion module 200. In some embodiments, the signal acquisition module 100 includes a MUX.

[0043] The analog-to-digital conversion module 200 is used to obtain the selection signal sent by the digital core module 300 and send the selection signal to the signal acquisition module 100; it is also used to convert the analog signal into a digital signal after obtaining the analog signal sent by the signal acquisition module 100, and send the digital signal to the digital core module 300. In some embodiments, the analog-to-digital conversion module 200 includes an analog-to-digital converter.

[0044] The digital core module 300 is used to send a selection signal and a PCLK_DIV signal to the analog-to-digital converter 200; and is also used to obtain and store the digital signal sent by the analog-to-digital conversion module 200. The digital core module 300 includes a digital control module 30A, and the digital control module 30A includes a state detection unit 301 and a time management unit 302; wherein the state detection unit 301 is used to receive instructions, such as data acquisition instructions; and is also used to receive data corresponding to the instructions, such as the collected data of the data acquisition instructions.

[0045] In the embodiments of the present application, Figure 2b As shown, the state detection unit 301 includes a master detection unit 3011 and a slave detection unit 3012. The master detection unit 3011 includes a monitoring unit 30111, and the slave detection unit 3012 includes a monitoring unit 30121. In some embodiments, the digital core module 300 also includes a CPU, SRAM, DMA, CMU, and the like.

[0046] It can be understood that the state detection unit 301 receives the data acquisition instruction and sends a release signal to the time management unit 302 based on the data acquisition instruction, wherein the release signal is used to instruct the time management unit 302 to release the PCLK_GATE signal and the PCLK_DIV signal. After the time management unit 302 releases the PCLK_GATE signal and the PCLK_DIV signal, the PCLK_GATE signal and the PCLK_DIV signal can be sent to the state detection unit 301, and the state detection unit 301 works based on the PCLK_GATE signal and sends the PCLK_DIV signal to the analog-to-digital conversion module 200, wherein the PCLK_DIV signal is used to control the acquisition speed of the analog-to-digital conversion module 200.

[0047] When receiving the acquisition data corresponding to the data acquisition instruction, the state detection unit 301 sends a shutdown signal to the time management unit 302, wherein the shutdown signal is used to instruct the time management unit 302 to stop releasing the PCLK_GATE signal and the PCLK_DIV signal. When the time management unit 302 stops releasing the PCLK_GATE signal and the PCLK_DIV signal, the state detection unit 301 stops sending the PCLK_DIV signal to the analog-to-digital conversion module 200.

[0048] Combine the following Figure 3a and Figure 3b The structure of the digital control module 30A will be described.

[0049] like Figure 3a As shown, the main detection unit 3011 (Main_Ctrl) includes a monitoring unit 30111. In some embodiments, as Figure 3b As shown, the monitoring unit 30111 includes a watchdog 1 (WatchDog1), and the main detection unit 3011 also includes a data processing unit 30112 and a state switching unit 30113. In some embodiments, as Figure 3bAs shown, the data processing unit 30112 includes a data trigger type trigger 1 (Data Flip-Flop1, Data DFF1), and the state switching unit 30113 includes a main finite state machine (Main-FSM). Among them, DataDFF1 is used to obtain and store the data sent by the analog-to-digital conversion module 200. WatchDog1 is used to determine whether the data sent by the analog-to-digital conversion module 200 is greater than the alarm threshold of the data sent by the analog-to-digital conversion module 200 when detecting the data sent by the analog-to-digital conversion module 200; if it is determined that the data sent by the analog-to-digital conversion module 200 is greater than the alarm threshold of the data sent by the analog-to-digital conversion module 200, an alarm signal is generated and sent to the main control via APBBUS. Main-FSM is used to determine the next state according to the preset conversion rules and the current state; Main-FSM can switch from one state to another according to the input signal or event. Among them, the conversion rules of Main-FSM are introduced below.

[0050] The slave detection unit 3012 (Sub_Ctrl) includes a monitoring unit 30121. In some embodiments, Figure 3b As shown, the monitoring unit 30121 includes a watchdog 2 (WatchDog2), and the detection unit 3012 also includes a data processing unit 30122 and a state switching unit 30123. Figure 3b As shown, the data processing unit 30122 includes a data-triggered trigger 2 (Data Flip-Flop1, Data DFF2), and the state switching unit 30123 includes a sub-finite state machine (Sub-FSM). Among them, DataDFF2 is used to obtain and store the data sent by the analog-to-digital conversion module 200. WatchDog2 is used to determine whether the data sent by the analog-to-digital conversion module 200 is greater than the alarm threshold of the data sent by the analog-to-digital conversion module 200 when detecting the data sent by the analog-to-digital conversion module 200; if it is determined that the data sent by the analog-to-digital conversion module 200 is greater than the alarm threshold of the data sent by the analog-to-digital conversion module 200, an alarm signal is generated and sent to the main control through the APB BUS to respond to abnormal situations more quickly and accurately and reduce the impact of the accident. Sub-FSM is used to determine the next state according to the preset conversion rules and the current state; Sub-FSM can switch from one state to another according to the input signal or event. Among them, the conversion rules of Sub-FSM are introduced below.

[0051] It can be understood that in the embodiment of the present application, a sampling channel group of the main detection unit 3011 and the sampling channel group of the slave detection unit 3012 can be set, and the sampling channel group of the main detection unit 3011 and the sampling channel group of the slave detection unit 3012 each include at least one channel, and the channels in the sampling channel group of the main detection unit 3011 and the channels in the sampling channel group of the slave detection unit 3012 can be the same or different.

[0052] For example, the sampling channel group of the main detection unit 3011 includes one channel, the sampling channel group of the slave detection unit 3012 includes one channel, and the channel of the sampling channel group of the main detection unit 3011 is the same as the channel of the sampling channel group of the slave detection unit 3012. For example, the sampling channel group of the main detection unit 3011 includes channel 1 (Channel-1), and the sampling channel group of the slave detection unit 3012 includes Channel-1.

[0053] For another example, the sampling channel group of the main detection unit 3011 includes one channel, and the sampling channel group of the slave detection unit 3012 includes one channel, and the channels of the sampling channel group of the main detection unit 3011 and the channels of the sampling channel group of the slave detection unit 3012 are different. For example, the sampling channel group of the main detection unit 3011 includes Channel-1, and the sampling channel group of the slave detection unit 3012 includes Channel 2 (Channel-2).

[0054] For another example, the sampling channel group of the main detection unit 3011 includes multiple channels, and the sampling channel group of the slave detection unit 3012 includes multiple channels, and the channels of the sampling channel group of the main detection unit 3011 are different from the channels of the sampling channel group of the slave detection unit 3012. For example, the sampling channel group of the main detection unit 3011 includes Channel-1, Channel-2, and Channel 3 (Channel-3), and the sampling channel group of the slave detection unit 3012 includes Channel-3, Channel 4 (Channel-4), Channel 5 (Channel-5), and Channel 6 (Channel-6).

[0055] For another example, the sampling channel group of the main detection unit 3011 includes multiple channels, the sampling channel group of the slave detection unit 3012 includes multiple channels, and the channels of the sampling channel group of the main detection unit 3011 and the channels of the sampling channel group of the slave detection unit 3012 are the same. For example, the sampling channel group of the main detection unit 3011 includes Channel-1, Channel-2, and Channel-3, and the sampling channel group of the slave detection unit 3012 includes Channel-1, Channel-2, and Channel-3.

[0056] The time management unit 302 includes a clock gating unit 3021 and a clock frequency dividing unit 3022. Figure 3b As shown, the clock gating unit 3021 includes GATE, and the clock frequency dividing unit 3022 includes CLK_DIV. GATE is used to obtain the PCLK signal and monitor the working status of the main detection unit 3011 and the slave detection unit 3012. When it is determined that the main detection unit 3011 or the slave detection unit 3012 is working, the PCLK_GATE signal is generated; wherein the PCLK_GATE signal is the clock signal required when the main detection unit 3011 and the slave detection unit 3012 are working. CLK_DIV is used to obtain the PCLK_GATE signal, and generate the PCLK_DIV signal required for the operation of the digital-to-analog conversion module 200 based on the PCLK_GATE signal.

[0057] It can be understood that setting the GATE inside the CMU will occupy the external chip volume, complicate the design, and require the formation of an independent control module; while setting the GATE inside the time management unit 302 can reduce the volume, form a small module inside, and have better controllability.

[0058] like Figure 3a As shown, the digital control module 30A (or ADC_Ctrl) further includes a start module 303 (Start), which is used to obtain instructions sent by the APB BUS, such as data acquisition instructions, and send the instructions to the state detection unit 301. It can be understood that if the start module 303 determines that the execution object corresponding to the instruction is the main detection unit 3011 (Main_Ctrl), the instruction is sent to the main detection unit 3011; if the start module 303 determines that the execution object corresponding to the instruction is the slave detection unit 3012 (Sub_Ctrl), the instruction is sent to the slave detection unit 3012.

[0059] It can be understood that both Main-FSM and Sub-FSM include the ready state (IDLE), the start state (STUP), the sampling state (SMPL), the conversion state (CONV) and the single cycle end state (EOC), and the conversion rules of Main-FSM and Sub-FSM are the same. Figure 4 This section introduces the transition rules of the Main-FSM state.

[0060] It is understood that when there is no clock signal in the digital control module 30A and the digital control module 30A is waiting for the instruction of the APB BUS, the Main-FSM is in the IDLE state. When the Main-FSM receives an instruction, such as a data acquisition instruction, the Main-FSM starts, sends a release signal to the time management unit 302, and enters the STUP state. It is understood that when the Main-FSM enters the STUP state, the Main-FSM sends a channel selection signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 is connected to the channel corresponding to the channel selection signal, and the capacitor of the analog-to-digital conversion module 200 starts to charge.

[0061] After the capacitor of the analog-to-digital conversion module 200 is charged, the analog-to-digital conversion module 200 sends a charging completion signal to the Main-FSM. The Main-FSM receives the charging completion signal and enters the SMPL state. After the analog-to-digital conversion module 200 completes sampling, it sends the collected data to DATADFF1. The Main-FSM detects that DATADFF1 has obtained the data and enters the CONV state. Among them, DATADFF1 can perform serial-to-parallel conversion on the collected data to convert the collected data from a 1-bit signal to multi-bit register data.

[0062] After DATADFF1 converts the collected data into multi-bit register data, Main-FSM determines whether there are unsampled channels based on the preset sampling channel group. If the judgment result is yes, it jumps to the SMPL state and sends a signal of the unsampled channel to the analog-to-digital conversion module 200 to switch the analog-to-digital conversion module 200 to the unsampled channel; if the judgment result is no, it jumps to the IDLE state and sends a shutdown signal to the time management unit 302.

[0063] Figure 5 According to an embodiment of the present application, a schematic diagram of a data collection method is shown. It can be understood that Figure 5 The execution subject of the schematic diagram shown is an electronic device 100, which has Figure 3b To simplify the description, Figure 5 The execution subject of each step will not be described repeatedly in the schematic diagram shown. Figure 5 As shown, the data collection method includes:

[0064] 101: The state detection unit 301 receives a data acquisition instruction, generates a channel selection signal based on the data acquisition instruction, sends the channel selection signal to the analog-to-digital conversion module 200, and sends a release signal to the time management unit 302 based on the data acquisition instruction.

[0065] In an embodiment of the present application, after receiving a data acquisition instruction, the state detection unit 301 of the digital control module 30A can generate a channel selection signal based on the data acquisition instruction, for example, generate a first channel signal and a second channel signal based on the data acquisition instruction, and the state detection unit 301 of the digital control module 30A can first send the first channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 selects the first channel based on the received first channel signal to collect the first data, and the analog-to-digital conversion module 200 can send the collected first data to the state detection unit 301 of the digital control module 30A; after receiving the first data, the state detection unit 301 of the digital control module 30A sends the second channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 selects the second channel based on the received second channel signal to collect the second data, and sends the collected second data to the state detection unit 301 of the digital control module 30A. The state detection unit 301 may also send a release signal to the time management unit 302 based on the data acquisition instruction, wherein the release signal is used to instruct the time management unit 302 to release the PCLK_GATE signal and the PCLK_DIV signal.

[0066] In the embodiment of the present application, the first channel and the second channel are the same, for example, the first channel and the second channel are both Channel-1. In other embodiments, the first channel and the second channel are different, for example, the first channel is Channel-1 and the second channel is Channel-2; for another example, the first channel is Channel-3 and the second channel is Channel-4.

[0067] In some embodiments, the CPU in the digital control module 30A can obtain the data acquisition instruction sent by the external master control, and send it to the Start of the digital control module 30A through the APB BUS, and Start can send the data acquisition instruction to the state detection unit 301. The state detection unit 301 generates a channel selection signal based on the data acquisition instruction, and sends the channel selection signal to the analog-to-digital conversion module 200. Among them, the data acquisition instruction includes an execution object and the number of conversions of the channel, and Start can send the data acquisition instruction to the corresponding unit according to the execution object included in the data acquisition instruction.

[0068] For example, if the startup module 303 determines that the execution object corresponding to the data acquisition instruction is the master detection unit 3011, the data acquisition instruction is sent to the master detection unit 3011 of the state detection unit 301, so that the master detection unit 3011 generates a channel selection signal based on the data acquisition instruction, and sends the channel selection signal to the analog-to-digital conversion module 200. If the startup module 303 determines that the execution object corresponding to the instruction is the slave detection unit 3012 of the state detection unit 301, the data acquisition instruction is sent to the slave detection unit 3012, so that the slave detection unit 3012 generates a channel selection signal based on the data acquisition instruction, and sends the channel selection signal to the analog-to-digital conversion module 200.

[0069] In an embodiment of the present application, the method for the state detection unit 301 to generate a channel selection signal based on a data acquisition instruction includes: when the main detection unit 3011 obtains the data acquisition instruction, the channel selection signal is generated based on the sampling channel group pre-set in the main detection unit 3011; when the slave detection unit 3012 obtains the data acquisition instruction, the channel selection signal is generated based on the sampling channel group pre-set in the slave detection unit 3012.

[0070] For example, if the sampling channel group pre-set in the main detection unit 3011 includes the first channel, and the number of conversions of the channel included in the data acquisition instruction is 2, the main detection unit 3011 can generate a first channel signal, and send the first channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 selects the first channel to collect the first data. The analog-to-digital conversion module 200 selects the first channel to collect the first data based on the received first channel signal, and sends the collected first data to the main detection unit 3011. After receiving the first data, the main detection unit 3011 sends the first channel signal to the analog-to-digital conversion module 200 again, so that the analog-to-digital conversion module 200 selects the first channel to collect the first data again.

[0071] For another example, the sampling channel group pre-set in the main detection unit 3011 includes a first channel and a second channel, then the main detection unit 3011 can generate a first channel signal, and send the first channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 selects the first channel to collect the first data. The analog-to-digital conversion module 200 selects the first channel to collect the first data based on the received first channel signal, and sends the collected first data to the main detection unit 3011. After receiving the first data, the main detection unit 3011 sends a second channel signal to the analog-to-digital conversion module 200; so that the analog-to-digital conversion module 200 selects the second channel to collect the second data.

[0072] In the embodiment of the present application, the main detection unit 3011 includes a monitoring unit 30111, and the slave detection unit 3012 includes a monitoring unit 30121. When the monitoring unit 30111 and the monitoring unit 30121 detect the data sent by the analog-to-digital conversion module 200, they can determine whether the data sent by the analog-to-digital conversion module 200 is greater than the alarm threshold corresponding to the data sent by the analog-to-digital conversion module 200, and if it is determined that the data sent by the analog-to-digital conversion module 200 is greater than the alarm threshold of the data sent by the analog-to-digital conversion module 200, an alarm signal is generated, and the alarm signal is sent to the master control through the APB BUS, so as to respond to abnormal situations more quickly and accurately and reduce the impact range of the accident.

[0073] 102 : The time management unit 302 receives the release signal, and sends a clock control signal to the analog-to-digital conversion module 200 based on the release signal, wherein the clock control signal is used to control the acquisition speed of the analog-to-digital conversion module 200 .

[0074] In the embodiment of the present application, the clock control signal includes a PCLK_DIV signal, and the PCLK_DIV signal is used to control the acquisition speed of the analog-to-digital conversion module 200 .

[0075] 103: The analog-to-digital conversion module 200 receives a clock control signal and a channel selection signal, selects a first channel based on the channel selection signal, and collects first data at a first collection speed corresponding to the clock control signal; and after completing the collection of the first data, switches from the first channel to the second channel based on the channel selection signal, and collects second data at a second collection speed corresponding to the clock control signal.

[0076] In the embodiment of the present application, the channel selection signal includes a first channel signal and a second channel signal. The analog-to-digital conversion module 200 can select the first channel based on the received channel selection signal and collect the first data at the first collection speed corresponding to the clock control signal, and send the collected first data to the state detection unit 301 after completing the collection of the first data. The state detection unit 301 sends the second channel signal to the analog-to-digital conversion module 200. After receiving the second channel signal, the analog-to-digital conversion module 200 switches to the second channel and collects the second data at the second collection speed corresponding to the clock control signal, and sends the collected second data to the state detection unit 301 after completing the collection of the second data. In the embodiment of the present application, the first collection speed and the second collection speed are the same; in other embodiments, the first collection speed and the second collection speed are different.

[0077] It can be understood that if the channel selection signal received by the analog-to-digital conversion module 200 is sent by the main detection unit 3011, the collected data will be sent to the main detection unit 3011; if the channel selection signal received by the analog-to-digital conversion module 200 is sent by the slave detection unit 3012, the collected data will be sent to the slave detection unit 3012.

[0078] In this way, the state detection unit 301 can switch the channel connected to the digital-to-analog conversion module 200 according to the data collected by the digital-to-analog conversion module 200, thereby eliminating the need for the main control to manually switch the sampling channel connected to the digital-to-analog conversion module 200, and automatically switching the channel connected to the digital-to-analog conversion module 200, thereby avoiding modification of the ADC configuration register and improving the processing efficiency of the main control.

[0079] The following describes an embodiment of the present application by taking the example of the main monitoring unit 3011 receiving a data collection instruction.

[0080] Figure 6 According to an embodiment of the present application, a schematic diagram of another data collection method is shown. It can be understood that Figure 6 The execution subject of the schematic diagram shown is an electronic device 100, which has Figure 3b To simplify the description, Figure 6 The execution subject of each step will not be described repeatedly in the schematic diagram shown. Figure 6 As shown, the data collection method includes:

[0081] 201 : The digital control module 30A sends a second channel signal to the analog-to-digital conversion module 200 through the main detection unit 3011 .

[0082] In the embodiment of the present application, if the sampling channel group corresponding to the main detection unit 3011 includes the first channel and the second channel, the main detection unit 3011 can first send the first channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 selects the first channel to collect the first data. After the main detection unit 3011 obtains the first data, it sends the second channel signal to the analog-to-digital conversion module 200.

[0083] 202 : When the analog-to-digital conversion module 200 collects the second data, the digital control module 30A receives a temporary collection instruction from the detection unit 3012 , generates a temporary channel signal based on the temporary collection instruction, and sends an interrupt signal to the main detection unit 3011 .

[0084] In the embodiment of the present application, the CPU of the digital core module 300 receives the temporary acquisition instruction sent by the master control, and sends the temporary acquisition instruction to the Start of the digital control module 30A through the APB BUS. The Start determines that the execution object is the slave detection unit 3012 based on the temporary acquisition instruction, and sends the temporary acquisition instruction to the slave detection unit 3012. When the slave detection unit 3012 receives the temporary acquisition instruction, it generates a temporary channel signal based on the temporary acquisition instruction, and sends an interrupt signal to the master detection unit 3011.

[0085] For example, the number of conversions corresponding to the temporary acquisition instruction is 1, and the sampling channel group of the slave detection unit 3012 includes Channel-3. When the slave detection unit 3012 receives the temporary acquisition instruction, it generates a third channel signal and sends an interrupt signal to the main detection unit 3011, so that the main detection unit 3011 sends a pause signal to the analog-to-digital conversion module.

[0086] 203 : In response to the interrupt signal, the master detection unit 3011 sends a pause signal to the analog-to-digital conversion module to make the analog-to-digital conversion module stop collecting the second data, and sends a first start signal to the slave detection unit 3012 .

[0087] 204 : The detection unit 3012 sends the temporary channel signal to the analog-to-digital conversion module 200 in response to the first start signal.

[0088] For example, if the temporary channel signal includes a third channel signal, after the detection unit 3012 obtains the first start signal, the third channel signal is sent to the analog-to-digital conversion module 200 so that the analog-to-digital conversion module 200 selects the third channel based on the third channel signal to collect the third data.

[0089] 205: The analog-to-digital conversion module 200 receives the clock control signal and the temporary channel signal, selects the third channel based on the temporary channel signal and collects the third data at the third collection speed corresponding to the clock control signal, and sends the third data to the slave detection unit 3012 after completing the collection of the third data.

[0090] In an embodiment of the present application, the third acquisition speed is the same as the first acquisition speed and the second acquisition speed; in other embodiments, the third acquisition speed is different from the first acquisition speed and the second acquisition speed.

[0091] 206 : When receiving the third data, the slave detection unit 3012 sends a second start signal to the master detection unit 3011 .

[0092] In an embodiment of the present application, if the temporary channel signal includes a third channel signal, when the slave detection unit 3012 receives the third data, it sends a second start signal to the main detection unit 3011, so that the main detection unit 3011 sends a channel switching signal to the analog-to-digital conversion module 200.

[0093] In other embodiments, if the temporary channel signal includes acquisition signals of multiple channels, after the detection unit 3012 obtains the sampling data of all channels included in the temporary channel signal, it sends a second start signal to the main detection unit 3011, so that the main detection unit 3011 sends a channel switching signal to the analog-to-digital conversion module 200.

[0094] For example, if the temporary channel signal includes a third channel signal and a fourth channel signal, after the slave detection unit 3012 obtains the first start signal, the third channel signal is sent to the analog-to-digital conversion module 200 so that the analog-to-digital conversion module 200 selects the third channel based on the third channel signal to collect the third data. After obtaining the third data, the slave detection unit 3012 sends the fourth channel signal to the analog-to-digital conversion module 200 so that the analog-to-digital conversion module 200 selects the fourth channel based on the fourth channel signal to collect the fourth data. After obtaining the fourth data, the slave detection unit 3012 sends a second start signal to the main detection unit 3011 so that the main detection unit 3011 sends a channel switching signal to the analog-to-digital conversion module 200.

[0095] 207 : The main detection unit 3011 sends a second channel signal to the analog-to-digital conversion module 200 in response to the second start signal.

[0096] In an embodiment of the present application, if the channel selection signal of the main detection unit 3011 includes a first channel signal and a second channel signal, the main detection unit 3011 obtains a second start signal and determines that the first data of the first channel has been collected, and then sends a second channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 selects the second channel based on the received second channel signal to collect the second data.

[0097] 208 : The analog-to-digital conversion module 200 receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal and collects second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the main detection unit 3011 .

[0098] In an embodiment of the present application, in the process of the analog-to-digital conversion module 200 collecting data based on the channel selection signal sent by the main detection unit 3011, in the scenario where it is necessary to temporarily collect data of a channel not included in the main detection unit 3011, the master control can send a temporary collection instruction to the slave detection unit 3012, so that the slave detection unit 3012 generates a temporary channel signal based on the temporary collection instruction, so that the analog-to-digital conversion module 200 collects data based on the temporary channel signal, and after collecting the data of the channel corresponding to the temporary channel signal, switches to the channel originally connected to the analog-to-digital conversion module 200 to collect data.

[0099] Figure 7 According to an embodiment of the present application, a schematic diagram of another data collection method is shown. It can be understood that Figure 7 The execution subject of the schematic diagram shown is an electronic device 100, which has Figure 3b To simplify the description, Figure 7 The execution subject of each step will not be described repeatedly in the schematic diagram shown. Figure 7 As shown, the data collection method includes:

[0100] 301 : in response to the master detection unit 3011 acquiring the alternation instruction, the master detection unit 3011 sends a third start signal to the slave detection unit 3012 after receiving the first data.

[0101] It can be understood that the alternating instruction is used to control the main detection unit 3011 and the slave detection unit 3012 to alternately send channel switching signals to the analog-to-digital conversion module 200.

[0102] For example, the sampling channel group of the main detection unit 3011 includes Channel-1 and Channel-2, and the sampling channel group of the slave detection unit 3012 includes Channel-3. Then, the main detection unit 3011 obtains the alternation instruction and sends the first channel signal to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 collects the first data of the first channel based on the first channel signal. After obtaining the first data, the main detection unit 3011 sends a third start signal to the slave detection unit 3012, so that the slave detection unit 3012 sends the third channel signal to the analog-to-digital conversion module 200.

[0103] 302 : Obtain a third start signal from the detection unit 3012 , and send a third channel signal to the analog-to-digital conversion module 200 .

[0104] 303: The analog-to-digital conversion module 200 receives the clock control signal and the third channel signal, selects the third channel based on the third channel signal and collects third data at a third collection speed corresponding to the clock control signal, and sends the collected third data to the slave detection unit 3012.

[0105] 304 : The slave detection unit 3012 obtains the third data and sends a fourth start signal to the main detection unit 3011 .

[0106] 305 : The main detection unit 3011 obtains the fourth start signal and sends the second channel signal to the analog-to-digital conversion module 200 .

[0107] It can be understood that the fourth start signal is used to enable the main detection unit 3011 to send a switching signal of a channel that has not been collected to the analog-to-digital conversion module 200.

[0108] For example, the sampling channel group of the main detection unit 3011 includes a first channel and a second channel. The main detection unit 3011 obtains the fourth start signal and determines that the first data of the first channel has been collected, and then sends a second channel signal to the analog-to-digital conversion module 200 to enable the analog-to-digital conversion module 200 to collect the second data of the second channel.

[0109] 306 : The analog-to-digital conversion module 200 receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal and collects second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the main detection unit 3011 .

[0110] In the embodiment of the present application, an alternating instruction is sent to the main detection unit 3011 so that the main detection unit 3011 and the slave detection unit 3012 alternately send channel switching signals to the analog-to-digital conversion module.

[0111] To make the purpose, technical solution and advantages of this application clearer, the following takes different types of sampling channel groups as examples, combined with the attached Figure 8a to Figure 8h The technical solutions in the embodiments of the present application are described clearly and in detail. It can be understood that if the number of channel conversions is m, and the sampling channel group includes n channels, then the sampling number of the sampling channel group = m / n.

[0112] The following first introduces the method of converting the same channel once during data acquisition. Figure 8a As shown, if the execution object corresponding to the data acquisition instruction is the main detection unit 3011, the channel conversion number is 1, for example, the data acquisition instruction is a Start-Main signal, and the acquisition channel group preset by the main detection unit 3011 includes Channel-1, then Figure 8aAs shown, the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, and the Main-FSM switches from the IDLE state to the STUP state. The Main-FSM sends the sampling signal (SAMPLE) of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM. The Main-FSM determines that the data corresponding to the Start-Main signal has been collected based on the Start-Main signal and the preset collection channel group, and the Main-FSM switches to the IDLE state. Among them, the process of the Main-FSM switching from the STUP state to the EOC state can be seen in Figure 4 The embodiments shown will not be described in detail here.

[0113] The following is an introduction to the method of continuously converting the same channel during data acquisition. Figure 8b As shown, if the execution object corresponding to the data acquisition instruction is the main detection unit 3011, the number of channel conversions is 3, for example, the data acquisition instruction is the Start-Main signal, and the acquisition channel group preset by the main detection unit 3011 includes Channel-1, then Figure 8bAs shown, the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, and the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM, and the Main-FSM jumps to the EOC state. The Main-FSM determines that it is necessary to collect the data of Channel-1 twice based on the Start-Main signal and the preset collection channel group. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM, and the Main-FSM jumps to the EOC state. The Main-FSM determines that it is necessary to collect the data of Channel-1 again based on the Start-Main signal and the preset collection channel group. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM. The Main-FSM determines that the data corresponding to the Start-Main signal has been collected based on the Start-Main signal and the preset collection channel group, and the Main-FSM switches to the IDLE state.

[0114] The following is an introduction to the method of converting the same channel group once during data acquisition, where the channel groups include different channels. Figure 8c As shown, if the execution object corresponding to the data acquisition instruction is the main detection unit 3011, the channel conversion number is 3, for example, the data acquisition instruction is the Start-Main signal, and the acquisition channel group preset by the main detection unit 3011 includes Channel-1, Channel-2, and Channel-3, then Figure 8cAs shown, the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, and the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM. The Main-FSM determines that Channel-2 and Channel-3 need to be collected based on the Start-Main signal and the preset collection channel group. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-2 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-2 and collects the data of Channel-2. The digital conversion module 200 sends the collected data of Channel-2 to the Main-FSM. The Main-FSM determines that the data of Channel-3 needs to be collected based on the Start-Main signal and the preset collection channel group. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-3 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-3 and collects the data of Channel-3. The digital conversion module 200 sends the collected data of Channel-3 to the Main-FSM. The Main-FSM determines that the data corresponding to the data collection instruction has been collected based on the Start-Main signal and the preset collection channel group, and the Main-FSM switches to the IDLE state.

[0115] The following is an introduction to the method of continuously converting the same channel group during data acquisition. Figure 8d As shown, if the execution object corresponding to the data acquisition instruction is the main detection unit 3011, the number of channel conversions is 6 times, for example, the data acquisition instruction is the Start-Main signal, and the acquisition channel group preset by the main detection unit 3011 includes Channel-1, Channel-2, and Channel-3, then Figure 8dAs shown, when the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM. The Main-FSM determines based on the Start-Main signal and the preset collection channel group that it is necessary to collect Channel-2, Channel-3, Channel-1, Channel-2, and Channel-3 once each. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-2 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-2 and collects the data of Channel-2. The digital conversion module 200 sends the collected data of Channel-2 to Main-FSM. Based on the Start-Main signal and the preset collection channel group, Main-FSM determines that it is necessary to collect Channel-3, Channel-1, Channel-2, and Channel-3 once each, and jumps from the EOC state to the SMPL state, and sends a sampling signal of Channel-3 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-3 and collects the data of Channel-3. The digital-to-analog conversion module 200 sends the collected data of Channel-3 to the Main-FSM. Based on the Start-Main signal and the preset collection channel group, the Main-FSM determines that it is necessary to collect Channel-1, Channel-2, and Channel-3 once each, and then sends the sampling signal of Channel-1, the sampling signal of Channel-2, and the sampling signal of Channel-3 to the analog-to-digital conversion module 200 in turn; until the Main-FSM receives the data collected from Channel-3 for the second time, the Main-FSM switches to the IDLE state.

[0116] The following is an introduction to the method of converting a channel group at a fixed number of times during data acquisition. Figure 8e As shown, if the execution object corresponding to the data acquisition instruction is the main detection unit 3011, the number of channel conversions is 2, for example, the data acquisition instruction is the Start-Main signal, and the acquisition channel group preset by the main detection unit 3011 includes Channel-1, Channel-2, Channel-3 and Channel-4, then Figure 8eAs shown, the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, and the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM. The Main-FSM determines that Channel-2 needs to be collected based on the Start-Main signal and the preset collection channel group. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-2 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-2 and collects the data of Channel-2. The data conversion module 200 sends the collected data of Channel-2 to the Main-FSM. The Main-FSM determines that the data corresponding to the Start-Main signal has been collected based on the Start-Main signal and the preset collection channel group, and the Main-FSM switches to the IDLE state.

[0117] like Figure 8e As shown, when the Main-FSM of the main detection unit 3011 obtains the Start-Main signal again, the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-3 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-3 and collects the data of Channel-3. The analog-to-digital conversion module 200 sends the collected data of Channel-3 to the Main-FSM, and the Main-FSM determines that it is necessary to collect the data of Channel-4 based on the Start-Main signal and the preset collection channel group. The Main-FSM jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-4 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-4 and collects the data of Channel-4. The data conversion module 200 sends the collected data of Channel-4 to the Main-FSM. The Main-FSM determines that the data corresponding to the Start-Main signal has been collected based on the Start-Main signal and the preset collection channel group, and the Main-FSM switches to the IDLE state.

[0118] The following describes a method in which the channel group of the slave detection unit 3012 interrupts the conversion process of the channel group of the master detection unit 3011 during data acquisition, and the channel group of the master detection unit 3011 waits for the channel group of the slave detection unit 3012 to complete the conversion, and then the channel group of the master detection unit 3011 continues to convert. Figure 8f As shown, if the execution object corresponding to the data acquisition instruction is the main detection unit 3011, the number of channel conversions is 3, for example, the data acquisition instruction is the Start-Main signal, the execution object corresponding to the interrupt signal is the slave detection unit 3012, the number of channel conversions is 3, for example, the interrupt signal is the Start-Sub signal; the preset acquisition channel group of the main detection unit 3011 includes Channel-1, Channel-2 and Channel-5, and the preset acquisition channel group of the slave detection unit 3012 includes Channel-3, Channel-4 and Channel-6; then Figure 8f As shown, the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, and the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM. Based on the Start-Main signal and the preset collection channel group, the Main-FSM determines that Channel-2 and Channel-5 need to be collected again, and jumps from the EOC state to the SMPL state, and sends the sampling signal of Channel-2 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-2 and collects the data of Channel-2.

[0119] In the process of the analog-to-digital conversion module 200 collecting data from Channel-2, the Sub-FSM of the detection unit 3012 obtains the Start-Sub signal, the Sub-FSM switches from the IDLE state to the STUP state, sends an interrupt signal to the Main-FSM, the Main-FSM jumps to the IDLE state, and sends a pause signal (Main-FSM-reset signal) to the analog-to-digital conversion module 200 to stop collecting data. The Sub-FSM sends a sampling signal of Channel-3 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-3 and collects data from Channel-3. The analog-to-digital conversion module 200 sends the collected data of Channel-3 to the Sub-FSM. Based on the Start-Sub signal and the preset collection channel group, the Sub-FSM determines that it is necessary to collect data from Channel-4 and Channel-6, and changes from the EOC state to the SMPL state, and sends the sampling signal of Channel-4 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-4 and collects data from Channel-4. The analog-to-digital conversion module 200 sends the collected data of Channel-4 to the Sub-FSM. Based on the Start-Sub signal and the preset collection channel group, the Sub-FSM determines that it is necessary to collect data from Channel-6, and changes from the EOC state to the SMPL state, and sends the sampling signal of Channel-6 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-6 and collects data from Channel-6. The analog-to-digital conversion module 200 sends the collected data of Channel-6 to the Sub-FSM. The Sub-FSM determines that the data corresponding to the Start-Sub signal has been collected based on the Start-Sub signal and the preset collection channel group, and sends a second start signal to the Main-FSM. In response to the second start signal, the Main-FSM determines that the second data of Channel-2 has not been collected, and sends a sampling signal of Channel-2 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 collects the data of Channel-2. The analog-to-digital conversion module 200 sends the collected data of Channel-2 to the Main-FSM. The Main-FSM determines that the data of Channel-5 needs to be collected based on the Start-Main signal and the preset collection channel group, and jumps from the EOC state to the SMPL state, and sends a sampling signal of Channel-5 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-5 and collects the data of Channel-5.The analog-to-digital conversion module 200 sends the collected data of Channel-5 to the Main-FSM. The Main-FSM determines that the data corresponding to the Start-Main signal has been collected based on the Start-Main signal and the preset collection channel group, and the Main-FSM switches to the IDLE state.

[0120] It can be understood that if the Main-FSM sends a sampling signal to the analog-to-digital conversion module 200, the Main-FSM-start signal is high, and if the Main-FSM sends a pause signal to the analog-to-digital conversion module 200, the Main-FSM-reset signal is high. Similarly, if the Sub-FSM sends a sampling signal to the analog-to-digital conversion module 200, the Sub-FSM-start signal is high.

[0121] The following describes a method for alternately switching between the channel group of the slave detection unit 3012 and the channel group of the master detection unit 3011 during data acquisition. Figure 8g As shown, if the execution object corresponding to the alternating instruction is the main detection unit 3011, the number of channel conversions is 4, for example, the data acquisition instruction is the Start-Main signal. The acquisition channel group preset by the main detection unit 3011 includes Channel-1, Channel-2, Channel-2 and Channel-5, and the acquisition channel group preset by the slave detection unit 3012 includes Channel-3, Channel-4 and Channel-6; then Figure 8gAs shown, the Main-FSM of the main detection unit 3011 obtains the Start-Main signal, the Main-FSM switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM, and the Main-FSM sends the third start signal to the Sub-FSM of the slave detection unit 3012. The Sub-FSM of the slave detection unit 3012 switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-3 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-3 and collects the data of Channel-3. The analog-to-digital conversion module 200 sends the collected Channel-3 data to the Sub-FSM, the Sub-FSM sends the fourth start signal to the main detection unit 3011, the Main-FSM of the main detection unit 3011 switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-2 to the analog-to-digital conversion module 200 until the data corresponding to the Start-Main signal has been collected, and the Main-FSM and Sub-FSM switch to the IDLE state.

[0122] Figure 8h The timing diagram of the clock signal Main-clk of the master detection unit 3011 and the clock signal Sub-clk of the slave detection unit 3012 is shown when the signal received by the digital control module 30A is an alternation instruction.

[0123] like Figure 8hAs shown, the execution object corresponding to the corresponding alternating instruction is the main detection unit 3011, the conversion number of the channel group is 1, and the conversion number of the channel in the channel group is 1. The acquisition channel group preset by the main detection unit 3011 includes Channel-1, Channel-2, and Channel-2, and the acquisition channel group preset by the slave detection unit 3012 includes Channel-1 and Channel-2; the Main-FSM of the main detection unit 3011 obtains the Start signal, and the Main-FSM switches from the IDLE state to the STUP state, and sends the main FSM release signal to GATE, so that CLK_DIV generates the PCLK_DIV signal and the Main_clk signal based on the PCLK_GATE signal, wherein the Main_clk signal is the clock signal required for the operation of the Main-FSM. The Main-FSM sends the sampling signal of Channel-1 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-1 and collects the data of Channel-1. The analog-to-digital conversion module 200 sends the collected data of Channel-1 to the Main-FSM, and the Main-FSM sends the third start signal to the slave detection unit 3012. The Main-FSM jumps to the IDLE state, sends the main FSM shutdown signal to GATE, and CLK_DIV stops the PCLK_GATE signal to generate the Main_clk signal. The Sub-FSM of the slave detection unit 3012 switches from the IDLE state to the STUP state, and sends the slave FSM release signal to GATE, so that CLK_DIV generates the PCLK_DIV signal and the Sub_clk signal based on the PCLK_GATE signal, wherein the Sub_clk signal is the clock signal required for the Sub-FSM to work. The Sub-FSM sends the sampling signal of Channel-3 to the analog-to-digital conversion module 200, so that the analog-to-digital conversion module 200 connects to Channel-3 and collects the data of Channel-3. The analog-to-digital conversion module 200 sends the collected data of Channel-3 to the Sub-FSM, the Sub-FSM sends the fourth start signal to the Main-FSM of the main detection unit 3011, the Main-FSM of the main detection unit 3011 switches from the IDLE state to the STUP state, and sends the sampling signal of Channel-2 to the analog-to-digital conversion module 200 until the data of each channel of the sampling channel group corresponding to the alternating instruction has been collected, and the Main-FSM and Sub-FSM switch to the IDLE state.

[0124] It can be understood that the method provided in the embodiment of the present application can be applied to any electronic device, including but not limited to a mobile station (MS), a mobile terminal (MT), etc. For example, the electronic device can be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a desktop computer, a laptop computer, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in self-driving, a terminal in remote medical surgery, a terminal in a smart grid, a terminal in transportation safety, a terminal in a smart city, a terminal in a smart home, etc. The embodiment of the present application does not limit the specific form of the electronic device.

[0125] According to an embodiment of the present application, Fig. 9 FIG. 1 is a block diagram of an electronic device 100 based on a system on chip (SOC). Fig. 9 In the FIG, similar components have the same reference numerals. In addition, the dashed boxes are optional features of more advanced SOCs. Fig. 9 In the embodiment, the electronic device 100 includes: an interconnect unit 1350, which is coupled to the processor 1315; a system agent unit 1370; a bus controller unit 1380; an integrated memory controller unit 1340; a group or one or more coprocessors 1320, which may include integrated graphics logic, image processors, audio processors, and video processors; a static random-access memory (SRAM) unit 1330; and a direct memory access (DMA) unit 1360. In one embodiment, the coprocessor 1320 includes a special-purpose processor, such as, for example, a network or communication processor, a compression engine, or an embedded processor.

[0126] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including but not limited to floppy disks, optical disks, optical disks, read-only memories (compact disc-read only memories, CD-ROMs), magneto-optical disks, read-only memories (read only memory, ROM), random access memories (random access memory, RAM), erasable programmable read-only memories (erasable programmable read-only memories, EPROM), electrically erasable programmable read-only memories (electrically erasable programmable read-only memories, EEPROM), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Accordingly, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0127] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0128] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0129] It should be noted that in the examples and description of this patent, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises one" does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0130] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A data collection method, characterized in that: Applied to an electronic device, the electronic device includes an analog-to-digital conversion module and a digital control module, the digital control module includes a state detection unit and a time management unit, and the data acquisition method includes: The state detection unit receives the data acquisition instruction, generates a channel selection signal based on the data acquisition instruction, sends the channel selection signal to the analog-to-digital conversion module, and sends a release signal to the time management unit based on the data acquisition instruction; The time management unit receives the release signal, and sends a clock control signal to the analog-to-digital conversion module based on the release signal, wherein the clock control signal is used to control the acquisition speed of the analog-to-digital conversion module; The analog-to-digital conversion module receives the clock control signal and the channel selection signal, selects a first channel based on the channel selection signal, and collects first data at a first collection speed corresponding to the clock control signal; and after completing the collection of the first data, switches from the first channel to the second channel based on the channel selection signal, and collects second data at a second collection speed corresponding to the clock control signal.

2. The data collection method according to claim 1, characterized in that: The channel selection signal includes a first channel signal and a second channel signal; The method further comprises: The digital control module sends the first channel signal to the analog-to-digital conversion module; The analog-to-digital conversion module receives the clock control signal and the first channel signal, selects the first channel based on the first channel signal, collects the first data at a first collection speed corresponding to the clock control signal, and sends the collected first data to the digital control module; After receiving the first data, the digital control module sends the second channel signal to the analog-to-digital conversion module; The analog-to-digital conversion module receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal, collects the second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the digital control module.

3. The data collection method according to claim 1, characterized in that: The method further comprises: When the state detection unit receives the collection data corresponding to the data collection instruction, the state detection unit sends a shutdown signal to the time management unit, wherein the collection data includes the first data and the second data, and the shutdown signal is used to instruct the time management unit to stop sending the clock control signal to the analog-to-digital conversion module.

4. The data collection method according to claim 1, characterized in that: The first channel and the second channel are the same; or, The first channel and the second channel are different.

5. The data collection method according to claim 1, characterized in that: The data acquisition instruction includes the conversion times of the channel.

6. The data collection method according to claim 3, characterized in that: The state detection unit includes a main detection unit and a slave detection unit; The method further comprises: The digital control module sends the second channel signal to the analog-to-digital conversion module through the main detection unit; When the analog-to-digital conversion module collects the second data, the digital control module receives a temporary collection instruction through the slave detection unit, generates a temporary channel signal based on the temporary collection instruction, and sends an interrupt signal to the master detection unit; In response to the interrupt signal, the master detection unit sends a pause signal to the analog-to-digital conversion module to stop the analog-to-digital conversion module from collecting the second data, and sends a first start signal to the slave detection unit; The slave detection unit sends the temporary channel signal to the analog-to-digital conversion module in response to the first start signal; The analog-to-digital conversion module receives the clock control signal and the temporary channel signal, selects a third channel based on the temporary channel signal, collects third data at a third collection speed corresponding to the clock control signal, and sends the third data to the slave detection unit after completing the collection of the third data.

7. The data collection method according to claim 6, characterized in that: The method further comprises: When receiving the third data, the slave detection unit sends a second start signal to the master detection unit; The main detection unit sends the second channel signal to the analog-to-digital conversion module in response to the second start signal; The analog-to-digital conversion module receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal, collects the second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the main detection unit.

8. The data collection method according to claim 1, characterized in that: The digital control module includes a master detection unit and a slave detection unit, and the method further includes: Corresponding to the master detection unit acquiring the alternation instruction, the master detection unit sends a third start signal to the slave detection unit after receiving the first data; The slave detection unit obtains the third start signal and sends a third channel signal to the analog-to-digital conversion module; The analog-to-digital conversion module receives the clock control signal and the third channel signal, selects a third channel based on the third channel signal, collects third data at a third collection speed corresponding to the clock control signal, and sends the collected third data to the slave detection unit; The slave detection unit acquires the third data and sends a fourth start signal to the master detection unit; The main detection unit obtains the fourth start signal and sends the second channel signal to the analog-to-digital conversion module; The analog-to-digital conversion module receives the clock control signal and the second channel signal, selects the second channel based on the second channel signal, collects the second data at a second collection speed corresponding to the clock control signal, and sends the collected second data to the main detection unit.

9. The data collection method according to claim 6, characterized in that: The master detection unit and the slave detection unit both include a monitoring unit, The monitoring unit is used to generate an alarm signal when detecting the data sent by the analog-to-digital conversion module, corresponding to determining that the data sent by the analog-to-digital conversion module is greater than the alarm threshold of the data sent by the analog-to-digital conversion module.

10. A chip, characterized in that: The chip includes a processor and a data interface, and the processor reads instructions stored in a memory through the data interface to execute the data acquisition method according to any one of claims 1 to 9.

11. An electronic device, characterized in that: It includes a memory for storing instructions executed by one or more processors of an electronic device; and a processor, which is one of the processors of the electronic device, for executing the instructions stored in the memory to implement the data collection method according to any one of claims 1 to 9.

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