Secure successive approximation register ADC

Abstract

The invention relates to a secure successive approximation register (ADC). An ADC (100) for converting an input signal to a digital value. In an ADC (100), a successive approximation register (110) is connected to a first DAC (120A) and a second DAC (120B) through its output. The switch matrix (130) is configured for capacitively coupling an input signal between the first input and the second input of the comparator (150), or for capacitively coupling an output signal of the first DAC (120A), or an output signal of the second DAC (120B), or both the output signal of the first DAC (120A) and the output signal of the second DAC (120B), between the first input and the second input of the comparator (150). The ADC (100) includes a comparator switch (160) located between a first input and a second input of a comparator (150). The output of the comparator (150) is connected to the input of the successive approximation register (110).

Description

Technical Field

[0001] The present invention relates to the field of analog-to-digital converters (ADCs). More specifically, it relates to an ADC that applies a binary lookup algorithm through different quantization levels to obtain a digital representation of an analog input signal. Background Art

[0002] Different applications (such as, for example, automotive products) require components that support self-diagnosis. In particular, major components (such as, for example, ADCs) should support self-diagnosis. Such a requirement can be implemented at the system level. For example, when a product has both an ADC and a digital-to-analog converter (DAC), feeding the output of the DAC to the input of the ADC in some test modes allows both blocks to be checked when comparing the output code of the ADC with the input code of the DAC. Gain, offset, and linearity errors can be easily estimated and tested according to some tolerances.

[0003] However, many products do not have any internal DAC: this is the case with sensors with digital output, or drivers (LEDs, motors), because this saves some area and is therefore cost-effective.

[0004] In some other architectures, the test DAC is implemented inside the ADC. However, such internal test DACs typically have reduced resolution and reduced accuracy. It only provides basic functional checks. Therefore, such solutions cannot be used for functional safety applications. The DAC needs to be significantly improved for complete ADC checks, which is not area efficient and therefore not cost efficient.

[0005] Another special case is the successive approximation register (SAR) ADC illustrated in Figure 1. It has a DAC that is used to generate a successive approximation with the correct resolution and accuracy as required by the binary lookup algorithm.

[0006] During a first sampling phase, switches SW1 and SW2 are closed (closed actually means enabled=conducting), while switch SW3 is open (open actually means disabled=non-conducting) and the input signal VIN is stored on capacitor CS.

[0007] During the second conversion phase, switches SW1 and SW2 are open, while switch SW3 is closed: the signal fed to the comparator is therefore the DAC output voltage minus the input signal stored on capacitor CS. The output of the comparator is the sign of this difference, i.e. it tells whether the DAC output voltage is greater than the input voltage. Based on such information, during the conversion, the logic block SAR generates an increasingly accurate digital estimate of the input signal VIN. The final estimate is finally copied into the output register REG.

[0008] After closing switch SW3 instead of SW1 during the sampling phase, the DAC output can be sampled on capacitor CS instead of the signal input VIN: This type of test mode would allow checking the correct behavior, but most faults would go undetected, since the test signal and subsequent approaches would be affected in the same way. That is, high leakage currents in only a few switches would make the DAC and ADC completely nonlinear, and this would not be detected. However, leakage currents may increase during the product lifetime (e.g., deep trench isolation (DTI) cracks propagate with repeated thermal shocks). Therefore, this solution cannot be used for functional safety applications either.

[0009] Therefore, there is a need for analog-to-digital converters that support self-diagnosis so that they can be used in functional safety applications. Summary of the invention

[0010] It is an object of embodiments of the present invention to provide a good analog-to-digital converter that can be used in a self-diagnostic test mode.

[0011] The above objects are achieved by the method and device according to the present invention.

[0012] An embodiment of the present invention relates to an analog-to-digital converter for converting an input signal into a digital value. The analog-to-digital converter includes a successive approximation register, a first digital-to-analog converter and a second digital-to-analog converter, a switch matrix, (optionally including) a register for storing digital values, a comparator, and a comparator switch between a first input and a second input of the comparator.

[0013] The successive approximation register is connected by its output to the first DAC, to the second DAC, and optionally to the register.

[0014] The switch matrix is ​​configured to capacitively couple the input signal between the first input and the second input of the comparator, or to capacitively couple the output signal of the first DAC, or the output signal of the second DAC, or both the output signal of the first DAC and the output signal of the second DAC between the first input and the second input of the comparator, and the output of the comparator is connected to the input of the successive approximation register.

[0015] An advantage of the ADC according to an embodiment of the present invention is that the ADC according to an embodiment of the present invention can be used in a functional mode and a self-diagnostic test mode. This is achieved by providing two DACs and a switch matrix, wherein the switch matrix is ​​configured to capacitively couple the input signal between the first input and the second input of the comparator, or to capacitively couple the first DAC, or the second DAC, or both the first DAC and the second DAC between the first input and the second input of the comparator.

[0016] In functional mode, two DACs are in parallel and their corresponding linear errors are averaged. When comparing this ADC architecture according to the present invention with the prior art ADC illustrated in FIG. 1 , when both have the same accuracy, the two ADCs will also have similar surface areas. In addition, advantageously, this architecture has no speed or power loss. In addition, the ADC according to the present invention has an architecture that allows self-diagnostic testing. In the self-diagnostic test mode, the output of one DAC is converted by the ADC using another DAC or using two DACs in parallel. In both cases, errors that affect only one DAC can be detected.

[0017] In an embodiment of the invention, each of the DACs may include a resistor string. In an embodiment of the invention, each string is composed of identical resistors. In an embodiment of the invention, both strings are preferably composed of the same number of identical resistors to allow for the best / minimum linearity error in each string for the same total area.

[0018] In an embodiment of the invention, the ADC comprises a controller configured to control a switch matrix.

[0019] In an embodiment of the invention, the controller is configured for controlling the comparator switch and the switch matrix for capacitively coupling an input signal between a first input and a second input of the comparator for sampling the input signal.

[0020] In an embodiment of the invention, the controller is configured for controlling the comparator switch and the switch matrix for capacitively coupling the output signal of the first digital-to-analog converter and the output signal of the second DAC between the first input and the second input of the comparator for conversion.

[0021] In an embodiment of the present invention, the controller is configured to control the comparator switch and the switch matrix for capacitively coupling the output signal of the first DAC between the first input and the second input of the comparator, or for capacitively coupling the output signal of the second DAC between the first input and the second input of the comparator for sampling.

[0022] After sampling the output signal of the first or second DAC, the controller is configured to control the comparator switch and the switch matrix to capacitively couple the output signal of the second DAC between the first input and the second input of the comparator after sampling the output of the first DAC for conversion; or to control the comparator switch and the switch matrix to capacitively couple the output signal of the first DAC between the first input and the second input of the comparator after sampling the output of the second DAC for conversion.

[0023] In an embodiment of the present invention, the ADC is single-ended. For a single-ended ADC according to an embodiment of the present invention, the switch matrix may include a first capacitor and a second capacitor, both of which are connected to the first input of the comparator through their second terminals. In addition, the switch matrix may include:

[0024] a first switch disposed between an input terminal for inputting a signal and a first terminal of the first capacitor,

[0025] a second switch disposed between the input terminal and the first terminal of the second capacitor,

[0026] a third switch disposed between the first DAC and the first terminal of the first capacitor,

[0027] a fourth switch disposed between the first DAC and the first terminal of the second capacitor,

[0028] a fifth switch disposed between the second DAC and the first terminal of the first capacitor,

[0029] The sixth switch is located between the second DAC and the first terminal of the second capacitor.

[0030] In an embodiment of the present invention, the controller is configured to close the first switch, the second switch and the comparator switch, and open the third switch, the fourth switch, the fifth switch and the sixth switch for sampling the input signal; and close the third switch and the sixth switch, and open the first switch, the second switch, the fourth switch, the fifth switch and the comparator switch for conversion.

[0031] In an embodiment of the present invention, the controller is configured to close the third switch, the fourth switch and the comparator switch, and open the first switch, the second switch, the fifth switch and the sixth switch for sampling the output of the first DAC; or close the fifth switch, the sixth switch and the comparator switch, and open the first switch, the second switch, the third switch and the fourth switch for sampling the output of the second DAC; and after sampling the output of the first DAC, close the fifth switch and the sixth switch and open the first switch, the second switch, the third switch, the fourth switch and the comparator switch for conversion; or after sampling the output of the second DAC, close the third switch and the fourth switch, and open the first switch, the second switch, the fifth switch, the sixth switch and the comparator switch for conversion.

[0032] In an embodiment of the present invention, each DAC may include at least one multiplexer controlled by an input digital code obtained from an output of a successive approximation register for connecting an internal node of the resistor string to an output of the DAC.

[0033] In an embodiment of the present invention, the ADC is a differential ADC. The differential ADC may include a first pair of capacitors and a second pair of capacitors, wherein the first pair of capacitors are connected to the first input and the second input of the comparator through their second terminals, respectively, and the second pair of capacitors are connected to the first input and the second input of the comparator through their second terminals, respectively.

[0034] In an embodiment of the present invention, the switch matrix comprises:

[0035] a first pair of switches disposed between the pair of input terminals and first terminals of the first pair of capacitors,

[0036] a second pair of switches disposed between the pair of input terminals and second terminals of the first pair of capacitors,

[0037] a third pair of switches disposed between the first DAC and the first terminals of the first pair of capacitors,

[0038] a fourth pair of switches disposed between the first DAC and the first terminals of the second pair of capacitors,

[0039] a fifth pair of switches disposed between the second DAC and the first terminals of the first pair of capacitors,

[0040] a sixth pair of switches disposed between the second DAC and the first terminals of the second pair of capacitors,

[0041] In an embodiment of the present invention, the ADC may be a differential ADC. Each DAC of such a differential ADC may include a resistor string. In addition, each DAC may include a matrix of four switches, a first multiplexer connected to the upper half of the resistor string, and a second multiplexer connected to the lower half of the resistor string. The multiplexer is controlled by an input digital code obtained from the output of a successive approximation register using a sign and amplitude encoding, wherein the amplitude controls the first and second multiplexers, and wherein the sign controls the matrix of the four switches, so that when the sign is positive, the output of the first multiplexer is connected to the positive output terminal of the DAC and the output of the second multiplexer is connected to the negative output terminal of the DAC, and when the sign is negative, the output of the first multiplexer is connected to the negative output terminal of the DAC and the output of the second multiplexer is connected to the positive output terminal of the DAC.

[0042] In an embodiment of the present invention, the resistor string of the first DAC and the resistor string of the second DAC are positioned so that a first symmetry axis and a second symmetry axis orthogonal to the first symmetry axis can be identified between the resistors, and wherein the center of gravity of any pair of resistors with the same index in the resistor string of the first DAC and the resistor string of the second DAC is located at the intersection of the first symmetry axis and the second symmetry axis.

[0043] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not just as explicitly set out in the claims.

[0044] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG. 1 shows a schematic diagram of a successive approximation register ADC according to the prior art.

[0046] Figure 2 A schematic diagram of a successive approximation register ADC according to an embodiment of the present invention is shown, the successive approximation register ADC comprising two DACs and a switch matrix.

[0047] Figure 3 A schematic diagram of a single-ended successive approximation register ADC according to an embodiment of the present invention is shown.

[0048] Figure 4 A schematic diagram of a differential successive approximation register ADC according to an embodiment of the present invention is shown.

[0049] Figure 5 A schematic diagram illustrating a single-ended resistor string DAC that may be used in an ADC according to an embodiment of the present invention.

[0050] Figure 6 A schematic diagram illustrating a differential resistor string DAC that may be used in an ADC according to an embodiment of the present invention.

[0051] Figure 7 An exemplary layout that satisfies the homocentroid requirement of two DACs of a single-ended architecture with an ADC according to an embodiment of the present invention is shown.

[0052] FIG. 8 shows a layout of a differential homocentric single resistor string DAC according to the prior art.

[0053] Fig. 9 An exemplary layout that satisfies the homocentroid requirement of two DACs with a differential architecture of an ADC according to an embodiment of the present invention is shown.

[0054] Any reference signs in the claims should not be construed as limiting the scope.

[0055] The same reference numbers in different drawings refer to the same or similar elements. DETAILED DESCRIPTION

[0056] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are merely illustrative and non-restrictive. In the drawings, for illustrative purposes, the size of some of the elements may be exaggerated and not drawn to scale. The dimensions and relative dimensions do not correspond to actual reductions in the practice of the invention.

[0057] The terms first, second, etc. in the specification and in the claims are used to distinguish between similar elements and not necessarily to describe a sequence in time, space, level, or in any other manner. It should be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in a sequence different from that described or illustrated herein.

[0058] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means listed thereafter; it does not exclude other elements or steps. Thus, the term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Therefore, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that for the present invention, the only relevant components of the device are A and B.

[0059] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment, but may do so. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner as would be apparent to one of ordinary skill in the art from this disclosure.

[0060] Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than those expressly recited in each claim. On the contrary, as reflected in the appended claims, the inventive aspects lie in fewer features than all of the features of a single preceding disclosed embodiment. Thus, the claims appended to the specific embodiments are hereby expressly incorporated into the present specific embodiments, with each claim itself representing a separate embodiment of the invention.

[0061] In addition, although some embodiments described herein include some features included in other embodiments but do not include other features included in other embodiments, as those skilled in the art will appreciate, combinations of features of different embodiments are intended to fall within the scope of the present invention and form different embodiments. For example, in the appended claims, any of the claimed embodiments may be used in any combination.

[0062] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be implemented without these specific details. In other examples, well-known methods, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification.

[0063] Embodiments of the present invention relate to an ADC 100 for converting an input signal into a digital value. Figure 2 The figure shows an example of a successive approximation register ADC according to an embodiment of the present invention.

[0064] ADC 100 includes a successive approximation register 110 , first and second DACs 120A and 120B, a switch matrix 130 , optionally including a register 140 for storing digital values ​​obtained by the ADC, a comparator 150 , and a comparator switch 160 between a first input and a second input of comparator 150 .

[0065] The successive approximation register 110 is connected such that its output is connected to the first DAC 120A, to the second DAC 120B, and optionally to the register 140. The register is not strictly necessary. The successive approximation register itself is a register that can be read out. The difference is that the successive approximation register changes continuously with the conversion, while the register 140 always holds the last result until a new result is written to the register.

[0066] In an embodiment of the present invention, the switch matrix 130 includes a plurality of switches for capacitively coupling an input signal between a first input and a second input of the comparator 150, or for capacitively coupling an output signal of the first DAC 120A or an output signal of the second DAC 120B or both the output signal of the first DAC 120A and the output signal of the second DAC 120B between the first input and the second input of the comparator 150.

[0067] The switch may be, for example, a MOS field effect transistor (p-type, n-type, intrinsic type, depletion type). A switch may also include different transistors, such as p-type and n-type transistors. The switch may also include a dedicated voltage control to open (non-conducting switch) or close (conducting switch) the switch.

[0068] The output of comparator 150 is connected to the input of successive approximation register 110 .

[0069] The ADC according to an embodiment of the present invention can be used in a functional mode and a self-diagnostic test mode. In the functional mode, two DACs are in parallel and their corresponding linearity errors are averaged. In the self-diagnostic test mode, the output of one DAC is converted by the ADC using another DAC or using two DACs in parallel.

[0070] In an embodiment of the present invention, a signal is capacitively coupled between a first input and a second input of a comparator in the following manner: in the case of a single-ended signal, by capacitively coupling the signal to the first input of the comparator and by connecting the second input of the comparator to a reference signal; or in the case of a differential signal comprising two complementary signals, by capacitively coupling the first complementary signal to the first input of the comparator and capacitively coupling the second complementary signal to the second input of the comparator.

[0071] In an embodiment of the present invention, two smaller DACs are used in parallel in a SAR ADC instead of a single larger DAC to achieve functional safety without adding extra cost. This can be achieved for any type of DAC used in a SAR ADC.

[0072] In an embodiment of the present invention, a DAC is used which comprises a resistor string. In an embodiment of the present invention, two independent resistor strings are implemented.

[0073] The present invention is not limited to resistor string DACs. Any other type of DAC may be used. In an embodiment of the present invention, two smaller DACs are used in parallel in a successive approximation register ADC instead of a single larger DAC to achieve functional safety without adding additional cost.

[0074] In functional mode, the two DACs are in parallel and their respective linearity errors are averaged: they can have half the size of the device that would otherwise be needed when using a single DAC (Pelgrom's law: matching error is inversely proportional to the square root of the area). The same applies to the output impedance: when connecting the blocks in parallel, the output impedance is divided by 2, so the switches used in each DAC are half the size of the switches required for a single DAC.

[0075] In the self-diagnostic test mode, the output of one DAC is converted via the ADC using the other DAC or both DACs in parallel: in both cases, errors affecting only one DAC will be detected. And the probability of correlated errors is no higher than with the external test DAC: again, the two DACs are completely independent, with their own set of switches and decoders. As described in the next section, such decoders further use a partially different architecture: this further reduces the probability of correlated errors.

[0076] In an embodiment of the present invention, ADC 100 includes a controller 180, which is configured to control the switch matrix 130. In an embodiment of the present invention, the controller for each conversion of the switch matrix can be implemented using a dedicated hardware logic block. For example, this can be a finite state machine. In an embodiment of the present invention, the diagnostic routine can be implemented using software running on a microcontroller.

[0077] In an embodiment of the present invention, the controller 180 is configured for controlling the comparator switch 160 and the switch matrix 130 for capacitively coupling the input signal between the first input and the second input of the comparator 150 for sampling the input signal.

[0078] In an embodiment of the present invention, the controller 180 is configured to control the comparator switch 160 and the switch matrix 130 for capacitively coupling the output signal of the first DAC 120A and the output signal of the second DAC 120B between the first input and the second input of the comparator 150 for conversion. An advantage of an embodiment of the present invention is that the two DACs are used in parallel and their respective linearity errors are averaged.

[0079] In an embodiment of the present invention, the controller 180 is configured to control the comparator switch 160 and the switch matrix 130 for capacitively coupling the output signal of the first DAC 120A between the first input and the second input of the comparator 150, or for capacitively coupling the output signal of the second DAC 120B between the first input and the second input of the comparator 150 for sampling.

[0080] In an embodiment of the present invention, the controller is configured to control the comparator switch 160 and the switch matrix 130 to capacitively couple the output signal of the second DAC 120B between the first input and the second input of the comparator 150 for conversion after sampling the output of the first DAC 120A, or to control the comparator switch 160 and the switch matrix 130 to capacitively couple the output signal of the first DAC 120A between the first input and the second input of the comparator 150 for conversion after sampling the output of the second DAC 120B. An advantage of an embodiment of the present invention is that when comparing one DAC with another DAC, the linearity of the two DACs can be checked.

[0081] Figure 3 An exemplary switch matrix 130 for a single-ended ADC 100 according to an embodiment of the present invention is shown in FIG. In this configuration, the ADC 100 includes a first capacitor 171 and a second capacitor 172. The first capacitor 171 is connected to a first input of a comparator 150 via its second terminal, and the second capacitor 171 is connected to a second input of the comparator 150 via its second terminal. In an embodiment of the present invention, the first capacitor 171 and the second capacitor 172 are preferably identical. For example, they may have half the value (and size) of the capacitor CS in FIG. 1 . When having identical capacitors and connecting two DACs in parallel, the outputs of the two DACs are averaged with equal weights, so that their nonlinearity errors are reduced on average by an optimal factor of the square root.

[0082] The switch matrix 130 comprises a first switch 131 between the input terminal 101 for a single-ended input signal and a first terminal of a first capacitor 171 .

[0083] The switch matrix 130 includes a second switch 132 located between the input terminal 101 and a first terminal of a second capacitor 172 .

[0084] The switch matrix 130 includes a third switch 133 located between the first DAC 120A and the first terminal of the first capacitor 171 .

[0085] The switch matrix 130 includes a fourth switch 134 located between the first DAC 120A and the first terminal of the second capacitor 172 .

[0086] The switch matrix 130 includes a fifth switch 135 located between the second DAC 120B and the first terminal of the first capacitor 171 .

[0087] The switch matrix 130 includes a sixth switch 136 located between the second DAC 120B and the first terminal of the second capacitor 172 .

[0088] In functional mode, according to an embodiment of the present invention, the ADC may operate in two phases.

[0089] During the sampling phase, the first switch 131, the second switch 132 and the comparator switch 160 are closed so that the input signal VIN is stored on the first capacitor 171 and the second capacitor 172. All other switches remain open.

[0090] During the conversion phase, the third switch 133 and the sixth switch 136 are closed, and Figure 3 All other switches shown in remain on.

[0091] An advantage of embodiments of the present invention is that, in addition to the functional mode, an alternative (test) mode is also available. Figure 3 In the illustrated exemplary embodiment, four different alternative (test) modes are available.

[0092] During the sampling phase, when the third and fourth switches 133 and 134 are closed instead of the first and second switches 131 and 132 , the output of the DAC 0 instead of the input signal VIN may be stored on the first and second capacitors 171 and 172 .

[0093] During the sampling phase, when the sixth switch 136 and the fifth switch 135 are closed instead of the first switch 131 and the second switch 132 , the output of the DAC 1 instead of the input signal VIN may be stored on the first capacitor 171 and the second capacitor 172 .

[0094] When the third switch 133 and the fourth switch 134 are closed instead of the third switch 133 and the sixth switch 136 , the DAC 0 may be used only during conversion.

[0095] When the sixth switch 136 and the fifth switch 135 are closed instead of the third switch 133 and the sixth switch 136 , the DAC 1 may be used only during conversion.

[0096] According to an embodiment of the present invention, the ADC can be single-ended or differential. In both cases, the ADC can be used in a functional mode or a test mode.

[0097] In functional mode, the two DACs are used in parallel and their respective linearity errors are averaged. In self-diagnostic test mode, the output of one DAC is converted by the ADC using the other DAC or both DACs in parallel.

[0098] In an embodiment of the present invention, in a test mode, the output of one DAC is converted by an ADC using another DAC or two DACs in parallel. In both cases, errors that affect only one DAC can be detected. The test mode can be applied to single-mode ADCs and differential ADCs. Detection can be done using a microcontroller, for example. The microcontroller can compare the error with a threshold value, and if the error exceeds the threshold value, a fault is reported. The threshold value can be an accuracy as targeted in the application. For example, this can be 0.5LSB. However, the present invention is not limited to this. In an embodiment of the present invention, the error can be measured with a resolution higher than the resolution of the ADC. This can be achieved by averaging. Several conversions (e.g., 16 conversions) can be performed, and the resulting encoding is then averaged to reduce noise and obtain a higher resolution. The microcontroller can be configured to do this.

[0099] The likelihood of facing exactly the same linearity errors on the first DAC 120A and the second DAC 120B is extremely low, and the linearity of both DACs can now be safely checked when comparing one DAC to the other.

[0100] Figure 4 An exemplary switch matrix 130 for the differential ADC 100 according to an embodiment of the present invention is shown in FIG.

[0101] Figure 4 The ADC 100 illustrated in FIG. 1 includes a first pair of capacitors 171a, 171b and a second pair of capacitors 172a, 172b, the first pair of capacitors 171a, 171b are connected to the first input and the second input of the comparator 150 through their second terminals, respectively, and the second pair of capacitors 172a, 172b are connected to the first input and the second input of the comparator 150 through their second terminals, respectively. The comparator switch 160 is connected between the first input and the second input of the comparator 150.

[0102] The switch matrix 130 includes:

[0103] a first pair of switches 131a, 131b, located between a pair of input terminals 101a, 101b and first terminals of a first pair of capacitors 171a, 171b (which means that switch 131a is connected between input terminal 101a and the first terminal of capacitor 171a, and switch 131b is connected between input terminal 101b and the first terminal of capacitor 171b; this logic can also be applied to the following switches),

[0104] The second pair of switches 132a, 132b are located between the pair of input terminals 101a, 101b and the first terminals of the second pair of capacitors 172a, 172b.

[0105] The third pair of switches 133a, 133b are located between the first DAC 120A and the first terminals of the first pair of capacitors 171a, 171b.

[0106] A fourth pair of switches 134a, 134b, located between the first DAC (120A) and the first terminals of the second pair of capacitors 172a, 172b,

[0107] A fifth pair of switches 135a, 135b, located between the second DAC 120B and the first terminals of the first pair of capacitors 171a, 171b,

[0108] The sixth pair of switches 136a, 136b are located between the second DAC 120B and the first terminals of the second pair of capacitors 172a, 172b.

[0109] The differential ADC according to an embodiment of the present invention may include a controller 180 for controlling the switch matrix so that the differential ADC can operate in a functional mode and a test mode.

[0110] In an embodiment of the present invention, each of the DACs 120A, 120B includes a resistor string 121 .

[0111] In an embodiment of the present invention, each DAC 120 includes at least one multiplexer 122, which is controlled by an input digital code obtained from the output of the successive approximation register 110 to connect the internal node of the resistor string 121 to the output of the DAC. The input digital code is obtained from the output of the successive approximation register. The input digital code may be equal to the output of the successive approximation register.

[0112] Figure 5 An example of a resistor string DAC with a single-ended architecture is illustrated in FIG. In this example, the DAC is a 2-bit resistor string DAC consisting of a set of 4 resistors R0-R3 connected in series between ground and the output of a reference buffer. For a single-ended architecture, a unique analog multiplexer MUX controlled by an input digital code DIN connects the output OUT to one of the internal nodes of the resistor string, assuming that all resistors are identical, and the voltage of the resistor string is Vref*DIN / 4. Therefore, the voltage Vref (Vreference) defines the range of the DAC.

[0113] For the differential architecture, 2 multiplexers MUXP and MUXN are used, connected to the lower and upper halves of the resistor string respectively.

[0114] Figure 6An example of this is illustrated in . The input code DIN is preferably obtained using sign and amplitude coding, where the amplitude controls 2 multiplexers and the sign controls a matrix MUXOUT of 4 switches to connect OUTP (output P) and OUTN (output N) to MUXP and MUXN (positive sign) or to MUXN and MUXP (negative sign), respectively.

[0115] Regardless of whether the architecture under consideration is single-ended or differential, using two strings instead of one provides significant advantages in terms of matching. Both cases are considered below.

[0116] A particularly advantageous layout for matching is a common-centroid layout. In a common-centroid layout, the devices to be matched have the same center of gravity so as to reject the effects of gradients in any direction. For resistor string DACs, it is particularly advantageous that all resistors located below the nodes selected by the multiplexer have the same center of gravity as all resistors located above these nodes, and this is true regardless of the input code DIN. It is possible but extremely complex to meet such requirements with a resistor string, namely when using a cochlear layout. However, this tricky layout results in interconnect lines of different lengths, and different voltage drops along such lines may affect the linearity of the DAC.

[0117] According to the embodiment of the present invention, by using a dual resistor string, since the outputs of the two DACs are averaged, a simpler and regular layout can be used to meet the homocentricity requirement. Figure 7 An example of such a layout with a single-ended architecture is shown in the figure. For simplicity, a dual 4-bit resistor string DAC is considered. The resistors R0 to R15 in the dual resistor string are organized as a matrix with rows and columns. The first symmetry axis exists in the middle of the row and separates the first DAC 121A from the second DAC 121B. The second symmetry axis exists in the middle of the column. In this example, the matrix includes 4 rows and 8 columns. The first DAC 121A is mirrored on the first symmetry axis and then on the second symmetry axis to obtain the second DAC 121B. It can be easily checked that the center of gravity of any pair of resistors with the same index in the first DAC 121A and the second DAC 121B is exactly at the intersection of the 2 symmetry axes: regardless of the input code DIN, all resistors below and above the selected output will have the same center of gravity located exactly at the intersection of the symmetry axes. In contrast to the cochlear type, this layout is very regular and also has interconnections of the same length and minimal.

[0118] Higher resolution resistor strings can be constructed in the same way by adjusting the number of rows and columns in the array so as to maintain the layout as square as possible (minimal distance between components means best match). The ratio of rows to columns therefore depends on the ratio of the width and length of the unit resistor, and this depends on the semiconductor technology used to implement the resistor.

[0119] This resistor arrangement can provide either single-ended or differential output (so that the ADC can then support both modes - and this is one of the features of all ADCs based on this technology).

[0120] Layout for dual single-ended resistor strings (see Figure 7 ) will meet the centroid requirement when used as a single differential string (see Figure 8). For example, for input code DIN=1, the DAC output is VREF*(R0) / RT, where RT is the total resistance of the entire string. The 2 resistors R0 together have the same centroid as all resistors in the string, which is located at the intersection of the 2 symmetry axes.

[0121] However, in any resistor array we are always faced with some kind of second order gradient, i.e. resistors closer to the center of the array are usually different from resistors closer to its borders. Usually, dummy devices surround the array to mitigate this phenomenon, but it has been observed to affect several rows of devices, and increasing the number of rows of dummy devices comes at the expense of increased total area issues and reduced speed, as the lines from the resistor string nodes to the MUX become very long. For the layout described in Figure 8, until input code 3, the resistors in the middle row are added. Above input code 3, resistors in the outer rows are added, and they are different from the resistors in the middle row: the slope of the DAC output characteristic will change, resulting in larger INL errors.

[0122] In an ADC according to an embodiment of the present invention, Fig. 9 The dual differential resistor string DAC depicted in is reducing this phenomenon. In the first DAC 121A and the second DAC 121B, each time a new resistor row is selected when the code is increased, a row closer to the border of the array and a row closer to its center are added, thereby achieving partial compensation of the second order gradient.

Claims

1. An analog-to-digital converter (100) for converting an input signal into a digital value, the analog-to-digital converter (100) comprising a successive approximation register (110), a first digital-to-analog converter (120A) and a second digital-to-analog converter (120B), a switch matrix (130), a comparator (150), and a comparator switch (160) located between a first input and a second input of the comparator (150), The successive approximation register (110) is connected to the first digital-to-analog converter (120A) and the second digital-to-analog converter (120B) via its output. in, The switch matrix (130) is configured to for capacitively coupling the input signal between the first input and the second input of the comparator (150), or for capacitively coupling the output signal of the first digital-to-analog converter (120A), or the output signal of the second digital-to-analog converter (120B), or both the output signal of the first digital-to-analog converter (120A) and the output signal of the second digital-to-analog converter (120B) between the first input and the second input of the comparator (150), And wherein the output of the comparator (150) is connected to the input of the successive approximation register (110).

2. The analog-to-digital converter (100) according to claim 1, wherein: Each of the digital-to-analog converters (120A, 120B) includes a resistor string (121).

3. The analog-to-digital converter (100) according to claim 2, wherein: The first digital-to-analog converter (120A) and the second digital-to-analog converter (120B) include the same resistor string.

4. The analog-to-digital converter (100) according to claim 1, wherein: The analog-to-digital converter (100) includes a controller (180) configured to control the switch matrix (130).

5. The analog-to-digital converter (100) of claim 4, wherein the controller (180) is configured to control the comparator switch (160) and the switch matrix (130) for capacitively coupling the input signal between the first input and the second input of the comparator (150) for sampling the input signal, And is configured to control the comparator switch (160) and the switch matrix (130) to capacitively couple the output signal of the first digital-to-analog converter (120A) and the output signal of the second digital-to-analog converter (120B) between the first input and the second input of the comparator (150) for conversion.

6. The analog-to-digital converter (100) according to claim 4, wherein: The controller (180) is configured to control the comparator switch (160) and the switch matrix (130) to capacitively couple the output signal of the first digital-to-analog converter (120A) between the first input and the second input of the comparator (150), or to capacitively couple the output signal of the second digital-to-analog converter (120B) between the first input and the second input of the comparator (150) for sampling, and is configured to control the comparator switch (160) and the switch matrix (130) so as to capacitively couple the output signal of the second digital-to-analog converter (120B) between the first input and the second input of the comparator (150) for conversion after sampling the output of the first digital-to-analog converter (120A); or is configured to control the comparator switch (160) and the switch matrix (130) so as to capacitively couple the output signal of the first digital-to-analog converter (120A) between the first input and the second input of the comparator (150) for conversion after sampling the output of the second digital-to-analog converter (120B).

7. The analog-to-digital converter (100) according to claim 4, wherein: The analog-to-digital converter is single-ended, and wherein the analog-to-digital converter (100) comprises a first capacitor (171) and a second capacitor (172), both of which are connected to the first input of the comparator (150) via their second terminals, and wherein the switch matrix (130) comprises a first switch (131) located between an input terminal (101) for the input signal and a first terminal of the first capacitor (171), a second switch (132) located between the input terminal (101) and the first terminal of the second capacitor (172), a third switch (133) disposed between the first digital-to-analog converter (120A) and the first terminal of the first capacitor (171), a fourth switch (134) disposed between the first digital-to-analog converter (120A) and the first terminal of the second capacitor (172), a fifth switch (135) disposed between the second digital-to-analog converter (120B) and the first terminal of the first capacitor (171), A sixth switch (136) is located between the second digital-to-analog converter (120B) and the first terminal of the second capacitor (172).

8. The analog-to-digital converter (100) according to claim 7, wherein: The controller (180) is configured to The first switch (131), the second switch (132) and the comparator switch (160) are closed, and the third switch (133), the fourth switch (134), the fifth switch (135) and the sixth switch (136) are opened to sample the input signal, And the third switch (133) and the sixth switch (136) are closed, and the first switch (131), the second switch (132), the fourth switch (134), the fifth switch (135) and the comparator switch (160) are opened for conversion.

9. The analog-to-digital converter (100) according to claim 8, wherein: The controller (180) is configured to The third switch (133), the fourth switch (134) and the comparator switch (160) are closed, and the first switch (131), the second switch (132), the fifth switch (135) and the sixth switch (136) are opened to sample the output of the first digital-to-analog converter (120A), or The fifth switch (135), the sixth switch (136) and the comparator switch (160) are closed, and the first switch (131), the second switch (132), the third switch (133) and the fourth switch (134) are opened to sample the output of the second digital-to-analog converter (120B), and After sampling the output of the first digital-to-analog converter (120A), the fifth switch (135) and the sixth switch (136) are closed, and the first switch (131), the second switch (132), the third switch (133), the fourth switch (134) and the comparator switch (160) are opened for conversion, or After sampling the output of the second digital-to-analog converter (120B), the third switch (133) and the fourth switch (134) are closed, and the first switch (131), the second switch (132), the fifth switch (135), the sixth switch (136) and the comparator switch (160) are opened for conversion.

10. The analog-to-digital converter (100) of claim 2, wherein each digital-to-analog converter (120) comprises at least one multiplexer (122), the at least one multiplexer (122) being controlled by an input digital code obtained from the output of the successive approximation register (110) for connecting an internal node of the resistor string (121) to the output of the digital-to-analog converter.

11. The analog-to-digital converter (100) according to claim 2, wherein: The analog-to-digital converter is a differential analog-to-digital converter (100), and wherein the analog-to-digital converter (100) comprises: a first pair of capacitors (171a, 171b) and a second pair of capacitors (172a, 172b), the first pair of capacitors (171a, 171b) being connected to the first input and the second input of the comparator (150) via their second terminals, respectively, and the second pair of capacitors (172a, 172b) being connected to the first input and the second input of the comparator (150) via their second terminals, respectively, and wherein the switch matrix (130) comprises a first pair of switches (131a, 131b) located between a pair of input terminals (101a, 101b) and first terminals of the first pair of capacitors (171a, 171b), a second pair of switches (132a, 132b) located between the pair of input terminals (101a, 101b) and first terminals of the second pair of capacitors (172a, 172b), a third pair of switches (133a, 133b) located between the first digital-to-analog converter (120A) and the first terminals of the first pair of capacitors (171a, 171b), a fourth pair of switches (134a, 134b) disposed between the first digital-to-analog converter (120A) and the first terminals of the second pair of capacitors (172a, 172b), a fifth pair of switches (135a, 135b) located between the second digital-to-analog converter (120B) and the first terminals of the first pair of capacitors (171a, 171b), A sixth pair of switches (136a, 136b) is located between the second digital-to-analog converter (120B) and the first terminals of the second pair of capacitors (172a, 172b).

12. The analog-to-digital converter (100) of claim 2, wherein the analog-to-digital converter (100) is a differential analog-to-digital converter (100), wherein each digital-to-analog converter (120) comprises a matrix (124) of four switches and comprises a first multiplexer (122P) connected to an upper half of the resistor string and a second multiplexer (122N) connected to a lower half of the resistor string, the first multiplexer (122P) and the second multiplexer (122N) being controlled by an input digital code obtained from an output of the successive approximation register (110) using a sign and magnitude encoding, wherein wherein the amplitude controls the first multiplexer and the second multiplexer, and wherein the sign controls the matrix (124) of four switches to connect the output of the first multiplexer to the positive output terminal of the digital-to-analog converter (120) and the output of the second multiplexer to the negative output terminal of the digital-to-analog converter (120) when the sign is positive, and to connect the output of the first multiplexer to the negative output terminal of the digital-to-analog converter (120) and the output of the second multiplexer to the positive output terminal of the digital-to-analog converter (120) when the sign is negative.

13. The analog-to-digital converter (100) for a single-ended analog-to-digital converter (100) according to claim 10 or the analog-to-digital converter (100) for a differential analog-to-digital converter (100) according to claim 12, wherein: The resistor string (121A) of the first digital-to-analog converter (120A) and the resistor string (121B) of the second digital-to-analog converter (120B) are positioned so that a first symmetry axis and a second symmetry axis orthogonal to the first symmetry axis can be identified between the resistors, and wherein the center of gravity of any pair of resistors with the same index in the resistor string (121A) of the first digital-to-analog converter (120A) and the resistor string (121B) of the second digital-to-analog converter (120B) is located exactly at the intersection of the first symmetry axis and the second symmetry axis.

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