An airborne jamming device based on FPGA and embedded SOC system
By adopting airborne interference equipment based on FPGA and embedded SOC systems in the control system, the problems of single control mode, low computing accuracy and insufficient storage capacity are solved, and the effects of diversified control modes, higher precision computing and greater storage processing capabilities are achieved.
Patent Information
- Application Number
- CN202411761387.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-04-04
AI Technical Summary
In the existing control system, the control mode is single, the calculation accuracy is not high, and the storage capacity is insufficient, making it difficult to meet the needs of high-performance application scenarios.
The on-board interference equipment based on FPGA and embedded SOC systems is adopted to realize the collaborative work of high-performance multi-core DSP and large-scale FPGA through the FPGA core board. The embedded SOC core board provides the functions of a multi-processing system development board, and builds real-time clock circuits, storage function circuits, GPIO and interface circuits, wireless WIFI module circuits, network port transformer circuits and power supply circuits on the carrier board to achieve diversified control modes, higher precision computing and greater storage processing capabilities.
It realizes diversification of control modes, improves computing accuracy and enhances storage and processing capabilities, and can better adapt to the needs of high-performance application scenarios.
Smart Images
Figure CN119766266A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to an airborne jamming device based on FPGA and an embedded SOC system. Background Art
[0002] With the development of wireless communication and Internet of Things technology, data-intensive applications have led to an exponential growth in mobile data traffic, which makes interference control technology an important challenge in wireless communication. In addition, modern control systems face challenges from multi-source heterogeneous interference, which is widely present in complex engineering systems and affects the control accuracy of the system.
[0003] For the entire interference module, based on the multifunctional architecture, and the signal is affected by environmental changes, equipment noise, model errors and other factors, its hardware design faces higher complexity, integration and reliability requirements. The use of a single dedicated integrated circuit can no longer meet high-performance application scenarios. In terms of control technology, FPGA is widely used in various industrial control fields due to its high performance, low latency, high reliability and flexibility. FPGA can implement complex control algorithms and has parallel processing capabilities, which makes it perform well in applications that require real-time and high-precision control. Embedded systems are used for control, monitoring, and auxiliary operation of equipment, etc. They are application-centric, and the software and hardware are tailored according to needs. Summary of the invention
[0004] The purpose of the present invention is to provide an airborne jammer based on FPGA and embedded SOC system to solve the problems of single control mode, low calculation accuracy and insufficient storage capacity in the original control system.
[0005] In order to solve the above technical problems, the present invention provides an airborne jamming device based on FPGA and embedded SOC system, comprising: an FPGA core board, an embedded SOC core board and a carrier board;
[0006] The FPGA core board is connected to the carrier board via a high-speed QSH connector to realize working status, workflow control, subsystem IO interface control, signal accumulation, classification, screening, and statistical recognition algorithms;
[0007] The embedded SOC core board is connected to the carrier board through a board-to-board connector, and memory chips of different sizes are selected according to user needs, and various related drivers are assisted in development to realize the storage function of specific signals;
[0008] The carrier board is designed with a low-frequency connector and a high-frequency connector as signal input and output.
[0009] In one embodiment, the FPGA core board is used to cooperate with the carrier board to work. The FPGA core board uses a high-performance multi-core DSP as the main control processor and a large-scale FPGA as auxiliary computing and external interface control to achieve real-time signal processing;
[0010] The DSP is connected to the FPGA via RapidIO, PCIE and SGMII are extended via a high-speed QSH connector, LVDS interface is extended via a high-speed QSH connector, and GTX interface of the FPGA is extended via a high-speed QSH connector.
[0011] In one embodiment, the embedded SOC core board is used to cooperate with the carrier board. The embedded SOC core board is a multi-processing system development board consisting of two main parts: a processing system composed of a dual-core ARM as the core, and a programmable logic part equivalent to an FPGA.
[0012] In one embodiment, a plurality of functional circuits are built in the carrier board, including a real-time clock circuit, a storage function circuit, a GPIO and interface circuit, a wireless WIFI module circuit, a network port transformer circuit, and a power supply circuit;
[0013] The real-time clock circuit is connected to the FPGA core board; the storage function circuit is respectively connected to the FPGA core board and the embedded SOC core board; the GPIO and interface circuit are respectively connected to the FPGA core board and the embedded SOC core board; the wireless WIFI module circuit is connected to the FPGA core board; the network port transformer circuit is connected to the embedded SOC core board; the power supply circuit is connected to the FPGA core board, the embedded SOC core board, the real-time clock circuit, the storage function circuit, the GPIO and interface circuit, the wireless WIFI module circuit, and the network port transformer.
[0014] In one embodiment, the real-time clock circuit is used to stably time and provide accurate time information, record event timestamps, and execute timing tasks; at the same time, the clock signal synchronizes the operation of each component to ensure that data is transmitted and processed at the correct time; the real-time clock circuit is configured with a backup battery, and when the power supply ends, the backup battery switches seamlessly and the clock chip continues to time; the real-time clock circuit is equipped with a low-power real-time clock chip to support multiple functions of calendar and clock timing; the real-time clock circuit is connected to the FPGA core board, communicates through the I2C interface, and realizes the serial port response mode.
[0015] In one embodiment, the GPIO and interface circuit includes a level conversion circuit, a serial port transceiver circuit, and a four-way differential line drive circuit;
[0016] The level conversion circuit solves the problem of conversion between 3.3V and 2.5V data signals in the circuit, as well as the problem of 3.3V signal driving. For large-scale directional signals, an 8-way level conversion chip is used to drive them. Some spare I / O ports are reserved during the design process. One side of the level conversion circuit is connected to the FPGA core board through a QSH connector, and the other side inputs or outputs various signals through a connector.
[0017] The serial port transceiver circuit achieves stronger anti-interference ability and good stability. Two 422 serial port circuits are designed in the serial port transceiver circuit, one for real-time configuration and the other for technical debugging. The chip is powered by 3.3V, and the transmission rate can reach 10Mbps. Both the serial port configuration and the serial port debugging are connected to the FPGA core board.
[0018] The four-way differential line drive circuit realizes long-distance signal output, and improves the stability and anti-interference ability of signal transmission by converting and transmitting differential signals. It is particularly suitable for high-speed and high-precision signal processing in the system. The four-way differential line drive circuit is connected to the FPGA core board.
[0019] In one embodiment, the storage circuit includes an SPI FLASH storage circuit, an EEPROM storage circuit and a TF card storage circuit; the storage circuit requires a large amount of data storage and processing, mainly storing configuration parameters, work logs and specific data;
[0020] The SPI FLASH storage circuit is connected to the FPGA core board to realize code storage and fast reading and writing, and can maintain data without power supply; the flash memory chip is small in size, and multiple memory chips are used to meet the requirement of sufficient storage capacity;
[0021] The EEPROM storage circuit is connected to the FPGA core board to retain the stored information in the event of a power outage, and to erase and rewrite data multiple times;
[0022] The TF card storage circuit is connected to the embedded SOC core board, and mainly cooperates with the embedded SOC core board to expand its storage space and store a large amount of data.
[0023] In one embodiment, the wireless WIFI module circuit is connected to the FPGA core board to achieve high-speed data transmission, support the connection of wireless terminal devices, and is compatible with various network protocols, including 802.11 protocol specifications and TCP / IP protocol, and supports 2.4GHz to 2.5GHz frequency bands; the wireless WIFI module is externally connected to an IPEX antenna and is connected to other RF cables via an IPEX to SMA cable.
[0024] In one embodiment, the network port transformer circuit is connected to the embedded SOC core board, and is mainly used for isolation and conversion of high-speed signals, improving the stability and reliability of network transmission, and preventing interference between devices with different voltages. The network port transformer circuit enhances the differential signal of PHY transmission through a combination of differential mode coupling and coil coupling, thereby improving data transmission quality.
[0025] In one embodiment, the power supply function circuit is connected to the FPGA core board, the embedded SOC core board, the real-time clock circuit, the storage circuit, the GPIO and interface circuit, the wireless WIFI module circuit, and the network port transformer, and is mainly responsible for converting the external 12V power supply into 5V, 3.3V, 2.5V and 1.8V required by various functional circuits on the carrier board through voltage reduction; it is mainly achieved through a DC-DC step-down chip and a low voltage difference linear voltage regulator circuit.
[0026] The present invention provides an airborne jammer based on FPGA and embedded SOC system, which realizes diversified control modes of the entire module, more accurate calculations and storage and processing of higher-level data by carrying two core boards, FPGA and embedded SOC, and building a variety of peripheral circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 The present invention provides a block diagram of the composition of an airborne jamming device system based on FPGA and embedded SOC system.
[0028] Figure 2 It is a block diagram of the functional circuits of the carrier board in the present invention.
[0029] Figure 3 It is the connection mode and composition block diagram of each module in the present invention. DETAILED DESCRIPTION
[0030] The following is a further detailed description of an airborne jammer based on FPGA and embedded SOC system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0031] The present invention provides an airborne jamming device based on FPGA and embedded SOC system, and its system composition block diagram is as follows: Figure 1As shown, it includes: an FPGA core board, an embedded SOC core board and a carrier board; the FPGA core board is connected to the carrier board through a high-speed QSH connector, and the embedded SOC core board is connected to the carrier board through a board-to-board connector. The carrier board is designed with a low-frequency connector and a high-frequency connector as signal input and output.
[0032] The FPGA core board is buckled on the carrier board through a high-speed QSH connector to cooperate with the carrier board. The FPGA core board uses a high-performance multi-core DSP as the main control processor and a large-scale FPGA as auxiliary computing and external interface control to achieve real-time signal processing. DSP connects to FPGA through RapidIO, expands PCIE and SGMII through a high-speed QSH connector, expands LVDS interface through a high-speed QSH connector, and expands FPGA's GTX interface through a high-speed QSH connector. The FPGA core board mainly realizes working status, workflow control, subsystem IO interface control; signal accumulation, classification, screening, statistical recognition and other algorithms.
[0033] The embedded SOC core board is buckled on the carrier board through a board-to-board connector and works with the carrier board. The embedded SOC core board is a multi-processing system development board, which consists of two main parts: a processing system composed of a dual-core ARM as the core, and a programmable logic part equivalent to a piece of FPGA. The embedded SOC core board can select memory chips of different sizes according to user needs and assist in the development of various related drivers. In the present invention, it mainly realizes the storage function of specific signals.
[0034] The carrier board is built with multiple functional circuits, such as Figure 2 The figure shows a block diagram of the functional circuits of the carrier board, including a real-time clock circuit, a storage function circuit, a GPIO and interface circuit, a wireless WIFI module circuit, a network port transformer circuit, and a power supply circuit. The real-time clock circuit is connected to the FPGA core board; the storage function circuit is respectively connected to the FPGA core board and the embedded SOC core board; the GPIO and interface circuit are respectively connected to the FPGA core board and the embedded SOC core board; the wireless WIFI module circuit is connected to the FPGA core board; the network port transformer circuit is connected to the embedded SOC core board; the power supply circuit is connected to the FPGA core board, the embedded SOC core board, the real-time clock circuit, the storage function circuit, the GPIO and interface circuit, the wireless WIFI module circuit, and the network port transformer.
[0035] The real-time clock circuit is designed on the carrier board, which can stably time and provide accurate time information, which is used to record the timestamp of events and execute timing tasks; at the same time, the clock signal can synchronize the operation of various components to ensure that data is transmitted and processed at the correct time. The real-time clock circuit needs to be equipped with a backup battery. When the power supply ends, the backup battery can be seamlessly switched, and the clock chip continues to time.
[0036] The real-time clock circuit is equipped with a low-power real-time clock chip, which supports multiple functions such as calendar (year, month, day, hour, minute, second) and clock timing. Figure 3 As shown, the real-time clock circuit is connected to the FPGA core board and communicates through the I2C interface to realize the serial port response mode.
[0037] The GPIO and interface circuits designed on the carrier board include a level conversion circuit, a serial port transceiver circuit, and a four-way differential line drive circuit.
[0038] The level conversion circuit solves the problem of converting 3.3V and 2.5V data signals in the circuit, as well as the problem of driving 3.3V signals. For large-scale directional signals, an 8-way level conversion chip can be used to drive them; in the design process, some spare I / O ports need to be reserved, so two-way level conversion chips can be selected as signal input and output to make signal control more flexible. Figure 3 As shown, the level conversion circuit is connected to the FPGA core board through a QSH connector on one side, and inputs or outputs various signals through the connector on the other side.
[0039] The serial port transceiver circuit can achieve stronger anti-interference ability and good stability. Two 422 serial port circuits are designed in this circuit, one for real-time configuration and the other for technical debugging. The chip is powered by 3.3V and the transmission rate can reach 10Mbps. Figure 3 As shown, serial port configuration and serial port debugging are both connected to the FPGA core board.
[0040] The four-way differential line drive circuit can realize the long-distance output of the signal, and improve the stability and anti-interference ability of the signal transmission by converting and transmitting the differential signal, and is particularly suitable for the high-speed and high-precision signal processing of the system. The four-way differential line drive circuit is connected to the FPGA core board.
[0041] The storage circuit is designed on the carrier board, including SPI FLASH storage circuit, EEPROM storage circuit and TF card storage circuit. The storage circuit requires a large amount of data storage and processing, mainly storing configuration parameters, work logs and specific data.
[0042] The SPI FLASH storage circuit can realize code storage and fast reading and writing, and can maintain data without power supply. The flash memory chip is small in size, and multiple memory chips can be used to meet the demand for sufficient storage capacity. The SPI FLASH storage circuit is connected to the FPGA core board.
[0043] The EEPROM storage circuit can retain the stored information even when the power is off, and can erase and rewrite data multiple times. The EEPROM storage circuit is connected to the FPGA core board.
[0044] The TF card storage circuit mainly cooperates with the embedded SOC core board to expand its storage space and store a large amount of data. The TF card storage circuit is connected to the embedded SOC core board.
[0045] The wireless WIFI module circuit designed on the carrier board can realize high-speed data transmission, support the connection of wireless terminal devices, and is compatible with various network protocols, including 802.11 protocol specifications and TCP / IP protocol, and supports 2.4GHz to 2.5GHz frequency band. The wireless WIFI module is connected to an external IPEX antenna, which can be connected to other RF cables via an IPEX to SMA cable. The wireless WIFI module circuit is connected to the FPGA core board.
[0046] The network port transformer circuit designed on the carrier board is mainly used for the isolation and conversion of high-speed signals, improving the stability and reliability of network transmission, and preventing interference between devices with different voltages. It enhances the differential signal transmitted by PHY through a combination of differential mode coupling and coil coupling, thereby improving the quality of data transmission. The network port transformer circuit is connected to the embedded SOC core board.
[0047] The power function circuit designed on the carrier board is mainly responsible for converting the external 12V power supply into 5V, 3.3V, 2.5V and 1.8V required by each functional circuit on the carrier board through voltage reduction; it is mainly realized by DC-DC voltage reduction chip and low voltage difference linear voltage regulator circuit. The power function circuit is connected to the FPGA core board, the embedded SOC core board, the real-time clock circuit, the storage circuit, the GPIO and interface circuit, the wireless WIFI module circuit, and the network port transformer.
[0048] The present invention provides an airborne jamming device based on FPGA and embedded SOC system, which realizes the jamming working state, workflow control and specific data storage according to the overall technical requirements, and realizes the external interface expansion at the same time, and completes real-time signal processing. The FPGA core board realizes the algorithms such as the accumulation, classification, screening, and statistical identification of the working state and workflow control subsystem IO interface control signals; the embedded SOC core board realizes the specific data storage function, and the carrier board builds a multifunctional circuit. The system has the functions of real-time feedback on the working state of the equipment, real-time setting of working parameters, storage of working logs, sampling and processing of information such as filter channels, jamming start time, duration, sample frequency, width, and results within the window; thereby achieving the goals of diversified control modes, more accurate calculations, and storage and processing of larger data magnitudes, and can also be widely used in various airborne jamming control systems.
[0049] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. An airborne jamming device based on FPGA and embedded SOC system, characterized in that: include: FPGA core board, embedded SOC core board and carrier board; The FPGA core board is connected to the carrier board via a high-speed QSH connector to realize working status, workflow control, subsystem IO interface control, signal accumulation, classification, screening, and statistical recognition algorithms; The embedded SOC core board is connected to the carrier board through a board-to-board connector, and memory chips of different sizes are selected according to user needs, and various related drivers are assisted in development to realize the storage function of specific signals; The carrier board is designed with a low-frequency connector and a high-frequency connector as signal input and output.
2. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 1, characterized in that: The FPGA core board is used to cooperate with the carrier board to work. The FPGA core board uses a high-performance multi-core DSP as the main control processor and a large-scale FPGA as auxiliary calculation and external interface control to achieve real-time signal processing; The DSP is connected to the FPGA via RapidIO, PCIE and SGMII are extended via a high-speed QSH connector, LVDS interface is extended via a high-speed QSH connector, and GTX interface of the FPGA is extended via a high-speed QSH connector.
3. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 1, characterized in that: The embedded SOC core board is used to work with the carrier board. The embedded SOC core board is a multi-processing system development board consisting of two main parts: a processing system composed of a dual-core ARM as the core, and a programmable logic part equivalent to a FPGA.
4. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 1, characterized in that: The carrier board is built with multiple functional circuits, including a real-time clock circuit, a storage function circuit, a GPIO and interface circuit, a wireless WIFI module circuit, a network port transformer circuit, and a power supply circuit; The real-time clock circuit is connected to the FPGA core board; the storage function circuit is respectively connected to the FPGA core board and the embedded SOC core board; the GPIO and interface circuit are respectively connected to the FPGA core board and the embedded SOC core board; the wireless WIFI module circuit is connected to the FPGA core board; the network port transformer circuit is connected to the embedded SOC core board; the power supply circuit is connected to the FPGA core board, the embedded SOC core board, the real-time clock circuit, the storage function circuit, the GPIO and interface circuit, the wireless WIFI module circuit, and the network port transformer.
5. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 4, characterized in that: The real-time clock circuit is used to stably time and provide accurate time information, record event timestamps, and perform timing tasks; at the same time, the clock signal synchronizes the operation of each component to ensure that data is transmitted and processed at the correct time; The real-time clock circuit is equipped with a backup battery. When the power supply ends, the backup battery switches seamlessly and the clock chip continues to time. The real-time clock circuit is equipped with a low-power real-time clock chip to support multiple functions such as calendar and clock timing; The real-time clock circuit is connected to the FPGA core board and communicates via the I2C interface to implement a serial port response mode.
6. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 4, characterized in that: The GPIO and interface circuit includes a level conversion circuit, a serial port transceiver circuit, and a four-way differential line drive circuit; The level conversion circuit solves the problem of conversion between 3.3V and 2.5V data signals in the circuit, as well as the problem of 3.3V signal driving. For large-scale directional signals, an 8-way level conversion chip is used to drive them. Some spare I / O ports are reserved during the design process. One side of the level conversion circuit is connected to the FPGA core board through a QSH connector, and the other side inputs or outputs various signals through a connector. The serial port transceiver circuit achieves stronger anti-interference ability and good stability. Two 422 serial port circuits are designed in the serial port transceiver circuit, one for real-time configuration and the other for technical debugging. The chip is powered by 3.3V, and the transmission rate can reach 10Mbps. Both the serial port configuration and the serial port debugging are connected to the FPGA core board. The four-way differential line drive circuit realizes long-distance signal output, and improves the stability and anti-interference ability of signal transmission by converting and transmitting differential signals. It is particularly suitable for high-speed and high-precision signal processing in the system. The four-way differential line drive circuit is connected to the FPGA core board.
7. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 4, characterized in that: The storage circuit includes a SPIFLASH storage circuit, an EEPROM storage circuit and a TF card storage circuit; the storage circuit requires a large amount of data storage and processing, mainly storing configuration parameters, work logs and specific data; The SPIFLASH storage circuit is connected to the FPGA core board to realize code storage and fast reading and writing, and can maintain data without power supply; Flash memory chips are small in size, and multiple memory chips are used to meet the demand for large enough storage capacity; The EEPROM storage circuit is connected to the FPGA core board to retain the stored information in the event of a power outage, and to erase and rewrite data multiple times; The TF card storage circuit is connected to the embedded SOC core board, and mainly cooperates with the embedded SOC core board to expand its storage space and store a large amount of data.
8. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 4, characterized in that: The wireless WIFI module circuit is connected to the FPGA core board to achieve high-speed data transmission, support the connection of wireless terminal devices, and is compatible with various network protocols, including 802.11 protocol specifications and TCP / IP protocol, and supports 2.4GHz to 2.5GHz frequency bands; the wireless WIFI module is externally connected to an IPEX antenna and is connected to other RF cables via an IPEX to SMA cable.
9. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 4, characterized in that: The network port transformer circuit is connected to the embedded SOC core board, and is mainly used for isolating and converting high-speed signals, improving the stability and reliability of network transmission, and preventing interference between devices with different voltages. The network port transformer circuit enhances the differential signal of PHY transmission through a combination of differential mode coupling and coil coupling, thereby improving data transmission quality.
10. The airborne jamming device based on FPGA and embedded SOC system as claimed in claim 4, characterized in that: The power supply function circuit is connected to the FPGA core board, the embedded SOC core board, the real-time clock circuit, the storage circuit, the GPIO and interface circuit, the wireless WIFI module circuit, and the network port transformer, and is mainly responsible for converting the external 12V power supply into 5V, 3.3V, 2.5V and 1.8V required by various functional circuits on the carrier board through voltage reduction; it is mainly achieved through a DC-DC step-down chip and a low voltage difference linear voltage regulator circuit.