CAN bus controller, message caching method and electronic equipment

Abstract

The invention relates to the technical field of bus controller design, and particularly provides a CAN bus controller, a message caching method and electronic equipment, a cache region in the CAN bus controller comprises a first sending cache partition, a second sending cache partition, a first receiving cache partition, a second receiving cache partition and a filtering partition, the first sending cache partition and the first receiving cache partition are target type cache partitions, the second sending cache partition and the second receiving cache partition are non-target type cache partitions, and the target type cache partition is any type of cache partition in multiple types of cache partitions; on the basis of reducing the chip area of the cache region, the performance integrity of the cache region is ensured, and the pressure of controller software is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of bus controller design, and in particular to a CAN bus controller, a message buffering method and an electronic device. Background Art

[0002] CAN (Controller Area Network) bus is an asynchronous serial bus that supports multiple hosts. It is widely used in many fields such as automotive industry and industrial control for its high performance, high reliability, flexible design and low price. Among them, CAN nodes usually include CAN transceivers and CAN controllers.

[0003] In the related art, the mailbox of the CAN controller includes a buffer area, which can usually be configured into multiple partitions to facilitate the controller to send and receive data; for example, the buffer area in the CAN controller can be configured to include First Input First Output (FIFO) type partitions, dedicated buffer type partitions and / or queue type partitions.

[0004] However, in the CAN controller provided in the related art, the types of multiple partitions in the cache area are usually fixed. When the cache area contains at least two types of partitions and the number of each partition includes multiple, the cache area requires a larger storage space, which leads to a larger chip area. Conversely, in order to reduce the area of ​​the chip where the cache area is located, a cache area can be designed to contain only one type of partition, but the cache area's capabilities regarding other types of partitions need to be transferred to the controller software, which increases the pressure on the controller software. Summary of the invention

[0005] The present disclosure is proposed in view of the above problems. The present disclosure provides a CAN bus controller, a message buffering method and an electronic device. The present disclosure reduces the chip area of ​​the buffer area, ensures the performance integrity of the buffer area, and reduces the pressure on the controller software.

[0006] According to one aspect of the present disclosure, a CAN bus controller is provided, wherein the CAN bus controller includes a cache area, wherein the cache area includes: a first sending cache partition, a second sending cache partition, a first receiving cache partition, a second receiving cache partition and a filtering partition, wherein the first sending cache partition and the first receiving cache partition are target type cache partitions, the second sending cache partition and the second receiving cache partition are non-target type cache partitions, and the target type cache partition is any type of cache partition among multiple types of cache partitions; The first sending buffer partition and the second sending buffer partition are used to buffer messages to be sent; The first receiving cache partition and the second receiving cache partition are used to cache messages to be received; The cache partition is used to store at least one cacheable message identifier that can be cached in the cache area.

[0007] According to another aspect of the present disclosure, a message caching method is provided, which is applied to the above-mentioned CAN bus controller and includes: In response to obtaining a message to be processed, comparing the message identifier of the message to be processed with each cacheable message identifier in the filtering partition, wherein the message to be processed is a message to be sent and a message to be received; When the message identifier of the to-be-processed message is the same as any cacheable message identifier, the to-be-processed message is pushed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition.

[0008] According to yet another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned CAN bus controller.

[0009] The CAN bus controller, message caching method and electronic device provided by the present disclosure, on the one hand, the cache area of ​​the controller can send and receive messages through two different types of cache partitions, the cache area containing the two types of cache partitions does not require an excessively large chip area, and can prevent the data processing pressure caused by a single type of cache partition on the controller software, thereby achieving the goal of ensuring the performance integrity of the cache area on the basis of reducing the chip area of ​​the cache area, thereby reducing the pressure on the controller software; on the other hand, the two types of multiple partitions of the cache area can be configured based on actual needs, without the need to fix the type of each receiving and sending partition in the cache area, so that the partitions of the cache area can be configured in a targeted manner according to the actual scenario, thereby improving the flexibility of the controller's usage scenarios.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0012] Figure 1 It is a schematic diagram of a CAN bus controller according to an embodiment of the present disclosure.

[0013] Figure 2 is a schematic diagram of another CAN bus controller according to an embodiment of the present disclosure.

[0014] Figure 3 It is a flowchart of a message caching method according to an embodiment of the present disclosure.

[0015] Figure 4 It is a flowchart of another message caching method according to an embodiment of the present disclosure.

[0016] Figure 5 It is a hardware block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present disclosure more obvious, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0018] In order to solve the above problems, the present disclosure provides a CAN bus controller, which includes a buffer area, such as Figure 1 As shown, the cache area includes: a first sending cache partition 101, a second sending cache partition 102, a first receiving cache partition 103, a second receiving cache partition 104 and a filtering partition 105, the first sending cache partition 101 and the first receiving cache partition 103 are target type cache partitions, the second sending cache partition 102 and the second receiving cache partition 104 are non-target type cache partitions, and the target type cache partition is any type of cache partition among multiple types of cache partitions; The first sending buffer partition and the second sending buffer partition are used to buffer the messages to be sent, so that the controller can provide the messages to be sent to the transceiver for transmission to the CAN bus.

[0019] The first receiving cache partition and the second receiving cache partition are used to cache the to-be-received message, so as to facilitate the controller to provide the to-be-received message to the processor for processing; It should be noted that in the embodiments of the present disclosure, each node on the CAN bus can process different pending messages. For example, in a vehicle network, the nodes on the CAN bus can be central control nodes, engine nodes, intelligent traffic system (ITS) nodes, and safety control nodes.

[0020] In order to prevent the CAN bus controller of each node from processing messages that cannot be processed by the node, the cache partition is used to store at least one cacheable message identifier that can be cached in the cache area, so as to determine whether the to-be-sent message or the to-be-received message received by the CAN bus controller needs to be cached by the cache area in the CAN bus controller of the node.

[0021] To summarize, the CAN bus controller provided in the embodiments of the present invention, on the one hand, the cache area of ​​the controller can send and receive messages through two different types of cache partitions. The cache area including the two types of cache partitions does not require an excessively large chip area, and can prevent the data processing pressure caused by a single type of cache partition on the controller software, thereby achieving the goal of ensuring the performance integrity of the cache area on the basis of reducing the chip area of ​​the cache area, thereby reducing the pressure on the controller software; on the other hand, the two types of multiple partitions of the cache area can be configured based on actual needs, without the need to fix the type of each transceiver partition in the cache area, so that the partitions of the cache area can be configured in a targeted manner according to the actual scenario, thereby improving the flexibility of the controller's usage scenarios.

[0022] It can be understood that in the embodiments of the present disclosure, the CAN bus controller is generally a controller of a node on the CAN bus, and each node is generally composed of a transceiver, a CAN bus controller connected to the transceiver, and a processor connected to the CAN bus controller; wherein the transceiver is used to transmit the to-be-received messages on the CAN bus to the processor for processing through the CAN bus controller; the transceiver is also used to receive the to-be-sent messages obtained by the CAN bus controller from the processor, and forward the to-be-sent messages to the CAN bus; the cacheable message identifier of the CAN bus controller of each node is pre-configured, and during the initialization process after the CAN bus controller is running, the cacheable message identifier can be written into the filter partition of the bus controller cache area of ​​each node, so that the controller of each node can filter the obtained to-be-processed messages.

[0023] It should be noted that in the embodiment of the present disclosure, the various types of cache partitions may include FIFO class, dedicated cache class and queue class; the first sending cache partition and the first receiving cache partition, the ability to process pending messages with the target type cache partition, the size of each cache partition (ie, the starting address), and at least one cacheable message identifier are achieved through the configuration of the cache area.

[0024] For example, configuring the first sending cache partition and the first receiving cache partition as dedicated type cache partitions, and configuring the second sending cache partition and the second receiving cache partition as fifo type cache partitions can be configured in advance. During the initialization process after the controller is running, the first sending cache partition and the first receiving cache partition in the cache area can operate as dedicated type cache partitions in response to the configuration information, and the second sending cache partition and the second receiving cache partition can operate as fifo type cache partitions in response to the configuration information.

[0025] In an optional embodiment, if Figure 2 As shown, the first sending cache partition 101 is a dedicated sending cache partition, the second sending cache partition 102 is a first-in-first-out fifo sending cache partition, the first receiving cache partition 103 is a dedicated receiving cache partition, and the second receiving cache partition 104 is a fifo sending cache partition, wherein the first sending cache partition and the first receiving cache partition are used to cache a CAN message, the second sending cache partition and the second receiving cache partition are used to cache CAN messages of a preset depth, the message processing priority of the first sending cache partition is higher than the message processing priority of the second sending cache partition, and the message processing priority of the first receiving cache partition is higher than the message processing priority of the second sending cache partition, wherein the preset depth can be determined based on actual needs, and the embodiment of the present disclosure does not limit this. The to-be-processed messages received in the cache area can be cached by using the fifo type and the dedicated type of cache partitions. Since the message processing priority of the dedicated type of cache partition is higher than the message processing priority of the fifo type of cache partition, it can meet the priority processing requirements of timely messages, but also ensure the processing requirements of non-timely messages.

[0026] Among them, the multiple partitions of the CAN bus controller are Figure 2 In the case of multiple partitions shown in, the first sending cache partition and the first receiving cache partition in the CAN bus controller are dedicated cache partitions, that is, the first sending cache partition and the first receiving cache partition are partitions for processing timely messages based on the FullCAN strategy, and the second sending cache partition and the second receiving cache partition are fifo cache partitions, that is, the second sending cache partition and the second receiving cache partition are cache partitions for processing non-timely messages based on the BasicCAN strategy.

[0027] Optionally, when the cache area is configured to include a dedicated cache partition and a fifo cache partition, the function of the fifo cache partition can be turned off without caching messages in a fifo manner to reduce the energy consumption of the CAN bus controller.

[0028] In an optional implementation, the second sending cache partition in the cache area is a closable cache partition. In a scenario where there is no need to send non-timely messages, the second sending cache partition for caching non-timely messages to be sent in a fifo manner may not be enabled, thereby reducing resource consumption of the CAN bus controller.

[0029] In an optional implementation, the second receiving cache partition is a closable cache partition. In a scenario where no non-timely messages need to be received, the second receiving cache partition for caching non-timely messages to be sent in a fifo manner may be disabled, thereby reducing resource consumption of the CAN bus controller.

[0030] It should be noted that in the embodiments of the present disclosure, not only the type and size of each partition in the cache area, whether to enable the fifo cache partition, and the cacheable message identifier can be configured, but also the maximum cached message amount of the entire cache area, the number of multiple cacheable message identifiers, the cacheable message amount of the fifo send cache partition (preset depth), the type and communication protocol of the CAN bus system used for message transmission, etc. can all be achieved through configuration. Specifically, it can be determined based on the application scenario of the CAN bus controller, and the embodiments of the present disclosure do not limit this.

[0031] For example, in the vehicle body control chip application scenario, CANBUS is mainly used to receive messages, and the number of sent messages is relatively small, as shown in Table 1. Table 1 shows a configuration information table when the memory size of the cache area does not exceed 2KB.

[0032] Table 1

[0033] Among them, in Table 1, the maximum number of messages that can be cached by all partitions of the configured buffer area is 71, the parameter value of the fifo send buffer partition switch is 1, indicating that the buffer area can process messages through the fifo send buffer partition, and the number of messages that can be cached by the fifo send buffer partition is 7, the number of multiple cacheable message identifiers is 1, the parameter value of the CAN bus with flexible data rate (CAN FD) system switch is 0, indicating that message processing is not performed through the CAN FD system, and the communication protocol used is CIA603.

[0034] like Figure 3 As shown, Figure 3 A flow chart of a message caching method provided by an embodiment of the present disclosure is shown. The message caching method can be applied to the above-mentioned CAN bus controller and is implemented by CAN bus controller software in the CAN bus controller, including: Step S301, in response to obtaining a message to be processed, comparing the message identifier of the message to be processed with each cacheable message identifier in the filtering partition; The messages to be processed are messages to be sent and messages to be received; Step S302: When the message identifier of the message to be processed is the same as any cacheable message identifier, the message to be processed is pushed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition.

[0035] To sum up, in the message caching method provided in the embodiment of the present invention, during the process of sending and receiving messages through cache partitions including two different types, the cache area including the two types of cache partitions does not need an excessively large chip area, which not only prevents the data processing pressure on the controller software caused by a single type of cache partition, but also achieves the goal of ensuring the performance integrity of the cache area on the basis of reducing the chip area of ​​the cache area; and the cacheable message identifier in the filter partition can be used to filter the messages to be processed, thereby improving the processing reliability of the messages to be processed.

[0036] In an optional implementation, the message to be processed is a message to be sent, the first sending cache partition is a dedicated sending cache partition, and the process of pushing the message to be processed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: when it is determined that the message to be sent is a FullCAN message, the message to be sent is pushed to the first sending cache partition, wherein the first sending cache partition is used to cache the message to be sent and instruct to send the message to the transceiver. Since FullCAN type messages are messages with high timeliness requirements, when it is determined that the message to be sent is a FullCAN type message, the message to be sent can be pushed to the dedicated sending cache partition to achieve timely sending of the message.

[0037] Among them, the filtering partition can determine whether the message to be sent is a FullCAN message through the message ID in the CAN message data of the message to be sent; wherein, when the message ID is the same as the identifier of the FullCAN message, it can be determined that the message to be sent is a FullCAN message; the first sending cache partition indicates that the message to be sent is sent to the transceiver, which means that the first sending cache partition instructs the CAN bus controller software to send the message to be sent to the transceiver.

[0038] In an optional implementation, the message to be processed is a message to be sent, the second sending cache partition is a fifo sending cache partition, and the process of pushing the message to be processed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: when it is determined that the message to be sent is a BasicCAN message, the message to be sent is pushed to the second sending cache partition, wherein the second sending cache partition is used to write the message to be sent, and when it is determined that the multiple messages to be sent cached in the second sending cache partition are the same as the number of cacheable messages specified by the preset depth, the multiple messages to be sent are instructed to be sent to the transceiver. Since BasicCAN type messages are messages that do not require high timeliness, when it is determined that the message to be sent is a BasicCAN type message, the message to be sent can be pushed to the fifo sending cache partition, and when the number of messages in the fifo sending cache partition reaches the upper limit, batch sending of messages can be achieved.

[0039] The second sending buffer partition instructing the multiple messages to be sent to the transceiver means that the second sending buffer partition instructs the CAN bus controller software to send the multiple messages to be sent to the transceiver.

[0040] In an optional implementation, the message to be processed is a message to be received, the first receiving cache partition is a dedicated receiving cache partition, and the process of pushing the message to be processed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: when it is determined that the message to be received is a FullCAN message, the message to be received is pushed to the first receiving cache partition, wherein the first receiving cache partition is used to cache the message to be received and instruct to send the message to be received to the processor. Since FullCAN type messages are messages with high timeliness requirements, when it is determined that the message to be received is a FullCAN type message, the message to be received can be pushed to the dedicated receiving cache partition to achieve timely forwarding of the message.

[0041] The first receiving cache partition instructing that the message to be received is sent to the processor means that the first receiving cache partition instructs the CAN bus controller software to send the message to be received to the processor.

[0042] In an optional implementation, the message to be processed is a message to be received, the second receiving cache partition is a fifo receiving cache partition, and the process of pushing the message to be processed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: when it is determined that the message to be received is a BasicCAN message, the message to be received is pushed to the second receiving cache partition, wherein the second receiving cache partition is used to write the message to be received, and when it is determined that the multiple messages to be received cached in the second receiving cache partition are the same as the number of cacheable messages specified by the preset depth, instructing to send the multiple messages to be received to the processor. Since BasicCAN type messages are messages with non-timely requirements, when it is determined that the message to be received is a BasicCAN type message, the message to be received can be pushed to the fifo receiving cache partition, and when the number of messages in the fifo receiving cache partition reaches the upper limit, batch forwarding of messages can be achieved.

[0043] The second receiving cache partition instructing that the multiple messages to be received are sent to the processor means that the second receiving cache partition instructs the CAN bus controller software to send the multiple messages to be received to the processor.

[0044] For example, the buffer area of ​​the CAN bus controller is as follows Figure 2 In the case of the cache area shown, Figure 4 As shown, Figure 4 A flow chart of another message caching method provided by an embodiment of the present disclosure is shown, including: Step S401, obtaining a message to be processed; Step S402, comparing the message identifier in the message to be processed with each cacheable message identifier in the plurality of cacheable message identifiers in turn, to determine whether the message identifier of the message to be processed is the same as any cacheable message identifier; Step S403, if the message identifier of the message to be processed is different from each cacheable message identifier, filtering the message to be processed; Step S404, if the message identifier of the message to be processed is the same as any cacheable message identifier, fuzzy matching is performed on the message to be processed, and it is determined whether the fuzzy matching is successful; Step S405, if the fuzzy match succeeds, then if the message to be processed is a message to be sent, the message to be processed is sent to the second sending cache partition, or if the message to be processed is a message to be received, the message to be processed is sent to the second receiving cache partition.

[0045] Step S406: If the fuzzy match is unsuccessful, then if the message to be processed is a message to be sent, the message to be processed is sent to the first sending cache partition, or if the message to be processed is a message to be received, the message to be processed is sent to the first receiving cache partition.

[0046] It should be noted that, when the fuzzy matching is successful, it indicates that the message to be processed is a non-timely message. On the contrary, when the fuzzy matching is unsuccessful, it indicates that the message to be processed is a timely message.

[0047] The exemplary embodiment of the present disclosure further provides an electronic device, which is a node device of each node on a CAN bus, and the electronic device includes the CAN bus controller in the above embodiment.

[0048] refer to Figure 5 , a block diagram of an electronic device 500 that can be used as the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0049] like Figure 5 As shown, the electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0050] A plurality of components in the electronic device 500 are connected to the I / O interface 505, including: an input unit 506, an output unit 507, a storage unit 508, and a communication unit 509. The input unit 506 may be any type of device capable of inputting information to the electronic device 500, and the input unit 506 may receive input digital or character information, and generate key signal inputs related to user settings and / or function control of the electronic device. The output unit 507 may be any type of device capable of presenting information, and may include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 508 may include, but is not limited to, a disk, an optical disk. The communication unit 509 allows the electronic device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0051] The computing unit 501 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above. For example, in some embodiments, the method of the exemplary embodiment of the present disclosure may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 500 via the ROM 502 and / or the communication unit 509. In some embodiments, the computing unit 501 may be configured to perform the method of the exemplary embodiment of the present disclosure in any other appropriate manner (e.g., by means of firmware).

[0052] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0053] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0054] As used in this disclosure, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0055] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0056] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0057] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc (DVD); it may also be a semiconductor medium, for example, a solid state drive (SSD).

[0058] Although the present disclosure has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely exemplary illustrations of the present disclosure as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A CAN bus controller, comprising a buffer area, characterized in that: The cache area includes: a first sending cache partition, a second sending cache partition, a first receiving cache partition, a second receiving cache partition and a filtering partition, the first sending cache partition and the first receiving cache partition are target type cache partitions, the second sending cache partition and the second receiving cache partition are non-target type cache partitions, and the target type cache partition is any type of cache partition among multiple types of cache partitions; The first sending buffer partition and the second sending buffer partition are used to buffer messages to be sent; The first receiving cache partition and the second receiving cache partition are used to cache messages to be received; The cache partition is used to store at least one cacheable message identifier that can be cached in the cache area.

2. The CAN bus controller according to claim 1, characterized in that: The first sending cache partition is a dedicated sending cache partition, the second sending cache partition is a first-in-first-out fifo sending cache partition, the first receiving cache partition is a dedicated receiving cache partition, and the second receiving cache partition is a fifo sending cache partition, wherein the first sending cache partition and the first receiving cache partition are used to cache a CAN message, the second sending cache partition and the second receiving cache partition are used to cache CAN messages of a preset depth, the message processing priority of the first sending cache partition is higher than the message processing priority of the second sending cache partition, and the message processing priority of the first receiving cache partition is higher than the message processing priority of the second sending cache partition.

3. The CAN bus controller according to claim 2, characterized in that: The second sending cache partition is a closable cache partition.

4. The CAN bus controller according to claim 2, characterized in that: The second receiving cache partition is a closable cache partition.

5. A message caching method, characterized in that: The method is applied to the CAN bus controller according to any one of claims 1 to 3, comprising: In response to obtaining a message to be processed, comparing the message identifier of the message to be processed with each cacheable message identifier in the filtering partition, wherein the message to be processed is a message to be sent and a message to be received; When the message identifier of the to-be-processed message is the same as any cacheable message identifier, the to-be-processed message is pushed to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition.

6. The message caching method according to claim 5, characterized in that: The to-be-processed message is a to-be-sent message, the first sending cache partition is a dedicated sending cache partition, and the pushing of the to-be-processed message to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: When it is determined that the message to be sent is a FullCAN message, the message to be sent is pushed to the first sending buffer partition, wherein the first sending buffer partition is used to buffer the message to be sent and instruct to send the message to be sent to the transceiver.

7. The message caching method according to claim 5, characterized in that: The to-be-processed message is a to-be-sent message, the second sending cache partition is a fifo sending cache partition, and the pushing of the to-be-processed message to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: When it is determined that the message to be sent is a BasicCAN message, the message to be sent is pushed to the second sending cache partition, wherein the second sending cache partition is used to write the message to be sent, and when it is determined that the multiple messages to be sent cached in the second sending cache partition are the same as the number of cacheable messages specified by the preset depth, an instruction is given to send the multiple messages to be sent to the transceiver.

8. The message caching method according to claim 5, characterized in that: The to-be-processed message is a to-be-received message, the first receiving cache partition is a dedicated receiving cache partition, and the pushing of the to-be-processed message to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: When it is determined that the message to be received is a FullCAN message, the message to be received is pushed to the first receiving cache partition, wherein the first receiving cache partition is used to cache the message to be received and instruct to send the message to be received to the processor.

9. The message caching method according to claim 5, characterized in that: The to-be-processed message is a to-be-received message, the second receiving cache partition is a fifo receiving cache partition, and the pushing of the to-be-processed message to the first sending cache partition, the second sending cache partition, the first receiving cache partition, or the second receiving cache partition includes: When it is determined that the message to be received is a BasicCAN message, the message to be received is pushed to the second receiving cache partition, wherein the second receiving cache partition is used to write the message to be received, and when it is determined that the multiple messages to be received cached in the second receiving cache partition are the same as the number of cacheable messages specified by the preset depth, an instruction is given to send the multiple messages to be received to the processor.

10. An electronic device, characterized in that: It comprises a CAN bus controller as described in any one of claims 1-4.

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