Dynamic circuit suitable for switch, switch and system

Abstract

The invention discloses a dynamic circuit suitable for a switch, the switch and a system, the dynamic circuit comprises selection circuits in one-to-one correspondence with transmission ports of the switch, and the selection circuits are used for controlling the transmission ports corresponding to the selection circuits to be electrically connected with one of other transmission ports; the selection circuit comprises a first port and a plurality of second ports, the first port is used for being electrically connected with a transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected with other transmission ports in a one-to-one correspondence manner, one of the first port and the second port is an input end, and the other port is an output port; the first port and the second port are respectively and electrically connected to form a plurality of transmission lines, each transmission line is provided with a plurality of controllable switches, and the controllable switches are used for controlling at most one transmission line to be conducted at the same moment. The data transmission delay of the switch can be reduced, and the working efficiency and the overall performance of the switch can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer network equipment, and in particular to a dynamic circuit, a switch and a system suitable for a switch. Background Art

[0002] With the development of artificial intelligence (AI) technology, computing needs are growing, prompting switches to expand the number of GPUs to meet higher computing power requirements. To this end, the number of ports on the switch continues to increase, which in turn increases the number of input lines of the high fan-in circuit between ports. However, in order to reduce power consumption and increase transistor switching speed, modern process technology has caused the threshold voltage of transistors to continue to decrease, resulting in the weakening of the driving ability of traditional high fan-in circuits, which are gradually replaced by circuits composed of multiple low fan-in circuits.

[0003] like Figure 1 As shown in FIG. 1 , a high fan-in circuit is constructed by cascading multiple low fan-in circuits to accommodate the increasing number of port inputs. These low fan-in circuits are synchronized by clock signals to ensure the correct transmission of data between different ports. Although the low fan-in circuit has lower power consumption and a simpler circuit design, it also meets the expansion requirements of the switch to a certain extent. However, the cascaded circuit design needs to wait for the clock signal during data transmission, which results in a large amount of delay accumulated in data transmission.

[0004] In summary, although low fan-in gate circuits have the advantages of low power consumption and simple design, they need to wait for the clock signal to transmit data, which leads to a large amount of delay in the transmission of data between these gate circuits. This delay not only affects the transmission efficiency of the switch, but also limits the improvement of the overall performance of the system.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The object of the present invention is to provide a dynamic circuit, a switch and a system suitable for a switch, which can improve the data transmission delay problem of the switch and improve the working efficiency and overall performance of the switch.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: A dynamic circuit applicable to a switch, the dynamic circuit comprising a plurality of selection circuits, the selection circuits corresponding to the transmission ports of the switch one by one, the selection circuits being configured to control the transmission port corresponding to the selection circuit to be electrically connected to one of the other transmission ports; The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, and the plurality of second ports are electrically connected to the other transmission ports in a one-to-one correspondence. It should be noted that the “multiple second ports are electrically connected to the other transmission ports in a one-to-one correspondence” in the present invention includes two situations, one is that the plurality of second ports are directly electrically connected to the other transmission ports in a one-to-one correspondence, and the other is that the plurality of second ports are directly electrically connected to the first ports corresponding to the other transmission ports in a one-to-one correspondence, and one of the first port and the second port is configured as an input port, and the other port is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines. A plurality of controllable switches are arranged on each of the transmission lines. The controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

[0008] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the selection circuit further includes a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches; A combination of control lines where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme of the corresponding transmission line, and control schemes of different transmission lines are not repeated.

[0009] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the controllable switch is an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

[0010] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of the control circuits is The number of NMOS switches provided on each transmission line is not less than .

[0011] Further, according to any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of NMOS switch tubes arranged on each of the control lines is not greater than .

[0012] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

[0013] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of the control circuits is The number of CMOS switches provided on each transmission line is not less than .

[0014] Further, according to any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of CMOS switch tubes arranged on each of the control lines is not greater than .

[0015] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the dynamic circuit further includes a clock signal management circuit, the clock signal management circuit includes a first switch tube, a second switch tube and a capacitor, the gate of the first switch tube is configured as an input end of the clock signal, the source of the first switch tube is configured to be electrically connected to the output end of the first power supply, and the drain of the first switch tube is electrically connected to the first end of the capacitor; The gate of the second switch tube is configured as an input end of a clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor; The clock signal management circuit corresponds to the selection circuit one by one, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

[0016] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the clock signal when each selection circuit is working is determined by the following method: If the capacitor is in a non-charged state, the clock signal must be 0; otherwise, the clock signal is 1; and / or, It also includes determining the output signal of the selection circuit when it is working in the following manner: when the clock signal is monitored to be 0, the capacitor is in a charging and discharging state; if the capacitor is in a discharging state, the output signal of the selection circuit is 0; otherwise, the output signal of the selection circuit is 1.

[0017] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube.

[0018] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, each of the selection circuits is layered on the same circuit unit, the number of transmission ports of the switch is N, and N layers of selection circuits are correspondingly arranged on the circuit unit; Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on circuits of different layers.

[0019] Further, according to any one of the technical solutions or a combination of multiple technical solutions mentioned above, a controllable switch is provided on each of the transmission lines, and each of the controllable switches is configured to be independently controlled.

[0020] According to another aspect of the present invention, the present invention provides a network selection circuit, comprising a first port and a plurality of second ports, wherein the first port and the second port are two ports, one of which is configured as an input port and the other port is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines, and a plurality of controllable switches are arranged on each of the transmission lines, and the controllable switches are configured to control at most one of the transmission lines to be turned on at the same time; The selection circuit further comprises a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches; A combination of control lines where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme of the corresponding transmission line, and control schemes of different transmission lines are not repeated.

[0021] According to another aspect of the present invention, the present invention provides a switch, wherein the switch includes the dynamic circuit as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0022] According to another aspect of the present invention, a computer system is provided, comprising a switch as described in any one of the above technical solutions or a combination of multiple technical solutions, and a device that needs to perform data transmission and is electrically connected to a transmission port of the switch.

[0023] The beneficial effects brought by the technical solution provided by the present invention are as follows: a. The present invention simplifies the logic gates of a large number of cascaded multiplexers and demultiplexers repeatedly used in a switch, constructs multiple straight-line transmission lines from the second port to the first port, and outputs data from different sources to the target end by controlling a matrix composed of multiple transmission lines with controllable switches. The dynamic circuit can quickly receive the transmitted data within one clock cycle, avoiding the delay caused by waiting for the clock signal in the traditional multi-cascade circuit, and the data from other transmission ports of the switch can be smoothly transmitted to another transmission port of the switch through the selection circuit corresponding to the other transmission ports, further improving the speed and efficiency of data transmission and reducing the complexity of the circuit; b. The logic function circuits of each selection circuit in the present invention can work independently, reducing the dependence on multiple cascade circuits, and can reduce the expansion cost of the switch. In addition, the first port in the selection circuit can be either an output port or an input port, which can facilitate two-way data transmission between the two transmission ports in the switch. In addition, there are two transmission lines between the two transmission ports in the switch, making it possible to simultaneously transmit data in both directions between the two transmission ports of the switch; c. The present invention designs a network-type selection circuit, which can control data transmission between multiple transmission ports through fewer control lines. The more transmission ports a switch has, the greater its advantages in reducing data transmission delay, simplifying circuit design, and improving the reliability of switch data transmission. In addition, the application of NMOS switch tubes that can provide lower power consumption and faster switching speed in the selection circuit can further reduce the data transmission delay of the switch. d. The present invention sets a clock signal management circuit corresponding to the selection circuit. By detecting whether the capacitor in the clock signal management circuit is discharged, it can be known whether the clock signal outputs 0 or 1 and whether the output end of the selection circuit is a high level signal or a low level. The clock signal corresponding to the data transmission of each port in the selection circuit can be recorded and the data transmission content can be confirmed. While reducing the data transmission delay between switch ports, the technical solution can also improve the accuracy and reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A circuit diagram of cascading multiple low fan-in circuits in the prior art; Figure 2 A dynamic circuit diagram applicable to a switch provided for an exemplary embodiment of the present invention; Figure 3 A schematic diagram of a nine-port selection circuit provided for an exemplary embodiment of the present invention; Figure 4 A schematic diagram of a five-port selection circuit provided for an exemplary embodiment of the present invention; Figure 5 A schematic diagram of a four-port selection circuit provided for an exemplary embodiment of the present invention; Figure 6 A schematic diagram of a clock signal management circuit provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0028] In one embodiment of the present invention, a dynamic circuit suitable for a switch is provided. Figures 1 to 5 , the dynamic circuit includes a plurality of selection circuits, the selection circuits correspond to the transmission ports of the switch one by one, and the selection circuit is configured to control the transmission port corresponding thereto to be electrically connected to one of the other transmission ports; The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected to other transmission ports in a one-to-one correspondence, and one of the first port and the second port is configured as an input port, and the other port is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines. A plurality of controllable switches are arranged on each of the transmission lines. The controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

[0029] The prior art multiplexer uses multiple small units to form a large unit, such as Figure 1 As shown in FIG. 1 , multiple 2-port to 1-port multiplexers are used to form an 8-port to 1-port multiplexer. The current needs to pass through several small multiplexers, which will cause a long delay. The dynamic circuit applicable to the switch described in this embodiment is to use a large number of repeated applications in the switch. Figure 1 The logic gates of the cascaded multiplexer and demultiplexer shown are simplified. By constructing multiple straight-line transmission lines from the second port to the first port, the distributed controllable switch matrix on each transmission line is controlled to output data from different sources to the target end. Therefore, the dynamic circuit designed in this application can quickly receive the transmitted data within one clock cycle, avoiding the delay caused by waiting for the clock signal in the traditional multi-cascade circuit. In addition, the data from other transmission ports of the switch can be smoothly transmitted to another transmission port of the switch through the selection circuit corresponding to the other transmission ports, further improving the speed and efficiency of data transmission.

[0030] The dynamic circuit not only reduces the delay in the data transmission path within the switch and improves the data transmission efficiency, but also enables each logic function circuit to work independently, reducing the dependence on multiple cascade circuits, thereby reducing the complexity of the circuit. When the switch needs to expand the interface, the corresponding selection circuit is configured for the expanded port and the first port and the second port in the selection circuit are connected to the transmission port of the switch accordingly, which can reduce the expansion cost of the switch. In addition, in the present technical solution, if Figure 2 As shown, the first port in each selection circuit can be either an output port or an input port, which can facilitate bidirectional data transmission between the two transmission ports in the switch, and there are two transmission lines between the two transmission ports in the switch, making it possible to simultaneously transmit data bidirectionally between the two transmission ports of the switch.

[0031] In one embodiment of the present invention, the selection circuit is a network structure, which also includes a plurality of control lines, and the plurality of controllable switches are distributed on the plurality of control lines, each of which is connected to a clock signal and is configured to input a control signal to some of the controllable switches. A combination of control lines where a controllable switch on a path electrically connected between a second port and a first port is located is defined as a control scheme for the corresponding transmission line, and control schemes for different transmission lines are not repeated. Taking a MOS switch tube as an example, the clock signal connected to each of the control lines is simultaneously input into the gate of the MOS switch tube located on the control line, and then all the MOS switch tubes on the control line are turned on or off at the same time.

[0032] It should be noted that the switching states of all the controllable switches are controlled by several control lines, and one control line is used to control the switching states of several controllable switches on different transmission lines, that is, one control line does not control the switching states of two controllable switches arranged on the same transmission line.

[0033] In this embodiment, the dynamic circuit further includes a clock signal management circuit, see Figure 6 , the clock signal management circuit includes a first switch tube, a second switch tube and a capacitor. The gate of the first switch tube is configured as the input end of the clock signal, the source of the first switch tube is configured to be electrically connected to the output end of the first power supply, and the drain of the first switch tube is electrically connected to the first end of the capacitor. The other end of the capacitor can be grounded or connected to other discharge circuits. The gate of the second switch tube is configured as the input end of the clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor. The clock signal management circuit corresponds to the selection circuit one by one, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

[0034] See also Figure 6Preferably, the first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube. When the clock signal is 1, the first switch tube is turned on and the first switch tube is not turned on, and the capacitor is in a charging state; when the clock signal is 0, the first switch tube is not turned on and the first switch tube is turned on. If the output signal of the selection circuit is 1, the capacitor is in a charging state or neither charged nor discharged. If the output signal of the selection circuit is 0, the capacitor is in a discharged state. Therefore, by monitoring the charging and discharging state of the capacitor when the clock signal is 0, it can be determined whether the signal transmitted from the input end of the selection circuit to the output end is 0 or 1, thereby accurately determining the data transmitted by the selection circuit. Therefore, while reducing the data transmission delay between switch ports, the technical solution can also improve the accuracy and reliability of data transmission.

[0035] In order to minimize the area of ​​the selection circuit, the number of controllable switches and the number of control lines, in one embodiment of the present invention, the controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

[0036] More preferably, the number of control circuits is The number of CMOS switches provided on each transmission line is not less than The number of CMOS switches provided on each control line is not greater than .

[0037] In another embodiment of the present invention, different from the above embodiment in which the controllable switch adopts a CMOS switch tube, in this embodiment, the controllable switch adopts an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

[0038] More preferably, the number of control circuits is The number of NMOS switches provided on each transmission line is not less than The number of NMOS switches provided on each control line is not greater than .

[0039] In this embodiment, the complementary metal oxide semiconductor (CMOS) switch tube is replaced with an N-type metal oxide semiconductor (NMOS) switch tube. Given that NMOS can provide lower power consumption and faster switching speed under certain conditions, this is crucial for reducing data transmission delay. Through this replacement, the solution can further reduce the delay of data in the circuit transmission process while ensuring data transmission accuracy.

[0040] In one embodiment of the present invention, in order to reduce the area of ​​the dynamic circuit and the delay of data transmission, for a switch with N transmission ports, N selection circuits are correspondingly set, and the N selection circuits are hierarchically arranged on the same circuit unit. Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on the circuit of different layers. The hierarchical setting scheme of the N selection circuits can be designed with reference to the technical solution disclosed in the Chinese patent application with application number 2024114493648. The dynamic circuit suitable for a switch provided by this application is described below through multiple specific embodiments.

[0041] Taking a nine-port switch as an example, to control one of the devices connected to the eight transmission ports of the switch to transmit data to the device connected to the ninth transmission port of the switch, if the existing technology is used, at least the following steps are required: Figure 1 The three-stage cascade multiplexer shown, the larger the multiplexer constructed using multiple small multiplexers, the higher the delay in data transmission, and there is also the problem of insufficient voltage caused by gate circuits such as AND gates and OR gates.

[0042] Adopt the technical scheme proposed by the present invention to construct Figure 3 The network selection circuit shown, Figure 3 The first ports a to h represent eight different input ports, and the second port O / P represents an output port. Ports a to h are electrically connected to port O / P to form 8 (9-1=8) transmission lines, and a number of series-connected NMOS switches are set on each transmission line. The control of the 8 transmission lines requires 6 The control scheme of the transmission line is defined as follows: Figure 3 The selection circuit is shown.

[0043] Figure 3S0, S1, and S2 are three control lines with the same output level. , , The output levels of the three control lines are consistent, and the s0 control line and If one of the control lines outputs a high level, the other outputs a low level. The s1 control line and If one of the control lines outputs a high level, the other outputs a low level. The s2 control line and If one of the control lines outputs a high level, the other outputs a low level. The gate of the NMOS switch is electrically connected to the output of its corresponding control line. When the control line output on the NMOS switch is a high level, the NMOS will be turned on. For example, when the s0, s1, and s2 control lines output a high level, only the h input terminal is turned on with the O / P output terminal. At this time, the device connected to the h input terminal transmits data to the device connected to the O / P output terminal. If you want to achieve data transmission from the device connected to the a input terminal to the device connected to the O / P output terminal, then the control , , The three control lines output high level respectively.

[0044] By adopting the selection circuit provided in the present application, only 6 control lines (at least 3) are needed to control the transmission of one of the 8 transmission lines, and the data transmission can be completed within one clock cycle, which effectively reduces the data delay and avoids the conflict of data transmission of two transmission lines at the same time.

[0045] Taking a five-port switch as an example, if the controllable switch uses an NMOS switch tube, the selection circuit corresponding to each transmission port in the switch is as follows: Figure 4 shown.

[0046] Taking a four-port switch as an example, the connection method between the dynamic circuit and the four transmission ports of the switch is as follows: Figure 2 As shown. The four-port switch includes transmission ports one to four, which are correspondingly configured with first to fourth selection circuits, and each selection circuit has a first port and three second ports. Taking the first selection circuit as an example, it includes a first port I1 and three second ports O12, O13 and O14, wherein the first port I1 is electrically connected to the transmission port one of the switch, the second port O12 is electrically connected to the transmission port two of the switch or the first port of the second selection circuit, the second port O13 is electrically connected to the transmission port three of the switch or the first port of the third selection circuit, and the second port O14 is electrically connected to the transmission port four of the switch or the first port of the fourth selection circuit. If the controllable switch in the first selection circuit adopts an NMOS switch tube, the structure of the first selection circuit is as follows: Figure 5The structures of the second selection circuit to the fourth selection circuit are the same as the circuit principles of the first selection circuit, and will not be described in detail.

[0047] It should be noted that the dynamic circuit applicable to the switch and the network selection circuit provided by the present invention have greater advantages in reducing data transmission delay, simplifying circuit design, improving reliability of switch data transmission, etc. for switches with more transmission ports. For switches with fewer transmission ports, one controllable switch can be directly provided on each transmission line, and each controllable switch is configured to be independently controlled. This method can reduce delay and save costs.

[0048] In one embodiment of the present invention, a network selection circuit is provided, which includes a first port and a plurality of second ports, wherein the first port and the second port are two ports, one of which is configured as an input port and the other is configured as an output port. The first port is electrically connected to each of the second ports to form a plurality of transmission lines, and a plurality of controllable switches are arranged on each of the transmission lines, and the controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

[0049] The selection circuit further includes a plurality of control lines, the plurality of controllable switches are distributed on the plurality of control lines, and each of the control lines is configured to input control signals to some of the plurality of controllable switches. A combination of control lines where a controllable switch on a path electrically connecting the second port to the first port is located is defined as a control scheme for the corresponding transmission line, and control schemes for different transmission lines are not repeated.

[0050] It should be noted that the network selection circuit is not only applicable to switches, but also applicable to other applications of one-to-multiple-end or multi-end-to-one-end electrical connection control or data transmission control.

[0051] In one embodiment of the present invention, a switch is provided, wherein the switch includes the dynamic circuit as described in any one of the above embodiments or a combination of multiple embodiments.

[0052] In one embodiment of the present invention, a computer system is provided. The computer system includes the switch described in the above embodiment and a plurality of devices that need to perform data transmission, wherein the devices are correspondingly connected to the transmission ports of the switch.

[0053] It should be noted that the network-based selection circuit embodiment, switch embodiment and computer system embodiment provided by the present invention are the same as the inventive concept of the above-mentioned dynamic circuit embodiment applicable to the switch, and all the contents of the dynamic circuit embodiment applicable to the switch are incorporated into the network-based selection circuit embodiment, switch embodiment and computer system embodiment by introduction.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0055] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A dynamic circuit suitable for a switch, characterized in that: The dynamic circuit includes a plurality of selection circuits, each of which corresponds to a transmission port of the switch, and each of which is configured to control the transmission port corresponding to the selection circuit to be electrically connected to one of the other transmission ports; The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected to other transmission ports in a one-to-one correspondence, and one of the first port and the second port is configured as an input port, and the other port is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines. A plurality of controllable switches are arranged on each of the transmission lines. The controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

2. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The selection circuit further comprises a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches; A combination of control lines where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme of the corresponding transmission line, and control schemes of different transmission lines are not repeated.

3. The dynamic circuit applicable to a switch according to claim 2, characterized in that: The controllable switch is an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

4. The dynamic circuit applicable to a switch according to claim 3, characterized in that: The number of control lines is The number of NMOS switches provided on each transmission line is not less than .

5. The dynamic circuit applicable to a switch according to claim 4, characterized in that: The number of NMOS switches provided on each control line is not greater than .

6. The dynamic circuit applicable to a switch according to claim 2, characterized in that: The controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than Among them, log is the logarithm operator, Express Round up.

7. The dynamic circuit applicable to a switch according to claim 6, characterized in that: The number of control lines is The number of CMOS switches provided on each transmission line is not less than .

8. The dynamic circuit applicable to a switch according to claim 7, characterized in that: The number of CMOS switches provided on each control line is not greater than .

9. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The dynamic circuit further includes a clock signal management circuit, the clock signal management circuit includes a first switch tube, a second switch tube and a capacitor, the gate of the first switch tube is configured as an input end of the clock signal, the source of the first switch tube is configured to be electrically connected to the output end of the first power supply, and the drain of the first switch tube is electrically connected to the first end of the capacitor; The gate of the second switch tube is configured as an input end of a clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor; The clock signal management circuit corresponds to the selection circuit one by one, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

10. The dynamic circuit applicable to a switch according to claim 9, characterized in that: The method further includes determining the clock signal of each selection circuit when the selection circuit is working in the following manner: if the capacitor is in a non-charging state, the clock signal is 0; otherwise, the clock signal is 1; and / or, It also includes determining the output signal of the selection circuit when it is working in the following manner: when the clock signal is monitored to be 0, the capacitor is in a charging and discharging state; if the capacitor is in a discharging state, the output signal of the selection circuit is 0; otherwise, the output signal of the selection circuit is 1.

11. The dynamic circuit applicable to a switch according to claim 9, characterized in that: The first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube.

12. The dynamic circuit applicable to a switch according to claim 1, characterized in that: Each of the selection circuits is hierarchically arranged on the same circuit unit, the number of the transmission ports of the switch is N, and the circuit unit is correspondingly provided with N layers of selection circuits; Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on circuits of different layers.

13. The dynamic circuit applicable to a switch according to claim 1, characterized in that: One controllable switch is provided on each of the transmission lines, and each of the controllable switches is configured to be independently controlled.

14. A switch, characterized in that: The switch comprises a dynamic circuit as claimed in any one of claims 1 to 13.

15. A computer system, characterized in that: The computer system comprises the switch as claimed in claim 14 and a device requiring data transmission which is electrically connected to a transmission port of the switch.

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